Semiconductor structure and overlay error measuring method

Abstract

The embodiment of the invention provides a semiconductor structure and an overlay error measuring method. The semiconductor structure comprises a semiconductor substrate and an alignment mark structure located on one side of the semiconductor substrate in the first direction. The alignment mark structure comprises a first dielectric layer and a second dielectric layer. The first dielectric layer comprises a first mark alignment pattern, and the first mark alignment pattern comprises a first grid bar; the second dielectric layer is located on one side of the first dielectric layer in the first direction and comprises a second mark alignment pattern. The second mark alignment pattern comprises a second grid bar and a third grid bar covering part of the second grid bar, and the second grid bar is the same as the first grid bar; in the direction intersecting with the first direction, the extension size of the second grid bars is larger than that of the third grid bars.

Description

Technical Field

[0001] This application relates to the field of semiconductor design and manufacturing, and more specifically, to a semiconductor structure and a method for measuring overlay error. Background Technology

[0002] As device dimensions continue to shrink in semiconductor manufacturing, stringent overlay (OVL) control is essential to ensure good device yield. In recent years, micro-diffraction-based overlay (μDBO) has increasingly become one of the leading technologies in the field of overlay error measurement, demonstrating superior performance in a wide range of applications.

[0003] In μDBO technology, as the wavelength changes, the diffracted light from the grating will produce an oscillating response. The bias between the two gratings will cause the corresponding signal to shift. The difference between the two shifted signals is the maximum potential signal of OVL, which can then be converted into the actual OVL value. Summary of the Invention

[0004] The embodiments of this application provide semiconductor structures that can at least partially solve the above-mentioned technical problems or other problems, as well as methods for measuring overlay errors.

[0005] This application provides a semiconductor structure, comprising: a semiconductor substrate; and an alignment mark structure located on one side of the semiconductor substrate along a first direction, and comprising: a first dielectric layer including a first mark alignment pattern, wherein the first mark alignment pattern includes a first gate strip; a second dielectric layer located on one side of the first dielectric layer along the first direction, and including a second mark alignment pattern, wherein the second mark alignment pattern includes a second gate strip and a third gate strip covering a portion of the second gate strip, wherein the second gate strip is identical to the first gate strip; and in a direction intersecting the first direction, the extension dimension of the second gate strip is greater than the extension dimension of the third gate strip.

[0006] In one embodiment of this application, the first grid bar includes a first sub-grid bar extending along a second direction and a second sub-grid bar extending along a third direction, wherein a plurality of first sub-grid bars are spaced apart in the third direction and a plurality of second sub-grid bars are spaced apart in the second direction, wherein the first direction, the second direction and the third direction intersect each other.

[0007] In one embodiment of this application, the second grid bar includes a third sub-grid bar extending along a second direction and a fourth sub-grid bar extending along a third direction, wherein a plurality of third sub-grid bars are spaced apart in the third direction and a plurality of third sub-grid bars are spaced apart in the second direction, wherein the first direction, the second direction and the third direction intersect each other.

[0008] In one embodiment of this application, the third grid strip includes a fifth sub-grid strip and a sixth sub-grid strip, wherein the fifth sub-grid strip extends along a second direction and covers a portion of the third sub-grid strip; the sixth sub-grid strip extends along a third direction and covers a portion of the fourth sub-grid strip; and a plurality of fifth sub-grid strips are spaced apart in the third direction, and a plurality of sixth sub-grid strips are spaced apart in the second direction.

[0009] In one embodiment of this application, the number of the first grid bar, the second grid bar, and the third grid bar are all equal.

[0010] In one embodiment of this application, the second grid bar extends in the same direction as the first grid bar; the dimension of the second grid bar perpendicular to its extension direction is equal to the dimension of the first grid bar perpendicular to its extension direction; the dimension of the second grid bar in its extension direction is equal to the dimension of the first grid bar in its extension direction; and the distance between adjacent second grid bars is equal to the distance between adjacent first grid bars.

[0011] In one embodiment of this application, the dimension of the second grid bar perpendicular to its extension direction is equal to the dimension of the third grid bar perpendicular to its extension direction.

[0012] In one embodiment of this application, the dimensions of the second grid bar in its extension direction and the dimensions of the third grid bar in its extension direction are both 5 micrometers to 50 micrometers.

[0013] In one embodiment of this application, in a direction intersecting with the first direction, the size of the first region is equal to the size of the second region, wherein the first region is the region where the third grid strip is located in the second mark alignment pattern, and the second region is a region in the second mark alignment pattern that is different from the first region.

[0014] In one embodiment of this application, both the first mark alignment pattern and the second mark alignment pattern include rotationally symmetric patterns.

[0015] In one embodiment of this application, the distance between adjacent second grid bars is equal to the distance between adjacent third grid bars.

[0016] In one embodiment of this application, both the first mark alignment pattern and the second mark alignment pattern include overlapping mark alignment patterns based on optical diffraction.

[0017] In one embodiment of this application, the first mark alignment pattern and the second mark alignment pattern are disposed opposite to each other along a first direction.

[0018] In one embodiment of this application, the semiconductor structure further includes a device and a cleavage along a first direction located on one side of the semiconductor substrate, wherein the cleavage is located between adjacent devices; and an alignment mark structure is located in at least one of the devices and the cleavage.

[0019] In one embodiment of this application, the dimension d1 of the second mark alignment pattern in the direction intersecting with the first direction and the dimension d2 of the cutting ditch in the direction perpendicular to its extension satisfy: 10% ≤ d1 / d2 ≤ 80%.

[0020] This application also provides a method for measuring overlay error. The method includes: sequentially forming a first dielectric layer and a second dielectric layer on one side of a semiconductor substrate along a first direction, wherein the first dielectric layer includes a first mark alignment pattern, the first mark alignment pattern includes a first gate strip, the second dielectric layer includes a second mark alignment pattern, the second mark alignment pattern includes a second gate strip and a third gate strip covering a portion of the second gate strip, the second gate strip is the same as the first gate strip, and in a direction intersecting the first direction, the extension dimension of the second gate strip is greater than the extension dimension of the third gate strip; and measuring the signal diffracted and reflected by the second mark alignment pattern, and determining the overlay error based on the signal.

[0021] In one embodiment of this application, measuring the signal diffracted and reflected by the alignment pattern via the second mark and determining the overlay error based on the signal includes: determining the signal by a single measurement and determining the overlay error based on the signal.

[0022] In one embodiment of this application, determining a signal through a single measurement and determining an overlay error based on the signal includes: in a single measurement, obtaining the light intensity of a first positive first-order diffracted light and a first negative first-order diffracted light diffracted and reflected by the second grating, and the light intensity of a second positive first-order diffracted light and a second negative first-order diffracted light diffracted and reflected by the second and third gratings; combining the light intensity of the first positive first-order diffracted light and the light intensity of the second positive first-order diffracted light to form a final value of the light intensity of the positive first-order diffracted light, and combining the light intensity of the first negative first-order diffracted light and the light intensity of the second negative first-order diffracted light to form a final value of the light intensity of the negative first-order diffracted light; and determining the overlay error based on the difference between the light intensity of the final value of the positive first-order diffracted light and the light intensity of the final value of the negative first-order diffracted light. Attached Figure Description

[0023] Other features, objects, and beneficial effects of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. In the drawings:

[0024] Figure 1 This is a top view schematic diagram of a semiconductor structure according to one embodiment of this application;

[0025] Figure 2 This is a partial top view schematic diagram of a semiconductor structure according to one embodiment of this application;

[0026] Figure 3This is a cross-sectional schematic diagram of an alignment mark structure according to one embodiment of this application;

[0027] Figure 4 This is a top view of a first mark alignment pattern according to one embodiment of this application;

[0028] Figure 5 This is a top view of a second mark alignment pattern according to one embodiment of this application;

[0029] Figure 6 This is a partial top view of a second mark alignment pattern according to one embodiment of this application;

[0030] Figure 7 This is a partial top view of a second mark alignment pattern according to one embodiment of this application;

[0031] Figure 8 This is a schematic diagram of the working process of a method for measuring overlay error according to one embodiment of this application;

[0032] Figure 9 This is a flowchart of a method for measuring overlay error according to one embodiment of this application; and

[0033] Figure 10 This is a schematic diagram illustrating the operation of measuring signals diffracted and reflected by a second mark aligned with a pattern according to one embodiment of this application.

[0034] Specific methods

[0035] The present application will now be described in detail with reference to the accompanying drawings. The exemplary embodiments mentioned herein are for illustrative purposes only and are not intended to limit the scope of the application. Throughout the specification, the same reference numerals refer to the same elements.

[0036] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used to indicate approximation rather than degree and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0037] It should also be understood that the expression "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "comprising," "including," "having," "having," and / or "having have" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence or addition of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. When describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to an example or illustration.

[0038] Furthermore, when terms such as "connection," "coverage," and / or "formed on" are used in this application, they may indicate direct or indirect contact between the corresponding components, unless there are other explicit limitations or can be inferred from the context. In addition, "connection" may also refer to electrical connection, such as the circuit conduction connection state of a semiconductor structure in operation.

[0039] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. Furthermore, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and shall not be interpreted in an idealized or overly formalized sense.

[0040] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0041] Figure 1 This is a top view schematic diagram of a semiconductor structure 1000 according to one embodiment of this application.

[0042] Figure 2 This is a partial top view of a semiconductor structure 1000 according to one embodiment of this application.

[0043] Figure 3 This is a cross-sectional schematic diagram of an alignment mark structure 100 according to one embodiment of this application.

[0044] Figure 4 This is a top view of the first mark alignment pattern 110 according to one embodiment of this application. Figure 5 This is a top view of the second mark alignment pattern 120 according to one embodiment of this application. Figure 6 This is a top view of a portion 120-1 of the second mark alignment pattern according to one embodiment of this application.

[0045] like Figures 1-6 As shown, the semiconductor structure 1000 includes an alignment mark structure 100 and a semiconductor substrate 200. The alignment mark structure 100 is located on one side of the semiconductor substrate 200 along a first direction (z-direction) and includes a first dielectric layer 101 and a second dielectric layer 102. The first dielectric layer 101 includes a first mark alignment pattern 110, wherein the first mark alignment pattern 110 includes a first gate strip 111. The second dielectric layer 102 is located on one side of the first dielectric layer 101 along the z-direction and includes a second mark alignment pattern 120, wherein the second mark alignment pattern 120 includes a second gate strip 121 and a third gate strip 122 covering a portion of the second gate strip 121. The second gate strip 121 is identical to the first gate strip 111, and in directions intersecting the z-direction (e.g., x-direction, y-direction), the extension dimension L2 of the second gate strip 121 is greater than the extension dimension L3 of the third gate strip 122.

[0046] According to at least one embodiment of the semiconductor structure provided in this application, the alignment mark structure includes a first mark alignment pattern and a second mark alignment pattern. The first mark alignment pattern is disposed in the front layer and includes a first gate strip. The second mark alignment pattern is disposed in the current layer and includes a second gate strip and a third gate strip covering a portion of the second gate strip, wherein the second gate strip is identical to the first gate strip. In other words, the first mark alignment pattern includes a first gate strip corresponding to the front layer, and the second mark alignment pattern includes a second gate strip corresponding to the front layer and a third gate strip corresponding to the current layer. Therefore, the second mark alignment pattern places the mark corresponding to the front layer in the current layer and merges it with the mark corresponding to the current layer into a single pattern, so as to accurately obtain the overlay error between the front layer and the current layer through a single observation, effectively improving the accuracy, stability, and efficiency of overlay error measurement.

[0047] Specifically, refer to Figure 1 and Figure 2 In some embodiments of this application, the semiconductor structure 1000 further includes a device 300 and a cleavage 400 located along the z-direction on one side of the semiconductor substrate 200, wherein the cleavage 400 is located between adjacent devices 300. Optionally, the device 300 may include a memory 310, logic circuitry 320, and input / output devices 330. Alignment mark structure 100 may be located in at least one of the devices 300 and the cleavage 400. For example, Figure 2 The alignment mark structure 100 shown is located at the cutting channel 400.

[0048] Optionally, the dimension of the alignment mark structure 100 in the direction intersecting the z-direction (e.g., the x-direction, y-direction) is smaller than the dimension b2 of the cutting sipe 400 in the direction perpendicular to its extension direction, where dimension b2 can be understood as the width of the cutting sipe 400. For example, the dimension of the first mark alignment pattern 110 of the alignment mark structure 100 in the direction intersecting the z-direction (e.g., the x-direction, y-direction) is smaller than the width b2 of the cutting sipe 400. Furthermore, the dimension b1 of the second mark alignment pattern 120 of the alignment mark structure 100 in the direction intersecting the z-direction (e.g., the x-direction, y-direction) and the width b2 of the cutting sipe 400 can satisfy 10% ≤ d1 / d2 ≤ 80%.

[0049] Taking the case where the width b2 of the dicing track 400 is 60 μm as an example, the size of the first mark alignment pattern 110 can be 34 μm × 34 μm, 16 μm × 16 μm, or 8 μm × 8 μm, etc. Similarly, when the width b2 of the dicing track 400 is 60 μm, the size of the second mark alignment pattern 120 can also be 34 μm × 34 μm, 16 μm × 16 μm, or 8 μm × 8 μm, etc. In other words, although the second mark alignment pattern includes marks corresponding to the previous layer and marks corresponding to the current layer, the size of the second mark alignment pattern is the same as that of a conventional mark alignment pattern (e.g., the first mark alignment pattern). Therefore, it does not need to occupy more area of ​​the dicing track, or more area of ​​the device when the alignment mark structure is located in the device. This can effectively improve the accuracy, stability, and efficiency of overlay error measurement while ensuring the area utilization of the semiconductor structure.

[0050] like Figure 5 and Figure 6 As shown, in some embodiments of this application, the dimensions L2 of the second grating 121 in its extending direction and the dimension L3 of the third grating 122 in its extending direction of the second mark alignment pattern 120 can both be from 5 micrometers to 50 micrometers. Furthermore, refer to... Figure 4 The dimension L1 of the first mark aligned with the first grid bar 111 of the pattern 110 in its extension direction can also be 5 micrometers to 50 micrometers.

[0051] Figure 7 This is a partial top view of the second mark alignment pattern 120 according to one embodiment of this application.

[0052] like Figure 7 As shown, in some embodiments of this application, the dimension d2 of the second grid bar 121 perpendicular to its extension direction is equal to the dimension d3 of the third grid bar 122 perpendicular to its extension direction. The distance s2 between adjacent second grid bars 121 is equal to the distance s3 between adjacent third grid bars 122. Optionally, the number of multiple second grid bars 121 is equal to the number of multiple third grid bars 122.

[0053] In addition, combined Figure 4 and Figure 7 The dimension d2 of the second grating 121 perpendicular to its extension direction is equal to the dimension d1 of the first grating 111 perpendicular to its extension direction. The dimension L2 of the second grating 121 in its extension direction is equal to the dimension L1 of the first grating 111 in its extension direction. The distance s2 between adjacent second gratings 121 is equal to the distance s1 between adjacent first gratings 111. In addition, the number of second gratings 121 is equal to the number of first gratings 111. In other words, the second gratings of the second mark alignment pattern are the same as the first gratings of the first mark alignment pattern, so the overlay error between the previous layer and the current layer can be accurately obtained by measuring the diffraction and reflection signals through the second mark alignment pattern with only one observation.

[0054] like Figure 3 As shown, optionally, the first mark alignment pattern 110 and the second mark alignment pattern 120 can be arranged opposite each other along the z-direction to simplify the process of preparing the mark alignment pattern and to make reasonable use of the area of ​​the cutting path.

[0055] like Figure 4 and Figure 5 As shown, alternatively, both the first mark alignment pattern 110 and the second mark alignment pattern 120 can include overlapping mark alignment patterns based on optical diffraction. In other words, the overlay error can be measured using the principle of light diffraction, for example, by shining a uniform light beam into the mark alignment pattern 100, which diffracts as it passes through the second mark alignment pattern 120. The overlay error can be obtained by combining the light intensity diffracted and reflected by the second grating 121 and the third grating 122, as well as the light intensity diffracted and reflected only by the second grating 121.

[0056] In some embodiments of this application, both the first mark alignment pattern 110 and the second mark alignment pattern 120 may include rotationally symmetric patterns. Taking the first mark alignment pattern 110 as an example, the first grid strip 111 of the first mark alignment pattern 110 may include a first sub-grid strip 1111 extending along the x-direction and a second sub-grid strip 1112 extending along the y-direction. Optionally, the x-direction, y-direction, and z-direction may intersect each other. For example, the x-direction, y-direction, and z-direction may be perpendicular to each other.

[0057] Furthermore, the first mark alignment pattern 110 may include a first partition 110-1, a second partition 110-2, a third partition 110-3, and a fourth partition 110-4. The first partition 110-1 may include a plurality of second sub-grid strips 1112 spaced apart along the x-direction; the second partition 110-2 may include a plurality of first sub-grid strips 1111 spaced apart along the y-direction; the third partition 110-3 may include a plurality of second sub-grid strips 1112 spaced apart along the x-direction; and the fourth partition 110-4 may include a plurality of first sub-grid strips 1111 spaced apart along the y-direction. In other words, the pattern formed by the plurality of first grid bars 111 located in the first partition 110-1 can be rotated 90° around the center of the first mark aligned with the pattern 110 to form the pattern formed by the plurality of first grid bars 111 located in the second partition 110-2; the pattern formed by the plurality of first grid bars 111 located in the second partition 110-2 can be rotated 90° around the center of the first mark aligned with the pattern 110 to form the pattern formed by the plurality of first grid bars 111 located in the third partition 110-3; and the pattern formed by the plurality of first grid bars 111 located in the third partition 110-3 can be rotated 90° around the center of the first mark aligned with the pattern 110 to form the pattern formed by the plurality of first grid bars 111 located in the fourth partition 110-4.

[0058] It should be noted that, Figure 4 A first mark alignment pattern in the shape of a square is shown, and the square pattern comprises four 90° rotationally symmetrical patterns. However, it is understood that the first and second mark alignment patterns shown in the figures and related content are for illustrative purposes only and are not intended to limit the scope of this application. Those skilled in the art can adjust the first and second mark alignment patterns according to the concept of this invention to achieve the same technical effect.

[0059] like Figure 4 and Figure 5 As shown, similar to the first mark alignment pattern 110, the second mark alignment pattern 120 may also include a rotationally symmetric pattern.

[0060] For example, the second grid bar 121 may include a third sub-grid bar 1211 extending along the x-direction and a fourth sub-grid bar 1212 extending along the y-direction. The plurality of third sub-grid bars 1211 are spaced apart in the y-direction, and the plurality of fourth sub-grid bars 1212 are spaced apart in the x-direction.

[0061] Furthermore, the third grid strip 122 may include a fifth sub-grid strip 1221 and a sixth sub-grid strip 1222, wherein the fifth sub-grid strip 1221 extends along the x-direction and partially covers the third sub-grid strip 1211; the sixth sub-grid strip 1222 extends along the y-direction and partially covers the fourth sub-grid strip 1212. Additionally, a plurality of fifth sub-grid strips 1221 may be spaced apart in the y-direction, and a plurality of sixth sub-grid strips 1222 may be spaced apart in the x-direction.

[0062] The second marker alignment pattern 120 may also include four partitions, such as a fifth partition 120-1, a sixth partition 120-2, a seventh partition 120-3, and an eighth partition 120-4. The fifth partition 120-1 may include a plurality of fourth sub-grid strips 1212 spaced apart along the x-direction, and a plurality of sixth sub-grid strips 1222 covering a portion of the fourth sub-grid strips 1212; the sixth partition 120-2 may include a plurality of third sub-grid strips 1211 spaced apart along the y-direction, and a fifth sub-grid strip 1221 covering a portion of the third sub-grid strips 1211; the seventh partition 120-3 may include a plurality of fourth sub-grid strips 1212 spaced apart along the x-direction, and a plurality of sixth sub-grid strips 1222 covering a portion of the fourth sub-grid strips 1212; and the eighth partition 120-4 may include a plurality of third sub-grid strips 1211 spaced apart along the y-direction, and a fifth sub-grid strip 1221 covering a portion of the third sub-grid strips 1211.

[0063] The pattern formed by the plurality of second grid bars 121 and third grid bars 122 located in the fifth partition 120-1 can be rotated 90° around the center of the second mark aligned with the pattern 120 to form the pattern formed by the plurality of second grid bars 121 and third grid bars 122 located in the sixth partition 120-2; the pattern formed by the plurality of second grid bars 121 and third grid bars 122 located in the sixth partition 120-2 can be rotated 90° around the center of the second mark aligned with the pattern 120 to form the pattern formed by the plurality of second grid bars 121 and third grid bars 122 located in the seventh partition 120-3; and the pattern formed by the plurality of second grid bars 121 and third grid bars 122 located in the seventh partition 120-3 can be rotated 90° around the center of the second mark aligned with the pattern 120 to form the pattern formed by the plurality of second grid bars 121 and third grid bars 122 located in the eighth partition 120-4.

[0064] In addition, refer to Figure 5 and Figure 6In some embodiments of this application, the second mark alignment pattern 120 may include a first region 01 and a second region 02, wherein the first region 01 is the region where the third grid strip 122 is located in the second mark alignment pattern 120, and the second region 02 is a region in the second mark alignment pattern 120 that is different from the first region 01. Alternatively, a plurality of second grid strips 121 are distributed in the first region 01 and the second region 02, while the third grid strips 122 only cover a portion of the second grid strips 121, and therefore the plurality of third grid strips 122 are only distributed in the first region 01.

[0065] Optionally, in directions intersecting the z-direction (e.g., the x-direction, y-direction), the size c1 of the first region 01 is equal to the size c2 of the second region 02, where size c1 can be understood as the maximum size of the first region 01, and size c2 can be understood as the maximum size of the second region 02. Alternatively, the third grid strip 122 used to mark the current layer and the second grid strip 121 used to mark the previous layer may have the same size in the xy-plane to facilitate the measurement of overlay errors.

[0066] Specifically, when the second mark alignment pattern 120 includes multiple partitions, such as the fifth partition 120-1, the sixth partition 120-2, the seventh partition 120-3, and the eighth partition 120-4, each partition may have a first region 01 and a second region 02. For example, the first region 01 and the second region 02 located in the fifth partition 120-1 are respectively the first sub-region 011 and the second sub-region 021; and the first region 01 and the second region 02 located in the sixth partition 120-2 are respectively the third sub-region 012 and the fourth sub-region 022, wherein the third grid strip 122 is distributed in the first sub-region 011 and the third sub-region 012.

[0067] Therefore, according to at least one embodiment of this application, the alignment mark structure includes a first mark alignment pattern and a second mark alignment pattern. The first mark alignment pattern is disposed on the front layer and includes a first grid strip. The second mark alignment pattern is disposed on the current layer and includes a second grid strip and a third grid strip covering a portion of the second grid strip, wherein the second grid strip is identical to the first grid strip. In other words, the first mark alignment pattern includes a first grid strip corresponding to the front layer, and the second mark alignment pattern includes a second grid strip corresponding to the front layer and a third grid strip corresponding to the current layer. Thus, the second mark alignment pattern places the mark corresponding to the front layer in the current layer and merges it with the mark corresponding to the current layer into a single pattern, so as to accurately obtain the overprinting error between the front layer and the current layer through a single observation, effectively improving the accuracy, stability, and efficiency of overprinting error measurement.

[0068] Figure 8 This is a schematic diagram of the working process of a method 2000 for measuring overlay error according to one embodiment of this application. Figure 9This is a flowchart of a method 2000 for measuring overprinting error according to one embodiment of this application. Figure 10 This is a schematic diagram illustrating the operation of measuring signals diffracted and reflected by a second mark aligned with a pattern according to one embodiment of this application.

[0069] like Figures 8-10 As shown, the method for measuring overlay error 2000 may include:

[0070] S1, a first dielectric layer and a second dielectric layer are sequentially formed on one side of a semiconductor substrate along a first direction, wherein the first dielectric layer includes a first mark alignment pattern, the first mark alignment pattern includes a first gate strip, the second dielectric layer includes a second mark alignment pattern, the second mark alignment pattern includes a second gate strip and a third gate strip covering a portion of the second gate strip, the second gate strip is the same as the first gate strip, and in the direction intersecting with the first direction, the extension dimension of the second gate strip is greater than the extension dimension of the third gate strip.

[0071] S2, measure the signals diffracted and reflected by the alignment pattern via the second mark, and determine the overlay error based on the signals.

[0072] The following will combine Figures 1-10 The specific process of each step of the above-mentioned method 2000 for measuring overprinting error is described in detail in the embodiments of this application.

[0073] Step S1

[0074] like Figure 9 As shown, step S1 sequentially forms a first dielectric layer and a second dielectric layer on one side of a semiconductor substrate along a first direction. The first dielectric layer includes a first mark alignment pattern, which includes a first gate strip. The second dielectric layer includes a second mark alignment pattern, which includes a second gate strip and a third gate strip covering a portion of the second gate strip. The second gate strip is identical to the first gate strip, and in the direction intersecting the first direction, the extension dimension of the second gate strip is greater than the extension dimension of the third gate strip. This step may include, for example, forming the first mark alignment pattern in the first dielectric layer; and forming the second mark alignment pattern in the second dielectric layer, wherein the second gate strip of the second mark alignment pattern is identical to the first gate strip of the first mark alignment pattern, and the third gate strip of the second mark alignment pattern covers a portion of the second gate strip, and in the direction intersecting the first direction, the extension dimension of the second gate strip is greater than the extension dimension of the third gate strip.

[0075] Specifically, a first mark alignment pattern can be formed using a photolithography process with the same parameters as the previous layer, and a second mark alignment pattern can be formed using a photolithography process with the same parameters as the previous and current layers. Thus, the first mark alignment pattern includes a first grating corresponding to the previous layer, and the second mark alignment pattern includes a second grating corresponding to the previous layer and a third grating corresponding to the current layer. Therefore, the second mark alignment pattern places the mark corresponding to the previous layer in the current layer and merges it with the mark corresponding to the current layer into a single pattern. This allows for accurate acquisition of the overlay error between the previous and current layers through a single observation, effectively improving the accuracy, stability, and efficiency of overlay error measurement.

[0076] Optionally, refer to Figure 1 and Figure 2 The semiconductor structure 1000 also includes a device 300 and a cleavage 400 located along the z-direction on one side of the semiconductor substrate 200, wherein the cleavage 400 is located between adjacent devices 300. Alignment mark structure 100 may be located in at least one of the devices 300 and the cleavage 400. For example, Figure 2 The alignment mark structure 100 shown is located at the cutting channel 400.

[0077] Furthermore, the dimension of the alignment mark structure 100 in the direction intersecting the z-direction (e.g., the x-direction, y-direction) is smaller than the dimension b2 of the cutting sipe 400 in its direction perpendicular to its extension, where dimension b2 can be understood as the width of the cutting sipe 400. For example, the dimension of the first mark alignment pattern 110 of the alignment mark structure 100 in the direction intersecting the z-direction (e.g., the x-direction, y-direction) is smaller than the width b2 of the cutting sipe 400. Furthermore, the dimension b1 of the second mark alignment pattern 120 of the alignment mark structure 100 in the direction intersecting the z-direction (e.g., the x-direction, y-direction) and the width b2 of the cutting sipe 400 can satisfy 10% ≤ d1 / d2 ≤ 80%.

[0078] In other words, although the second mark alignment pattern includes marks corresponding to the previous layer and marks corresponding to the current layer, the second mark alignment pattern has the same size as the conventional mark alignment pattern (e.g., the first mark alignment pattern). Therefore, it does not require additional area of ​​the dicing channel or additional area of ​​the device when the alignment mark structure is located in the device. This can effectively improve the accuracy, stability and efficiency of overlay error measurement while ensuring the area utilization of the semiconductor structure.

[0079] like Figure 5 and Figure 6As shown, in some embodiments of this application, the dimensions L2 of the second grating 121 in its extending direction and the dimension L3 of the third grating 122 in its extending direction of the second mark alignment pattern 120 can both be from 5 micrometers to 50 micrometers. Furthermore, refer to... Figure 4 The dimension L1 of the first mark aligned with the first grid bar 111 of the pattern 110 in its extension direction can also be 5 micrometers to 50 micrometers.

[0080] like Figure 7 As shown, in some embodiments of this application, the dimension d2 of the second grid bar 121 perpendicular to its extension direction is equal to the dimension d3 of the third grid bar 122 perpendicular to its extension direction. The distance s2 between adjacent second grid bars 121 is equal to the distance s3 between adjacent third grid bars 122. Optionally, the number of multiple second grid bars 121 is equal to the number of multiple third grid bars 122.

[0081] In addition, combined Figure 4 and Figure 7 The dimension d2 of the second grating 121 perpendicular to its extension direction is equal to the dimension d1 of the first grating 111 perpendicular to its extension direction. The dimension L2 of the second grating 121 in its extension direction is equal to the dimension L1 of the first grating 111 in its extension direction. The distance s2 between adjacent second gratings 121 is equal to the distance s1 between adjacent first gratings 111. In addition, the number of second gratings 121 is equal to the number of first gratings 111. In other words, the second gratings of the second mark alignment pattern are the same as the first gratings of the first mark alignment pattern, so the overlay error between the previous layer and the current layer can be accurately obtained by measuring the diffraction and reflection signals through the second mark alignment pattern with only one observation.

[0082] like Figure 4 and Figure 5 As shown, as an option, both the first mark alignment pattern 110 and the second mark alignment pattern 120 may include overlapping mark alignment patterns based on optical diffraction.

[0083] Optionally, the first grid strip 111 of the first mark alignment pattern 110 may include a first sub-grid strip 1111 extending in the x-direction and a second sub-grid strip 1112 extending in the y-direction. Optionally, the x-direction, y-direction, and z-direction may intersect each other. For example, the x-direction, y-direction, and z-direction may be perpendicular to each other.

[0084] Furthermore, the second grid strip 121 of the second mark alignment pattern 120 may include a third sub-grid strip 1211 extending along the x-direction and a fourth sub-grid strip 1212 extending along the y-direction. A plurality of third sub-grid strips 1211 are spaced apart in the y-direction, and a plurality of fourth sub-grid strips 1212 are spaced apart in the x-direction. The third grid strip 122 of the second mark alignment pattern 120 may include a fifth sub-grid strip 1221 and a sixth sub-grid strip 1222, wherein the fifth sub-grid strip 1221 extends along the x-direction and partially covers the third sub-grid strip 1211; and the sixth sub-grid strip 1222 extends along the y-direction and partially covers the fourth sub-grid strip 1212. Additionally, a plurality of fifth sub-grid strips 1221 may be spaced apart in the y-direction, and a plurality of sixth sub-grid strips 1222 may be spaced apart in the x-direction.

[0085] refer to Figure 5 and Figure 6 In some embodiments of this application, the second mark alignment pattern 120 may include a first region 01 and a second region 02, wherein the first region 01 is the region where the third grid strip 122 is located in the second mark alignment pattern 120, and the second region 02 is a region in the second mark alignment pattern 120 that is different from the first region 01. Alternatively, a plurality of second grid strips 121 are distributed in the first region 01 and the second region 02, while the third grid strips 122 only cover a portion of the second grid strips 121, and therefore the plurality of third grid strips 122 are only distributed in the first region 01.

[0086] Optionally, in directions intersecting the z-direction (e.g., the x-direction, y-direction), the size c1 of the first region 01 is equal to the size c2 of the second region 02, where size c1 can be understood as the maximum size of the first region 01, and size c2 can be understood as the maximum size of the second region 02. Alternatively, the third grid strip 122 used to mark the current layer and the second grid strip 121 used to mark the previous layer may have the same size in the xy-plane to facilitate the measurement of overlay errors.

[0087] Specifically, when the second mark alignment pattern 120 includes multiple partitions, such as the fifth partition 120-1, the sixth partition 120-2, the seventh partition 120-3, and the eighth partition 120-4, each partition may have a first region 01 and a second region 02. For example, the first region 01 and the second region 02 located in the fifth partition 120-1 are respectively the first sub-region 011 and the second sub-region 021; and the first region 01 and the second region 02 located in the sixth partition 120-2 are respectively the third sub-region 012 and the fourth sub-region 022, wherein the third grid strip 122 is distributed in the first sub-region 011 and the third sub-region 012.

[0088] Step S2

[0089] like Figures 8-10As shown, step S2, measuring the signals diffracted and reflected by the alignment pattern via the second mark and determining the overlay error based on the signals, may include, for example, determining the signals diffracted and reflected by the alignment pattern via the second mark through a single measurement and determining the overlay error between the previous layer and the current layer based on the signals.

[0090] The measurement value of the current layer and the reference value of the previous layer can be obtained in one measurement, which simplifies the steps of the overlay error measurement method and improves the efficiency of the overlay error measurement method. In addition, obtaining the measurement value of the current layer and the reference value of the previous layer in one measurement can reduce the "additional" error caused by obtaining the measurement value of the current layer and the reference value of the previous layer in "two" separate measurements, thereby improving the accuracy of the overlay error.

[0091] Combination Figure 8 and Figure 10 In some embodiments of this application, the light intensity of the first positive first-order diffracted light and the light intensity of the first negative first-order diffracted light diffracted and reflected by the second grating strip, as well as the light intensity of the second positive first-order diffracted light and the light intensity of the second negative first-order diffracted light diffracted and reflected by the second and third grating strips, can be obtained in a single measurement. The light intensity of the first positive first-order diffracted light and the light intensity of the second positive first-order diffracted light are combined to form the final value of the positive first-order diffracted light intensity, and the light intensity of the first negative first-order diffracted light and the light intensity of the second negative first-order diffracted light are combined to form the final value of the negative first-order diffracted light intensity. The overlay error is determined based on the difference between the light intensity of the final value of the positive first-order diffracted light and the light intensity of the final value of the negative first-order diffracted light.

[0092] Specifically, the overlay error measurement system may include an optical system, an analysis module, and a sample to be measured. During a single measurement, the light source of the optical system projects a uniform beam of light onto the mark alignment pattern 100. The beam undergoes diffraction and reflection as it passes through the second mark alignment pattern 120. The detector of the optical system obtains the light intensities 501 and 502 of the first positive first-order diffracted light diffracted and reflected by the second grating 121, and 503 and 504 of the second positive first-order diffracted light diffracted and reflected by the second grating 121 and the third grating 122. After analysis by the analysis module, the light intensities 501 and 503 of the first positive first-order diffracted light can be combined to obtain the final value of the positive first-order diffracted light intensity, and the light intensities 502 and 504 of the first negative first-order diffracted light can be combined to obtain the final value of the negative first-order diffracted light intensity. The difference between the light intensity of the final positive first-order diffraction light and the light intensity of the final negative first-order diffraction light is proportional to the overlay error between the previous layer and the current layer within a certain range. Therefore, the overlay error between the previous layer and the current layer can be obtained efficiently and accurately by using the difference between the light intensity of the final positive first-order diffraction light and the light intensity of the final negative first-order diffraction light.

[0093] Therefore, according to the overprinting error measurement method provided in at least one embodiment of this application, the alignment mark structure includes a first mark alignment pattern and a second mark alignment pattern. The first mark alignment pattern is disposed on the front layer and includes a first grid strip. The second mark alignment pattern is disposed on the current layer and includes a second grid strip and a third grid strip covering a portion of the second grid strip, wherein the second grid strip is identical to the first grid strip. In other words, the first mark alignment pattern includes a first grid strip corresponding to the front layer, and the second mark alignment pattern includes a second grid strip corresponding to the front layer and a third grid strip corresponding to the current layer. Thus, the second mark alignment pattern places the mark corresponding to the front layer in the current layer and merges it with the mark corresponding to the current layer into a single pattern, so as to accurately obtain the overprinting error between the front layer and the current layer through a single observation, effectively improving the accuracy, stability, and efficiency of overprinting error measurement.

[0094] Although exemplary structures of semiconductor structures and methods for measuring overlay errors are described herein, it is understood that one or more features may be omitted, substituted, or added from the structure of the semiconductor structure or the measurement methods.

[0095] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to the technical solutions formed by the selected combination of the above-described technical features, but should also cover other technical solutions formed by any combination of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A semiconductor structure, comprising: Semiconductor substrate; as well as An alignment mark structure is located on one side of a semiconductor substrate along a first direction and includes: A first dielectric layer includes a first mark alignment pattern, wherein the first mark alignment pattern includes a first grid strip; A second dielectric layer, located on one side of the first dielectric layer along the first direction, includes a second mark alignment pattern, wherein the second mark alignment pattern includes a second grid strip and a third grid strip covering a portion of the second grid strip. Wherein, the second grid bar is the same as the first grid bar; and In the direction intersecting the first direction, the extension dimension of the second grid bar is greater than the extension dimension of the third grid bar.

2. The semiconductor structure according to claim 1, wherein, The first grid bar includes a first sub-grid bar extending along a second direction and a second sub-grid bar extending along a third direction. In this configuration, a plurality of first sub-grid strips are spaced apart in the third direction, and a plurality of second sub-grid strips are spaced apart in the second direction, wherein the first direction, the second direction, and the third direction intersect each other.

3. The semiconductor structure according to claim 1, wherein, The second grid bar includes a third sub-grid bar extending along a second direction and a fourth sub-grid bar extending along a third direction. The plurality of third sub-grid strips are spaced apart in the third direction, and the plurality of fourth sub-grid strips are spaced apart in the second direction, wherein the first direction, the second direction and the third direction intersect each other.

4. The semiconductor structure according to claim 3, wherein, The third grid bar includes a fifth sub-grid bar and a sixth sub-grid bar. The fifth sub-grid strip extends along the second direction and partially covers the third sub-grid strip; The sixth sub-grid strip extends along the third direction and partially covers the fourth sub-grid strip; and The plurality of fifth sub-grid strips are spaced apart in the third direction, and the plurality of sixth sub-grid strips are spaced apart in the second direction.

5. The semiconductor structure according to claim 1, wherein, The number of the first grid strip, the second grid strip, and the third grid strip are all equal.

6. The semiconductor structure according to claim 1, wherein, The second grid bar extends in the same direction as the first grid bar; The dimension of the second grid bar perpendicular to its extension direction is equal to the dimension of the first grid bar perpendicular to its extension direction; The dimension of the second grid bar in its extending direction is equal to the dimension of the first grid bar in its extending direction; and The distance between adjacent second bars is equal to the distance between adjacent first bars.

7. The semiconductor structure according to claim 1, wherein, The second grid bar has the same dimension perpendicular to its extension direction as the third grid bar.

8. The semiconductor structure according to claim 1, wherein, The dimensions of the second grid bar in its extension direction and the dimensions of the third grid bar in its extension direction are both 5 micrometers to 50 micrometers.

9. The semiconductor structure according to claim 1, wherein, In the direction intersecting the first direction, the size of the first region is equal to the size of the second region. The first region is the region where the third grid strip is located in the second mark alignment pattern, and the second region is a region in the second mark alignment pattern that is different from the first region.

10. The semiconductor structure according to claim 1, wherein, Both the first mark alignment pattern and the second mark alignment pattern include rotationally symmetric patterns.

11. The semiconductor structure according to claim 1, wherein, The distance between adjacent second grid bars is equal to the distance between adjacent third grid bars.

12. The semiconductor structure according to claim 1, wherein, Both the first mark alignment pattern and the second mark alignment pattern include overlapping mark alignment patterns based on optical diffraction.

13. The semiconductor structure according to claim 1, wherein, The first mark alignment pattern and the second mark alignment pattern are arranged opposite each other along the first direction.

14. The semiconductor structure according to any one of claims 1-13, wherein, The semiconductor structure further includes devices and cleavage paths located on one side of the semiconductor substrate along the first direction. Wherein, the cutting channel is located between adjacent devices; and The alignment mark structure is located in at least one of the device and the cutting channel.

15. The semiconductor structure according to claim 14, wherein, The second mark alignment pattern, in the direction intersecting the first direction, has a dimension d1, and the cutting path, in the direction perpendicular to its extension, has a dimension d2, which satisfies the following: 10% ≤ d1 / d2 ≤ 80%.

16. A method for measuring overlay error, comprising: A first dielectric layer and a second dielectric layer are sequentially formed on one side of a semiconductor substrate along a first direction, wherein the first dielectric layer includes a first mark alignment pattern, the first mark alignment pattern includes a first gate strip, the second dielectric layer includes a second mark alignment pattern, the second mark alignment pattern includes a second gate strip and a third gate strip covering a portion of the second gate strip, the second gate strip is the same as the first gate strip, and in a direction intersecting the first direction, the extension dimension of the second gate strip is greater than the extension dimension of the third gate strip; as well as The signal diffracted and reflected by the alignment pattern via the second mark is measured, and the overlay error is determined based on the signal.

17. The measurement method according to claim 16, wherein, Measuring the signals diffracted and reflected by the alignment pattern via the second mark, and determining the overlay error based on the signals, includes: The signal is determined by a single measurement, and the overlay error is determined based on the signal.

18. The measurement method according to claim 17, wherein, Determining the signal through a single measurement and determining the overlay error based on the signal includes: In one of the measurements, the light intensity of the first positive first-order diffracted light and the light intensity of the first negative first-order diffracted light diffracted and reflected by the second grating are obtained, as well as the light intensity of the second positive first-order diffracted light and the light intensity of the second negative first-order diffracted light diffracted and reflected by the second grating and the third grating. The light intensity of the first positive first-order diffracted light is combined with the light intensity of the second positive first-order diffracted light to form the final value of the positive first-order diffracted light intensity, and the light intensity of the first negative first-order diffracted light is combined with the light intensity of the second negative first-order diffracted light to form the final value of the negative first-order diffracted light intensity; and The overlay error is determined based on the difference between the light intensity of the final positive first-order diffracted light and the light intensity of the final negative first-order diffracted light.

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