Glass interposer stack substrate with passive element and semiconductor package structure

Abstract

The invention discloses a glass interposer stacked substrate with a passive component and a semiconductor packaging structure, and the glass interposer stacked substrate is characterized in that a conventional glass packaging substrate is divided into at least two independent glass sub-substrates; each sub-substrate comprises a glass core plate with a conductive through hole, two-side rewiring structures (including interlayer passive elements) and a metal bonding layer, and the glass core plate, the two-side rewiring structures and the metal bonding layer are stacked through metal bonding and filled with heat-conducting glue to form the multi-layer glass interposer substrate integrated with the passive elements. Therefore, through the design and parallel processing of the modularized sub-substrates, the problems of complex single-layer board multilayer metal interconnection process, low yield and insufficient capacitance density in the prior art are solved.

Description

Technical Field

[0001] This invention relates to the field of advanced semiconductor packaging, and in particular to a glass interposer stacked substrate with passive components and a semiconductor packaging structure. Background Technology

[0002] With the surge in computing power demands from AI and high-performance computing chips, traditional organic substrates, due to their poor thermal stability, high signal transmission loss, and low interconnect density, can no longer meet the requirements of advanced packaging. While glass substrates offer higher mechanical strength and dimensional stability, effectively suppressing chip warping under high thermal loads; their lower coefficient of thermal expansion, similar to silicon chips, reduces reliability issues caused by thermal stress; and their superior electrical properties help reduce signal transmission loss and power consumption, improving signal integrity under high-speed computation, thus supporting higher interconnect densities and enabling AI chips to achieve greater computing power, current glass substrate technology still faces many challenges: high-density chip integration technology for large-size glass substrates is not yet mature; multilayer board processes are difficult; multilayer wiring yields are low; and processing costs are high. In particular, the effective embedding of passive components such as resistors, capacitors, and inductors into glass substrates urgently needs to be addressed, with the embedding of high-density capacitors being especially challenging.

[0003] like Figure 1 The silicon adapter plate for the integrated capacitor shown fully utilizes the vertical space and thin-film technology advantages of the adapter plate, providing decoupling for the chip and effectively reducing the impedance and noise of the power distribution network. It is one of the key technologies for achieving high-performance 2.5D / 3D packaging. However, through-glass vias (TGVs) have significant disadvantages compared to through-silicon vias (TSVs): the positioning and dimensional accuracy of TGVs can currently only reach ±1 micrometer; the sidewall roughness is generally 0.1-0.2 micrometers, much larger than that of TSVs; and the perpendicularity is also poor. These factors make it challenging to fabricate high-density capacitors inside glass substrates. In addition, when using a planar metal-dielectric-metal MIM capacitor structure, the capacitance density is difficult to reach the hundreds or even thousands of nF / mm² required for practical applications due to limitations in area and process complexity. 2 These technological bottlenecks severely restrict the application and promotion of glass substrates in high-end packaging fields.

[0004] The information disclosed in this background section was already known to the inventors prior to the implementation of this application or was acquired during the implementation of this disclosure. Therefore, it may contain information that does not constitute prior art known to the public. Summary of the Invention

[0005] To address the aforementioned issues, this invention provides a glass interposer stacked substrate with passive components and a semiconductor package. Through modular sub-substrate design and parallel processing, it solves the problems of complex multilayer processes, low yield, and insufficient capacitance density in the prior art.

[0006] According to one or more embodiments, a glass interposer stack substrate is provided, comprising: At least two glass sub-substrates disposed along the stacking direction, each glass sub-substrate comprising: A glass core board having a through-hole in the glass, wherein the through-hole is filled with a conductive material to form a conductive through-hole; Two redistribution structures are formed on opposite sides of the glass core plate in a one-to-one correspondence and are electrically interconnected through the conductive vias; each redistribution structure has at least two redistribution layers; at least one redistribution structure has a passive component layer, which is included in at least one redistribution layer of the redistribution structure or between two adjacent redistribution layers and is electrically connected to the redistribution layer. A metal bonding layer is disposed on the side of each redistribution structure opposite to the glass core board and is electrically connected to the redistribution structure; Along the stacking direction, any two adjacent glass sub-substrates are stacked and bonded through the metal bonding layer, and the bonding gap between the two adjacent glass sub-substrates is filled with thermally conductive adhesive to form a multilayer glass interposer stacked substrate.

[0007] According to a glass interposer stacked substrate of the present invention, a traditional glass packaging substrate is split into at least two independent glass sub-substrates. Each sub-substrate includes a glass core plate with conductive vias, redistribution structures on both sides (containing interlayer passive components), and a metal bonding layer. By stacking the metal bonding layers and filling with thermally conductive adhesive, a multilayer glass interposer substrate integrating passive components is formed. Thus, parallel processing of the sub-substrates reduces the difficulty of multilayer wiring, improves yield, and reduces processing time. High-density integration is achieved through multilayer sub-substrate stacking. The multilayer accumulation of interlayer passive components (such as MIM capacitors) can achieve a capacitance density of several hundred nF / mm². 2 It can integrate high-density capacitors to meet the computing power requirements of AI chips; thermally conductive adhesive is filled between adjacent sub-substrates for good heat dissipation; and the overall stress is low.

[0008] In addition, the glass interposer stacked substrate proposed according to the present invention may also have the following additional technical features: Optionally, the passive component layer consists of multiple passive components arranged in a spaced array on the same horizontal plane.

[0009] Furthermore, the passive component is a capacitor, resistor, or inductor; the capacitor is a MIM capacitor formed by electrode plate-insulating layer-electrode plate.

[0010] Furthermore, the redistribution layer includes a dielectric layer, a metal wiring layer, and a plurality of vias; the vias electrically connect the metal wiring layers of two adjacent redistribution layers, the passive component layer is included in the dielectric layer, and the passive component is electrically connected to the metal wiring layer and the vias.

[0011] Optionally, the metal bonding layer consists of a plurality of protrusions spaced apart on the side of the redistribution structure opposite to the glass core.

[0012] Furthermore, the bumps on one of the redistribution structures of the glass sub-substrate are solder balls or gold balls, and the bumps on the other redistribution structure are copper pillars.

[0013] Optionally, the glass cores of at least two of the glass sub-substrates may be made of different glass materials. Thus, different glass substrates can be used for the sub-substrates to meet requirements such as overall stress, warpage, transmission loss, and processing capability.

[0014] Optionally, the thickness of the glass core plate is ≥50 μm.

[0015] According to another aspect of one or more embodiments, a method for fabricating a glass interposer stacked substrate is provided, comprising the following steps: Provide glass core boards with conductive through holes; A redistribution structure is provided on each of the opposite sides of the glass core plate, and a passive component layer is provided in at least one of the redistribution structures; each redistribution structure has at least two redistribution layers; the passive component layer is provided in at least one redistribution layer of the redistribution structure or between two adjacent redistribution layers. A metal bonding layer is provided on the side of each redistribution structure opposite to the glass core, and the wafer is cut to form multiple glass sub-substrates; The plurality of glass sub-substrates are sequentially stacked and bonded along the stacking direction using the metal bonding layer, and thermally conductive adhesive is filled into the bonding gap between two adjacent glass sub-substrates to form a multilayer glass interposer stacked substrate.

[0016] According to a method for fabricating a glass interposer stacked substrate of the present invention, by fabricating a redistribution structure, a passive component layer, and a metal bonding layer on a large-size glass wafer, and then cutting it into multiple glass sub-substrates, the large-scale mass production of sub-substrates can be achieved. After cutting into multiple glass sub-substrates, each sub-substrate can be independently inspected, and qualified sub-substrates can be selected for subsequent stacking. Process defects in a single sub-substrate only cause that sub-substrate to be scrapped, avoiding the failure of the entire wafer due to local defects in traditional monolithic substrates, thus improving yield. The three-dimensional integration of passive components and the wiring layer does not require additional space on the substrate surface. By stacking multiple glass sub-substrates, the density of passive components can be multiplied through multi-layer accumulation, meeting the demand of AI chips for high-density passive components. Thermally conductive adhesive can eliminate air gaps at the bonding interface, forming a vertical heat dissipation channel from the chip to the substrate, resulting in good heat dissipation.

[0017] In addition, the method for manufacturing a glass interposer stacked substrate according to the present invention may also have the following additional technical features: Optionally, the redistribution structure includes providing a dielectric layer, a metal wiring layer, and a plurality of vias, and the provision of a passive component layer includes providing the passive component layer in the dielectric layer.

[0018] Furthermore, the passive component layer consists of multiple passive components arranged in a spaced array on the same horizontal plane, and each passive component is connected to the metal wiring layer and the multiple vias.

[0019] Furthermore, the passive component is a capacitor, resistor, or inductor; the capacitor is a MIM capacitor formed by electrode plate-insulating layer-electrode plate.

[0020] Optionally, the metal bonding layer includes a plurality of spaced-apart bumps electrically connected to the redistribution structure on the side of the redistribution structure opposite to the glass core.

[0021] Optionally, providing a glass core plate with conductive vias includes providing glass core plates made of at least two different glass materials, and forming the conductive vias on each of the glass core plates; Furthermore, each glass core board having the conductive vias is provided with the redistribution structure, the passive component layer, and the metal bonding layer, and each wafer is cut to form at least two types of glass sub-substrates; The at least two types of glass sub-substrates are stacked and bonded using the metal bonding layer, and thermally conductive adhesive is filled into the bonding gaps between adjacent glass sub-substrates to form a multilayer glass interposer stacked substrate. In this way, different glass substrates can be used for the sub-substrates to meet requirements such as overall stress, warpage, transmission loss, and processing capabilities.

[0022] Optionally, providing a glass core plate with conductive vias includes providing at least two glass core plates and forming the conductive vias on each of the glass core plates; Furthermore, each of the glass core boards having the conductive vias is provided with the redistribution structure, the passive component layer, and the metal bonding layer, wherein the dielectric layer of the redistribution structure of at least two of the glass core boards is made of different materials, and each wafer is cut to form at least two types of glass sub-substrates; The at least two types of glass sub-substrates are stacked and bonded using the metal bonding layer, and thermally conductive adhesive is filled into the bonding gaps between adjacent glass sub-substrates to form a multilayer glass interposer stacked substrate. In this way, the redistribution structures of different sub-substrates can use different dielectric layer materials to adapt to requirements such as overall stress, warpage, transmission loss, and processing capability.

[0023] According to another aspect of one or more embodiments, a semiconductor packaging structure is provided, including the glass interposer stacked substrate described above, or the glass interposer stacked substrate prepared by the fabrication method described above. A semiconductor chip is flip-chip mounted on the glass interposer stack substrate and electrically connected to the metal bonding layer of the uppermost glass sub-substrate; and Bottom filler adhesive is used to fill the space between the semiconductor chip and the glass sub-substrate.

[0024] Optionally, the semiconductor chip includes a high-bandwidth memory (HBM) and a graphics processing unit (GPU) chip, both of which are flip-chip mounted on the uppermost glass sub-substrate; the side of the glass interposer stack substrate facing away from the semiconductor chip is connected to a PCB board to achieve electrical interconnection with external circuits. Attached Figure Description

[0025] Figure 1 This is a cross-sectional view of a silicon interposer substrate in related technologies; Figure 2 This is a schematic flowchart of a method for fabricating a glass interposer stacked substrate according to an embodiment of the present invention. Figures 3-13 This is a cross-sectional schematic diagram of the substrate for each step of the method for manufacturing a glass interposer stacked substrate according to an embodiment of the present invention. Figure 14 This is a cross-sectional schematic diagram of the semiconductor packaging structure according to an embodiment of the present invention; Figure 15 A comparison of the warpage of the glass interposer stacked substrate in an embodiment of the present invention with that of a conventional multilayer board. Figure 16 This is a warpage map of the glass interposer stacked substrate according to an embodiment of the present invention. Warpage: 93 μm; Figure 17 Warpage: 122 μm, representing the warp contour of a traditional multilayer board.

[0026] Label Explanation: Glass interlayer stacked substrate 1; Glass sub-substrate 10, glass core plate 100, first side 100a, second side 100b, conductive via 110, redistribution structure 200, first redistribution structure 200a, first redistribution layer 210a, first dielectric layer 211a, first metal wiring layer 212a, first via 213a, second redistribution structure 200b, second redistribution layer 210b, second dielectric layer 211b, second metal wiring layer 212b, second via 213b, passive component layer 300, metal bonding layer 400, first metal bonding layer 400a, second metal bonding layer 400b; Thermal adhesive 20; High-bandwidth memory HBM 2; Graphics processing unit (GPU) chip 3. Detailed Implementation

[0027] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0028] To better understand the above technical solutions, exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the invention to those skilled in the art.

[0029] In this paper, the direction parallel to the main surface of the glass core plate 100 can be referred to as the horizontal direction (X direction), and the direction perpendicular to both the horizontal direction (X direction) and the main surface of the glass core plate 100 can be referred to as the vertical direction (Z direction), which is also the stacking direction.

[0030] According to one or more embodiments, a glass interposer stacked substrate provides a method for dividing a multilayer glass substrate into at least two independent glass sub-substrates. Each sub-substrate includes a glass core with conductive vias, redistribution structures on both sides (containing interlayer passive components), and a metal bonding layer. The sub-substrates are stacked using metal bonding and filled with thermally conductive adhesive to form a multilayer glass interposer substrate integrating passive components. This allows for parallel processing of the sub-substrates, reducing the difficulty of multilayer wiring, improving yield, and reducing processing time. High-density integration is achieved through the stacking of multiple sub-substrates. The multilayer accumulation of interlayer passive components (such as MIM capacitors) can achieve a capacitance density of several hundred nF / mm². 2 It can integrate high-density capacitors to meet the computing power requirements of AI chips; thermally conductive adhesive is filled between adjacent sub-substrates for good heat dissipation; and the overall stress is low.

[0031] Figure 13 A glass interposer stack substrate according to one or more embodiments is shown.

[0032] refer to Figure 13 The glass interposer stacked substrate 1 includes at least two glass sub-substrates 10 disposed along the stacking direction. Each glass sub-substrate 10 includes a glass core 100, two redistribution structures 200, a passive component layer 300, a metal bonding layer 400, and a thermally conductive adhesive 20.

[0033] The glass core board 100 has a through-hole 110; that is, the glass core board 100 has a through-hole 110 that vertically penetrates the glass core board 100. Using glass as the core board offers advantages in power integrity, allowing for improved power distribution network design and signal integration, especially at relatively high frequencies. Furthermore, glass enables larger panel-level packaging, making parallel processing of each glass sub-substrate 10 possible, thus reducing processing time and manufacturing costs.

[0034] Conductive vias 110 may be provided between two redistribution structures 200, providing an electrical connection path between the two redistribution structures 200. There may be one or more conductive vias 110, each containing a conductive material, which may be copper, aluminum, silver, gold, molybdenum, titanium, or a combination thereof. Conductive vias 110 may have upper and lower surfaces spaced apart from each other in a vertical direction. The upper surface of the conductive via 110 may be coplanar with a first side 100a of the glass core board 100, and the lower surface of the conductive via 110 may be coplanar with a second side 100b of the glass core board 100. The upper surface of the conductive via 110 may be connected to the redistribution structure 200a of the first side 100a, and the lower surface of the conductive via 110 may be connected to the redistribution structure 200b of the second side 100b.

[0035] Additionally, each conductive via 110 can have any suitable shape, including, for example, a cylindrical shape. In one or more other embodiments, each conductive via 110 can have a vertically symmetrical tapered shape.

[0036] Two redistribution structures 200 are formed one-to-one on opposite sides of the glass core board 100 (i.e., the first side 100a and the second side 100b) and electrically interconnected through conductive vias 110. Each redistribution structure 200 has at least two redistribution layers (e.g., 210a or 210b). At least one redistribution structure 200 has a passive component layer 300, which is included in at least one redistribution layer (e.g., 210a or 210b) of the redistribution structure 200 or between two adjacent redistribution layers (e.g., 210a or 210b) and electrically connected to the redistribution layer (e.g., 210a or 210b). The redistribution structure on the first side 100a of the glass core board 100 can be defined as the first redistribution structure 200a; the redistribution structure on the second side 100b of the glass core board 100 can be defined as the second redistribution structure 200b.

[0037] The first redistribution structure 200a includes at least two first redistribution layers 210a. A passive component layer 300 may be included in at least one first redistribution layer 210a or between two adjacent first redistribution layers 210a, and is electrically connected to the first redistribution layer 210a; for example... Figure 2 In this configuration, the passive component layer 300 is included in the uppermost first redistribution layer 210a of the first redistribution structure 200. In one or more other embodiments, the passive component layer 300 may also be included in the first redistribution layer 210a of other layers in the first redistribution structure 200, or between two adjacent first redistribution layers 210a.

[0038] Each first redistribution layer 210a may include a first dielectric layer 211a, a first metal wiring layer 212a, and a plurality of first vias 213a; each first via 213a is electrically connected to the first metal wiring layer 212a of two adjacent first redistribution layers 210a, and the first metal wiring layer 212a and the first via 213a may be included in or surrounded in the first dielectric layer 211a; the passive component layer 300 is included in the first dielectric layer 211a, and the passive components are electrically connected to the first metal wiring layer 212a and the first via 213a.

[0039] The first dielectric layer 211a may be stacked in the vertical direction. The first dielectric layer 211a may include an insulating material, such as a photosensitive imaging dielectric resin prepared by combining an epoxy resin and a photoinitiator, and may further include photosensitive polyimide and / or inorganic fillers, but is not limited thereto. The first metal wiring layer 212a and the first via 213a may be provided as conductive patterns, and the conductive patterns may be positioned within the first dielectric layer 211a. The first metal wiring layer 212a may be provided to extend horizontally within the first dielectric layer 211a. The first via 213a may penetrate one or more of the first dielectric layers 211a in the vertical direction, thereby contacting and electrically connecting with some wiring patterns in the first metal wiring layer 212a. The first metal wiring layer 212a has a metal linewidth or spacing ≥ 5 μm and a metal thickness ≥ 5 μm. According to some specific embodiments, the first via 213a may have any suitable shape, including, for example, a tapered or cylindrical shape. The first metal wiring layer 212a and the first via 213a are made of conductive metals, such as copper, aluminum, titanium, tantalum, molybdenum and their alloys, but are not limited thereto.

[0040] The passive component layer 300 may include multiple passive components arranged in a spaced array on the same horizontal plane. For example... Figure 2 As shown, the uppermost redistribution layer 210a of the first redistribution structure 200a includes a passive component layer 300. This passive component layer 300 consists of multiple passive components arranged in a spaced array between the first metal wiring layer 212a and the first vias 213a of the first redistribution layer 210a, with each passive component 310 corresponding to each first via 213a. The upper surfaces of the multiple passive components are coplanar with the lower surfaces of the first metal wiring layer 212a, and the lower surfaces of the multiple passive components are coplanar with the upper surfaces of the multiple first vias 213a; thus, multiple passive components on the same horizontal plane constitute a passive component layer 300. This direct integration of passive components into the redistribution structure avoids additional assembly processes, improving integration density and reliability. This integration method is particularly suitable for packaging applications of AI chips and high-performance computing chips that require high-density decoupling capacitors.

[0041] In one or more embodiments, the passive component can be a capacitor, resistor, or inductor; wherein the capacitor can be a MIM capacitor formed by an electrode plate-insulating layer-electrode plate. Thus, the capacitance density of a single-layer passive component layer 300 can reach tens of nF / mm². 2 The capacitance density of the stacked substrate 1, achieved through multiple layers of stacked glass interlayers, can reach the required several hundred nF / mm². 2 In one or more embodiments, the electrode plate material of the MIM capacitor may be a conductive metal such as aluminum, copper or titanium, and the insulating layer material may be silicon dioxide, silicon nitride or a high dielectric constant material.

[0042] The second redistribution structure 200b includes at least two layers of second redistribution layers 210b. Each layer of the second redistribution layer 210b may include a second dielectric layer 211b, a second metal wiring layer 212b, and a plurality of second vias 213b; each second via 213b electrically connects to the second metal wiring layers 212b of two adjacent second redistribution layers 210b, and the second metal wiring layers 212b and the second vias 213b may be included in or surrounded in the second dielectric layer 211b. The second dielectric layers 211b may be stacked in a vertical direction. The second dielectric layers 211b may include an insulating material, such as a photosensitive imaging dielectric resin prepared by combining epoxy resin and a photoinitiator, and may further include photosensitive polyimide and / or inorganic fillers, but are not limited thereto. The second metal wiring layers 212b and the second vias 213b may be provided as conductive patterns, and the conductive patterns may be positioned in the second dielectric layer 211b. The second metal wiring layer 212b may be provided to extend in a horizontal direction in the second dielectric layer 211b. The second via 213b can penetrate one or more second dielectric layers 211b in the vertical direction, thereby contacting and electrically connecting with some wiring patterns in the second metal wiring layer 212b. The metal linewidth or spacing of the second metal wiring layer 212b is ≥5 μm, and the metal thickness is ≥5 μm. According to some specific embodiments, the second via 213b can have any suitable shape, including, for example, a tapered or cylindrical shape. The second metal wiring layer 212b and the second via 213b are made of conductive metals, such as copper, aluminum, titanium, tantalum, molybdenum, and their alloys, but are not limited thereto.

[0043] A metal bonding layer 400 is disposed on the side of each redistribution structure 200 facing away from the glass core plate 100 and is electrically connected to the redistribution structure 200. Along the stacking direction, any two adjacent glass sub-substrates 10 are stacked and bonded through the metal bonding layer 400. That is, a metal bonding layer is disposed on the lower surface (the side facing away from the glass core plate 100) of the first redistribution structure 200a, which can be defined as the first metal bonding layer 400a; a metal bonding layer is also disposed on the upper surface (the side facing away from the glass core plate 100) of the second redistribution structure 200b, which can be defined as the second metal bonding layer 400b. Thus, the stacking of multiple glass sub-substrates 10 can be achieved by bonding two vertically opposite first metal bonding layers 400a and second metal bonding layers 400b. In one or more embodiments, the metal bonding layer 400 consists of a plurality of protrusions spaced apart on the side of the redistribution structure 200 facing away from the glass core plate 100.

[0044] Specifically, the bumps, as a concrete implementation of the metal bonding layer 400, can adopt spherical or columnar structures. Spherical bumps include, but are not limited to, reflowable solderable materials such as solder balls and gold balls; columnar bumps are preferably copper column structures, and their height can be precisely controlled through electroplating. The spacing of the bump array must meet the alignment accuracy requirements when adjacent glass sub-substrates 10 are stacked. The electrical connection between the bumps and the redistribution structure is achieved as follows: a bump under-metal (UBM) layer is fabricated on the outermost metal wiring layer of the redistribution structure, followed by the formation of the bump structure through ball placement or electroplating. Furthermore, the bump height needs to be controlled within the range of 50-250 μm to ensure that the bonding gaps are fully filled during stacking and bonding without causing structural deformation.

[0045] Thus, the staggered arrangement of bumps effectively releases the thermal stress generated during stacking, avoiding interface delamination caused by differences in thermal expansion coefficients. Secondly, the bump structure can compensate for flatness errors between substrates through plastic deformation during bonding, improving bonding yield. In addition, the air gaps formed by the bump array facilitate the full filling of thermally conductive adhesive, thereby improving the overall heat dissipation performance. Compared to traditional monolithic glass substrates that require the processing of multiple redistribution layers in a single step, this embodiment utilizes the bonding of the metal bonding layer 400 to significantly reduce the process difficulty of multi-layer stacking while ensuring electrical interconnect reliability.

[0046] In one or more specific embodiments, the bumps on one of the redistribution structures 200 of the glass sub-substrate 10 are solder balls or gold balls, and the bumps on the other redistribution structure 200 are copper pillars. For example, the bumps on the first redistribution structure 200a are copper pillars, and the bumps on the second redistribution structure 200b are solder balls or gold balls.

[0047] Specifically, when solder balls or gold balls are used as bump materials, their low melting points allow for interconnection of the metal bonding layers 400 during the bonding process via thermoforming or reflow soldering. When copper pillars are used as bump materials, their high mechanical strength and excellent conductivity enable them to withstand mechanical stress during the stacking process and ensure the quality of electrical signal transmission. The combination of these two bump materials allows for differentiated bonding: solder balls or gold balls provide good wettability and interfacial bonding, while copper pillars provide structural support and current carrying capacity. As a preferred embodiment, the diameter of the solder balls can be controlled between 50-200 μm, the diameter of the gold balls between 50-100 μm, and the height of the copper pillars between 50-150 μm, with the diameter matching that of the solder / gold balls.

[0048] The thickness of the glass sub-substrate 10 thus formed can be ≥150 μm. The thickness of the glass sub-substrate 10 is set to 150 μm or more primarily based on the following considerations: In multilayer glass interposer stacked structures, excessively thin sub-substrates are insufficient in terms of mechanical strength, thermal stability, and processing yield. Insufficient thickness may cause warping or cracking of the substrate during high-temperature bonding, affecting stacking accuracy and reliability.

[0049] The bonding gaps between two adjacent glass sub-substrates 10 are filled with thermally conductive adhesive 20 to form a multilayer glass interposer stack substrate 1. That is, after the multilayer glass sub-substrates 10 are stacked and bonded, thermally conductive adhesive 20 can be filled into the bonding gaps between every two adjacent glass sub-substrates 10. The thermally conductive adhesive 20 is provided to be adjacent to and surrounding each bonding bump of the metal bonding layer 400. The thermally conductive adhesive 20 can be a high thermal conductivity filler, such as St 8202 thermally conductive adhesive. The total thickness of the bonded glass interposer stack substrate 1 is ≤1.4 mm.

[0050] Furthermore, in one or more embodiments, the glass core plates 100 of at least two glass sub-substrates 10 are made of different glass materials. Specifically, the glass material of the glass core plate 100 can be selected from at least two of borosilicate glass, aluminosilicate glass, quartz glass, or soda-lime glass. For example, the upper glass sub-substrate 10 can use borosilicate glass with a lower coefficient of thermal expansion to improve dimensional stability, while the lower glass sub-substrate 10 can use aluminosilicate glass with higher mechanical strength to enhance structural support. Thus, by using a combination of different glass materials, the performance of each glass sub-substrate 10 can be optimized in a targeted manner: glass combinations with different coefficients of thermal expansion can alleviate interlayer thermal stress, glass materials with different dielectric constants can achieve impedance matching of the signal transmission layer, and glass combinations with complementary mechanical properties can simultaneously meet the requirements of structural strength and thinness. This can solve the overall performance bottleneck problem caused by the performance limitations of a single glass material in multilayer stacked structures, and has a better comprehensive performance adaptability compared to traditional single-material solutions. Therefore, based on the thermo-mechanical-electrical simulation of the overall structure, different glass substrates can be used for the glass sub-substrate 10 to meet the requirements of overall stress, warpage, transmission loss, and processing capability.

[0051] It should be noted that the number of redistribution layers of the redistribution structure 200 in each glass sub-substrate 10 of the glass interposer stacked substrate 1 can be customized as needed to satisfy the following: the first redistribution structure 200a includes at least two first redistribution layers 210a, and the second redistribution structure 200b includes at least two second redistribution layers 210b; and the number of redistribution layers of the redistribution structure 200 in different glass sub-substrates 10 of the glass interposer stacked substrate 1 can be the same or different. For example, the glass interposer stacked substrate 1 has three glass sub-substrates 10: upper, middle, and lower. The upper glass sub-substrate 10 has a first redistribution structure 200a with two first redistribution layers 210a and a second redistribution structure 200b with three second redistribution layers 210b. Alternatively, the first redistribution structure 200a may have three first redistribution layers 210a, and the second redistribution structure 200b may have two second redistribution layers 210b. Or, the first redistribution structure 200a may have three first redistribution layers 210a, and the second redistribution structure 200b may have three second redistribution layers 210b. Similarly, the number of redistribution layers in the redistribution structure 200 of the middle glass sub-substrate 10 may be the same as or different from that of the upper glass sub-substrate 10. Likewise, the number of redistribution layers in the redistribution structure 200 of the lower glass sub-substrate 10 may be the same as or different from that of the upper glass sub-substrate 10 and / or the lower glass sub-substrate 10. Preferably, the number of redistribution layers in each redistribution structure 200 does not exceed four.

[0052] In one or more embodiments, the dielectric layers in the redistribution structures 200 of different glass sub-substrates 10 from top to bottom may also use different dielectric materials to meet requirements such as overall stress, warpage, and transmission loss.

[0053] Figure 2 A schematic flowchart illustrating a method for fabricating a glass interposer stacked substrate according to one or more embodiments is shown.

[0054] Please refer to Figure 2 This application proposes a method for fabricating a glass interposer stacked substrate, comprising the following steps: S1: Provides a glass core board with conductive through holes; S2: A redistribution structure is provided on each of the opposite sides of the glass core plate and a passive component layer is provided in at least one of the redistribution structures; each redistribution structure has at least two redistribution layers; the passive component layer is provided in at least one redistribution layer of the redistribution structure or between two adjacent redistribution layers; S3: Provide a metal bonding layer on the side of each redistribution structure away from the glass core board, and cut the wafer to form multiple glass sub-substrates; S4: The plurality of glass sub-substrates are sequentially stacked and bonded along the stacking direction using the metal bonding layer, and thermally conductive adhesive is filled into the bonding gap between two adjacent glass sub-substrates to form a multilayer glass interposer stacked substrate.

[0055] In other words, this method enables large-scale mass production of sub-substrates by fabricating redistribution structures, passive component layers, and metal bonding layers on large-size glass wafers, and then cutting them into multiple glass sub-substrates. After cutting into multiple glass sub-substrates, each sub-substrate can be independently inspected to select qualified sub-substrates for subsequent stacking. Process defects in a single sub-substrate only result in the scrapping of that sub-substrate, avoiding the failure of the entire wafer due to local defects in traditional monolithic substrates, thus improving yield. The three-dimensional integration of passive components and wiring layers does not require additional space on the substrate surface. By stacking multiple glass sub-substrates, the density of passive components can be multiplied through multi-layer accumulation, meeting the high-density passive component requirements of AI chips. Thermally conductive adhesive can eliminate air gaps at the bonding interface, forming a vertical heat dissipation channel from the chip to the substrate, resulting in good heat dissipation.

[0056] Figures 3-13 This is a schematic cross-sectional view of a substrate illustrating the steps of a method for fabricating a glass interposer stacked substrate according to one or more embodiments. For brevity, descriptions overlapping with the previous figures will be omitted, and the differences will be primarily described. The glass core 100, redistribution structure 200, passive component layer 300, and metal bonding layer 400 manufactured in the method described below can be or correspond to Figure 13 The glass core 100, redistribution structure 200, passive component layer 300, and metal bonding layer 400 shown herein, and therefore, can be used hereinafter. Figure 13 The same reference numerals are shown in the figures.

[0057] refer to Figure 3 First, a glass core board 100 is provided. The thickness of the glass core board 100 is ≥50 μm. Glass is used as the substrate material of the substrate, and its thickness affects the thickness of the overall substrate. The thinnest glass core board 100 can be 50 μm. Then, the glass core board 100 is surface cleaned.

[0058] refer to Figure 4The glass core plate 100 is subjected to laser-induced wet etching to obtain TGV holes. Laser induction involves using a pulsed laser to create continuous modified regions on the glass. Compared to unmodified glass, modified glass has a faster etching rate in hydrofluoric acid or alkaline systems. Based on this phenomenon, through-holes, blind holes, or through-grooves and blind grooves can be fabricated on the glass. Specifically, one of nanosecond lasers, picosecond lasers, or femtosecond lasers is first used to create modified regions on the glass, and then the laser-treated glass is immersed in a hydrofluoric acid solution or alkaline solution for etching, resulting in highly uniform glass through-holes and blind holes. Subsequently, metal material is filled into the TGV holes to form conductive through-holes 110. The metal material can include conductive materials, such as copper, aluminum, silver, gold, molybdenum, titanium, and combinations thereof. The upper surface of the conductive through-hole 110 can be coplanar with the upper surface of the glass core plate 100. Specifically, a seed layer can be sputtered by PVD, followed by a conductive layer electroplated with metal, and finally CMP surface treatment. In this embodiment, the conductive via 110 is fabricated by first forming a blind via, then forming a metal material within the blind via, and finally fabricating a single-sided redistribution structure. In other embodiments, the conductive via 110 can also be directly fabricated as a through-hole penetrating the first side 100a and the second side 100b of the glass core plate 100, then forming a metal material within the through-hole, and finally fabricating a double-sided redistribution structure simultaneously.

[0059] refer to Figure 5 A first metal wiring layer 212a may be provided on a first side 100a of the glass core plate 100 and cover a surface of the conductive via 110, thereby making the two electrically connected.

[0060] refer to Figure 6 A passive component layer 300, such as a MIM capacitor, can be provided on the first metal wiring layer 212a described above. The electrode plate below the MIM capacitor is in contact with the first metal wiring layer 212a. Specifically, the MIM capacitor can be fabricated by physical vapor deposition (PVD) or chemical mechanical polishing (CMP) processes to create flat electrodes, and by using plasma-enhanced chemical vapor deposition (PECVD) and deep reactive ion etching (DRIE) processes to create a high-precision insulating layer. More specifically, the upper and lower electrode materials of the MIM capacitor can be aluminum + aluminum or aluminum + copper. The aluminum substrate is fabricated using physical vapor deposition (PVD) and deep reactive ion etching (DRIE) processes; the copper substrate is fabricated using photolithography + electroplating + CMP methods; the dielectric layer material is silicon nitride, and a high-precision insulating layer is created using plasma-enhanced chemical vapor deposition (PECVD) and deep reactive ion etching (DRIE) processes. The size range of the MIM capacitor is: 50 μm × 50 μm × 3 μm to 500 μm × 500 μm × 5 μm.

[0061] Preferably, the lower aluminum electrode is first deposited over the entire surface using physical vapor deposition (PVD), followed by the deposition of a silicon nitride (SIN) dielectric layer using plasma-enhanced chemical vapor deposition (PECVD) and then the deposition of an upper aluminum electrode using physical vapor deposition (PVD). Subsequently, the corresponding morphologies of the lower electrode, dielectric layer, and upper electrode are sequentially etched using photolithography and deep reactive ion etching (DRIE) processes to complete the fabrication of the MIM capacitor.

[0062] refer to Figure 7 The first dielectric layer 211a can be laminated on the first side 100a of the glass core board 100, the first metal wiring layer 212a, and the passive component layer 300. Then, a first via 213a is formed in the first dielectric layer 211a. One or more first vias 213a can penetrate one or more first dielectric layers 211a and contact the upper electrode plate of the MIM capacitor. Then, one or more multilayer films (first dielectric layers) are laminated on the upper surface of the first dielectric layer 211a, and the first metal wiring layer 212a and the first via 213a of each first redistribution layer 210a are fabricated accordingly to complete the fabrication of the first redistribution structure 200a. The first dielectric layer 211a can be a wet film, a dry film, or a non-photosensitive material. The wet film uses a coating, baking, exposure, and development process; the dry film uses a roller or vacuum lamination, baking, exposure, and development process; and the non-photosensitive material uses a roller or vacuum lamination, baking, and laser drilling process.

[0063] Subsequently, a first metal bonding layer 400a is fabricated on the outer surface of the first redistribution layer 210a, the outermost layer of the first redistribution structure 200a. The fabrication of the first metal bonding layer 400a can involve forming a passivation layer, a metal under bump (UBM) layer, and a conductive layer on the first redistribution layer 210a, followed by forming bumps, such as solder balls or gold balls, on the conductive layer.

[0064] refer to Figure 8 Next, a temporary bonding adhesive is applied to the temporary carrier and baked to temporarily bond it to the first metal bonding layer 400a of the glass core board 100, so as to temporarily protect the first metal bonding layer 400a, the first rewiring structure 200a and the passive component layer 300 on that side.

[0065] refer to Figure 9 Then, the glass core plate 100 with the temporary carrier plate is flipped over, and the back side of the glass core plate 100 is thinned to expose the conductive through hole 110.

[0066] Next, refer to Figure 10A second redistribution structure 200b is fabricated on the second side 100b of the glass core board 100. Specifically, a second metal wiring layer 212b is first provided on the second side 100b of the glass core board 100, covering one surface of the conductive via 110, thereby electrically connecting the two. Then, a second dielectric layer 211b is laminated onto the second side 100b of the glass core board 100 and the second metal wiring layer 212b, and a second via 213b is formed in the second dielectric layer 211b. One or more second vias 213b can penetrate one or more second dielectric layers 211b and contact the second metal wiring layer 212b. Then, one or more laminated films (second dielectric layers) are laminated onto the upper surface of the second dielectric layer 211b, and correspondingly, the second metal wiring layer 212b and the second via 213b of each second redistribution layer 210b are fabricated to complete the fabrication of the second redistribution structure 200b. The second dielectric layer 211b can be made of wet film, dry film, or non-photosensitive material. The wet film is made of coating, baking, exposure, and development process. The dry film is made of roller or vacuum lamination, baking, exposure, and development process. The non-photosensitive material is made of roller or vacuum lamination, baking, and laser drilling process.

[0067] Then, a second metal bonding layer 400b is fabricated on the outer surface of the outermost second redistribution layer 210b of the second redistribution structure 200b. The fabrication of the second metal bonding layer 400b can be achieved by forming a passivation layer on the second redistribution layer 210b, followed by window electroplating to form bumps, such as copper pillars.

[0068] Then, refer to Figure 11 Laser debonding is used to remove the temporary carrier board, and then the wafer is cut to form multiple glass sub-substrates 10.

[0069] Next, refer to Figure 12 The first metal bonding layer 400a of one glass sub-substrate 10 and the second metal bonding layer 400b of another glass sub-substrate 10 are aligned and thermo-pressed together, and then stacked in multiple layers to form a stack. The thermo-pressing temperature is 250-300℃; the pressure is 5-10 MPa; and the time is 5-10 min. Furthermore, the number of stacked layers can be designed according to actual needs, such as capacitance density requirements.

[0070] Finally, refer to Figure 13 The bonding gaps between two adjacent glass sub-substrates 10 of the above-mentioned stack are filled with thermally conductive adhesive to form a multilayer glass interposer stack substrate 1. The thermally conductive adhesive can be applied by underfilling a measured amount of adhesive to the bottom edge of the sub-substrate. After the adhesive fills the entire gap between the sub-substrates under capillary action, it is thermally cured to solidify the adhesive and achieve functions such as bonding, support, and protection.

[0071] As can be seen from the above, the multiple glass sub-substrates 10 of the multilayer glass interposer stacked substrate 1 can be processed in parallel, shortening the process flow. Each glass sub-substrate 10 contains a glass core plate 100, which reduces the overall structural warpage, results in low glass dielectric loss, and provides excellent transmission performance. Adjacent glass sub-substrates 10 are aligned and bonded through a metal bonding layer 400, improving product yield. When the glass material used for the glass core plate 100 is the same, the warpage of the fabricated glass interposer stacked substrate 1 on the PCB is compared with the warpage of a traditional multilayer board (i.e., multiple RDLs are fabricated on a single glass core plate), as shown below. Figures 15-17 As shown, the overall warpage of the glass interposer stacked substrate 1 after being mounted in this embodiment is about 95 μm; the overall warpage of a conventional multilayer board after being mounted is about 122 μm. The warpage reduction of the glass interposer stacked substrate 1 in this embodiment is about 24%.

[0072] In one or more embodiments, each glass sub-substrate 10 of the multilayer glass interposer stacked substrate 1 can be made of different glass substrates; thus, when manufacturing each glass sub-substrate 10, glass core boards of different glass materials can be used to perform the above steps S1 to S3, thereby obtaining multiple glass sub-substrates 10 of various glass materials. Then, based on the thermo-mechanical-electrical simulation of the overall structure of the multilayer glass interposer stacked substrate 1, the selection and matching of each layer of glass sub-substrate 10 can be performed, and stacking and bonding can be carried out. The multilayer glass interposer stacked substrate 1 obtained in this way can meet the requirements of overall stress, warpage, transmission loss, processing capability, etc.

[0073] In one or more embodiments, the redistribution structure 200 of each glass sub-substrate 10 of the multilayer glass interposer stacked substrate 1 can be fabricated with dielectric layers made of different insulating materials. Thus, when fabricating each glass sub-substrate 10, multiple glass core boards of the same glass material can be used to perform the above-described steps S1 to S3. In the processing of S2, each glass core board 100 uses a different insulating material to fabricate the dielectric layer of the redistribution structure 200, thereby obtaining multiple glass sub-substrates 10 with various dielectric layer materials. Subsequently, based on the thermo-mechanical-electrical simulation of the overall structure of the multilayer glass interposer stacked substrate 1, the selection and matching of each glass sub-substrate 10 can be performed, and stacking and bonding can be carried out. The multilayer glass interposer stacked substrate 1 obtained in this way can meet the requirements of overall stress, warpage, transmission loss, processing capability, etc.

[0074] refer to Figure 14According to one or more embodiments of the present invention, a semiconductor packaging structure is also provided, comprising the aforementioned multilayer glass interposer stacked substrate 1 and a semiconductor chip. The semiconductor chip may include a high-bandwidth memory (HBM) 2 and a graphics processing unit (GPU) chip 3; both the HBM 2 and the GPU chip 3 are flip-chip mounted on the uppermost glass sub-substrate 10; the side of the glass interposer stacked substrate 1 facing away from the semiconductor chip is connected to a PCB board to achieve electrical interconnection with external circuits. However, the embodiments are not limited to this, and semiconductor chips other than SOCs or HBMs may be provided, such as logic chips: central processing units (CPUs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), or memory chips: dynamic random access memory (DRAM) chips and NAND chips.

[0075] The high-bandwidth memory HBM 2 is a stacked multilayer chip, with an underfill adhesive filling the space between adjacent chip layers. Additionally, an underfill adhesive is also filled between the high-bandwidth memory HBM 2 / GPU chip 3 and the multilayer glass interposer substrate 1. The underfill layer may include epoxy resin or a mixture of two or more silicon materials.

[0076] Therefore, this semiconductor packaging structure, utilizing the three-dimensional stacked structure of the aforementioned multilayer glass interposer substrate 1 and the integration of passive components between layers, achieves high-density heterogeneous integration and reduces package size. The passive component layers between layers (such as MIM capacitors) can replace external capacitors, providing near-chip decoupling for the GPU and HBM, reducing the number of external components in the package. The multilayered thermal conduction paths of the glass interposer substrate, combined with the thermal conduction assistance of the bottom filler adhesive, enable efficient heat dissipation and suppress heat buildup between the HBM and GPU. This solves the three core pain points in HBM-GPU interconnection: high bandwidth, high thermal management, and high-density integration, providing miniaturized and highly reliable semiconductor packaging for high-performance computing fields such as AI servers and high-end graphics cards.

[0077] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0078] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0079] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0080] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0081] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. The illustrative expressions of the above terms in this specification should not be construed as necessarily referring to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0082] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A glass interposer stacked substrate, characterized in that, include: At least two glass sub-substrates disposed along the stacking direction, each glass sub-substrate comprising: A glass core board having a through-hole in the glass, wherein the through-hole is filled with a conductive material to form a conductive through-hole; Two redistribution structures are formed on opposite sides of the glass core plate in a one-to-one correspondence and are electrically interconnected through the conductive vias; each redistribution structure has at least two redistribution layers; at least one redistribution structure has a passive component layer, which is included in at least one redistribution layer of the redistribution structure or between two adjacent redistribution layers and is electrically connected to the redistribution layer. A metal bonding layer is disposed on the side of each redistribution structure opposite to the glass core board and is electrically connected to the redistribution structure; Along the stacking direction, any two adjacent glass sub-substrates are stacked and bonded through the metal bonding layer, and the bonding gap between the two adjacent glass sub-substrates is filled with thermally conductive adhesive to form a multilayer glass interposer stacked substrate.

2. The glass interposer stacked substrate as described in claim 1, characterized in that, The passive component layer consists of multiple passive components arranged in a spaced array on the same horizontal plane.

3. The glass interposer stacked substrate as described in claim 2, characterized in that, The passive component is a capacitor, resistor, or inductor; the capacitor is a MIM capacitor formed by electrode plate-insulating layer-electrode plate.

4. The glass interposer stacked substrate as described in claim 2, characterized in that, The redistribution layer includes a dielectric layer, a metal wiring layer, and a plurality of vias; the vias electrically connect the metal wiring layers of two adjacent redistribution layers, the passive component layer is included in the dielectric layer, and the passive component is electrically connected to the metal wiring layer and the vias.

5. The glass interposer stacked substrate as described in claim 1, characterized in that, The metal bonding layer consists of multiple protrusions spaced apart on the side of the redistribution structure opposite to the glass core.

6. The glass interposer stacked substrate as described in claim 5, characterized in that, The bumps on one of the redistribution structures of the glass sub-substrate are solder balls or gold balls, and the bumps on the other redistribution structure are copper pillars.

7. The glass interposer stacked substrate as described in claim 1, characterized in that, The glass cores of at least two of the glass sub-substrates are made of different glass materials.

8. The glass interposer stacked substrate as described in claim 1, characterized in that, The thickness of the glass core plate is ≥50 μm.

9. A method for fabricating a glass interposer stacked substrate, characterized in that, Includes the following steps: Provide glass core boards with conductive through holes; A redistribution structure is provided on each of the opposite sides of the glass core plate, and a passive component layer is provided in at least one of the redistribution structures; each of the redistribution structures has at least two redistribution layers; The passive component layer is provided in at least one redistribution layer of the redistribution structure or between two adjacent redistribution layers; A metal bonding layer is provided on the side of each redistribution structure opposite to the glass core, and the wafer is cut to form multiple glass sub-substrates; The plurality of glass sub-substrates are sequentially stacked and bonded along the stacking direction using the metal bonding layer, and thermally conductive adhesive is filled into the bonding gap between two adjacent glass sub-substrates to form a multilayer glass interposer stacked substrate.

10. The method for fabricating a glass interposer stacked substrate as described in claim 9, characterized in that, The redistribution structure includes providing a dielectric layer, a metal wiring layer, and a plurality of vias, and the provision of a passive component layer includes providing the passive component layer in the dielectric layer.

11. The method for fabricating a glass interposer stacked substrate as described in claim 10, characterized in that, The passive component layer consists of multiple passive components arranged in a spaced array on the same horizontal plane, and each passive component is connected to the metal wiring layer and the multiple vias.

12. The method for fabricating a glass interposer stacked substrate as described in claim 11, characterized in that, The passive component is a capacitor, resistor, or inductor; the capacitor is a MIM capacitor formed by electrode plate-insulating layer-electrode plate.

13. The method for fabricating a glass interposer stacked substrate as described in claim 9, characterized in that, The metal bonding layer includes a plurality of spaced bumps that are electrically connected to the redistribution structure on the side of the redistribution structure opposite to the glass core.

14. The method for fabricating a glass interposer stacked substrate as described in claim 9, characterized in that, The provision of the glass core plate with conductive through holes includes providing glass core plates of at least two different glass materials, and forming the conductive through holes on each of the glass core plates; Furthermore, each glass core board having the conductive vias is provided with the redistribution structure, the passive component layer, and the metal bonding layer, and each wafer is cut to form at least two types of glass sub-substrates; The at least two types of glass sub-substrates are stacked and bonded using the metal bonding layer, and thermally conductive adhesive is filled into the bonding gap between two adjacent glass sub-substrates to form a multilayer glass interposer stacked substrate.

15. The method for fabricating a glass interposer stacked substrate as described in claim 9, characterized in that, Providing a glass core plate with conductive vias includes providing at least two glass core plates and forming the conductive vias on each of the glass core plates; Furthermore, each of the glass core boards having the conductive vias is provided with the redistribution structure, the passive component layer, and the metal bonding layer, wherein the dielectric layer of the redistribution structure of at least two of the glass core boards is made of different materials, and each wafer is cut to form at least two types of glass sub-substrates; The at least two types of glass sub-substrates are stacked and bonded using the metal bonding layer, and thermally conductive adhesive is filled into the bonding gap between two adjacent glass sub-substrates to form a multilayer glass interposer stacked substrate.

16. A semiconductor packaging structure, characterized in that, The glass interposer stacked substrate includes any one of claims 1-8, or a glass interposer stacked substrate prepared by any one of claims 9-15; A semiconductor chip is flip-chip mounted on the glass interposer stack substrate and electrically connected to the metal bonding layer of the uppermost glass sub-substrate. as well as Bottom filler adhesive is used to fill the space between the semiconductor chip and the glass sub-substrate.

17. The semiconductor packaging structure as described in claim 16, characterized in that, The semiconductor chip includes a high-bandwidth memory (HBM) and a graphics processing unit (GPU) chip, both of which are flip-chip mounted on the uppermost glass sub-substrate. The side of the glass interposer stack substrate facing away from the semiconductor chip is connected to the PCB board to achieve electrical interconnection with external circuits.

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