Automatic clock rate synchronization for single wire radio frequency front end interface

Abstract

A clock generation apparatus includes: a counter configured to count transitions in a locally generated clock signal when a data signal is received from a single wire serial bus; a latch configured to capture an output of the counter and to provide a latched output representing a transition counted in a locally generated clock signal when a synchronization mode is received in the data signal; a trigger; and a comparator configured to drive the decision signal to a first signaling state when the output of the counter matches the latched output, and to drive the decision signal to a second signaling state when the output of the counter does not match the latched output. The flip-flop has an output that changes the signaling state in response to an edge in the decision signal. When the decision signal is driven to the first signaling state, the counter is reset.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to pending U.S. non-provisional application No. 18 / 449,554, filed August 14, 2023, which has been assigned to the assignee of this application and is expressly incorporated herein by reference, as fully set forth below and for all applicable purposes. Technical Field

[0003] This disclosure relates in general to serial communication, and more specifically to clock management in a device configured for single-wire communication via a radio frequency front-end interface. Background Technology

[0004] Mobile communication devices may include various components, including circuit boards, integrated circuit (IC) devices, and / or system-on-a-chip (SoC) devices. These components may include processing circuitry, user interface components, storage devices, and other peripheral components that communicate via a serial bus. The serial bus may operate according to standardized or proprietary protocols. In one example, a two-wire multipoint serial bus operates according to an inter-integrated circuit (I2C or I²C) protocol, which was developed to connect low-speed peripheral devices to a processor. The I2C bus provides a serial data line (SDA) carrying data signals and a serial clock line (SCL) carrying clock signals. In another example, the Improved Internal Integrated Circuit (I3C) protocol, defined by the Mobile Industry Processor Interface (MIPI) consortium, derives certain specific implementations from the I2C protocol, which includes separate clock and data lines. In yet another example, the Radio Frequency Front-End (RFFE) interface, defined by the MIPI consortium, provides a communication interface for controlling various radio frequency (RF) front-end devices, including power amplifiers (PAs), low-noise amplifiers (LNAs), antenna tuners, filters, sensors, power management devices, switches, etc. These devices may be cascaded in a single IC device or provided in multiple IC devices. In mobile communication devices, multiple antennas and radio transceivers can support multiple concurrent RF links. In another example, the System Power Management Interface (SPMI), defined by the MIPI Alliance, provides a hardware interface that can be implemented between the baseband or application processor and peripheral components, with purposes including power management within the device.

[0005] Increased device complexity and the growing need for associated general-purpose input / output (GPIO) pins have spurred the use of single-wire serial buses operating according to standards-compliant or compatible protocols. There is a continued need to increase reliability and throughput via single-wire serial buses, including those operating according to MIPI-defined protocols. Summary of the Invention

[0006] Certain aspects of this disclosure relate to systems, apparatuses, methods, and techniques for improving clock generation at a receiver coupled to a single-wire serial bus. In one example, the reliability of data acquisition can be enhanced when the transmitter clock rate is determined quickly and reliably by the receiver. In some implementations, aspects of control signaling and Manchester encoding can be used to initiate clock rate detection. The single-wire serial bus may operate according to protocols defined by RFFE, SPMI, or other standards.

[0007] In various aspects of this disclosure, a clock generation apparatus includes: a counter configured to count transitions in a locally generated clock signal when a data signal is received from a single-wire serial bus; a latch configured to capture the output of the counter and provide a latched output representing the transitions counted in the locally generated clock signal when a synchronization mode is received in the data signal; a flip-flop; and a comparator configured to drive the decision signal to a first signaling state when the output of the counter matches the latched output, and to drive the decision signal to a second signaling state when the output of the counter does not match the latched output. The flip-flop has an output that changes the signaling state in response to an edge in the decision signal. When the decision signal is driven to the first signaling state, the counter is reset.

[0008] In various aspects of this disclosure, an apparatus includes: components for counting transitions in a locally generated clock signal, the components including a counter configured to count the transitions when a data signal is received from a single-wire serial bus; components for capturing the output of the counter, the components including a latch configured to provide a latched output representing the transitions counted in the locally generated clock signal when a synchronization mode is received in the data signal; a trigger; and components for comparing the output of the counter with the latched output, the components including a comparator configured to drive the decision signal to a first signaling state when the output of the counter matches the latched output, and to drive the decision signal to a second signaling state when the output of the counter does not match the latched output. The trigger may be clock-controlled by the decision signal and may have an output that changes the signaling state in response to an edge in the decision signal. The counter may be reset when the decision signal is driven to the first signaling state.

[0009] In various aspects of this disclosure, a method for generating a rate-matched clock signal includes: configuring a counter to count transitions in a locally generated clock signal when a data signal is received from a single-wire serial bus; configuring a latch to capture the output of the counter and provide a latched output representing the transitions counted in the locally generated clock signal when a synchronization mode is received in the data signal; and configuring a comparator to: drive a decision signal to a first signaling state when the output of the counter matches the latched output; and drive the decision signal to a second signaling state when the output of the counter does not match the latched output. The decision signal may be configured to clock a flip-flop having an output that changes the signaling state in response to an edge in the decision signal. When the decision signal is driven to the first signaling state, the counter may be reset.

[0010] In some respects, the latched output represents the transition counted in the locally generated clock signal during a portion of the synchronization mode. This portion of the synchronization mode may include two transitions in the signaling state of the data signal. This portion of the synchronization mode may correspond to one or more bit transmission intervals. This portion of the synchronization mode may correspond to a half-bit transmission interval.

[0011] In one aspect, the gating logic unit can be configured to select the bit in the output of the counter to be captured by the latch.

[0012] In some respects, the controller can be configured to enable the latch and the counter when the synchronization mode is being received in the data signal, and to enable the counter and the trigger after the synchronization mode has ended and a transition is detected in the data signal. The controller can also be configured to disable the trigger when the synchronization mode is being received in the data signal, and to disable the latch after the synchronization mode has ended. The output of the trigger provides a receive clock signal whose frequency is matched to the data rate associated with the data signal. The controller can also be configured to reset the counter when a transition is detected at the center of a bit transmission interval after the synchronization mode has ended.

[0013] In one respect, the data signal is encoded using Manchester encoding. Attached Figure Description

[0014] Figure 1 An example is illustrated of a device employing a data link between IC devices, which operates selectively according to one of a number of available standards.

[0015] Figure 2 A first example of an apparatus employing a data link that can be used to communicatively couple two or more devices is illustrated.

[0016] Figure 3 A second example of an apparatus is illustrated, which employs a data link that can be used to communicatively couple two or more devices, including various radio frequency front-end devices.

[0017] Figure 4 This includes timing diagrams illustrating the signaling sent to depict the boundaries of RFFE and SPMI datagrams.

[0018] Figure 5 An example is illustrated of a system in which a host device communicates with one or more single-line slave devices according to certain aspects disclosed herein.

[0019] Figure 6 Examples of single-wire serial interfaces that can be configured according to certain aspects of this disclosure are illustrated.

[0020] Figure 7 Examples of Manchester-coded and control signaling, according to certain aspects of this disclosure, that can be used to exchange data between a host device and a single-line slave device are illustrated.

[0021] Figure 8 Examples are given of certain aspects of the timing of signals received at a single-wire serial interface of a receiving device configured according to certain aspects of this disclosure.

[0022] Figure 9 This illustrates certain aspects of the timing of a signal received at a single-wire serial interface of a receiving device when two bits of a two-bit synchronous mode 814 are used to measure the period of a transmitter clock signal, according to certain aspects of this disclosure.

[0023] Figure 10 A first example is illustrated of the timing of a signal received at a single-wire serial interface of a receiving device when a half bit of a synchronization mode is used to measure the period of a transmitter clock signal, according to certain aspects of this disclosure.

[0024] Figure 11 A second example is illustrated of the timing of a signal received at a single-wire serial interface of a receiving device when a half bit of the synchronization mode is used to measure the period of the transmitter clock signal, according to certain aspects of this disclosure.

[0025] Figure 12 An example of a rate-matched clock generation circuit configured according to certain aspects of this disclosure is illustrated.

[0026] Figure 13 Examples Figure 12 Some timing aspects of the rate-matched clock generation circuit illustrated in the figure.

[0027] Figure 14An example of an apparatus employing processing circuitry adaptable to certain aspects disclosed herein is illustrated.

[0028] Figure 15 This is a flowchart illustrating a method for generating a rate-matched clock signal according to certain aspects disclosed herein.

[0029] Figure 16 Examples of specific hardware implementations of devices adapted to certain aspects disclosed herein are illustrated. Detailed Implementation

[0030] The detailed description below, illustrated with reference to the accompanying drawings, is intended as a description of various configurations and not as representing the only configuration in which the concepts described herein can be practiced. To provide a thorough understanding of the various concepts, the detailed description includes specific details. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0031] Several aspects of the invention will now be described with reference to various apparatuses and methods. These apparatuses and methods will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, modules, components, circuits, steps, processes, algorithms, etc. (collectively, “elements”). These elements can be implemented using electronic hardware, computer software, or any combination thereof. Whether such elements are implemented as hardware or software depends on the specific application and the design constraints imposed on the system as a whole.

[0032] Certain aspects of this disclosure relate to a multipoint serial bus configuration in which multiple devices can communicate at various times. The described serial bus typically operates in a hierarchical manner, as one device controls communication during a transaction. The controlling device may be referred to as a master device, bus master, management device, or another term supported by a standard defining a protocol implemented by the controlling device. In some serial bus configurations, a single controlling device manages or controls communication during all transactions conducted via the serial bus. In other serial bus configurations, multiple devices may operate as controlling devices for each transaction conducted via the serial bus, and one device may act as the controlling device. The controlling device may provide a common clock signal transmitted over a conventional two-wire serial bus. The controlling device may provide control signaling that identifies the type of transaction to be conducted over the conventional two-wire serial bus. During certain transactions, the controlling device may send commands to one or more receiving devices using address information provided in or with a command. Receiving devices may be referred to as slave devices, client devices, slaves, peripheral devices, or another term supported by a standard defining a protocol implemented by the controlling device. For the purposes of this disclosure, the controlling device will be referred to as a master device, and the associated receiving device will be referred to as a slave device.

[0033] Overview

[0034] Devices comprising multiple SoCs and other IC devices typically employ a shared communication interface, which may include a serial bus or other data communication link to connect the processor to modems and other peripherals. The serial bus or other data communication link may operate according to multiple standards or protocols. For example, a serial bus may operate according to I2C, I3C, SPMI, and / or RFFE protocols, or another protocol that can be configured for half-duplex operation. The increased functionality and complexity of operating devices coupled to a serial bus, and the imposition of tighter timing constraints to support applications, peripherals, and sensors, can lead to greater demands on general-purpose input / output (GPIO) pin availability and communication link throughput.

[0035] Certain aspects of this disclosure relate to techniques for communicating over a single-wire serial bus using Manchester encoding and synchronization signaling that can be used by a slave device to generate rate-matched clock signals. In one example, a slave device configured according to certain aspects of this disclosure may configure a counter to count transitions in a locally generated clock signal when a Manchester-encoded data signal is received from the single-wire serial bus. The slave device may configure a latch to capture the output of the counter and provide a latched output representing the transitions counted in the locally generated clock signal when a synchronization pattern is received in the data signal. A comparator in the slave device may be configured to drive a decision signal to a first signaling state when the output of the counter matches the latched output, and to drive the decision signal to a second signaling state when the output of the counter does not match the latched output. The decision signal may be provided to the clock input of a flip-flop, and transitions in the decision signal may toggle the output of the flip-flop. That is, the output of the flip-flop may change the signaling state in response to an edge in the decision signal. When the decision signal is driven to the first signaling state, the counter may be reset. Two or more Manchester-encoded data bits may be used to provide the synchronization pulse.

[0036] Some aspects disclosed herein provide alternatives to or complements to serial bus protocols, such as I2C, I3C, SPMI, and / or RFFE protocols. Some aspects are suitable for serial buses operating in half-duplex or full-duplex mode. Some aspects are suitable for point-to-point Universal Asynchronous Receiver / Transmitter (UART) interfaces, Line-Multiplexed UART (LM-UART) interfaces, or another type of point-to-point interface. In some implementations, some aspects disclosed herein can be deployed to support the exchange of Virtual GPIO (VGI) messages, which can be used to convey the state or state change of physical GPIO pins without physical connections between devices. Some aspects are suitable for multipoint interfaces, point-to-point interfaces, or interfaces capable of switching between point-to-point and multipoint modes.

[0037] Example of a device using a serial data link

[0038] According to certain aspects of this disclosure, serial data links can be used to interconnect electronic devices that are subcomponents of devices such as: cellular phones, smartphones, Session Initiation Protocol (SIP) phones, laptops, notebooks, netbooks, smartbooks, personal digital assistants (PDAs), satellite radios, Global Positioning System (GPS) devices, smart home devices, smart lighting, multimedia devices, video devices, digital audio players (e.g., MP3 players), cameras, game consoles, entertainment devices, vehicle components, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.), appliances, sensors, security devices, vending machines, smart meters, drones, multi-rotor helicopters, or any other similar functional devices.

[0039] Figure 1 An example of a device 100 that may employ a data communication bus is illustrated. Device 100 may include processing circuitry 102 having multiple circuits or devices 104, 106, and / or 108, which may be implemented in a SoC or one or more ASICs. In one example, device 100 may be a communication device, and processing circuitry 102 may include processing devices provided in ASIC 104, one or more peripheral devices 106, and a transceiver 108 enabling the device to communicate with a radio access network, a core access network, the Internet, and / or another network via antenna 124.

[0040] ASIC 104 may have one or more processors 112, one or more modems 110, onboard memory 114, bus interface circuitry 116, and / or other logic circuitry or functions. Processing circuitry 102 may be controlled by an operating system that provides an application programming interface (API) layer, enabling one or more processors 112 to execute software modules residing in onboard memory 114 or other processor-readable storage device 122 provided on processing circuitry 102. Software modules may include instructions and data stored in onboard memory 114 or processor-readable storage device 122. ASIC 104 may access its onboard memory 114, processor-readable storage device 122, and / or storage devices external to processing circuitry 102. Onboard memory 114 and processor-readable storage device 122 may include read-only memory (ROM) or random access memory (RAM), electrically erasable programmable ROM (EEPROM), flash cards, or any memory device that can be used in processing systems and computing platforms. Processing circuitry 102 may include, implement, or access a local database or other parameter storage device that can maintain operating parameters and other information for configuring and operating device 100 and / or processing circuitry 102. The local database may be implemented using registers, database modules, flash memory, magnetic media, EEPROM, floppy disks, or hard disks, etc. Processing circuitry 102 may also be operatively coupled to external devices such as antenna 124, display 126, operator controls such as switches or buttons 128, 130 and / or integrated or external keyboard 132, and other components. The user interface module may be configured to operate with display 126, external keyboard 132, etc., via a dedicated communication link or via one or more serial data interconnects.

[0041] Processing circuitry 102 may provide one or more buses 118a, 118b, 120 that enable communication between certain devices 104, 106, and / or 108. In one example, ASIC 104 may include bus interface circuitry 116, which includes a combination of circuits, counters, timers, control logic units, and other configurable circuitry or modules. In one example, bus interface circuitry 116 may be configured to operate according to a communication specification or protocol. Processing circuitry 102 may include or control power management functions for configuring and managing the operation of device 100.

[0042] Figure 2 A first example of an apparatus 200 employing a data link that can be used to communicatively couple two or more devices is illustrated. Here, apparatus 200 includes multiple devices 202 and 2220 to 2220 coupled to a two-wire serial bus 220. N Equipment 202 and 2220 to 222N It can be implemented in one or more semiconductor IC devices, such as application processors, SoCs, or ASICs. In various specific implementations, devices 202 and 2220 to 222... N Some of the devices may include, support modems, signal processing devices, display drivers, cameras, user interfaces, sensors, sensor controllers, media players, transceivers, and / or other such components or devices, or operate as such. In some examples, one or more devices 2220 to 222 N It can be used to control, manage, or monitor sensor devices. Devices 202 and 2220 to 222 are connected via serial bus 220. N Communication between them is controlled by the host device 202. Some types of buses can support multiple host devices 202.

[0043] In one example, host device 202 may include interface controller 204 that manages access to the serial bus, configures dynamic addresses for slave devices, and / or generates clock signals 228 to be transmitted on clock line 218 of serial bus 220. Host device 202 may include configuration register 206 or other storage device 224 and other control logic components 212 configured to process protocols and / or higher-level functions. Control logic component 212 may include processing circuitry such as a state machine, sequencer, signal processor, or general-purpose processor. Host device 202 includes transceiver 210 and line driver / receiver 214a and 214b. Transceiver 210 may include receiver, transmitter, and common circuitry, where such common circuitry may include timing, logic, and storage circuitry and / or devices. In one example, the transmitter encodes and transmits data based on timing in clock signal 228 provided by clock generation circuitry 208. Additional timing clocks 226 may be used by control logic component 212 and other functions, circuitry, or modules.

[0044] One or more devices 2220 to 222 NIt can be configured to operate as a slave device. In some examples, a slave device may include circuitry and modules supporting a display, an image sensor, and / or circuitry and modules controlling and communicating with one or more sensors measuring environmental conditions. In one example, device 2220 configured to operate as a slave device may provide control functions, modules, or circuitry 232, including circuitry and modules for supporting a display, an image sensor, and / or controlling and communicating with one or more sensors measuring environmental conditions. In this example, device 2220 may include a configuration register 234 or other storage device 236, control logic unit 242, transceiver 240, and line drivers / receivers 244a and 244b. Control logic unit 242 may include processing circuitry, such as a state machine, sequencer, signal processor, or general-purpose processor. Transceiver 240 may include a receiver, a transmitter, and common circuitry, wherein these common circuitry may include timing, logic, and storage circuitry and / or devices. In one example, the transmitter encodes and transmits data based on timing in clock signal 248 provided by clock generation and / or recovery circuitry 246. In some instances, clock signal 248 may be derived from a signal received from clock line 218. Other timing clocks 238 may be used by control logic unit 242 and other functions, circuits, or modules.

[0045] Serial bus 220 can operate according to RFFE, I2C, I3C, SPMI, or other protocols. Devices 202 and 2220 to 222 N At least one of them can be configured to operate as both a master device and a slave device on serial bus 220. Devices 202 and 2220 to 222 N Two or more of these devices can be configured to operate as master devices on serial bus 220. The protocol selected to control the operation of serial bus 220 can define DC characteristics affecting certain signal levels associated with serial bus 220, and / or AC characteristics affecting certain timing aspects of signals transmitted on serial bus 220. In various examples, the two-wire serial bus 220 transmits data on data line 216 and a clock signal on clock line 218. In some cases, the data can be encoded in signaling states or in signaling state transitions between data line 216 and clock line 218.

[0046] Figure 3A second example of an apparatus 300 employing a data link that can be used to communicatively couple two or more devices is illustrated. In this example, a chipset or device 302 employs multiple RFFE buses 330, 332, 334 to couple various RF front-end devices 318, 320, 322, 324, 326, 328. A modem 304 includes an RFFE interface 308 that couples the modem 304 to a first RFFE bus 330. The modem 304 can communicate with a baseband processor 306 and a radio frequency IC (RFIC 312) via one or more communication links 310, 336. The illustrated device 302 may be embodied in one or more of the following: mobile communication devices, mobile phones, mobile computing systems, laptops, tablet computing devices, media players, gaming devices, wearable computing devices and / or communication devices, electrical appliances, etc.

[0047] In various examples, device 302 may be implemented using one or more baseband processors 306, modems 304, RFICs 312, multiple communication links 310, 336, multiple RFFE buses 330, 332, 334, and / or other types of buses. Device 302 may include other processors, circuitry, modules, and may be configured for various operations and / or different functionalities. Figure 3 In the illustrated example, the modem is coupled to the RF tuner 318 via its RFFE interface 308 and first RFFE bus 330. The RFIC 312 may include one or more RFFE interfaces 314, 316, a controller, a state machine, and / or a processor that configures and controls certain aspects of the RF front end. The RFIC 312 can communicate with the PA 320 and the power tracking module 322 via the first RFFE interface and the second RFFE bus 332 in its RFFE interface 314. The RFIC 312 can communicate with the switch 324 and one or more LNAs 326, 328 via the second RFFE interface and the third RFFE bus 334 in its RFFE interface 316.

[0048] Bus latency can affect the serial bus's ability to process high-priority, real-time, and / or other time-constrained messages. Low-latency messages, or messages requiring low bus latency, may involve sensor states, device-generated real-time events, and virtualized GPIO states. In one example, bus latency can be measured as the time elapsed between when a message becomes available for transmission and the delivery of that message, or in some cases, the start of its transmission. Other measurements of bus latency may be employed. Bus latency typically includes delays incurred when transmitting higher-priority messages, interrupt handling, the time required to terminate datagrams in progress on the serial bus, the time for sending commands that cause the bus to switch between transmit and receive modes, bus arbitration, and / or command transmission specified by the protocol.

[0049] In some examples, delay-sensitive messages may include coexistence messages. Sending coexistence messages in a multi-system platform prevents or reduces conflicts between certain device types, including, for example, switches 324, LNAs 326, 328, PAs 320, and other types of devices operating concurrently in a manner that may generate inter-device interference or potentially damage one or more devices. Devices that may interfere with each other can exchange coexistence management (CxM) messages to allow each device to signal impending actions that may cause interference or conflict. CxM messages can be used to manage the operation of shared components, including switches 324, LNAs 326, 328, PAs 320, and / or antennas.

[0050] Multipoint interfaces (such as RFFE, SPMI, I3C, etc.) can reduce the number of physical input / output (I / O) pins used for communication between multiple devices. Protocols supporting communication over multipoint serial buses define datagram structures for sending command, control, and data payloads. Certain common features are defined for the datagram structures of different protocols, including addressing for selecting devices to receive or send data, clock generation and management, interrupt handling, and device priority. In this disclosure, examples of the RFFE protocol may be used to illustrate certain aspects disclosed herein. However, the concepts disclosed herein are applicable to other serial bus protocols and standards.

[0051] Figure 4 Timing diagrams 400 and 420 illustrate signaling transmitted to delineate the boundaries of datagrams sent according to the RFFE protocol. Timing diagrams 400 and 420 show the relative timing of signals transmitted on a two-wire serial bus, which provides a clock signal on SCLK 402 and facilitates data exchange via SDATA 404. The first timing diagram 400 illustrates the timing of a sequence start condition (SSC 408), which is transmitted to signal the start of a transaction, such as the transmission of datagram 410. SSC 408 is transmitted when the serial bus is in idle state 406. In idle state 406, SCLK 402 is driven at full strength by the master device, while slave devices coupled to the serial bus present high impedance to SCLK 402. SCLK 402 is held in a low signaling state (here, zero volts) by the master device. In idle state 406, SDATA 404 is weakly driven by the host device or held in a weakly driven low signaling state 412 using a hold circuit or a weak pull-down circuit. For example, the hold circuit or weak pull-down circuit can maintain the signaling state of SDATA 404 when the host device has put its line driver into a high-impedance state, and when no other device is driving SDATA 404. The weakly driven low signaling state 412 can be easily overcome by another line driver capable of driving SDATA 404 at full strength.

[0052] In the master-driven SSC 408, the master device begins transmitting SSC 408 at a first time point 414, at which time the master device begins driving SDATA 404, which is initially in a low signaling state, at full strength. The master device then provides pulse 416 on SDATA 404 while continuing to drive SCLK 402 to a low signaling state. Pulse 416 has a duration of at least one cycle of the clock signal provided on SCLK 402 during the transmission of datagram 410. At a second time point 418, the master device begins transmitting clock pulses on SCLK 402, thereby providing a clock signal for controlling or indicating the timing of datagram 410 transmitted on SDATA 404.

[0053] For example, second timing diagram 420 illustrates the timing of a bus pause cycle (BPC 424) that can be sent to signal the termination of datagram 422. BPC 424 is sent by providing a falling edge 428 on SDATA 404 when SCLK 402 is in a high signaling state 430. By protocol, transitions on SDATA 404 are permitted only during the transmission of datagram 422 when the clock signal is in a low signaling state, and the falling edge 428 occurring when SCLK 402 is in a high signaling state 430 is interpreted as control signaling (i.e., BPC 424). The falling edge 428 is provided by the master device driving SDATA 404 low at full strength. The master device then drives SCLK 402 low and continues to drive SCLK 402 at full strength through subsequent bus idle intervals 426, 436. After driving SCLK 402 low, the host device initiates a bus idle period 436 at time 432 when it puts its line driver into a high-impedance state. When no other device is driving SDATA 404, SDATA 404 remains in a weakly driven low signaling state 434. BPC 424 is terminated, and the serial bus enters a bus idle period 426 until the next datagram is ready to be transmitted.

[0054] Figure 5 Examples are illustrated of a host device 502 and one or more single-line slave devices 5041 to 504 according to certain aspects disclosed herein. N The communication system 500. The host device 502 may be located in an RFIC, modem, application processor, or other type of device. The host device 502 may be adapted to communicate with single-line slave devices 5041 to 504. NData is exchanged on this single line, referred to as SDATA line 506 in the illustrated system 500. The data is encoded in a signal transmitted via SDATA line 506, wherein the signal includes embedded clock information that can be used by a receiving device to decode the data from the signal.

[0055] Master device 502 and single-line slave devices 5041 to 504 N This typically includes the corresponding protocol controllers 508, 5101 to 510. N Protocol controllers 508, 5101 to 510 N This may include a processor, controller, state machine, or other logic circuit configured to support one or more protocols. The protocol controller 508 in host device 502 may also be configured to manage communication via SDATA line 506. In some instances, the protocol controller 508 performs some of the functions of the host. In some specific implementations, the protocol controller 508 in host device 502 may be used to configure single-wire slave devices 5041 to 504. N One or more of them. The host device 502 can identify single-line slave devices 5041 to 504 as the designated recipients of data to be sent via the SDATA line 506. N The configuration allows the protocol controller 508 to be configured for use with receiver single-wire slave devices 5041 to 504. N The data encoding is to be sent via SDATA line 506 and addressed to single-wire slave devices 5041 to 504. N The signal.

[0056] The host device 502 may include a transmit clock generator 512, which can be used to define the timing of transmissions made via the SDATA line 506. Single-wire slave devices 5041 to 504 N Each of them includes local clock generation circuits 5141 to 514. N It provides corresponding protocol controllers 5101 to 510. N Timing. Local clock generation circuits 5141 to 514. N A synchronization pulse can be used after the SSC, sent by the host device 502, or after line turnaround, sent by the host device 502 or by single-line slave devices 5041 to 504. N Synchronization is achieved by sending a synchronization pulse from one of the circuits. According to certain aspects of this disclosure, local clock generation circuits 5141 to 514... N Synchronization can be achieved using transitions in the Manchester-encoded command and data payload transmitted via SDATA line 506. Local clock generation circuits 5141 to 514. NThis may include a ring oscillator or a delay-locked loop. In some specific implementations, the local clock generation circuits 5141 to 514... N It may include an injection-locked oscillator that responds to synchronization pulses and / or transitions in the transmission of Manchester-encoded command and data payloads.

[0057] Holder circuit 516 may be coupled to SDATA line 506 to facilitate line turnaround, in-band interruption requests, or arbitration processes according to certain aspects disclosed herein. In one example, holder circuit 516 may be configured as a positive feedback circuit that drives SDATA line 506 through a high-impedance output and receives feedback from SDATA line 506 through a low-impedance input. Holder circuit 516 may be configured to maintain the voltage of the last asserted value on SDATA line 506. Holder circuit 516 may be in host device 502 or single-line slave devices 5041 to 504. N The active line driver in one of them can be easily overcome.

[0058] Conventional implementations of single-wire bidirectional communication buses are hampered by their inherently slow data rates. Many conventional single-wire bidirectional communication buses are limited to signaling rates below megahertz (MHz) and are unsuitable for high-speed RF front-end control applications that may require clock rates up to 52 MHz. Some conventional single-wire bidirectional communication buses attempt to increase data rates by using pulse-width modulation (PWM) and other data encoding schemes. However, these subsequent communication buses typically cannot achieve signaling rates greater than 4 MHz, for example, due to various limitations of PWM signaling.

[0059] A single-wire bidirectional communication bus implemented according to certain aspects disclosed herein can achieve data rates up to and exceeding 52 MHz. In some examples, the signaling scheme provided for communication via the single-wire communication bus uses a combination of the RFFE protocol, Manchester encoding, and control signaling that can indicate and distinguish modifications to various types of transactions.

[0060] Figure 6An example of a single-wire serial interface 600 configurable according to certain aspects of this disclosure is illustrated. In this example, a host device 602 and a single-wire slave device 604 are illustrated. The host device 602 includes a protocol controller 614. The protocol controller 614 may be implemented using a processor, microcontroller, or finite state machine and may be used to control the transmit and receive functions of the host device 602. The protocol controller 614 may include or be coupled to a signal generation circuit 604 that generates synchronization signals and SSC signals transmitted on the SDATA line 620 that couples the host device 602 to one or more slave devices 604. The signal generation circuit 604 may be configured to generate different types of SSCs to initiate arbitration, initiate data transmission, or abandon arbitration. The signal generation circuit 604 may be configured to generate synchronization pulses used to synchronize a clock signal generated at the slave device 604 with a transmit clock signal generated in the host device 602.

[0061] Protocol controller 614 can be configured to selectively activate Manchester encoder 606 and Manchester decoder 608 based on the operating mode of single-wire serial interface 600. Manchester decoder 608 can extract data and clock information from signals received from SDATA line 620. Protocol controller 614 can also be configured to format datagrams for transmission via SDATA line 620. Protocol controller 614 can also be configured to generate commands to be transmitted via SDATA line 620.

[0062] The illustrated host device 602 includes a clock generator 614, which comprises one or more clock generation circuits. The clock generator 614 can be configured to generate a clock signal 616 used during transmit and receive operations. In one example, the clock signal 616 generated by the clock generator 614 includes a transmitter clock signal used by a Manchester encoder 606 to control the data rate transmitted by the host device 602 via the SDATA line 620. In another example, the transmitter clock signal or a frequency-scaled version of the clock signal provided by the clock generator 614 to the signal generation circuit 604 can be used to control the timing of SSC, synchronization pulses, and other signaling transmitted by the host device 602. In yet another example, the clock signal 616 generated by the clock generator 614 includes a receiver clock signal used by a Manchester decoder 608 to sample or detect transitions in the signal received via the SDATA line 620. Clock generator 614 can be configured to receive edge detection signal 618 from Manchester decoder 608, and can use edge detection signal 618 and / or the received Manchester-encoded signal to synchronize or calibrate the edges in the receiver clock signal to certain edges in the Manchester-encoded signal.

[0063] In the illustrated example, the single-wire slave device 604 includes a protocol controller 622. The protocol controller 622 can be implemented using a processor, microcontroller, or finite state machine, and can be used to control the transmit and receive functions of the single-wire slave device 604. The protocol controller 622 may include or be coupled to a signal generation circuit 624 that generates a synchronization pulse to be transmitted when the single-wire slave device 604 is transmitting via the SDATA line 620. The synchronization pulse generated by the signal generation circuit 604 can be configured to synchronize a clock signal generated at the master device 602 with a transmit clock signal generated in the slave device 604.

[0064] Protocol controller 622 can be configured to selectively activate Manchester encoder 626 and Manchester decoder 628 based on the operating mode of single-wire serial interface 600. Manchester decoder 628 can extract data and clock information from signals received from SDATA line 620. Protocol controller 622 can also be configured to format datagrams for transmission via SDATA line 620. Protocol controller 622 can also be configured to decompose datagrams and / or respond to commands received from SDATA line 620.

[0065] The illustrated single-wire slave device 604 includes a clock generator 634 comprising one or more clock generation circuits. The clock generator 634 can be configured to generate a clock signal 636 used during transmit and receive operations. In one example, the clock signal 636 generated by the clock generator 634 includes a transmitter clock signal used by a Manchester encoder 626 to control the data rate transmitted by the single-wire slave device 604 via the SDATA line 620. In another example, the transmitter clock signal or a frequency-scaled version of the clock signal provided by the clock generator 634 to the signal generation circuit 624 can be used to control the timing of SSC, sync pulses, and other signaling transmitted by the single-wire slave device 604. In yet another example, the clock signal 636 generated by the clock generator 634 includes a receiver clock signal used by a Manchester decoder 628 to sample or detect transitions in the signal received via the SDATA line 620. Clock generator 634 can be configured to receive edge detection signal 638 from Manchester encoder 628, and can use edge detection signal 638 and / or the received Manchester encoded signal to synchronize or calibrate the edges in the receiver clock signal to certain edges in the Manchester encoded signal.

[0066] Protocol controller 614 can be configured to manage and control the operation of line driver 612 and line receiver 610. Protocol controller 622 can be configured to manage and control the operation of line driver 632 and line receiver 630. When inactive or deactivated, line drivers 612, 632 may present high impedance to SDATA line 620. For example, when single-line slave device 604 is configured or expected to send data or control signals through SDATA line 620, the output of line driver 612 in master device 602 may present high impedance to SDATA line 620. When master device 602 is driving SDATA line 620, the output of line driver 632 in single-line slave device 604 is normally in a high impedance state.

[0067] A hold circuit 640 coupled to the SDATA line 620 facilitates line turnaround, in-band interrupt requests, and arbitration processes in a bidirectional single-wire serial bus. Maintaining the state of the SDATA line 620 is typically desirable when all devices are in high-impedance mode, during line turnaround, or during arbitration. Line turnaround occurs when the master device 602 transitions from transmit to receive or from receive to transmit. During arbitration, the master device 602 may enter high-impedance mode when the single-wire slave device 604 has the transmit option and the line driver in the master device 602 can present high impedance to the SDATA line 620 to avoid contention. The hold circuit 640 can be used to maintain the state of the SDATA line 620. In one example, the hold circuit 640 can be configured as a positive feedback circuit that drives the SDATA line 620 through a high-impedance output and receives feedback from the SDATA line 620 through a low-impedance input. The hold circuit 640 can be configured to maintain the voltage of the last asserted statement on the SDATA line 620. The retainer circuit 640 can be easily overcome by the line drivers 612 and 632 in the host device 602 and the single-line slave device 604, respectively.

[0068] Figure 7 Examples of Manchester-encoded and control signaling, according to certain aspects of this disclosure, are illustrated for use in exchanging data between a host device and a single-wire slave device via a single-wire serial bus. The signal lines of the single-wire serial bus are referred to herein as SDATA 722 (reference 1). Figure 5 and Figure 6Referring to the first timing diagram 700, Manchester encoding encodes data based on the direction of transitions occurring in the middle of the bit transmission interval 702. In some embodiments, SDATA 722 may initially be low and transition 704 to high indicates a "1" value bit. SDATA 722 may initially be high and transition 706 to low indicates a "0" value bit. In other embodiments, transition 704 to high indicates a "0" value bit, and transition 706 to low indicates a "1" value bit. Clock information is embedded in the data signal transitions occurring within each bit transmission interval 702. Some examples illustrated in this disclosure are based on implementations where transition 704 to high indicates a "1" value bit and transition 706 to low indicates a "0" value bit.

[0069] The second timing diagram 710 illustrates five bit transmission intervals 714a to 714e in the signal carried on SDATA 712. The bit sequence {0, 0, 1, 1, 0} is transmitted in the five bit transmission intervals 714a to 714e, and the transitions within each of the five bit transmission intervals 714a to 714e are illustrated. It will be observed that transitions may occur at some boundaries between the bit transmission intervals 714a to 714e, and no transitions occur at the other boundaries between the bit transmission intervals 714a to 714e.

[0070] Control signaling provided according to certain aspects of this disclosure can be used to indicate the start of a datagram, clock synchronization, the start of data exchange for both writing and reading datagrams, and the end of a datagram. Third timing diagram 720 illustrates the configuration of an SSC 724 according to certain aspects of this disclosure and a synchronization mode (Sync 726) defined for a basic transaction. The SSC 724 operates as a control signal transmitted via SDATA 722 to signal the start of a transaction. The SSC 724 has the form of a pulse initiated when SDATA 722 is idle. In the illustrated example, SDATA 722 is in a low signaling state when idle. The SSC 724 is initiated by driving SDATA 722 to a high signaling state. The SSC 724 is terminated by driving SDATA 722 to a low signaling state. In the illustrated example, the SSC 724 has a duration of three cycles of an internal transmit clock signal 730 used by the host device to control the timing of transmissions via a single-wire serial bus.

[0071] In some implementations, SSC 724 and Sync 726 are separated by a duration corresponding to one cycle of the internal transmit clock signal 730. Sync 726 has a duration defined by multiple cycles of the internal transmit clock signal 730. In the illustrated example, Sync 726 has a duration corresponding to two cycles of the internal transmit clock signal 730. Other implementations may specify a synchronization mode defined by any number of cycles of the internal transmit clock signal 730 or by a minimum and / or maximum number of cycles of the internal transmit clock signal 730.

[0072] Sync 726 includes synchronization pulses 732 and 734, which are provided to enable the clock generation circuitry in the receiving device to synchronize with the internal transmit clock signal 730 used by the host device. Sync 726 can be encoded using binary values. In the illustrated example, Sync 726 is transmitted as two Manchester-coded bits with values ​​"0" and "1". Synchronization pulses 732 and 734 enable clock synchronization, including frequency and phase synchronization. The number of synchronization pulses transmitted sequentially can be configured or selected based on the application, receiver capabilities, or under the control of the application. The number of clock ticks can be selected to achieve clock frequency and phase synchronization for different types of clock generation circuitry, including ring oscillators, delay-locked loops, and other circuitry. The use of Manchester encoding allows for clock phase adjustment in each bit transmission interval and supports long-running datagrams without loss of clock synchronization.

[0073] In some current implementations, a single-wire serial bus operating according to the RFFE protocol may be expected to support data rates corresponding to transmit clock frequencies of 26 MHz and 52 MHz. In some applications, it may be desirable to implement a single-wire serial bus supporting a range of data rates, including clock rates defined by earlier versions of the RFFE protocol. In one example, a device coupled to a single-wire serial bus operating according to the RFFE protocol may be configured to support transmit clock frequencies of 9.6 MHz, 19.2 MHz, 26 MHz, 38.4 MHz, and 52 MHz. Clock rate detection and synchronization circuitry provided according to certain aspects of this disclosure enables receivers coupled to a single-wire serial bus to support a large number or wide range of clock frequencies. Conventional clock rate synchronizers (including phase-locked loop (PLL) based synchronizers) can significantly increase die area and the power consumption required to implement and operate a PLL, and may prove impractical in cost-sensitive applications.

[0074] According to certain aspects of this disclosure, a receiver coupled to a single-wire serial bus can be configured to detect the clock rate by measuring the time elapsed between edges in the RFFE synchronization signaling. In one example, from synchronization mode (e.g., Figure 7Measurements obtained from Sync 726 can be used to configure or control the clock generation circuitry. In some implementations, the clock signal provided by the local oscillator can be used by the measurement circuitry to automatically determine the clock period associated with a synchronization pulse transmitted via a single-wire serial bus. The measurement circuitry can generate an identifier that selects one of a plurality of clock gears configured to configure the receiver clock signal used by the Manchester decoder in the receiver. In some implementations, measurement circuitry configured to count the rising, falling, or both rising and falling edges of the clock signal (LO clock signal) generated by the local oscillator can determine the duration of one or more synchronization pulses. The duration of the synchronization pulses can be determined by counting the edges of the LO clock signal between pairs of rising, falling, or some combination of rising and falling edges of the synchronization pulses. The measured duration of the synchronization pulses can be used to maintain clock generation at the identified transmitter clock rate based on timing at a fixed frequency of the clock signal provided by the local oscillator.

[0075] Figure 8Some aspects of the timing 800 of a signal received at a single-wire serial interface of a receiving device are illustrated. The single-wire serial interface may operate according to the RFFE protocol and may be configured to identify the period of a transmitter clock used to encode the signal. In the illustrated example, the signal is transmitted via the data line of a serial bus (here, SDATA 802). Commands, data, and other information may be encoded using Manchester encoding in the transmitted signal. For example, after completing a previous transaction 804, SDATA 802 is initially in an idle state 806. At a first time point 832, a transition 820 is detected in SDATA 802. Transition 820 corresponds to the start of SSC 808 and causes the receiving device to turn on, enable, or initialize its internal clock generator. The internal clock generator may generate one or more receiver clock signals that can be used to sample or capture data from SDATA 802. The internal clock generator may include or be coupled to a local oscillator that generates an internal LO clock signal. The LO clock signal can be used to derive one or more receiver clock signals. SDATA 802 returns to a low signaling state at the second time point 834 and remains in a low signaling state for duration 812 after SSC 808 has terminated and before synchronization mode 814 is sent. The duration and / or duration 812 of SSC 808 can vary based on application requirements. In one example, the duration and / or duration 812 of SSC 808 can be configured to provide sufficient time for the internal clock generator to achieve stability before sending synchronization mode 814. In some specific implementations, the duration of SSC 808 can be configured to select between single-wire and two-wire operation when the serial bus is coupled to some combination of single-wire and two-wire devices.

[0076] Synchronization mode 814 begins at the third time point 836. For proper detection and confirmation of the synchronization mode's contents, it is expected that the internal clock generator has achieved stable operation at the beginning of synchronization mode 814. In the illustrated example, synchronization mode 814 includes a first bit encoding the value "0" and a second bit encoding the value "1". Depending on certain aspects, the internal clock generator may be rate-matched and / or synchronized with the edges 824, 826 appearing at the respective centers of the two bits in synchronization mode 814.

[0077] Synchronization mode 814 precedes the transaction performed via SDATA 802. The transaction begins at the fourth time point 838 corresponding to the end of synchronization mode 814. SDATA 802 remains active for duration 816 until the transaction completes. Upon termination of the transaction, SDATA 802 exits the active state and is driven into a low signaling state for a period 818 before becoming idle. SDATA 802 can be considered active when data, commands, or control signaling are being transmitted.

[0078] According to certain aspects of this disclosure, the receiving device can measure the period of the transmitter clock signal while transmitting in synchronization mode 814. Figure 8 In the illustrated example, the receiving device measures the period of the transmitter clock signal based on the duration 810 between edges 824 and 826 that occur at the center of two bits in synchronization mode 814. This measured duration 810 nominally corresponds to a bit transmission interval. The duration 810 between edges 824 and 826 can be measured using an LO clock signal. In some specific implementations, the LO clock signal is generated at a frequency that is a multiple of the transmitter clock signal frequency, and the duration 810 between edges 824 and 826 can be measured by counting the edges in the internal clock signal.

[0079] In one example, a counter clocked by the LO clock signal is reset at the second time point 834, enabled to count when a first edge 824 is detected at the center of the first transmission interval 8220 in synchronization mode 814, and disabled to count when an edge 826 is detected at the center of the second transmission interval 8221 in synchronization mode 814. The counter output represents a time value that can be used to generate an index or code that indicates or controls the period of the receiver clock signal used to sample or capture data from the SDATA802. The counter value and the index or code can be locked at the end of synchronization mode 814 (indicated as the fourth time point 838).

[0080] Figure 9 An example of timing 900 of a signal received at a single-wire serial interface of a receiving device is illustrated when two bits of synchronization mode 814 are used to measure the period of a transmitter clock signal, according to certain aspects of this disclosure. This example may be applicable when it is known that SDATA 802 will be driven to low signaling state 916 immediately after the transmission of synchronization mode 814. SDATA 802 may be driven to low signaling state 916 when an additional synchronization bit (not shown) is transmitted as part of synchronization mode 814. It may be known that SDATA 802 will be driven to low signaling state 916 when the first bit of a transaction following synchronization mode 814 has a value of "1". When using synchronization mode 814 of other types or configurations, other conditions may allow the use of two bits of synchronization mode 814 to measure the period of a transmitter clock signal.

[0081] exist Figure 9In the illustrated example, the duration 910 between the edges 902 and 904 that occur at the beginning and end of two bits in synchronization mode 814 can be measured. The duration 910 between edges 902 and 904 nominally corresponds to two bit transmission intervals. The duration 910 between edges 902 and 904 can be measured using an LO clock signal. In some specific implementations, the LO clock signal is generated at a frequency that is a multiple of the frequency of the transmitter clock signal, and the duration 910 between edges 902 and 904 can be measured by counting the edges in the LO clock signal.

[0082] In one example, a counter clocked by the LO clock signal is reset at the second time point 834, enabled to count when an edge 902 is detected at the beginning of synchronization mode 814, and disabled to count when an edge 904 is detected at the end of synchronization mode 814. The counter's output represents a time value that can be used to generate an index or code that indicates or controls the period of the receiver clock signal used to sample or capture data from SDATA 802. The counter value and the index or code can be locked at the end of synchronization mode 814 (indicated as the fourth time point 838).

[0083] Figure 10 A first example is illustrated of the timing 1000 of a signal received at a single-wire serial interface of a receiving device when a half-bit of synchronization mode 814 is used to determine the period of a transmitter clock signal, according to certain aspects of this disclosure. In this example, the duration 1010 between a first edge 1002 and a third edge 1004 of synchronization mode 814 can be measured. The measured duration 1010 nominally corresponds to a half-bit transmission interval. The duration 1010 between edges 1002 and 1004 can be measured using an LO clock signal. In some specific embodiments, the LO clock signal is generated at a frequency that is a multiple of the frequency of the transmitter clock signal, and the duration 1010 between edges 1002 and 1004 can be measured by counting the edges in the LO clock signal.

[0084] In one example, a counter clocked by the LO clock signal is reset at the second time point 834, enabled to count when the first edge 1002 is detected at the beginning of synchronization mode 814, and disabled to count when the edge 1004 occurring at the center of the second bit transmission interval 8221 in synchronization mode 814 is detected. The counter output represents a value that can be used to generate an index or code that indicates or controls the period of the receiver clock signal used to sample or capture data from SDATA 802. The counter value and the index or code can be locked at the end of synchronization mode 814 (indicated as the fourth time point 838).

[0085] Figure 11 A second example illustrates the timing 1100 of a signal received at a single-wire serial interface of a receiving device when a half-bit of synchronization mode 814 is used to measure the period of a transmitter clock signal, according to certain aspects of this disclosure. This example may be applicable when it is known that SDATA 802 will be driven to a low signaling state 1116 immediately after the transmission of synchronization mode 814. SDATA 802 may be driven to a low signaling state 1116 when an additional synchronization bit (not shown) is transmitted as part of synchronization mode 814. It may be known that SDATA 802 will be driven to a low signaling state 1116 when the first bit of a transaction following synchronization mode 814 has a value of "1". When using other types or configurations of synchronization mode 814, other conditions may allow the use of both bits of synchronization mode 814 to measure the period of the transmitter clock signal.

[0086] In this example, the duration 1110 between the second edge 1102 and the last edge 1104 of the two-bit synchronization mode 814 can be measured. The measured duration 1010 nominally corresponds to a half-bit transmission interval. The duration 1110 between edges 1102 and 1104 can be measured using an LO clock signal. In some specific implementations, the LO clock signal is generated at a frequency that is a multiple of the transmitter clock signal frequency, and the duration 1110 between edges 1102 and 1104 can be measured by counting the edges in the LO clock signal.

[0087] In one example, a counter clocked by the LO clock signal is reset at the second time point 834, enabled to count when an edge 1102 is detected at the center of the first transmit interval 8220 of synchronization mode 814, and disabled to count when an edge 1104 is detected at the end of the second synchronization mode 814. The counter output represents a time value that can be used to generate an index or code that indicates or controls the period of the receiver clock signal used to sample or capture data from SDATA 802. The counter value and the index or code can be locked at the end of synchronization mode 814 (indicated as the fourth time point 838).

[0088] Figure 12 An example of a rate-matched clock generation circuit 1200 configured according to certain aspects of this disclosure is illustrated. In some specific embodiments, the rate-matched clock may be configured to measure the period of the transmitter clock signal using a synchronization mode 814 transmitted via a single-wire serial bus, such as, for example... Figures 8 to 10As illustrated in the diagram, the rate-matched clock generation circuit 1200 includes a controller 1210 configured to monitor, manage, and control the operation of the transmitter clock rate measurement circuit and the receiver clock generation circuit. The controller 1210 may be incorporated into processing circuitry and / or may include a finite state machine, microprocessor, microcontroller, digital signal processor (DSP), sequencer, combinational logic unit, etc. The controller 1210 can provide control signals 1224, 1226, and 1228 to enable the operation of the counter 1202, latch 1206, and gate circuit 1204.

[0089] In the illustrated example, controller 1210 is configured to monitor signals transmitted via the data line (SDATA 802) of a serial bus operating according to an RFFE protocol adapted or configured for single-wire communication. Controller 1210 can be configured to identify SSC and synchronization modes transmitted via SDATA 802, including... Figures 8 to 10 The SSC 808 and Synchronization Mode 814 are shown. See also: Figure 8 The controller 1210 can detect transition 820 in SDATA 802, which corresponds to the start of SSC 808 at a first time point 832. In some embodiments, the controller 1210 responds to the start of SSC 808 by turning on, enabling, or initializing a local oscillator (not shown) that provides the LO clock signal 1220. In other embodiments, the local oscillator is controlled independently of the rate-matched clock generation circuit 1200 and may include or be derived from the system clock signal.

[0090] Synchronization mode 814 begins at a third time point 836, which occurs after SSC 808 has terminated. Controller 1210 can be configured to measure the elapsed time between selected edges in synchronization mode 814. Figure 8 In the illustrated example, controller 1210 responds to the first edge 824 by enabling counter 1202, latch 1206, and configuring gating circuitry 1204. When enabled, counter 1202 counts the edges in the LO clock signal 1220. In one example, counter 1202 counts the rising edge of the LO clock signal 1220. In another example, counter 1202 counts the falling edge of the LO clock signal 1220. In some examples, counter 1202 counts both the rising and falling edges of the LO clock signal 1220 to provide increased measurement resolution.

[0091] The counter output 1218 provided by counter 1202 is coupled to latch 1206 via gating circuit 1204. Counter output 1218 can represent all or part of the count bits provided by counter 1202. The number of bits provided in counter output 1218 can be selected to reliably represent the transmitter clock frequency to be measured or estimated using rate-matched clock generation circuit 1200. In one example, the frequency of LO clock signal 1220 is greater than the transmitter clock frequency, and it may be desirable to divide the count value by 2. M The number represented. In the latter example, the counter output 1218 can be omitted. M The least significant bit. In some implementations, the counter output 1218 includes all the count bits provided by the counter 1202, and the gating circuit 1204 can select which bits to be coupled to the latch 1206. In some implementations, the gating circuit 1204 may include logic circuitry that performs mathematical division on the count value output by the counter 1202.

[0092] Controller 1210 can be configured to disable the counting of counter 1202 after detecting the second edge 824 in synchronization mode 814, and to cause latch 1206 to capture and hold counter output 1218 when counting is disabled. Gating circuitry 1204 can be disabled after latching counter output 1218. In some embodiments, latched output 1238 includes all bits of counter output 1218. In some embodiments, latched output 1238 includes fewer bits than those provided in counter output 1218. For example, latched output 1238 may include one less bit than counter output 1218, such that when... N When the counter outputs a value of 1218, the latched output 1238 indicates... N The value of / 2. The latched output 1238 can be used to represent the duration of a period of the transmitter clock signal, expressed as the number of cycles of the LO clock signal 1220 or as the number of division cycles of the LO clock signal 1220. The latched output 1238 can be used to represent the data rate associated with the signal transmitted via SDATA 802. In one example, the data rate, expressed in bits per second, corresponds to the frequency of the transmitter clock signal when one data bit is encoded in each cycle of the transmitter clock signal.

[0093] In the illustrated example, the rate-matched clock generation circuit 1200 uses a counter 1202, a comparator 1208, a flip-flop 1212, combinational logic (AND gate 1214), and the output of a latch 1206 to generate a receive clock signal used to sample or decode data from a signal transmitted via SDATA 802. For each bit interval, the counter is reset and enabled to count edges in the LO clock signal 1220. The edges counted by counter 1202 may correspond to edges counted during the measurement of the transmitter clock signal period based on the timing of edges in synchronization mode 814. Therefore, counter 1202 may be configured to count rising edges, falling edges, or both rising and falling edges in the LO clock signal 1220.

[0094] Counter output 1218 and latched output 1238 are provided to comparator 1208. Comparator 1208 compares the bits of counter output 1218 with the corresponding bits of latched output 1238 and generates a decision signal 1230 indicating (i) whether the value of counter output 1218 matches the value of latched output 1238, or (ii) whether the value of counter output 1218 does not match the value of latched output 1238. In the illustrated example, comparator 1208 uses XOR logic to determine whether a match exists between counter output 1218 and latched output 1238. When a match exists, decision signal 1230 is driven low, triggering flip-flop 1212, which in turn causes the output of flip-flop 1212 to switch signaling states.

[0095] Decision signal 1230 is coupled to the counter via AND gate 1214. Reset_C signal 1236 is provided at the output of AND gate 1214 and is driven low when decision signal 1230 is driven low to signal a match between counter output 1218 and latched output 1238. When in a low signaling state, Reset_C signal 1236 resets counter 1202, thereby clearing counter output 1218 so that counter output 1218 no longer matches the value of latched output 1238. Therefore, decision signal 1230 is driven high, and the output of AND gate 1214 follows R_Out signal 1232 provided by controller 1210. R_Out signal 1232 is held high by controller 1210 when rate-matched clock generation circuit 1200 actively generates a receive clock signal. Therefore, counter 1202 is enabled to count edges in LO clock signal 1220 after being reset during active receive clock signal generation mode.

[0096] The controller can be configured to provide an enable signal (EnC 1224) that enables the counter 1202 to count during transmitter clock signal period measurement and receive clock signal generation modes in the first signaling state. When EnC 1224 is in the second signaling state, typically during idle mode and / or when the SSC 808 is transmitting via SDATA 802, the counting is disabled. In some implementations, counter 1202 can be used to determine the length and / or type of the SSC 808 being transmitted via SDATA 802.

[0097] The controller can also be configured to provide a signal (Reset_T signal 1234) that drives the reset input of the trigger 1212. The Reset_T signal 1234 can be used to phase-align the generated receive clock with transitions and / or bit transmission intervals in the signal transmitted via SDATA 802. In the illustrated example, the output of the trigger 1212 provides or is used to derive a rate-matched clock signal 1240 output by the rate-matched clock generation circuit 1200. Due to variations, such as those caused by manufacturing processes, voltage, or temperature (PVT) changes, the rate-matched clock signal 1240 may not be perfectly matched to the frequency of the transmitter clock signal. Frequency or phase mismatch can be accommodated by synchronizing the rate-matched clock signal 1240 with transitions at the center of each bit transmission interval guaranteed by Manchester encoding. In some specific implementations, phase and frequency alignment can be performed by circuitry downstream of the rate-matched clock generation circuit 1200.

[0098] In some implementations, the rate-matching clock generation circuit 1200 configured according to certain aspects of this disclosure may be synchronized with a guaranteed transition at the center of each bit transmission interval. In one example, the controller 1210 may be configured to assert the R_Out signal 1232 in response to detecting a transition at the center of the bit transmission interval. When the transition at the center of the bit transmission interval occurs before the decision signal 1230 is asserted (driven low), the controller may drive the R_Out signal 1232 to a low signaling state, thereby preempting the match detection. When the transition at the center of the bit transmission interval occurs after the decision signal 1230 is asserted (driven low), the controller may drive the R_Out signal 1232 to a low signaling state, thereby resetting the counter 1202 a second time near the center of the bit transmission interval. In some implementations, the rate-matching clock generation circuit 1200 is effectively configured such that the comparator resets the counter 1202 at the beginning of each bit transmission interval, and the transition detection logic provided by the controller 1210 resets the counter 1202 in the middle of each bit transmission interval.

[0099] Figure 13 Examples Figure 12The illustrated diagram shows certain timing aspects of the rate-matched clock generation circuit 1200. Timing diagram 1300 illustrates rate measurement when the frequency of the LO clock signal 1220 exceeds eight times the frequency of the transmitter clock signal. In the illustrated example, synchronization mode 814 has a duration corresponding to two bit transmission intervals and 16.5 cycles of the LO clock signal 1220. In one example, counter 1202 is configured to count the rising and falling edges of the LO clock signal 1220, and synchronization mode 814 has a duration corresponding to the LO clock signal 1220. N =The duration corresponding to 34 edges. In obtaining... Figure 8 When performing the measurement corresponding to the example shown, it may be expected that counter 1202 will produce a value. N The counter 1218 outputs 17 edges ( / 2), but if the phase of the transmitter clock signal does not perfectly match the phase of the LO clock signal 1220, the counter 1202 can capture 16 edges. It has a value... N The counter output 1218, representing a transmit bit interval, is 1 / 2. When the receive clock signal is generated, the flip-flop 1212 toggles twice for each transmit bit interval, and the latch can be configured to provide a latched output 1238, which omits the least significant bit of the counter output 1218 to obtain a value... N The latched output 1238 is 1 / 4. Since the omission of the least significant bit of counter output 1218 corresponds to an integer division by two operation, a value of 8 might be expected for the latched output 1238 in the illustrated example. Counter 1202 is reset after counting eight edges during the receive clock signal generation.

[0100] State diagram 1340 illustrates certain aspects of the generation of the receive clock signal. State diagram 1340 includes two states 1342 and 1346 of a rate-matched clock signal 1240, which is provided at the output of flip-flop 1212 in the rate-matched clock generation circuit 1200. In the first state 1342, the rate-matched clock signal 1240 is driven, pulled, or held at a low signaling level, and in the second state 1346, the rate-matched clock signal 1240 is driven, pulled, or held at a high signaling level. Transitions 1344 and 1348 between states 1342 and 1346 occur when counter 1202 has counted eight edges during receive clock signal generation. Transitions 1344 and 1348 between states 1342 and 1346 repeat until controller 1210 holds R_Out signal 1232 at a low signaling state and / or disables the counting performed by counter 1202 using EnC 1224.

[0101] Among the various examples provided herein, examples of a single-wire serial bus are described, in which data and commands are configured according to the RFFE protocol. The RFFE protocol is used to illustrate certain aspects of this disclosure. The single-wire serial bus may operate according to different types of serial multipoint protocols, including, for example, the SPMI protocol or the I3C protocol. Certain aspects of the serial multipoint protocol selected for controlling and managing transmissions via the single-wire serial bus may be adapted, configured, or modified to support arbitration, line turnaround, and transmissions performed without an explicit clock reference (such as a clock signal transmitted on a dedicated clock line).

[0102] Examples of processing circuits and methods

[0103] Figure 14 This is a diagram illustrating an example of a hardware implementation of device 1400. In some examples, device 1400 may perform one or more functions disclosed herein. According to various aspects of this disclosure, processing circuitry 1402 may be used to implement elements, any portion of elements, or any combination of elements as disclosed herein. Processing circuitry 1402 may include one or more processors 1404 controlled by some combination of hardware modules and software modules. Examples of processors 1404 include microprocessors, microcontrollers, DSPs, SoCs, ASICs, field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, sequencers, gated logic components, discrete hardware circuitry, and other suitable hardware configured to perform the various functionalities described throughout this disclosure. One or more processors 1404 may include dedicated processors that perform specific functions and may be configured, enhanced, or controlled by one of the software modules 1416. One or more processors 1404 may be configured by a combination of software modules 1416 loaded during initialization and may be further configured by loading or unloading one or more software modules 1416 during operation.

[0104] In the illustrated example, processing circuitry 1402 may be implemented using a bus architecture, typically represented by bus 1410. Bus 1410 may include any number of interconnect buses and bridges, depending on the specific application of processing circuitry 1402 and overall design constraints. Bus 1410 links together various circuits including one or more processors 1404 and storage devices 1406. Storage devices 1406 may include memory devices and mass storage devices, and may be referred to herein as computer-readable media and / or processor-readable media. Bus 1410 may also link various other circuits, such as timing sources, timers, peripherals, voltage regulators, and power management circuitry. Bus interface 1408 provides an interface between bus 1410 and one or more transceivers 1412a, 1412b. Transceivers 1412a, 1412b may be provided for each networking technology supported by the processing circuitry. In some instances, multiple networking technologies may share some or all of the circuitry or processing modules found in transceivers 1412a, 1412b. Each transceiver 1412a, 1412b provides components for communicating with various other devices via a transmission medium. In one example, transceiver 1412a may be used to couple device 1400 to a multi-wire bus. In another example, transceiver 1412b may be used to connect device 1400 to a radio access network. Depending on the nature of device 1400, a user interface 1418 (e.g., keypad, display, speaker, microphone, joystick) may also be provided, and this user interface may be communicatively coupled to bus 1410, either directly or via bus interface 1408.

[0105] Processor 1404 may be responsible for managing bus 1410 and for general processing, which may include executing software stored in a computer-readable medium (which may include storage device 1406). In this regard, processing circuitry 1402 (including processor 1404) may be used to implement any of the methods, functions, and techniques disclosed herein. Storage device 1406 may be used to store data manipulated by processor 1404 during software execution, and the software may be configured to implement any of the methods disclosed herein.

[0106] One or more processors 1404 in processing circuitry 1402 can execute software. Software should be broadly interpreted as instructions, instruction sets, code, code segments, program code, programs, subroutines, software modules, applications, software applications, software packages, routines, subroutines, objects, executable files, threads of execution, procedures, functions, algorithms, etc., regardless of whether it is referred to as software, firmware, middleware, microcode, hardware description languages, or other names. The software may reside in a computer-readable form in storage device 1406 or on an external computer-readable medium. External computer-readable media and / or storage device 1406 may include non-transitory computer-readable media. For example, non-transitory computer-readable media include magnetic storage devices (e.g., hard disks, floppy disks, magnetic stripes), optical discs (e.g., compact discs (CDs) or digital multifunction discs (DVDs)), smart cards, flash memory devices (e.g., "flash drives," cards, sticks, or key drives), RAM, ROM, programmable read-only memory (PROM), erasable PROM (EPROM, including EEPROM), registers, removable disks, and any other suitable media for storing software and / or instructions that can be accessed and read by a computer. Computer-readable media and / or storage device 1406 may also include, for example, carrier waves, transmission lines, and any other suitable media for transmitting software and / or instructions that can be accessed and read by a computer. Computer-readable media and / or storage device 1406 may reside in processing circuitry 1402, in processor 1404, outside of processing circuitry 1402, or distributed across multiple entities including processing circuitry 1402. Computer-readable media and / or storage device 1406 may be embodied in a computer program product. For example, a computer program product may include computer-readable media in packaging material. Those skilled in the art will recognize how best to achieve the functionality described throughout this disclosure depends on the specific application and the overall design constraints imposed on the system as a whole.

[0107] Storage device 1406 can maintain and / or organize software in loadable code segments, modules, applications, programs, etc., which may be referred to herein as software module 1416. Each software module in software module 1416 may include instructions and data that, when installed or loaded on processing circuitry 1402 and executed by one or more processors 1404, contribute to a runtime image 1414 that controls the operation of one or more processors 1404. Some instructions, when executed, cause processing circuitry 1402 to perform functions according to certain methods, algorithms, and processes described herein.

[0108] Some software modules in software module 1416 may be loaded during the initialization of processing circuitry 1402, and these software modules 1416 may configure processing circuitry 1402 to perform the various functions disclosed herein. For example, some software modules 1416 may configure the internal devices and / or logic circuitry 1422 of processor 1404, and may manage access to external devices such as transceivers 1412a, 1412b, bus interface 1408, user interface 1418, timers, math coprocessors, etc. Software module 1416 may include control programs and / or operating systems that interact with interrupt handlers and device drivers and control access to various resources provided by processing circuitry 1402. Resources may include memory, processing time, access to transceivers 1412a, 1412b, user interface 1418, etc.

[0109] One or more processors 1404 of the processing circuitry 1402 can be multifunctional, whereby some software modules in software module 1416 are loaded and configured to perform different functions or different instances of the same function. One or more processors 1404 may be additionally adapted to manage background tasks initiated in response to inputs, such as from user interface 1418, transceivers 1412a, 1412b, and device drivers. To support the execution of multiple functions, one or more processors 1404 can be configured to provide a multitasking environment, whereby each of the multiple functions is implemented as a set of tasks to be served by one or more processors 1404 as needed or desired. In one example, the multitasking environment can be implemented using a time-sharing program 1420 that transfers control of the processors 1404 between different tasks, whereby each task returns control of the one or more processors 1404 to the time-sharing program 1420 upon completion of any incomplete operation and / or in response to inputs such as interrupts. When a task has control over one or more processors 1404, the processing circuitry is effectively dedicated to the purpose addressed by the functions associated with the control task. The time-sharing program 1420 may include an operating system, a main loop for loop-based transfer control, functions for allocating control of one or more processors 1404 according to function priority, and / or an interrupt-driven main loop for providing control of one or more processors 1404 to processing functions in response to external events.

[0110] Processing circuitry 1402 may be configured to perform one or more of the functions disclosed herein. For example, processing circuitry 1402 may be configured to operate as a master device coupled to a serial bus. Processing circuitry 1402 may be configured to initiate a pulse on a line coupling processing circuitry 1402 to a slave device, present a high impedance to the line after initiating the pulse, and determine whether the slave device has prematurely terminated the pulse, thereby indicating a first encoded value. If the slave device has not terminated the pulse, processing circuitry 1402 may be configured to terminate the pulse after a duration sufficient to indicate a second encoded value. In one example, the first encoded value is assigned binary 1 and the second encoded value is assigned binary 0. In another example, the first encoded value is assigned binary 0 and the second encoded value is assigned binary 1. Processing circuitry 1402 may be configured to determine the encoded value or may employ a separate PWM decoder.

[0111] Figure 15 This is a flowchart 1500 of a method for generating a rate-matched clock signal, which can be executed at a receiving device coupled to a single-wire serial bus. A master device and one or more slave devices can be coupled to the single-wire serial bus. The master device can exchange Manchester-encoded data with the slave devices. Depending on the type of transaction conducted via the single-wire serial bus, the master device and slave devices can be a transmitter and a receiver.

[0112] At block 1502, the receiving device can configure a counter to count transitions in a locally generated clock signal when a data signal is received from a single-wire serial bus. At block 1504, the receiving device can configure a latch to capture the output of the counter and provide a latched output representing the transitions counted in the locally generated clock signal when a synchronization mode is received in the data signal. At block 1506, the receiving device can configure a comparator to drive a decision signal to a first signaling state when the output of the counter matches the latched output, and to drive the decision signal to a second signaling state when the output of the counter does not match the latched output. The decision signal can be configured to clock a flip-flop having an output that changes the signaling state in response to an edge in the decision signal. When the decision signal is driven to the first signaling state, the counter can be reset. The data signal can be encoded using Manchester encoding.

[0113] In some examples, the latched output represents a transition counted in a locally generated clock signal during a portion of the synchronization mode. This portion of the synchronization mode may include two transitions in the signaling state of the data signal. This portion of the synchronization mode may correspond to one or more bit transmission intervals. This portion of the synchronization mode may correspond to a half-bit transmission interval.

[0114] In one example, the method includes configuring the gating logic unit to select the bits in the output of the counter to be captured by the latch.

[0115] In some implementations, the controller is configured to enable the latch and counter when a synchronization mode is being received in the data signal, and to enable the counter and trigger after the synchronization mode has ended and a transition is detected in the data signal. The controller can also be configured to disable the trigger when a synchronization mode is being received in the data signal, and to disable the latch after the synchronization mode has ended. The controller can also be configured to reset the counter when a transition is detected at the center of the bit transmission interval after the synchronization mode has ended.

[0116] Figure 16 This is an illustration of an example of a hardware implementation of a device 1600 employing processing circuitry 1602. The processing circuitry typically has a controller or processor 1616 that may include one or more microprocessors, microcontrollers, digital signal processors, sequencers, and / or state machines. Processing circuitry 1602 may be implemented using a bus architecture, typically represented by bus 1620. Bus 1620 may include any number of interconnect buses and bridges, depending on the specific application of processing circuitry 1602 and overall design constraints. Bus 1620 links together various circuits including one or more processors and / or hardware modules represented by controller or processor 1616, modules or circuits 1604, 1606, 1608, and 1610, and processor-readable storage medium 1618. One or more physical layer circuits and / or modules 1614 may be provided to support communication links implemented using multi-wire bus 1612, communication via antennas or antenna arrays 1622 (e.g., to a radio access network), etc. Bus 1620 can also link various other circuits such as timing sources, peripheral devices, voltage regulators and power management circuits, which are well known in the art and will therefore not be described further.

[0117] Processor 1616 is responsible for general processing, including executing software, code, and / or instructions stored on processor-readable storage medium 1618. Processor-readable storage medium 1618 may include non-transitory storage medium. When executed by processor 1616, the software causes processing circuitry 1602 to perform various functions described herein and for any particular device. Processor-readable storage medium 1618 may be used to store data manipulated by processor 1616 during software execution. Processing circuitry 1602 also includes at least one of modules 1604, 1606, 1608, and 1610. Modules 1604, 1606, 1608, and 1610 may be software modules running in processor 1616, residing in / stored in processor-readable storage medium 1618, one or more hardware modules coupled to processor 1616, or some combination thereof. Modules 1604, 1606, 1608, and 1610 may include microcontroller instructions, state machine configuration parameters, or some combination thereof.

[0118] In one configuration, the device 1600 includes a module and / or circuit 1604 configured or adapted to generate a rate-matched received clock signal, a module and / or circuit 1606 configured or adapted to count clock edges in an internal clock signal, a module and / or circuit 1608 configured or adapted to compare the counts of clock edges, and a module and / or circuit 1610 configured or adapted to encode and decode data and commands using Manchester encoding.

[0119] In one example, device 1600 includes physical layer circuitry and / or modules 1614 that implement interface circuitry with at least one line driver adapted or configured to couple device 1600 to a single-wire serial bus. Device 1600 may have a processor 1616 or a protocol controller. Device 1600 may include or be coupled to a hold circuit via the single-wire serial bus. The hold circuit may be operable to maintain the single-wire serial bus in a constant signaling state after the line drivers in the host and slave devices present a high impedance to the single-wire serial bus.

[0120] In a first example, device 1600 includes components for counting transitions in a locally generated clock signal, components for capturing the output of a counter, and components for comparing counter values. The components for counting transitions in the locally generated clock signal may include a counter configured to count transitions when a data signal is received from a single-wire serial bus. The components for capturing the output of the counter may include a latch configured to provide a latched output representing the transitions counted in the locally generated clock signal when a synchronization mode is received in the data signal. The components for comparing the counter value may include a comparator configured to: compare the output of the counter with the latched output; drive a decision signal to a first signaling state when the output of the counter matches the latched output; and drive the decision signal to a second signaling state when the output of the counter does not match the latched output. Device 1600 may include a flip-flop clocked by the decision signal and having an output that changes the signaling state in response to an edge in the decision signal. When the decision signal is driven to the first signaling state, the counter can be reset. The data signal may be encoded using Manchester encoding.

[0121] In some examples, the latched output represents a transition counted in a locally generated clock signal during a portion of the synchronization mode. This portion of the synchronization mode may include two transitions in the signaling state of the data signal. This portion of the synchronization mode may correspond to one or more bit transmission intervals. This portion of the synchronization mode may correspond to a half-bit transmission interval.

[0122] In one example, the component used to capture the output of the counter includes a gating logic component that is configured to select the bits in the output of the counter to be captured by the latch.

[0123] In some implementations, device 1600 includes a controller configured to enable a latch and a counter when a synchronization mode is being received in the data signal, and to enable the counter and a trigger after the synchronization mode has ended and a transition is detected in the data signal. The controller may also be configured to disable the trigger when a synchronization mode is being received in the data signal, and to disable the latch after the synchronization mode has ended. The controller may also be configured to reset the counter when a transition is detected at the center of a bit transmission interval after the synchronization mode has ended.

[0124] Device 1600 can be configured as a clock generation circuit having: a counter configured to count transitions in a locally generated clock signal when a data signal is received from a single-wire serial bus; a latch configured to capture the output of the counter and provide a latched output representing the transitions counted in the locally generated clock signal when a synchronization mode is received in the data signal; a comparator configured to drive a decision signal to a first signaling state when the output of the counter matches the latched output, and to drive the decision signal to a second signaling state when the output of the counter does not match the latched output; and a flip-flop having an output that changes the signaling state in response to an edge in the decision signal. The counter can be reset when the decision signal is driven to the first signaling state. The data signal can be encoded using Manchester encoding.

[0125] In some examples, the latched output represents a transition counted in a locally generated clock signal during a portion of the synchronization mode. This portion of the synchronization mode may include two transitions in the signaling state of the data signal. This portion of the synchronization mode may correspond to one or more bit transmission intervals. This portion of the synchronization mode may correspond to a half-bit transmission interval.

[0126] In one example, the method includes configuring the gating logic unit to select the bits in the output of the counter to be captured by the latch.

[0127] In some implementations, the controller is configured to enable the latch and counter when a synchronization mode is being received in the data signal, and to enable the counter and trigger after the synchronization mode has ended and a transition is detected in the data signal. The controller can also be configured to disable the trigger when a synchronization mode is being received in the data signal, and to disable the latch after the synchronization mode has ended. The controller can also be configured to reset the counter when a transition is detected at the center of the bit transmission interval after the synchronization mode has ended.

[0128] Processor-readable storage medium 1618 may include software, code, and / or instructions configured to cause processor 1616 to: configure a counter to count transitions in a locally generated clock signal when a data signal is received from a single-wire serial bus; configure a latch to capture the output of the counter and provide a latched output representing the transitions counted in the locally generated clock signal when a synchronization mode is received in the data signal; and configure a comparator to drive a decision signal to a first signaling state when the output of the counter matches the latched output, and to drive the decision signal to a second signaling state when the output of the counter does not match the latched output. The decision signal may be configured to clock a flip-flop having an output that changes the signaling state in response to an edge in the decision signal. When the decision signal is driven to the first signaling state, the counter may be reset. The data signal may be encoded using Manchester encoding.

[0129] In some examples, the latched output represents a transition counted in a locally generated clock signal during a portion of the synchronization mode. This portion of the synchronization mode may include two transitions in the signaling state of the data signal. This portion of the synchronization mode may correspond to one or more bit transmission intervals. This portion of the synchronization mode may correspond to a half-bit transmission interval.

[0130] In one example, software, code, and / or instructions may enable processor 1616 to configure gating logic units to select bits in the output of a counter to be captured by a latch.

[0131] In some implementations, the processor 1616 or controller is configured to enable the latch and counter when a synchronization mode is being received in the data signal, and to enable the counter and trigger after the synchronization mode has ended and a transition is detected in the data signal. The controller can also be configured to disable the trigger when a synchronization mode is being received in the data signal, and to disable the latch after the synchronization mode has ended. The controller can also be configured to reset the counter when a transition is detected at the center of the bit transmission interval after the synchronization mode has ended.

[0132] Some specific implementation examples are described in the following numbered clauses: 1. A clock generation circuit, the clock generation circuit comprising: a counter configured to count transitions in a locally generated clock signal when a data signal is received from a single-wire serial bus; a latch configured to capture the output of the counter and provide a latched output representing the transitions counted in the locally generated clock signal when a synchronization mode is received in the data signal; a comparator configured to: drive the decision signal to a first signaling state when the output of the counter matches the latched output; and drive the decision signal to a second signaling state when the output of the counter does not match the latched output; and a trigger having an output that changes the signaling state in response to an edge in the decision signal, wherein the counter is reset when the decision signal is driven to the first signaling state.

[0133] 2. The clock generation circuit according to Clause 1, wherein the latched output represents the transition counted in the locally generated clock signal during a portion of the synchronization mode.

[0134] 3. The clock generation circuit according to Clause 2, wherein the portion of the synchronization mode includes two transitions in the signaling state of the data signal.

[0135] 4. The clock generation circuit according to Clause 2 or Clause 3, wherein the portion of the synchronization mode corresponds to one or more bit transmission intervals.

[0136] 5. The clock generation circuit according to any one of Clause 2 or Clause 3, wherein the portion of the synchronization mode corresponds to a half-bit transmission interval.

[0137] 6. The clock generation circuit according to any one of clauses 1 to 5, the clock generation circuit further comprising a gating logic component configured to select a bit in the output of the counter to be captured by the latch.

[0138] 7. The clock generation circuit according to any one of clauses 1 to 6, the clock generation circuit further comprising a controller configured to: enable the latch and the counter when the synchronization mode is being received in the data signal; and enable the counter and the trigger after the synchronization mode has terminated and a transition is detected in the data signal.

[0139] 8. The clock generation circuit according to Clause 7, wherein the controller is further configured to: disable the trigger when the synchronization mode is being received in the data signal; and disable the latch after the synchronization mode has terminated, wherein the output of the trigger provides a receive clock signal whose frequency matches the data rate associated with the data signal.

[0140] 9. The clock generation circuit according to Clause 7 or Clause 8, wherein the controller is further configured to reset the counter when a transition is detected at the center of the bit transmission interval after the synchronization mode has been terminated.

[0141] 10. The clock generation circuit according to any one of clauses 1 to 9, wherein the data signal is encoded using Manchester encoding.

[0142] 11. An apparatus comprising: means for counting transitions in a locally generated clock signal, the means including a counter configured to count the transitions when a data signal is received from a single-wire serial bus; means for capturing the output of the counter, the means including a latch configured to provide a latched output representing the transitions counted in the locally generated clock signal when a synchronization mode is received in the data signal; means for comparing the output of the counter with the latched output, the means including a comparator configured to: drive the decision signal to a first signaling state when the output of the counter matches the latched output; and drive the decision signal to a second signaling state when the output of the counter does not match the latched output; and a trigger controlled by the decision signal and having an output that changes the signaling state in response to an edge in the decision signal, wherein the counter is reset when the decision signal is driven to the first signaling state.

[0143] 12. The apparatus according to Clause 11, wherein the latched output represents the transition counted in the locally generated clock signal during a portion of the synchronization mode.

[0144] 13. The apparatus according to Clause 12, wherein the portion of the synchronization mode includes two transitions in the signaling state of the data signal.

[0145] 14. The apparatus according to Clause 12 or Clause 13, wherein the portion of the synchronization mode corresponds to one or more bit transmission intervals.

[0146] 15. The apparatus according to Clause 12 or Clause 13, wherein the portion of the synchronization mode corresponds to a half-bit transmission interval.

[0147] 16. The apparatus according to any one of clauses 11 to 15, wherein the component for capturing the output of the counter includes a gating logic component configured to select a bit in the output of the counter to be captured by the latch.

[0148] 17. The apparatus according to any one of clauses 11 to 16, the apparatus further comprising a controller configured to: enable the latch and the counter when the synchronization mode is being received in the data signal; and enable the counter and the trigger after the synchronization mode has terminated and a transition is detected in the data signal.

[0149] 18. The apparatus according to Clause 17, wherein the controller is further configured to: disable the trigger when the synchronization mode is being received in the data signal; and disable the latch after the synchronization mode has terminated.

[0150] 19. The apparatus according to Clause 17 or Clause 18, wherein the controller is further configured to reset the counter when a transition is detected at the center of the bit transmission interval after the synchronization mode has been terminated.

[0151] 20. The apparatus according to any one of clauses 11 to 19, wherein the data signal is encoded using Manchester encoding.

[0152] 21. A method for generating a rate-matched clock signal, the method comprising: configuring a counter to count transitions in a locally generated clock signal when a data signal is received from a single-wire serial bus; configuring a latch to capture an output of the counter and provide a latched output representing the transitions counted in the locally generated clock signal when a synchronization mode is received in the data signal; and configuring a comparator to: drive the decision signal to a first signaling state when the output of the counter matches the latched output; and drive the decision signal to a second signaling state when the output of the counter does not match the latched output, wherein the decision signal is configured to clock-control a trigger having an output that changes the signaling state in response to an edge in the decision signal, and wherein the counter is reset when the decision signal is driven to the first signaling state.

[0153] 22. The method according to Clause 21, wherein the latched output represents the transition counted in the locally generated clock signal during a portion of the synchronization mode.

[0154] 23. The method according to Clause 22, wherein the portion of the synchronization mode includes two transitions in the signaling state of the data signal.

[0155] 24. The method according to Clause 22 or Clause 23, wherein the portion of the synchronization mode corresponds to one or more bit transmission intervals.

[0156] 25. The method according to Clause 22 or Clause 23, wherein the portion of the synchronization mode corresponds to a half-bit transmission interval.

[0157] 26. The method according to any one of clauses 21 to 25, the method further comprising configuring a gating logic component to select a bit in the output of the counter to be captured by the latch.

[0158] 27. The method according to any one of clauses 21 to 26, wherein the controller is configured to: enable the latch and the counter when the synchronization mode is being received in the data signal; and enable the counter and the trigger after the synchronization mode has terminated and a transition is detected in the data signal.

[0159] 28. The method according to Clause 27, wherein the controller is further configured to: disable the trigger when the synchronization mode is being received in the data signal; and disable the latch after the synchronization mode has terminated.

[0160] 29. The method according to Clause 27 or Clause 28, wherein the controller is further configured to reset the counter when a transition is detected at the center of the bit transmission interval after the synchronization mode has been terminated.

[0161] 30. The method according to any one of clauses 21 to 29, wherein the data signal is encoded using Manchester encoding.

[0162] It should be understood that the specific order or hierarchy of the steps in the disclosed process is an example of the exemplary method. It should be understood that the specific order or hierarchy of the steps in these processes can be rearranged according to design preferences. Furthermore, some steps can be combined or omitted. The appended method claims present elements of multiple steps in a sample order, but are not intended to limit one to the specific order or hierarchy presented.

[0163] The foregoing description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. Therefore, the claims are not intended to limit themselves to the aspects shown herein, but should be given the full scope consistent with the claims, wherein references to elements in the singular form, unless specifically stated otherwise, are not intended to mean “one and only one,” but rather “one or more.” Unless otherwise specifically stated, the term “some” refers to one or more. All structural and functional equivalents of elements throughout the various aspects described herein that are known to or will later be known to a person skilled in the art are expressly incorporated herein by reference and are intended to be covered by the claims. Furthermore, nothing disclosed herein is intended to be offered to the public, whether or not such disclosure is explicitly recited in the claims. No element of a claim should be construed as a component plus a function unless that element is explicitly stated using the phrase “component for…”.

Claims

1. A clock generation circuit, the clock generation circuit comprising: A counter configured to count transitions in a locally generated clock signal when a data signal is received from a single-wire serial bus; A latch configured to capture the output of the counter and, upon receiving a synchronization mode in the data signal, provide a latched output representing the transition counted in the locally generated clock signal; The comparator is configured to: When the output of the counter matches the latched output, the decision signal is driven to the first signaling state; as well as When the output of the counter does not match the latched output, the decision signal is driven to the second signaling state; and A trigger, the trigger having an output that changes the signaling state in response to an edge in the decision signal. When the decision signal is driven to the first signaling state, the counter is reset.

2. The clock generation circuit of claim 1, wherein the latched output represents the transition counted in the locally generated clock signal during a portion of the synchronization mode.

3. The clock generation circuit of claim 2, wherein the portion of the synchronization mode includes two transitions in the signaling state of the data signal.

4. The clock generation circuit of claim 2, wherein the portion of the synchronization mode corresponds to one or more bit transmission intervals.

5. The clock generation circuit according to claim 2, wherein the portion of the synchronization mode corresponds to a half-bit transmission interval.

6. The clock generation circuit of claim 1, further comprising a gating logic component configured to select a bit in the output of the counter to be captured by the latch.

7. The clock generation circuit according to claim 1, further comprising a controller, the controller being configured to: The latch and the counter are enabled when the synchronization mode is being received in the data signal; and The counter and the trigger are activated after the synchronization mode has been terminated and a transition is detected in the data signal.

8. The clock generation circuit of claim 7, wherein the controller is further configured to: The trigger is disabled when the synchronization mode is being received in the data signal; and The latch is disabled after the synchronization mode has been terminated. The output of the trigger provides a receive clock signal whose frequency matches the data rate associated with the data signal.

9. The clock generation circuit of claim 7, wherein the controller is further configured to reset the counter when a transition is detected at the center of the bit transmission interval after the synchronization mode has been terminated.

10. The clock generation circuit of claim 1, wherein the data signal is encoded using Manchester encoding.

11. An apparatus comprising: A component for counting transitions in a locally generated clock signal, the component including a counter configured to count the transitions when a data signal is received from a single-wire serial bus; A component for capturing the output of the counter includes a latch configured to provide a latched output representing the transition counted in the locally generated clock signal when a synchronization mode is received in the data signal; A component for comparing the output of the counter with the latched output, the component including a comparator configured to: When the output of the counter matches the latched output, the decision signal is driven to the first signaling state; as well as When the output of the counter does not match the latched output, the decision signal is driven to the second signaling state; and A trigger, which is clock-controlled by the decision signal and has an output that changes the signaling state in response to an edge in the decision signal. When the decision signal is driven to the first signaling state, the counter is reset.

12. The apparatus of claim 11, wherein the latched output represents the transition counted in the locally generated clock signal during a portion of the synchronization mode.

13. The apparatus of claim 12, wherein the portion of the synchronization mode includes two transitions in the signaling state of the data signal.

14. The apparatus of claim 12, wherein the portion of the synchronization mode corresponds to one or more bit transmission intervals.

15. The apparatus of claim 12, wherein the portion of the synchronization mode corresponds to a half-bit transmission interval.

16. The apparatus of claim 11, wherein the component for capturing the output of the counter includes a gating logic component configured to select a bit in the output of the counter to be captured by the latch.

17. The apparatus of claim 11, further comprising a controller configured to: The latch and the counter are enabled when the synchronization mode is being received in the data signal; and The counter and the trigger are activated after the synchronization mode has been terminated and a transition is detected in the data signal.

18. The apparatus of claim 17, wherein the controller is further configured to: The trigger is disabled when the synchronization mode is being received in the data signal; and The latch is disabled after the synchronization mode has been terminated.

19. The apparatus of claim 17, wherein the controller is further configured to reset the counter when a transition is detected at the center of the bit transmission interval after the synchronization mode has been terminated.

20. The apparatus of claim 11, wherein the data signal is encoded using Manchester encoding.

21. A method for generating a rate-matched clock signal, the method comprising: Configure the counter to count transitions in the locally generated clock signal when a data signal is received from a single-wire serial bus; The latch is configured to capture the output of the counter and, when a synchronization mode is received in the data signal, provide a latched output representing the transition counted in the locally generated clock signal; as well as Configure the comparator as follows: When the output of the counter matches the latched output, the decision signal is driven to the first signaling state; as well as When the output of the counter does not match the latched output, the decision signal is driven to the second signaling state. The decision signal is configured to clock a trigger, the trigger having an output that changes the signaling state in response to an edge in the decision signal. When the decision signal is driven to the first signaling state, the counter is reset.

22. The method of claim 21, wherein the latched output represents the transition counted in the locally generated clock signal during a portion of the synchronization mode.

23. The method of claim 22, wherein the portion of the synchronization mode includes two transitions in the signaling state of the data signal.

24. The method of claim 22, wherein the portion of the synchronization mode corresponds to one or more bit transmission intervals.

25. The method of claim 22, wherein the portion of the synchronization mode corresponds to a half-bit transmission interval.

26. The method of claim 21, further comprising configuring a gating logic unit to select a bit in the output of the counter to be captured by the latch.

27. The method of claim 21, wherein the controller is configured to: The latch and the counter are enabled when the synchronization mode is being received in the data signal; and The counter and the trigger are activated after the synchronization mode has been terminated and a transition is detected in the data signal.

28. The method of claim 27, wherein the controller is further configured to: The trigger is disabled when the synchronization mode is being received in the data signal; and The latch is disabled after the synchronization mode has been terminated.

29. The method of claim 27, wherein the controller is further configured to reset the counter when a transition is detected at the center of the bit transmission interval after the synchronization mode has been terminated.

30. The method of claim 21, wherein the data signal is encoded using Manchester encoding.

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