Memory scheduling method and device, electronic equipment and storage medium

Abstract

The invention discloses a memory scheduling method and device, electronic equipment and a storage medium, and belongs to the technical field of network security. The method is applied to a memory module comprising a local memory and a computing fast link memory. The method comprises the following steps: acquiring swap-out frequency of the local memory; the swap-out frequency is a rate at which data in the local memory is swapped out to a disk exchange partition within unit time; according to the swap-out frequency and a preset dynamic scheduling rule, adjusting the distribution proportion of the local memory and the computing fast link memory; the allocation proportion represents the proportion of the computing fast link memory in the physical memory address space of the memory module; and allocating the available space of the computing fast link memory according to the adjusted allocation proportion. The problem that the existing memory expansion technology cannot ensure the performance while greatly expanding the memory can be solved.

Description

Technical Field

[0001] This application belongs to the field of data storage technology, specifically relating to a memory scheduling method, apparatus, electronic device, and storage medium. Background Technology

[0002] Compute Express Link (CXL) is a high-performance, low-latency interconnect protocol used to connect processors, accelerators, storage, and other computing resources. CXL not only supports the expansion of memory subsystem capacity and bandwidth but also enables interconnection between heterogeneous processors and peripherals, achieving decoupling and pooling of computing and memory resources. In this way, by expanding host machine memory through CXL memory pools, the Central Processing Unit (CPU) resources can be fully utilized.

[0003] However, CXL memory suffers from a certain performance degradation compared to the host machine's local memory, making it impossible to maintain performance while significantly expanding memory. Summary of the Invention

[0004] The purpose of this application is to provide a memory scheduling method, apparatus, electronic device, and storage medium that can solve the problem that existing memory expansion technologies cannot guarantee performance while significantly expanding memory.

[0005] In a first aspect, embodiments of this application provide a memory scheduling method applied to a memory module including local memory and fast-link memory for computation, the method comprising: Obtain the swap-out frequency of the local memory; the swap-out frequency is the rate at which data in the local memory is swapped out to the disk swap partition per unit time; Based on the swapping frequency and preset dynamic scheduling rules, the allocation ratio between the local memory and the fast-link computing memory is adjusted; the allocation ratio represents the proportion of the fast-link computing memory in the physical memory address space of the memory module. Allocate the available space of the fast link memory according to the adjusted allocation ratio.

[0006] Secondly, embodiments of this application provide a memory scheduling device applied to a memory module including local memory and fast-link memory for computation, the device comprising: The acquisition module is used to acquire the swap-out frequency of the local memory; the swap-out frequency is the rate at which data in the local memory is swapped out to the disk swap partition per unit time. An adjustment module is used to adjust the allocation ratio of the local memory and the fast-link computing memory according to the swapping frequency and preset dynamic scheduling rules; the allocation ratio represents the proportion of the fast-link computing memory in the physical memory address space of the memory module; The allocation module is used to allocate the available space of the fast link memory according to the adjusted allocation ratio.

[0007] Thirdly, embodiments of this application provide an electronic device including a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement the steps of the memory scheduling method as described in the first aspect.

[0008] Fourthly, embodiments of this application provide a readable storage medium on which a program or instructions are stored, which, when executed by a processor, implement the steps of the memory scheduling method as described in the first aspect.

[0009] In this embodiment, adjusting the proportion of compute-fast link memory in the physical memory address space of the memory module according to the swapping frequency of local memory reduces local memory pressure, ensures local memory serves high-frequency data, and minimizes the impact on overall system performance. Furthermore, while meeting performance requirements, using compute-fast link memory from the memory module to replace part of the local memory expansion needs not only achieves memory expansion but also avoids impacting system performance, reduces redundant local memory configuration, and lowers hardware costs. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of memory expansion in the prior art provided in an embodiment of this application.

[0011] Figure 2 This is a schematic diagram of an application environment provided in an embodiment of this application.

[0012] Figure 3 This is a flowchart of a memory scheduling method provided in an embodiment of this application.

[0013] Figure 4 This is a flowchart illustrating the specific steps of a memory scheduling method provided in an embodiment of this application.

[0014] Figure 5 This is a schematic diagram of an expanded memory provided in an embodiment of this application.

[0015] Figure 6 This is a block diagram of a memory scheduling device provided in an embodiment of this application.

[0016] Figure 7This is a block diagram of an electronic device provided in an embodiment of this application.

[0017] Figure 8 This is a block diagram of another electronic device provided in the embodiments of this application. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0019] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0020] Cloud providers offer users computing instances, or virtual machines, with different configurations through virtualization technology. Users can purchase them on demand. In scenarios such as in-memory databases and large model training, where memory resources are in high demand, users usually purchase virtual machines with large memory configurations. However, since virtual machines are virtualized from host machines, their memory size is limited by the host machine's memory. The memory configuration of a virtual machine will not exceed the host machine's memory size, making it impossible to achieve virtual machines with ultra-large memory. At the same time, due to the limitation of memory resources, the remaining CPU resources of the host machine cannot be sold, resulting in a waste of CPU resources.

[0021] CXL is a high-speed serial protocol that allows for fast and reliable data transfer between different components within a computer system. Therefore, CXL memory pools can be built based on CXL to expand the host machine's memory. This allows the host machine to provide multiple large-memory virtual machines exceeding its own memory size, while also fully utilizing CPU resources. However, as an extension of the host machine's memory, CXL memory suffers from a performance degradation compared to the host's native memory.

[0022] Addressing CXL memory performance degradation typically involves memory tiering schemes, such as the Flat Memory Model. The Flat Memory Model is a memory management approach where all available memory addresses form a contiguous linear address space, simplifying memory management. By tiering local memory and CXL memory—using local memory as a cache layer for CXL memory—performance degradation can be mitigated.

[0023] Flat Memory Mode employs a memory tiering strategy, using the host machine's local memory as a cache for CXL memory, to achieve memory expansion in the following ways: Figure 1 As shown. See also Figure 1 The ratio of host machine local memory to CXL memory is 1:1. Host machine local memory and CXL memory together constitute the host machine memory, forming the host machine's physical memory address space. The address space of local memory and the address space of CXL memory may have the same memory addresses mapped to local memory.

[0024] However, this scheme has a drawback. If the ratio of host local memory to CXL memory is 1:1, the host can only expand its memory size by one time. When a user accesses a memory address that is the physical address of B, and finds that the data in memory B is in local memory, it is retrieved directly from local memory. If the user accesses a memory address that is the physical address of A, and finds that the corresponding data for A is not in local memory but in CXL memory, the data is retrieved from CXL memory. Based on the principle of temporal locality of memory access, the data in local memory B and the data in CXL memory A will be swapped. It can be seen that the local memory and physical memory address space have a 1:2 relationship, that is, local memory and CXL memory are 1:1. The reason for limiting it to 1:1 is to reduce memory performance degradation, but it also limits the amount of host memory expansion; the host memory can only be expanded to twice its original size.

[0025] If the ratio of local memory to CXL memory is 1:n (n≥2), then the relationship between local memory and physical memory space is 1 to n+1. This can expand the host machine memory to n+1 times the original size. However, due to the increased probability of local memory access conflicts, frequent data exchange between CXL memory and local memory is caused, leading to memory performance degradation.

[0026] The frequent data exchange between CXL memory and local memory can lead to memory performance degradation for the following reasons: 1. Transmission medium and distance: Host machine local memory transmits data through the memory bus directly connected to the CPU, with an extremely short signal path; while CXL memory needs to transmit through the high-speed interface standard (Peripheral Component Interconnect Express, PCIe) and CXL bus, with a longer path, and the electrical signal attenuation and crosstalk of PCIe and CXL will introduce additional delay.

[0027] 2. To achieve device interconnection, cache consistency, and memory sharing, the CXL protocol introduces a multi-layered protocol stack, which incurs additional overhead during data transmission. Address translation and routing for CXL memory require multiple levels of routing and translation through the PCIe root complex, CXL switch, and memory controller. In contrast, local memory address translation is directly handled by the CPU, resulting in a shorter path and less overhead.

[0028] 3. The system needs to use a memory tiering strategy at the software or hardware level to cache high-frequency data in local memory and sink low-frequency data to CXL memory. This scheduling process consumes CPU cycles or hardware resources, introducing additional overhead.

[0029] To address the aforementioned problems, this application provides a memory scheduling method, apparatus, electronic device, and storage medium. The memory scheduling method provided by the embodiments of this application will be described in detail below with reference to the accompanying drawings and through specific embodiments and application scenarios.

[0030] First, an application scenario involving an embodiment of this application will be described.

[0031] See Figure 2 The memory scheduling method provided in this application embodiment can be applied to, for example, Figure 2 The system architecture shown includes a virtual machine layer, a host machine layer, and a CXL memory pool layer.

[0032] In some embodiments, the virtual machine layer is a virtual environment running on the host machine and is the direct carrier of user services. In traditional architectures, memory is limited by the physical capacity of a single host machine.

[0033] In some embodiments, the host layer is a physical server that connects to the lower-level CXL memory pool via the CXL protocol, thus overcoming the capacity limitations of its own physical memory.

[0034] In some embodiments, the CXL memory pool layer consists of a shared memory resource pool formed by interconnecting multiple CXL memory cards. These CXL cards form a unified memory pool via a CXL switch or direct connection, providing elastic memory expansion for all host machines. For example, in a server rack connected by CXL 2.0, the CXL memory cards can be memory cards that insert DDR4 memory and support PCIe connections.

[0035] In some embodiments, the DDR4 memory of the CXL memory card is aggregated into a shared memory pool. The host machine can dynamically allocate and distribute memory from the pool as its own extended memory. For example, if the host machine has 128GB of local memory, it can be allocated 256GB of CXL extended memory from the shared memory pool.

[0036] In some embodiments, a memory module consisting of local memory and compute fast link memory, which is host memory, constitutes the host physical memory address space.

[0037] It should be noted that in unified virtualization, the virtual machine's memory is limited by the host machine's physical memory. However, using... Figure 1 The architecture shown demonstrates that virtual machine memory is no longer limited by the physical memory of a single host machine. Through the CXL memory pool, virtual machine memory can be expanded across host machines and nodes. Resources in the CXL memory pool are indirectly accessed by the host machine, achieving a three-level elastic expansion of virtual machine memory → host machine memory → CXL memory pool, supporting virtual machines with extremely large memory allocations. In this way, memory pool resources can be dynamically allocated and reclaimed across multiple host machines and multiple virtual machines, avoiding idle or insufficient memory on a single node and improving the overall resource utilization of the data center.

[0038] The memory scheduling method provided in the embodiments of this application will be described in detail below.

[0039] Figure 3 This is a flowchart of a memory scheduling method provided in an embodiment of this application. The method is applied to a memory module including local memory and fast-link memory for computation, and includes the following steps.

[0040] Step 101: Obtain the local memory swap frequency.

[0041] In this embodiment of the application, the swap-out frequency is the rate at which data in local memory is swapped out to the disk swap partition per unit time.

[0042] In some embodiments, the local memory swapping frequency is periodically determined by a local memory swapping frequency monitor, and the local memory swapping frequency is stored in the local memory swapping frequency monitor.

[0043] In some embodiments, prior to step 101, the memory scheduling method may further include: when memory pressure exceeds a preset memory threshold, traversing multiple memory pages in local memory and dividing the multiple memory pages into active pages and inactive pages according to access frequency; selecting the least accessed page among the inactive pages as the target page; writing the data of the kernel target page to the swap partition on the disk and recording the location of the swap partition.

[0044] In some embodiments, the swapping rate of local memory is collected in real time using the Virtual Memory Statistics (vmstat) tool and the sys file system, and the swapping frequency is calculated.

[0045] In some embodiments, if the duration of the swapping frequency exceeding the preset frequency threshold is longer than a first duration, a hardware prefetch mechanism is activated to preload high-frequency data in the CXL memory to the local memory cache partition via the CXL controller, thereby reducing the swapping frequency.

[0046] Understandably, swapping frequency reflects the load status of local memory. A high swapping frequency indicates insufficient local memory, causing the system to frequently swap data to disk, resulting in a sharp drop in performance.

[0047] Step 102: Adjust the allocation ratio of fast link memory and local memory according to the swapping frequency and preset dynamic scheduling rules.

[0048] In the embodiments of this application, the allocation ratio represents the proportion of fast link memory calculated in the physical memory address space of the memory module.

[0049] In some embodiments, the physical memory address space of the memory module can be the system's global physical address space. The global physical address space includes the host physical memory address space and the CXL memory address space.

[0050] In some embodiments, the allocation ratio between fast link memory and local memory is adjusted based on the swapping frequency and a preset frequency threshold.

[0051] In some embodiments, the preset dynamic scheduling rules may include: increasing the available space ratio of CXL memory when the swap frequency is less than a preset frequency threshold; and decreasing the available space ratio of CXL memory when the swap frequency is greater than or equal to the frequency threshold.

[0052] Step 103: Allocate the available space for computing fast link memory according to the adjusted allocation ratio.

[0053] In the embodiments of this application, the available space of CXL represents the range of the accessible address range of CXL. For example, if the range of the accessible address range of CXL is 2 terabytes (TB), then the available space is also 2TB.

[0054] In some embodiments, the available space for computing fast link memory is allocated according to an adjusted allocation ratio through a memory management unit (MMU) or a CXL controller.

[0055] In this embodiment, the memory management unit is also called the "paged memory management unit" and is used to process CPU memory access requests, perform virtual address to physical address translation, memory protection, and control of the central processing unit cache.

[0056] In this embodiment of the application, the CXL controller is used to allocate and release resources in the CXL memory, for example, to identify newly added or removed CXL devices and to divide the CXL memory address range.

[0057] In some embodiments, when the available space ratio of CXL memory is increased, the CXL controller allocates an independent address segment for the newly added CXL memory in the global physical address space according to the adjusted allocation ratio.

[0058] In other embodiments, while reducing the available space percentage of CXL memory, the address segment corresponding to the CXL memory to be reduced is released.

[0059] In other embodiments, upon detecting the removal of a CXL device, the link connection to the removed CXL device is disconnected via the CXL controller, and the link bandwidth is reclaimed.

[0060] In summary, in this embodiment, adjusting the proportion of compute-fast link memory in the physical memory address space of the memory module according to the swapping frequency of local memory can reduce local memory pressure, ensure that local memory serves high-frequency data, and reduce the impact on overall system performance. Furthermore, while meeting performance requirements, using compute-fast link memory from the memory module to replace part of the local memory expansion needs not only achieves memory expansion but also avoids impacting system performance, reduces redundant local memory configuration, and lowers hardware costs.

[0061] Figure 4 This is a flowchart illustrating the specific steps of a memory scheduling method provided in an embodiment of this application. See also... Figure 4 This method is applied to a memory module that includes local memory and compute fast linked memory, and includes the following steps.

[0062] Step 201: Based on the system storage topology information, divide the local memory into multiple independent local memory slices.

[0063] In some embodiments, system memory topology information characterizes the memory distribution features at the hardware level. For example, system memory topology information includes: Non-Uniform Memory Access (NUMA) nodes, memory distribution, physical distribution of local memory, memory topology and addresses, etc.

[0064] In one possible implementation, the memory of each NUMA node is used as an independent shard, and the local memory is divided into multiple independent local memory shards. For example, the memory of each NUMA node is used as an independent shard, with shard 0 corresponding to 64GB of memory in node0 and shard 1 corresponding to 64GB of memory in node1.

[0065] In another possible implementation, the memory of the NUMA node is split into multiple memory channels according to a preset granularity, and each memory channel is treated as an independent local memory shard.

[0066] In some embodiments, after step 201, the memory scheduling method further includes: Sub-step A1: Set the local memory slice corresponding to the frequently accessed data as a locked region; Sub-step A2 sets the local memory fragments, excluding the locked region, as shared fragments.

[0067] In this embodiment of the application, low-frequency data is prohibited from replacing high-frequency access data in the locked area.

[0068] In one possible implementation, the local memory corresponding to frequently accessed data can be a slice of the local memory with the highest access frequency.

[0069] In one possible implementation, a locked region is used to prevent any process from swapping memory pages from the locked region to disk. For example, the physical address range of the locked region is 0x00000000-0x0FFFFFFFFF. The MMU marks this locked region as non-swapable, and the CPU prioritizes accessing this region.

[0070] In another possible implementation, the locked region is used to prevent low-frequency data in the shared fragment from being replaced by high-frequency parameters of the locked region by CXL memory cache data.

[0071] In this embodiment, the shared shard is used to dynamically cache access data in the fast link memory and adjust the allocation object of the shared shard according to the access frequency.

[0072] In one possible implementation, the accessed data in the CXL memory cache is not bound to a fixed business logic, and the allocation of objects is dynamically adjusted based on the data access frequency.

[0073] In this way, even if the system runs other tasks at the same time, causing the local memory pressure to increase, the high-frequency access data in the locked area will not be squeezed out, which can reduce the latency of local memory and ensure system performance. At the same time, the shared shards will not occupy fixed data for a long time, but will be dynamically adjusted according to the data access frequency, which can improve the utilization of memory space, avoid local memory idleness, and reduce repeated access to CXL memory.

[0074] Step 202: Bind the corresponding fast-link memory address shard to the local memory shard to obtain the hierarchical cache architecture of the memory module.

[0075] In this embodiment, the hierarchical caching architecture is used to enable dynamic migration of data between local memory shards and computation fast-link memory shards.

[0076] It should be noted that in step 202, each local memory slice can be bound to one fast-link memory address slice, or multiple fast-link memory address slices can be bound to each local memory slice. Alternatively, m local memory slices can be bound to n fast-link memory address slices, where m and n are both positive integers. For example, m can be in the range [1, 4], and n can be in the range [2, 5]. In one possible implementation, a corresponding CXL memory address segment is allocated to each local memory slice, and a mapping relationship is established between the local memory slice and the computation fast link memory address slice, resulting in a hierarchical cache architecture for the memory module.

[0077] In one possible implementation, there can be a one-to-one correspondence between local memory slices and CXL memory address slices, or a one-to-many correspondence, or an m-to-n correspondence.

[0078] It's important to note that the ratio of local memory shards to compute fast link memory address shards, as well as the mapping relationship between them, are dynamically adjusted. For example, the relationship between local memory and physical memory space can be m to n+1, meaning n+1 physical address spaces map to m local memory locations. This mitigates the performance degradation when the ratio of local memory to CXL memory is 1:n. The m-to-n+1 approach is used because memory usage exhibits spatial locality, and virtual machines on the same host typically do not reach peak memory utilization simultaneously.

[0079] For example, see Figure 5 The ratio of local memory to CXL memory is 1:2. A 2:3 mapping method is used between local memory and physical memory address spaces to triple the original host memory. Furthermore, the local memory swapping frequency is periodically determined by a local memory swapping frequency monitor.

[0080] For example, the host machine has 1.5TB of local memory. A CXL memory pool is built based on CXL and DDR4 memory. The initial correspondence between the host machine's local memory and physical memory addresses is 2 to 3. The ratio of local memory to CXL memory is 1:2. The memory of each host machine is expanded to 3 times the original amount, with a total memory of 4.5TB. The maximum memory supported by virtual machines on the host machine is approximately 4.5TB.

[0081] In one possible implementation, when local memory shards are bound to compute fast link memory address shards, the system will establish a mapping table between local shard addresses and CXL shard addresses in the MMU, and configure the address routing rules of the CXL controller; when access to the local shard is not found, it will automatically route to the bound CXL shard.

[0082] In this embodiment, the fast link memory address shards are obtained from the fast link memory pool. Each shard has an independent physical address and they do not overlap. The shard boundaries are locked by the system kernel configuration to prevent data from being accessed out of bounds.

[0083] In this embodiment, the compute fast link memory pool is obtained by interconnecting multiple compute fast link memory cards via the compute fast link protocol.

[0084] For example, a CXL memory pool can be obtained by interconnecting four CXL memory cards through the CXL protocol, supporting address access and data migration across CXL memory cards. The CXL memory shards in the CXL memory pool are logical partitions and do not affect the physical hardware layout.

[0085] In this way, CXL technology is used to expand the host machine's memory through the CXL memory pool, thereby providing a CXL-based virtual machine with ultra-large memory. Secondly, local memory sharding is bound to the memory address sharding of the fast computing link, making data migration more accurate, avoiding redundant access across shards, and improving the utilization of CXL link bandwidth. Finally, the dynamic migration mechanism automatically adapts to changes in data access frequency without the need for manual adjustment of shard binding relationships, adapting to the mixed load scenarios of distributed databases.

[0086] In some embodiments, after step 202, the memory scheduling method further includes: Sub-step S1: In response to a memory access request, determine the target physical address in the memory access request; Sub-step S2: If the target physical address is within the address range of the local memory slice and the local memory slice stores the target data, read the target data from the local memory slice. Sub-step S3: If the target physical address belongs to the compute fast link memory shard or the local memory shard does not store the target data, the access request is forwarded to the compute fast link memory shard according to the mapping relationship, and the target data is read from the compute fast link memory shard.

[0087] In one possible implementation, after receiving an access request, the database uses Structured Query Language (SQL) to parse and index the data to determine the physical address corresponding to the target data.

[0088] In one possible implementation, the memory page table of the local memory slice is queried to confirm whether the target physical address belongs to the address range of the local memory slice.

[0089] In one possible implementation, if the target physical address falls within the address range of the local memory shard and the local memory shard stores the target data, the MMU directly routes the physical address to the storage unit of the local memory shard to read the target data so that the query is completed instantly.

[0090] In one possible implementation, if the target physical address falls within the address range of the local memory shard and the local memory shard stores the target data, the system forwards the access request to the CXL shard address through the CXL controller based on the mapping relationship between the local shard address and the CXL shard address; the CXL controller then resolves the target physical address and reads the target data from the corresponding CXL memory storage unit.

[0091] In one possible implementation, after reading the target data from the computationally fast link memory slice, the memory call method described above may further include: caching the target data in the free space of the local memory slice so that when the target physical address is accessed again, the local memory is hit directly.

[0092] For example, see Figure 5 Assuming A, B, and C reside in the same virtual machine, if accessing the physical address of memory A, the mapped local memory is traversed, and A is found and read directly. If accessing the physical address of memory B, the mapped local memory is similarly traversed. If the first mapped local memory is A, the second mapped local memory is traversed, and if B is found, it is read directly. If a 1-to-3 mapping relationship is used, when accessing the physical address of B, A is found in the local memory, so a swap occurs between the local memory and the CXL memory. Therefore, compared to a direct 1-to-3 mapping, where A, B, and C only map the location of A, this reduces the frequency of swapping between CXL memory and local memory, thus reducing memory performance degradation.

[0093] Step 203: Obtain the local memory swap frequency.

[0094] In this embodiment of the application, the swap frequency is the rate at which data in local memory is swapped out to the disk swap partition per unit time.

[0095] The method for this step has been explained in step 101 above, and will not be repeated here.

[0096] Step 204: If the swapping frequency is less than a preset frequency threshold, increase the proportion of fast link memory used for computation.

[0097] In this embodiment of the application, the rate at which data in local memory is swapped to the disk swap partition per unit time is used to reflect the load pressure on local memory.

[0098] Understandably, if the swapping frequency is less than the preset frequency threshold, it means that the swapping frequency is low and there is no need to frequently swap data to the disk. In other words, the local memory is idle and under low pressure, so the CXL memory ratio can be increased and the range of available address space of CXL can be expanded.

[0099] For example, the preset frequency threshold can be 50 kilobytes per second (KB / s), or it can be 100 KB / s. In practical applications, the preset frequency threshold can be set as needed.

[0100] In this embodiment, the proportion of compute fast link memory can be the percentage of CXL memory's capacity in the system's global physical address space. Increasing the proportion of compute fast link memory essentially expands the upper limit of CXL memory's allocatable capacity. For example, the system's total physical memory is 1.25TB, of which 1TB is CXL memory and 256GB is local memory, with CXL accounting for 80%.

[0101] In this embodiment, the available address space range for the fast link memory can be an independent physical address segment allocated by the system for the CXL memory. The size of the range directly corresponds to the maximum usable capacity of the CXL memory; that is, the longer the accessible address segment, the larger the allocatable CXL memory capacity. For example, the physical address segment corresponding to the available address space range is 0x80000000-0x8FFFFFFFF.

[0102] In one possible implementation, the CXL controller allocates an additional address segment in the global physical address space for the newly added CXL memory. This ensures that the new CXL memory can be recognized and accessed by the CPU. For example, the original address segment of the CXL memory, 0x80000000-0x87FFFFFFFF, is expanded to 0x80000000-0x8FFFFFFFF.

[0103] In one possible implementation, after step 204, the aforementioned inbound call method may further include: migrating data from local memory from disk to CXL memory.

[0104] Step 205: If the swapping frequency is greater than or equal to the frequency threshold, reduce the proportion of fast link memory used for computation.

[0105] It is understandable that if the swapping frequency is greater than or equal to the frequency threshold, it means that the swapping frequency is high and data needs to be swapped out frequently to free up space. In other words, local memory is tight and under pressure, which can easily lead to a surge in disk overhead and system lag.

[0106] In this embodiment of the application, reducing the proportion of computational fast link memory is used to shrink the upper limit of the allocatable capacity of CXL memory.

[0107] It's important to note that reducing the proportion of compute fast link memory (CXL) does not require shrinking the available address space of local memory. This is because the address range of local memory is fixed; shrinking the CXL proportion only releases the address range corresponding to CXL, without affecting the address range and capacity of local memory.

[0108] In some embodiments, the system first migrates the valid data stored in the CXL memory to be shrunk to the free space of the remaining CXL memory or local memory, and then releases the excess CXL address segments to avoid data loss.

[0109] For example, during peak hours of the distributed database server, the volume of business queries surges, and the local memory swapping frequency is 80KB / s, which is higher than the threshold of 50KB / s. The system automatically reduces the CXL memory ratio from 80% to 50%, releases the bus bandwidth occupied by CXL memory, and uses all local memory to cache frequently accessed order table and user table data, reducing the disk swapping frequency to 30KB / s, thereby increasing the system's query throughput by 40%.

[0110] In this way, by optimizing the mapping method of local memory and the host memory physical address consisting of CXL memory and local memory, the limitation of 1:1 between host local memory and CXL memory in Flat Memory Mode is broken. While ensuring memory performance, the amount of host expandable memory is increased, thereby providing larger virtual machines.

[0111] In some embodiments, after step 205, the memory scheduling method described above may further include: Sub-step B1: When shrinking the accessible address segment of the computational fast link memory, determine whether valid data is stored in the computational fast link memory corresponding to the accessible address segment to be shrunk by using the computational fast link controller. Sub-step B2, if valid data is stored, migrates the valid data to the remaining fast-link memory or local memory.

[0112] In this embodiment of the application, the cache partition of local memory is used to store frequently accessed data.

[0113] In one possible implementation, the system sends a CXL accessible address segment shrinkage command to the CXL controller; wherein the CXL accessible address segment shrinkage command includes the target address segment to be shrunk and the remaining CXL accessible address segment.

[0114] In one possible implementation, after receiving the instruction, the CXL controller locates the CXL memory physical region corresponding to the address segment to be reduced through its own address mapping table; and checks the data status within the CXL memory physical region.

[0115] In one possible implementation, valid data can be data that has been allocated by the business process, is in use, or has not been explicitly released; unallocated blank data and released data are both invalid data.

[0116] In one possible implementation, the CXL controller reads the metadata area of ​​the CXL memory to obtain the occupancy status of each address block; the occupancy status includes allocated or unallocated; based on the occupancy status, it is determined whether each address block stores valid data. For example, if the occupancy status is allocated, it is determined that each address block stores valid data; if the occupancy status is unallocated, it is determined that each address block does not store valid data.

[0117] In one possible implementation, if no valid data is stored, address segment shrinking is performed directly to release the corresponding CXL memory physical resources.

[0118] In another possible implementation, while storing valid data, the physical CXL memory resources corresponding to the address segment to be reduced are released through the CXL controller, thereby completing the reduction of the CXL memory ratio.

[0119] In one possible implementation, sub-step B2 may include: if valid data is stored, requesting a contiguous free address space in the remaining CXL address segment through the CXL controller; directly copying the valid data in the address segment to be reduced to the target address space of the remaining CXL through the memory-to-memory direct transfer (DMAC) function of the CX protocol; after the migration is completed, the CXL controller synchronously updates its own address mapping table and notifies the operating system to update the page table.

[0120] In another possible implementation, sub-step B2 may also include: when storing valid data, the CXL controller first requests local memory free space from the operating system so that the system can allocate a free area in local memory that matches the amount of data to be migrated, and inform the CXL controller of the physical address of the free area; the CXL controller works with the local memory controller through the CXL link to transfer the valid data in the address segment to be reduced to the free area of ​​local memory.

[0121] In some embodiments, after the migration is complete, the CXL controller notifies the operating system to update the page table; the process that originally accessed the CXL address is rebound to the new address in local memory, and the data is marked as locally resident, so that subsequent access requests will directly hit local memory.

[0122] Step 206: Based on the adjusted allocation ratio, expand or shrink the accessible address range of the fast link memory by calculating the fast link controller.

[0123] In the embodiments of this application, the accessible address segment and the address segment of local memory constitute the physical memory address space of the memory module.

[0124] In some embodiments, extending the accessible address range of compute fast link memory via the CXL controller may include binding the extended address range to free physical storage units in the CXL memory pool. For example, activating a newly added CXL memory card or enabling the unused physical space of an existing CXL memory card.

[0125] In some embodiments, an extended address range and its corresponding CXL physical storage unit are added to the internal address mapping table of the CXL controller to ensure that when the CPU accesses the address range, it can be routed to the correct CXL memory via the CXL link.

[0126] In some embodiments, shrinking the accessible address range of compute fast link memory by the CXL controller may include: deleting the mapping relationship of the address range to be shrunk from the address mapping table of the CXL controller, and determining that CPU access to the address range will be an invalid address to avoid access conflicts.

[0127] Step 207: The memory management unit updates the mapping relationship between the accessible address segment and the local memory according to the new accessible address segment.

[0128] In some embodiments, step 207 may include: adding an extended address range to the page table of the MMU; updating the mapping relationship between the local fragment address and the extended CXL address range; and synchronizing the updated page table to the CPU's Translation Lookaside Buffer (TLB) through the MMU to avoid access errors caused by address translation cache failure.

[0129] In some other embodiments, step 207 may further include: deleting the address segment to be reduced in the page table of the MMU; clearing the mapping relationship between the local fragment address and the extended CXL address segment corresponding to the address segment to be reduced; and clearing the cache entries related to the address segment to be reduced in the CPU's TLB to avoid subsequent address translation hitting invalid mappings.

[0130] In some embodiments, a cache partition of local memory is allocated through the memory management unit according to an adjusted allocation ratio.

[0131] In summary, in this embodiment, CXL technology is used to expand the host machine's memory through the CXL memory pool, thereby providing a CXL-based virtual machine with ultra-large memory. Secondly, local memory sharding is bound to the memory address sharding of the fast computing link, making data migration more accurate, avoiding redundant access across shards, and improving the utilization rate of CXL link bandwidth. Thirdly, the dynamic migration mechanism automatically adapts to changes in data access frequency without the need for manual adjustment of shard binding relationships, adapting to the mixed load scenarios of distributed databases. Finally, a local memory swap-out frequency monitor is added to dynamically adjust the relationship between the physical address space and memory mapping, thereby achieving dynamic adjustment of the host machine's CXL memory ratio.

[0132] Figure 6 This is a block diagram of a memory scheduling device provided in an embodiment of this application, such as... Figure 6 As shown, the memory scheduling device is applied to computing nodes in a virtual network and to memory modules that include local memory and fast-link memory for computing. The memory scheduling device 400 includes the following modules.

[0133] The acquisition module 401 is used to acquire the local memory swap frequency; the swap frequency is the rate at which data in local memory is swapped out to the disk swap partition per unit time. The adjustment module 402 is used to adjust the allocation ratio of local memory and computing fast link memory according to the swapping frequency and preset dynamic scheduling rules; the allocation ratio represents the proportion of computing fast link memory in the physical memory address space of the memory module. The allocation module 403 is used to allocate available space for computing fast link memory according to the adjusted allocation ratio.

[0134] Optionally, adjustment module 402 includes: The enlargement submodule is used to increase the proportion of fast link memory for computation when the swapping frequency is less than a preset frequency threshold. The reduction submodule is used to reduce the proportion of fast link memory used for computation when the swapping frequency is greater than or equal to the frequency threshold.

[0135] Optionally, the available space characterizes the range of accessible address segments. Allocation module 403 includes: The address adjustment submodule is used to expand or shrink the accessible address segment of the fast link memory according to the adjusted allocation ratio by calculating the fast link controller; the accessible address segment and the address segment of the local memory constitute the physical memory address space of the memory module.

[0136] The update submodule is used to update the mapping between the accessible address segment and local memory based on the new accessible address segment through the memory management unit.

[0137] Optionally, the memory scheduling device 400 also includes: The storage determination submodule is used to determine, through the computational fast link controller, whether valid data is stored in the computational fast link memory corresponding to the accessible address segment to be shrunk when shrinking the accessible address segment of the computational fast link memory. The data migration submodule is used to migrate valid data to the remaining fast-link memory or local memory, provided that valid data is stored.

[0138] Optionally, the memory scheduling device 400 also includes: The memory partitioning module is used to divide the local memory into multiple independent local memory slices based on the system memory topology information. The memory binding module is used to bind the corresponding fast-link memory address to the local memory shard, resulting in a hierarchical caching architecture for the memory module. The compute fast link memory address fragments are obtained from the compute fast link memory pool, which is formed by interconnecting multiple compute fast link memory cards through the compute fast link protocol.

[0139] Optionally, the memory scheduling device 400 also includes: The address determination module is used to determine the target physical address in the memory access request in response to the memory access request. The data reading module is used to read target data from the local memory slice when the target physical address is within the address range of the local memory slice and the local memory slice stores the target data. The request forwarding module is used to forward access requests to the compute fast link memory shard according to the mapping relationship when the target physical address belongs to the compute fast link memory shard or the local memory shard does not store the target data, and to read the target data from the compute fast link memory shard.

[0140] Optionally, the memory scheduling device 400 also includes: The locking setting module is used to set the local memory slice corresponding to high-frequency access data as a locked area, and low-frequency data is prohibited from replacing high-frequency access data in the locked area; The shared settings module is used to set local memory shards other than locked regions as shared shards. Shared shards are used to dynamically cache access data in fast-link memory and adjust the allocation objects of shared shards according to the access frequency.

[0141] As the device embodiment is basically similar to the method embodiment, the description is relatively simple, and relevant parts can be found in the description of the method embodiment.

[0142] Optionally, such as Figure 7 As shown, this application embodiment also provides an electronic device 500, including a processor 501 and a memory 502. The memory 502 stores a program or instructions that can run on the processor 501. When the program or instructions are executed by the processor 501, they implement the various steps of the memory scheduling method embodiment described above and can achieve the same technical effect. To avoid repetition, they will not be described again here.

[0143] It should be noted that the electronic devices in the embodiments of this application include the mobile electronic devices and non-mobile electronic devices described above.

[0144] Figure 8 A schematic diagram of the hardware structure of an electronic device to implement an embodiment of this application.

[0145] The electronic device 600 includes, but is not limited to, components such as: radio frequency unit 601, network module 602, audio output unit 603, input unit 604, sensor 605, display unit 606, user input unit 607, interface unit 608, memory 609, and processor 610.

[0146] Those skilled in the art will understand that the electronic device 600 may also include a power supply (such as a battery) for supplying power to various components. The power supply may be logically connected to the processor 610 through a power management system, thereby enabling functions such as managing charging, discharging, and power consumption through the power management system. Figure 8 The electronic device structure shown does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown, or combine certain components, or have different component arrangements, which will not be elaborated here.

[0147] The processor 610 is used to implement the memory scheduling method described above.

[0148] It should be understood that, in this embodiment, the input unit 604 may include a graphics processing unit (GPU) 6041 and a microphone 6042. The GPU 6041 processes image data of still images or videos obtained by an image capture device (such as a camera) in video capture mode or image capture mode. The display unit 606 may include a display panel 6061, which may be configured in the form of a liquid crystal display, an organic light-emitting diode, or the like. The user input unit 607 includes at least one of a touch panel 6071 and other input devices 6072. The touch panel 6071 is also called a touch screen. The touch panel 6071 may include a touch detection device and a touch controller. Other input devices 6072 may include, but are not limited to, physical keyboards, function keys (such as volume control buttons, power buttons, etc.), trackballs, mice, and joysticks, which will not be described in detail here.

[0149] The memory 609 can be used to store software programs and various data. The memory 609 may primarily include a first storage area for storing programs or instructions and a second storage area for storing data. The first storage area may store the operating system, application programs, or instructions required for functions (such as sound playback functions, image playback functions, etc.). Furthermore, the memory 609 may include volatile memory or non-volatile memory, or it may include both volatile and non-volatile memory. The non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (Synchlink DRAM, SLDRAM), and direct memory bus RAM (DRRAM). The memory 609 in this embodiment includes, but is not limited to, these and any other suitable types of memory.

[0150] Processor 610 may include one or more processing units; optionally, processor 610 integrates an application processor and a modem processor, wherein the application processor mainly handles operations involving the operating system, user interface, and applications, and the modem processor mainly handles wireless communication signals, such as a baseband processor. It is understood that the aforementioned modem processor may also not be integrated into processor 610.

[0151] This application also provides a readable storage medium storing a program or instructions. When the program or instructions are executed by a processor, they implement the various processes of the memory scheduling method embodiments described above and achieve the same technical effect. To avoid repetition, they will not be described again here.

[0152] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0153] This application also provides a chip, which includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is used to run programs or instructions to implement the various processes of the memory scheduling method embodiments described above, and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0154] It should be understood that the chip mentioned in the embodiments of this application may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0155] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0156] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0157] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A memory scheduling method, characterized by, The method is applied to a memory module including a local memory and a compute express link memory, and comprises the following steps: an out frequency of the local memory is obtained; the out frequency is a rate of data in the local memory being swapped out to a disk swap partition per unit time; an allocation ratio of the local memory and the compute express link memory is adjusted according to the out frequency and a preset dynamic scheduling rule; the allocation ratio represents a proportion of the compute express link memory in a physical memory address space of the memory module; available space of the compute express link memory is allocated according to the adjusted allocation ratio.

2. The method of claim 1, wherein, The step of adjusting the allocation ratio of the local memory and the compute express link memory according to the out frequency and the preset dynamic scheduling rule comprises the following steps: in a case where the out frequency is less than a preset frequency threshold, the proportion of the compute express link memory is increased; in a case where the out frequency is greater than or equal to the frequency threshold, the proportion of the compute express link memory is decreased.

3. The method of claim 1, wherein, The available space represents a range of an accessible address segment, and the step of allocating the available space of the compute express link memory according to the adjusted allocation ratio comprises the following steps: an accessible address segment of the compute express link memory is extended or shrunk by a compute express link controller according to the adjusted allocation ratio; the accessible address segment and an address segment of the local memory constitute a physical memory address space of the memory module. a mapping relationship between the accessible address segment and the local memory is updated by a memory management unit according to the new accessible address segment.

4. The method of claim 3, wherein, After the step of extending or shrinking the accessible address segment of the compute express link memory by the compute express link controller according to the adjusted allocation ratio, the method further comprises the following steps: in a case where the accessible address segment of the compute express link memory is shrunk, it is determined by the compute express link controller whether valid data is stored in the compute express link memory corresponding to the to-be-reduced accessible address segment; in a case where the valid data is stored, the valid data is migrated to remaining compute express link memory or the local memory.

5. The method of claim 1, wherein, Before the step of obtaining the out frequency of the local memory, the method further comprises the following steps: the local memory is divided into a plurality of independent local memory shards according to system storage topology information; a corresponding compute express link memory address shard is bound to each local memory shard to obtain a hierarchical cache architecture of the memory module; wherein the compute express link memory address shard is obtained by dividing a compute express link memory pool, and the compute express link memory pool is obtained by interconnecting a plurality of compute express link memory cards through a compute express link protocol.

6. The method of claim 5, wherein, After the step of establishing the mapping relationship between the local memory shard and the compute express link memory shard to obtain the hierarchical cache architecture of the memory module, the method further comprises the following steps: a target physical address in a memory access request is determined in response to the memory access request; in a case where the target physical address belongs to an address range of the local memory shard and the local memory shard stores target data, the target data is read from the local memory shard; In a case that the target physical address belongs to the compute express link memory segment, or the local memory segment does not store the target data, the access request is forwarded to the compute express link memory segment according to the mapping relationship, and the target data is read from the compute express link memory segment.

7. The method of claim 5, wherein, After the local memory is divided into a plurality of independent local memory segments according to the system storage topology information, the method further comprises: setting the local memory segment corresponding to the high-frequency access data as a lock region, and prohibiting low-frequency data from replacing the high-frequency access data in the lock region; setting the local memory segments other than the lock region as shared segments, and using the shared segments to dynamically cache access data in the compute express link memory and adjust allocation objects of the shared segments according to access frequencies.

8. A memory scheduling apparatus, comprising: The device is applied to a memory module including a local memory and a compute express link memory, and comprises: an obtaining module configured to obtain an eviction frequency of the local memory; the eviction frequency is a rate at which data in the local memory is evicted to a disk exchange partition per unit time; an adjusting module configured to adjust an allocation ratio of the local memory and the compute express link memory according to the eviction frequency and a preset dynamic scheduling rule; the allocation ratio represents a proportion of the compute express link memory in a physical memory address space of the memory module; an allocating module configured to allocate available space of the compute express link memory according to the adjusted allocation ratio.

9. An electronic device, comprising: The device comprises a processor, a memory, and a program or instruction stored on the memory and executable on the processor, and the program or instruction is executed by the processor to implement steps of the memory scheduling method according to any one of claims 1-7.

10. A readable storage medium, characterized by, The readable storage medium stores a program or instruction, and the program or instruction is executed by the processor to implement steps of the memory scheduling method according to any one of claims 1-7.

Images