Matrix data protocol processing device and method

Abstract

The invention discloses a matrix data protocol processing device and method. According to the embodiment of the invention, a cooperative effect is achieved under a closed loop of tile loading, hardware grouping rearrangement, parallel protocol and fixed prefix slot single-beat write-back; according to the method, higher throughput, lower end-to-end delay, less data migration / instruction quantity and better energy efficiency are obtained under the same example and resource constraint, and consistent and efficient hardware support is provided for a matrix protocol in the row / column direction through a unified instruction interface.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of computer architecture and data processing technology, and in particular to a matrix data reduction processing device and method. BACKGROUND

[0002] As a core tool of linear algebra, matrix data is widely used in scientific computing, engineering simulation, graphics and images, machine learning and data analysis, etc. Due to the hierarchical storage system and memory locality of modern processors, the performance of matrix operation depends largely on data layout and access pattern. How to improve the efficiency of matrix operation in large-scale scenarios has become a technical problem to be solved in the field. SUMMARY

[0003] The present application provides a matrix data reduction processing device and method, which can reduce the calculation time and improve the efficiency of matrix operation.

[0004] The present application provides a matrix data reduction processing device, comprising: a data read-write interface, a vector register, a decoder, an input data buffer module, a data arrangement module, a reduction operation module, and an output data buffer module; wherein: The data read-write interface is configured to exchange data with an external memory and read the matrix data to be processed into the vector register; wherein the matrix data to be processed is MxN matrix data stored in m x n sub-block format; The vector register is configured to load data from the data read-write interface and form data composed of p x n elements of a sub-block when triggered to perform matrix data reduction processing; wherein m is divisible by p, M, N, m, n, and p are positive integers and M ≥ m ≥ p ≥ 1, N ≥ n ≥ 1; The decoder is configured to generate corresponding function control signals according to the reduction instruction; The input data buffer module is configured to buffer p x n elements from the vector register in blocks according to the function control signals from the decoder; The data arrangement module is configured to rearrange the buffered p x n elements into p groups of n-element row vectors in row mode or n groups of p-element column vectors in column mode according to the function control signals from the decoder; The reduction operation module includes parallel reduction channels corresponding to the output group number, and is configured to perform the reduction indicated by the operation code on p groups of row vectors to simultaneously generate p reduction results, or perform the reduction indicated by the operation code on n groups of column vectors to simultaneously generate n reduction results; The output data buffer module is configured to buffer the output p or n reduction results.

[0005] In an example, the number of parallel reduction lanes of the reduction operation module corresponds to the number p or n of output groups, and each of the parallel reduction lanes is configured to perform a reduction operation on a group of input vectors in the same clock cycle to output the p reduction results or the n reduction results simultaneously.

[0006] In an example, the output data buffer module buffers and writes back the p reduction results or the n reduction results in a fixed order.

[0007] In an example, the decoder is configured to parse the reduction instruction into the function control signals, the reduction instruction including a row / column mode bit, a reduction opcode, a destination register identifier, a source register identifier, and an optional mask / segment length field.

[0008] In an example, the function control signals include a row / column selection signal and a function selection signal.

[0009] In an example, the reduction instruction format is: instruction destination register, source register; where the instruction is a reduction operation indicated by a reduction opcode.

[0010] In an example, the reduction operation indicated by the reduction opcode includes at least one of: accumulation, multiplication, maximum, minimum, AND, OR, XOR.

[0011] Embodiments of the present application also provide a matrix data reduction processing method, including: preprocessing the matrix data to be processed to obtain M×N matrix data stored in an m×n tile format, where M, N, m, and n are positive integers and M ≥ m ≥ 1 and N ≥ n ≥ 1; loading the matrix data to be processed to form p×n elements of a tile, where m is divisible by p, and M, N, m, n, and p are positive integers and M ≥ m ≥ p ≥ 1 and N ≥ n ≥ 1; rearranging the buffered p×n elements into p groups of n-element row vectors in row mode or n groups of p-element column vectors in column mode according to the current function control signal; performing a reduction operation indicated by the opcode on the p groups of row vectors to simultaneously generate p reduction results or on the n groups of column vectors to simultaneously generate n reduction results; buffering the p or n reduction results.

[0012] The embodiment of the present application further provides a computer readable storage medium, which stores computer executable instructions, and the computer executable instructions are used for the matrix data reduction processing method.

[0013] The embodiment of the present application further provides a computer device, which comprises a memory and a processor, wherein the memory stores instructions executable by the processor, and the instructions are used for performing the steps of the matrix data reduction processing method.

[0014] The matrix data reduction processing device provided by the embodiment of the present application realizes higher throughput, lower end-to-end delay, less data movement / instruction quantity and better energy efficiency under the same calculation example and resource constraint by tile loading, hardware grouping rearrangement and parallel reduction, and provides consistent and efficient hardware support for row / column direction matrix reduction through a unified instruction interface. The device is especially suitable for improving the efficiency of matrix operation in a large matrix scenario.

[0015] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent to those skilled in the art from the description, or can be learned by practice of the present application. The objects and other advantages of the present application can be achieved and obtained by the structure particularly pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF DRAWINGS

[0016] The accompanying drawings are included to provide a further understanding of the technical scheme of the present application, and constitute a part of the specification, and are used to explain the technical scheme of the present application together with the embodiments of the present application, and do not constitute a limitation on the technical scheme of the present application.

[0017] Figure 1 FIG. 1 is a schematic diagram of the component structure of the matrix data reduction processing device in the embodiment of the present application; Figure 2 FIG. 2 is a flowchart of the matrix data reduction processing method in the embodiment of the present application. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical scheme and advantages of the present application more clear, the embodiments of the present application will be described in detail below with reference to the drawings. It should be noted that, in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined with each other at will.

[0019] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the related drawings. The embodiments of the present application are shown in the drawings. However, the present application can be realized in many different forms, and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0021] It is understood that the terms "first" and "second" used in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0022] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0023] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0024] The steps illustrated in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases the steps shown or described may be performed in a different order than that presented here.

[0025] With the rise of deep learning models, exemplified by Transformer, computations increasingly involve axis-based (row / column) reduction operations (such as summation, maximum / minimum, mean / variance). Under real-world workloads involving large dimensions and long sequences, reduction performance is not only affected by computational power but also constrained by memory access efficiency determined by storage hierarchy and data layout. Therefore, without altering the upper-level tensor interface and common linear storage layouts (row-major / column-major), how to efficiently perform large-scale matrix reduction operations simultaneously on rows and columns with higher parallelism and lower data transfer overhead, while balancing throughput and energy efficiency, has become a crucial challenge in this field.

[0026] In practice, optimizations have been made at multiple levels: On the software and library side, block / blocking and packing, transposition, and cache-friendly traversal are used to improve locality; a general instruction set provides vector reduction primitives and combines shuffle / permute to generate scalar or segmented reduction results; on the hardware side, dedicated circuits and data layout schemes supporting vector / segmented reduction have also emerged. These paths alleviate memory access bottlenecks to some extent, but to accommodate column-oriented access, pre-rearrangement (transposition, packing, block) is often required, introducing additional copying and write-back, resulting in I / O amplification and increased power consumption; under a unified layout, simultaneously and efficiently supporting row / column reduction usually relies on a large number of rearrangement sequences, increasing the number of instructions and dependency chains, thus limiting end-to-end throughput; in addition, the coupling between the reduction unit and the storage / bus protocol is limited, and the ability for cross-block and cross-axis parallel collaboration and complex reduction within a single memory access is insufficient.

[0027] Under the current computing units and supporting computer instruction framework, given the conventional data memory layout, row-based reduction allows for the continuous reading of multiple elements in the same row. However, column-based reduction often results in long-step accesses across cache rows, limiting actual parallelism and reducing memory access efficiency. Furthermore, data rearrangement to circumvent this problem introduces additional data movement and latency. Therefore, in large matrix scenarios with hundreds or even thousands of dimensions, the reduction process can easily become a bottleneck for overall performance and energy efficiency.

[0028] Therefore, this application proposes a matrix data reduction processing device, including: a data read / write interface, a vector register, a decoder, an input data buffer module, a data sorting module, a reduction operation module, and an output data buffer module; wherein: The data read / write interface is configured to exchange data with external memory, reading the matrix data to be processed into a vector register; wherein the matrix data to be processed is M×N matrix data stored in m×n tile format. In this embodiment, by loading the matrix data to be processed in units of tiles, the cache / bandwidth utilization and locality are improved, and the number of discrete accesses and bursts across rows and columns is reduced, thereby reducing memory access latency and bus power consumption.

[0029] The vector register is configured to load data from the data read / write interface and form a data block of p×n elements when matrix data reduction is triggered, where m is divisible by p, and M, N, m, n, and p are positive integers with M ≥ m ≥ p ≥ 1 and N ≥ n ≥ 1. This loading allows each reduction to directly cover the p-row × n-column data surface, reducing the number of loading rounds and boundary handling overhead, thereby shortening the preparation phase latency.

[0030] The decoder is configured to generate corresponding function control signals according to the reduction instructions. In some embodiments, the function control signals include, but are not limited to, row / column selection signals and function selection signals, such as row / column mode bits and reduction opcodes (SUM, MAX, MIN, AND, OR, or XOR, etc.). The function selection signals at least indicate the reduction operation type and the output write-back option. In this embodiment, row / column and operation type are selected in a direct instruction-control manner, eliminating the need for explicit software rearrangement / judgment, reducing the number of instructions and control branches.

[0031] The input data buffer module is configured to buffer p×n elements from the vector register in its entirety, according to the function control signal from the decoder.

[0032] The data preparation module is configured to rearrange the buffered p×n elements into p groups of n-element row vectors in row mode, and into n groups of p-element column vectors in column mode, based on the function control signals from the decoder. In other words, the data preparation module groups and organizes the input data according to the function control signals to facilitate operations by the reduction module. For a large matrix, either row operations or column operations are performed. If row operations are performed, the submatrix must also be row-operated; if column operations are performed, the submatrix must also be column-operated. The choice between row and column operations is based on the algorithm to be implemented.

[0033] The reduction operation module, including parallel reduction channels corresponding to the number of output groups, is configured to perform reduction on p groups of row vectors indicated by opcodes to simultaneously produce p (row-mode) reduction results; or, to perform reduction on n groups of column vectors indicated by opcodes to simultaneously produce n (column-mode) reduction results. Compared to traditional reduction paths that produce only one reduction result at a time, simultaneously producing p or n reduction results linearly improves parallelism, shortens the total reduction latency, and reduces register / cache round trips. In one embodiment, the p row operations are the same reduction operations; for example, if the maximum value of each row is required for p rows of data, then a maximum value operation is performed on each row. The same applies to submatrices; the ultimate goal is to find a specific reduction operation for the entire large matrix. In one embodiment, the reduction operation may include, but is not limited to, operations such as accumulation, multiplication, finding the maximum value, finding the minimum value, AND, OR, XOR, etc.

[0034] The output data buffer module is configured to buffer p or n reduction results. In one embodiment, p or n reduction results are output and placed into a register in sequence.

[0035] In this embodiment, the protocol instruction is the input command, and the function control signal is the execution control after the protocol instruction is decoded. The opcode is a key field in the protocol instruction, which determines the value of the operation selection signal in the function control signal.

[0036] The matrix data reduction processing device provided in this application embodiment works in a closed loop with tile loading, hardware group rearrangement, parallel reduction, and fixed prefix slot single-cycle write-back. This achieves higher throughput, lower end-to-end latency, fewer data moves / instructions, and better energy efficiency under the same computational and resource constraints. It also provides consistent and efficient hardware support for matrix reduction in the row / column direction with a unified instruction interface.

[0037] This application also provides a matrix data reduction processing method, such as... Figure 2 As shown, it includes: Step 200: Preprocess the matrix data to be processed to obtain M×N matrix data stored in m×n tile format, where M, N, m, and n are positive integers and M ≥ m ≥ 1, N ≥ n ≥ 1.

[0038] In one exemplary instance, step 200 divides a matrix A of size M×N into (M / m)×(N / n) submatrices of size m×n. , ... , ...and all submatrices are stored in memory in row-major order, with each submatrix's internal data also stored in row-major order. The size of m×n can be pre-defined and is generally adapted to the computer's matrix operation unit. In one embodiment, if all matrices in the entire Transformer operation are stored according to this rule, and the computer's operation unit is adapted to this storage method, then only the initial data needs to be processed once; matrices generated during the intermediate operation will naturally be stored according to this rule.

[0039] For example, a 16×16 matrix A can be divided into 2×2 8×8 submatrices. , , , And store it in memory. Assume the original matrix A is as follows: where the numbers represent the original memory location of each data point in the matrix: Therefore, a submatrix can include: Stored in memory as: 1,2......8,17,18......24,......9,10......16,25,26......32,129,130......136,145,146......152,......137,138......144,153,154......160,249,250......256 Step 201: During matrix data reduction processing, load the matrix data to be processed and form data consisting of p×n elements of a certain sub-block, where m is divisible by p, M, N, m, n, and p are positive integers and M ≥ m ≥ p ≥ 1, N ≥ n ≥ 1.

[0040] In one exemplary instance, m, n, and p are constrained by computer hardware conditions and can also be adjusted through later configuration. m×n is a pre-defined size. Taking a chip with m=32, n=32, and p=4 as an example, the matrix operation unit is 32×32, the vector register size is 128, and p can also be selected as 2 based on the vector register size and the matrix operation unit.

[0041] Step 202: Based on the current function control signal, in row mode, rearrange the buffered p×n elements into p groups of n elements into a row vector, and in column mode, rearrange the buffered p×n elements into n groups of p elements into a column vector.

[0042] In one exemplary instance, for a large matrix, either row operations or column operations are performed. Taking row operations as an example, submatrices must also be subjected to row operations.

[0043] Based on the current function control signal, i.e., the algorithm to be implemented, the choice can be made between row operations and column operations. For row operation control signals, the p×n input data are grouped into groups of n data, for a total of p groups. For column operation control signals, the p×n input data are grouped into groups of the 1st, n+1st, 2n+1st...(p-1)n+1st data, the 2nd, n+2nd, 2n+2nd...(p-1)n+2nd data, and so on, with the last group consisting of the nth, 2×n, 3×n...p×n data, for a total of n groups.

[0044] Step 203: Perform reduction on p groups of row vectors as indicated by the opcode to produce p reduction results simultaneously; or, perform reduction on n groups of column vectors as indicated by the opcode to produce n reduction results simultaneously.

[0045] In this step, for row operations, the p input data sets are reduced row by row, producing p reduced results. The p row operations are identical; for example, if the maximum value is to be found in each of the p rows, then a maximum value operation is performed on each row. The same applies to submatrices; the ultimate goal is to find a specific reduction operation for the entire large matrix. For column operations, the n input data sets are reduced column by column, producing n reduced results.

[0046] In one embodiment, the reduction operation may include, but is not limited to, addition, multiplication, taking the maximum value, taking the minimum value, AND, OR, XOR, etc.

[0047] Step 204: Buffer p or n reduction results.

[0048] In one exemplary instance, the output consists of p reduction results or n reduction results, which can be placed into the register in sequence.

[0049] Let's look at a few examples to see how reduction operations are implemented. Based on the above... Taking a submatrix as an example, assuming m=8, n=8, p=4, the numbers in the submatrix represent the positions of the data in the original matrix: ; Assume the reduction operation is a pair If the submatrix is ​​summed row by row, then m / p = 2 calculations are required. In the first calculation, the data input to the first vector register is data with serial numbers 1, 2......8, 17, 18......24,......49, 50......56; The data processing module divides the data into the following 4 groups: ; ; ; ; Summing each set of data yields: ; ; ; ; The first summation results SUM1 to SUM4 are used as output data. After being buffered, they are output as the reduction operation result R1.

[0050] In the second calculation, the data input to the second vector register is the data with serial numbers 65, 66......72, 81, 82......88, 113, 114......120; The data processing module divides the data into the following 4 groups: ; ; ; ; Summing each set of data yields: ; ; ; ; The summation results SUM1 to SUM4 from the second time are used as output data. After being buffered, they are output as the reduction operation result R2. Combining the results R1 and R2 from the two reduction operations, the eight SUM results are: The result of row-by-row summation of the submatrices. It should be noted that the merging instruction can be a standard or extended instruction of a general processor; the specific implementation is not intended to limit the scope of protection of this application.

[0051] Assume the reduction operation is a pair If the submatrix is ​​taken by taking the maximum value of each column, then... The data input to the first vector register is the data with serial numbers 1, 2......8, 17, 18......24,......49, 50......56; the data input to the second vector register is the data with serial numbers 65, 66......72, 81, 82......88, 113, 114......120. Using a standard vector maximum instruction, the data at each position of the two vectors is compared, and the maximum value is stored as the result in the third vector register. It should be noted that the standard vector maximum instruction is a standard or extended instruction for general processors, and its specific implementation is not intended to limit the scope of protection of this application. Assume the data in the third vector register is: ; The data processing module then divides the data into the following 8 groups: ; ; ; ; ; ; ; ; Find the maximum value for each set of data. ; ; ; ; ; ; ; ; The results MAX1 to MAX8 obtained by finding the maximum value are used as output data. After being buffered, they are output as the result of the reduction operation. The result of taking the maximum value of each column of the submatrix.

[0052] To complement the matrix data reduction processing method in the embodiments of this application, several instructions for calling the aforementioned reduction operation unit are also provided, with the format: instruction destination register, source register. For example: The instruction format for row-by-row accumulation is: VREDRSUM dst, src; The command format for column-wise accumulation is: VREDCSUM dst, src; The instruction format for retrieving the maximum value from each row is: VREDRMAX dst, src; The command format for retrieving the maximum value by column is: VREDCMAX dst, src; The command format for retrieving the minimum value from each row is: VREDRMIN dst, src; The command format for retrieving the minimum value by column is: VREDCMIN dst, src.

[0053] In the above instruction characters, VRED represents a vector reduction operation, R represents row operations, C represents column operations, and abbreviations such as SUM, MAX, and MIN represent reduction operations. It should be noted that the above are merely examples and are not intended to limit the scope of protection of this application.

[0054] Taking the row summation of matrix A mentioned above as an example, assuming m=8, n=8, p=4, and the vector register stores 32 data.

[0055] Traditional arithmetic units and their associated computer instructions are represented using pseudocode. Data is stored in memory according to the traditional layout. The instructions are as follows: LOAD V1, &1 / / Read data from the address of the first data and put it into vector register V1; CLEAR V1 / / Sets the 16th to 32nd data in the register to 0; VREDSUM V1, V1 / / Reduce summation, storing one result in vector register V1; LOAD V2, &17 / / Read data from the address of the 17th data point into vector register V2; CLEAR V2 / / Sets the 16th to 32nd data in the register to 0; VREDSUM V2, V2 / / Reduce summation, store one result in vector register V2; ...... LOAD V16, &241 / / Read data from the address of data number 241 into vector register V16; CLEAR V16 / / Sets the 16th to 32nd data in the register to 0; VREDSUM V16, V16 / / Reduce summation, storing one result in vector register V6; CONCUT V21, V1, V2, 1 CONCUT V22, V3, V4, 1 CONCUT V23, V5, V6, 1 CONCUT V24, V7, V8, 1 CONCUT V25, V9, V10, 1 CONCUT V26, V11, V12, 1 CONCUT V27, V13, V14, 1 CONCUT V28, V15, V16, 1 CONCUT V41, V21, V22, 2 CONCUT V42, V23, V24, 2 CONCUT V43, V25, V26, 2 CONCUT V44, V27, V28, 2 CONCUT V61, V41, V42, 4 CONCUT V62, V43, V44, 4 CONCUT V17, V61, V62, 8 / / Concatenate the first data in registers V1 to V16 in sequence and store it in register V17; The result in vector register V17 is the result of summing matrix A by row.

[0056] Assuming each instruction takes one clock cycle to execute, a total of 3 × 16 + 15 = 63 clock cycles are required.

[0057] The arithmetic unit and its associated computer instructions in this embodiment are represented using pseudocode, and the data is arranged according to sub-matrices. , , , The arrangement is stored in memory, as instructed below: LOAD V1, &1 / / Read data from the address of the first data and put it into vector register V1; LOAD V2, &65 / / Read data from the address of the 65th data point into vector register V2; LOAD V3, &9 / / Read data from the address of the 9th data point into vector register V3; LOAD V4, &73 / / Read data from the address of the 73rd data point into vector register V4; LOAD V5, &129 / / Read data from the address of data number 129 into vector register V5; LOAD V6, &193 / / Read data from the address of data number 193 into vector register V6; LOAD V7, &137 / / Read data from the address of data number 137 into vector register V7; LOAD V8, &201 / / Read data from the address of data number 201 into vector register V8; VSUM V21, V1, V3 VSUM V22, V2, V4 VSUM V23, V5, V7 VSUM V24, V6, V8 / / Adds the data in the same row in half; VREDRSUM V41,V21 VREDRSUM V42,V22 VREDRSUM V43, V23 VREDRSUM V44,V24 / / Protocol calculation; CONCUT V61, V41, V42, 4 CONCUT V62, V43, V44, 4 CONCUT V17, V61, V62, 8 / / Concatenate the first four data entries from registers V41 to V44 in sequence and store them in register V17; The result in vector register V17 is the result of summing matrix A by row.

[0058] Assuming each instruction takes one clock cycle to execute, a total of 19 clock cycles are required. Compared to traditional arithmetic units and their associated computer instructions, this significantly reduces computation time.

[0059] Taking the example of finding the maximum value of matrix A by column in the above text, assuming m=8, n=8, p=4, and the vector register stores 32 data.

[0060] Traditional arithmetic units and their associated computer instructions are represented using pseudocode. Data is stored in memory according to the traditional layout. The instructions are as follows: LOAD V1, &1 / / Read data from the address of the first data and put it into vector register V1; CLEAR V1 / / Sets the 16th to 32nd data in the register to 0; LOAD V2, &17 / / Read data from the address of the 17th data point into vector register V2; CLEAR V2 / / Sets the 16th to 32nd data in the register to 0; ...... LOAD V16, &241 / / Read data from the address of data number 241 into vector register V16; CLEAR V16 / / Sets the 16th to 32nd data in the register to 0; VMAX V21, V1, V2 / / Compare the maximum value of each element in V1 and V2 and put it into V21; VMAX V22, V3, V4 / / Compare the maximum value of each element in V3 and V4 and put it into V22; VMAX V23, V5, V6 / / Compare the maximum value of each element in V5 and V6 and put it into V23; VMAX V24, V7, V8 / / Compare the maximum value of each element in V7 and V8 and put it into V24; VMAX V25, V9, V10 / / Compare the maximum value of each element in V9 and V10 and put it into V25; VMAX V26, V11, V12 / / Compare the maximum value of each element in V11 and V12 and put it into V26; VMAX V27, V13, V14 / / Compare the maximum value of each element in V13 and V14 and put it into V27; VMAX V28, V15, V16 / / Compare the maximum value of each element in V15 and V16 and put it into V28; VMAX V41, V21, V22 / / Compare the maximum value of each element in V21 and V22 and put it into V41; VMAX V42, V23, V24 / / Compare the maximum value of each element in V23 and V24 and put it into V42; VMAX V43, V25, V26 / / Compare the maximum value of each element in V25 and V26 and put it into V43; VMAX V44, V27, V28 / / Compare the maximum value of each element in V27 and V28 and put it into V44; VMAX V61, V41, V42 / / Compare the maximum value of each element in V41 and V42 and put it into V61; VMAX V62, V43, V44 / / Compare the maximum value of each element in V43 and V44 and put it into V62; VMAX V17, V61, V62 / / Compare the maximum value of each element in V61 and V62 and put it into V17; The result in vector register V17 is the result of finding the maximum value of matrix A column by column.

[0061] Assuming each instruction takes one clock cycle to execute, a total of 32 + 8 + 4 + 2 + 1 = 47 clock cycles are required.

[0062] The arithmetic unit and its associated computer instructions in this embodiment are represented using pseudocode, and the data is arranged according to sub-matrices. , , , The arrangement is stored in memory, as instructed below: LOAD V1, &1 / / Read data from the address of the first data and put it into vector register V1; LOAD V2, &65 / / Read data from the address of the 65th data point into vector register V2; LOAD V3, &9 / / Read data from the address of the 9th data point into vector register V3; LOAD V4, &73 / / Read data from the address of the 73rd data point into vector register V4; LOAD V5, &129 / / Read data from the address of data number 129 into vector register V5; LOAD V6, &193 / / Read data from the address of data number 193 into vector register V6; LOAD V7, &137 / / Read data from the address of data number 137 into vector register V7; LOAD V8, &201 / / Read data from the address of data 201 into vector register V8 VMAX V21, V1, V5 VMAX V22, V2, V6 VMAX V23, V3, V7 VMAX V24, V4, V8 / / Halving comparison of maximum value; VMAX V41, V21, V22 VMAX V42, V23, V24 / / MAX4; VREDCMAX V41, V41 VREDCMAX V42, V42 / / Maximum value reduced by column; CONCUT V17, V41, V42, 8 / / Concatenate the maximum values ​​of the first 8 columns and the last 8 columns, and put them into V17; The result in vector register V17 is the result of finding the maximum value of matrix A column by column.

[0063] Assuming each instruction takes one clock cycle to execute, a total of 17 clock cycles are required. Compared to traditional arithmetic units and their associated computer instructions, this significantly reduces computation time.

[0064] This application also provides a computer-readable storage medium storing computer-executable instructions for performing the matrix data reduction processing method described in any of the above claims.

[0065] This application further provides a computer device, including a memory and a processor, wherein the memory stores the following instructions executable by the processor: steps for performing the matrix data reduction processing method described in any of the preceding claims.

[0066] Although the embodiments disclosed in this application are as described above, the content described is merely for the purpose of understanding this application and is not intended to limit this application. Any person skilled in the art to which this application pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application; however, the scope of patent protection of this application shall still be determined by the scope defined in the appended claims.

Claims

1. A matrix data reduction processing device, characterized by, The application comprises a data read-write interface, a vector register, a decoder, an input data buffer module, a data arrangement module, a reduction operation module, and an output data buffer module. The data read-write interface is configured to exchange data with an external memory and read matrix data to be processed into the vector register. The vector register is configured to load data from the data read-write interface and form data composed of p×n elements of a tile when triggered to perform reduction processing on matrix data. The decoder is configured to generate corresponding function control signals according to a reduction instruction. The input data buffer module is configured to buffer p×n elements from the vector register in a block according to the function control signals from the decoder. The data arrangement module is configured to rearrange the buffered p×n elements into p groups of n-element row vectors in a row mode or n groups of p-element column vectors in a column mode according to the function control signals from the decoder. The reduction operation module comprises parallel reduction channels corresponding to the output group number and is configured to perform a reduction indicated by an operation code on p groups of row vectors to simultaneously generate p reduction results or perform a reduction indicated by an operation code on n groups of column vectors to simultaneously generate n reduction results. The output data buffer module is configured to buffer the output p or n reduction results. The number of parallel reduction channels of the reduction operation module corresponds to the output group number p or n, and each parallel reduction channel is configured to perform a reduction operation on a group of input vectors in the same clock cycle to simultaneously output the p reduction results or the n reduction results.

2. The matrix data reduction processing device of claim 1, wherein, The output data buffer module buffers and writes back the p reduction results or the n reduction results in a fixed order.

3. The matrix data reduction processing device of claim 1, wherein, The decoder is configured to parse the reduction instruction into the function control signals, and the reduction instruction comprises a row / column mode bit, a reduction operation code, a destination register identifier, a source register identifier, and an optional mask / segment length field.

4. The matrix data reduction processing device according to any one of claims 1 to 3, wherein, The function control signals comprise a row / column selection signal and a function selection signal.

5. The matrix data reduction processing device of claim 4, wherein, The reduction instruction format is: instruction destination register, source register; wherein the instruction is a reduction operation indicated by a reduction code.

6. The matrix data reduction processing device of claim 4, wherein, The reduction operation indicated by the reduction code comprises at least one of the following: accumulation, multiplication, maximum value taking, minimum value taking, AND, OR, and XOR.

7. The matrix data reduction processing device of claim 6, wherein, The application comprises the following steps:

8. A method of processing matrix data reduction, characterized by, Preprocessing matrix data to be processed to obtain M×N matrix data stored in an m×n tile format, wherein M, N, m, and n are positive integers and M ≥ m ≥ 1 and N ≥ n ≥ 1; Loading the matrix data to be processed and forming data composed of p×n elements of a tile when performing reduction processing on matrix data, wherein m is divisible by p, M, N, m, n, and p are positive integers and M ≥ m ≥ p ≥ 1 and N ≥ n ≥ 1; ​ According to the current function control signal, the buffered p x n elements are rearranged into p groups of n-element row vectors in the row mode, or into n groups of p-element column vectors in the column mode; The reduction indicated by the operation code is performed on the p groups of row vectors to simultaneously generate p reduction results, or on the n groups of column vectors to simultaneously generate n reduction results; The p or n reduction results are cached as output.

9. A computer readable storage medium storing computer executable instructions for performing the matrix data reduction processing method of claim 8.

10. A computer device comprising a memory and a processor, wherein, The memory stores instructions executable by the processor for performing the steps of the matrix data reduction processing method of claim 8.

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