Discharge circuit, negative voltage power supply, and electronic device

Abstract

The application belongs to the technical field of electronic circuits, and provides a discharge circuit, a negative voltage power supply and an electronic device. The discharge circuit comprises a logic module, a switch module and a capacitor module. A first end of the logic module is used for receiving a power supply voltage. A second end of the logic module is used for receiving an enable signal. A third end of the logic module is connected with a first end of the capacitor module. A fourth end of the logic module and a first end of the switch module are both used for grounding. A fifth end of the logic module is connected with a second end of the switch module. A third end of the switch module is used for being connected with a negative voltage node. A second end of the capacitor module is used for grounding or being connected with the negative voltage node. The discharge circuit provided in the application realizes fast and complete discharge of the voltage of the negative voltage node, and simultaneously realizes zero static power consumption. The problems of slow discharge speed, high power consumption and inability to realize complete discharge existing in the prior negative voltage discharge scheme are solved, and the reliability of the system is improved.

Description

Technical Field

[0001] This application belongs to the field of electronic circuit technology, and in particular relates to a discharge circuit, a negative voltage power supply, and an electronic device. Background Technology

[0002] In the field of electronic circuits and power management, negative voltage power supplies containing energy storage capacitors, such as negative charge pumps and negative power supplies for LCD screens, are prone to system reset anomalies, restart failures, and LCD screen flickering or display problems after being turned off or losing power. This is because the residual charge in the internal capacitors cannot be released quickly enough. To ensure the reliability of the system under frequent power-on and power-off scenarios, a discharge circuit needs to be introduced.

[0003] Existing negative voltage discharge schemes are mainly divided into two categories: one is the passive resistor discharge scheme, which uses a large-value resistor with a resistance of tens to hundreds of kiloohms to connect the negative voltage node to ground. When the system is turned off, the negative charge is slowly released through the resistor. This scheme has drawbacks such as slow discharge speed and high power consumption. The second is the discharge scheme based on PMOS transistors, which achieves the discharge of negative charge by controlling the conduction of PMOS transistors. This scheme has drawbacks such as slow discharge speed, gradual decay of the discharge speed during the discharge process, and inability to achieve complete discharge. In power management systems, if rapid discharge cannot be achieved, the voltage of the internal capacitors drops slowly after the system is powered off. When power is restored, residual charge can easily cause abnormal system operation, such as screen distortion, abnormal camera startup, or direct system crash, thus affecting the reliability of the system.

[0004] Therefore, existing negative voltage discharge schemes have drawbacks such as slow discharge speed, high power consumption, and inability to achieve complete discharge. Summary of the Invention

[0005] This application provides a discharge circuit, a negative voltage power supply, and an electronic device, which can solve the problems of slow discharge speed, high power consumption, and inability to achieve complete discharge in existing negative voltage discharge schemes.

[0006] In a first aspect, embodiments of this application provide a discharge circuit, including a logic module, a switch module, and a capacitor module. The first terminal of the logic module is used to receive a power supply voltage, the second terminal of the logic module is used to receive an enable signal, the third terminal of the logic module is connected to the first terminal of the capacitor module, the fourth terminal of the logic module and the first terminal of the switch module are both grounded, the fifth terminal of the logic module is connected to the second terminal of the switch module, the third terminal of the switch module is used to connect to a negative voltage node, and the second terminal of the capacitor module is used to ground or to connect to a negative voltage node.

[0007] When the second terminal of the capacitor module is grounded and the enable signal is high, the logic module is used to connect the first terminal of the capacitor module to the power supply voltage according to the enable signal, thereby charging the capacitor module with the power supply voltage, and simultaneously disconnecting the first terminal of the capacitor module from the second terminal of the switch module; the switch module is used to turn off according to the negative voltage node voltage;

[0008] When the enable signal goes low, the logic module disconnects the first terminal of the capacitor module from the power supply voltage according to the enable signal, and connects the first terminal of the capacitor module to the second terminal of the switch module, thereby transferring the charge stored on the capacitor module to the switch module, controlling the switch module to turn on, and realizing the discharge of the negative voltage node voltage.

[0009] In one possible implementation of the first aspect, when the second terminal of the capacitor module is connected to the negative voltage node and the enable signal is high, the logic module is configured to connect the first terminal of the capacitor module to the power supply voltage according to the enable signal, thereby charging the capacitor module with the power supply voltage, and simultaneously disconnecting the first terminal of the capacitor module from the second terminal of the switch module; the switch module is configured to turn off according to the negative voltage node voltage;

[0010] When the enable signal goes low, the logic module is used to disconnect the first terminal of the capacitor module from the power supply voltage according to the enable signal, and connect the first terminal of the capacitor module to the second terminal of the switch module, thereby transferring the charge stored on the capacitor module to the switch module, controlling the switch module to conduct, and realizing the discharge of the negative voltage node voltage.

[0011] During the discharge process of the negative voltage node, the increase in the negative voltage node will raise the voltage at the first terminal of the capacitor module through the coupling effect of the capacitor module, thereby increasing the conduction degree of the switch module.

[0012] In one possible implementation of the first aspect, the logic module includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The source and body of the first transistor are both used to receive a power supply voltage. The gates of the first transistor, the second transistor, and the third transistor are all used to receive an enable signal. The drain of the first transistor is connected to the body of the fourth transistor, the source and body of the second transistor, and the first terminal of the capacitor module, respectively. The drain of the second transistor is connected to the drain of the third transistor and the source of the fourth transistor, respectively. The drain of the fourth transistor is connected to the second terminal of the switching module. The gate of the fourth transistor and the source and body of the third transistor are all grounded.

[0013] In one possible implementation of the first aspect, the first transistor and the third transistor are NMOS transistors, and the second transistor and the fourth transistor are PMOS transistors.

[0014] In one possible implementation of the first aspect, the logic module includes a first diode, a second transistor, a third transistor, and a fourth transistor. The anode of the first diode is used to receive a power supply voltage. The cathode of the first diode is connected to the body terminal of the fourth transistor, the source and body terminal of the second transistor, and the first terminal of the capacitor module. The gates of the second transistor and the third transistor are both used to receive an enable signal. The drain of the second transistor is connected to the drain of the third transistor and the source of the fourth transistor. The drain of the fourth transistor is connected to the second terminal of the switching module. The gate of the fourth transistor and the source and body terminal of the third transistor are both grounded.

[0015] In one possible implementation of the first aspect, the switching module includes a first resistor and a fifth transistor, a first terminal of the first resistor being connected to the gate of the fifth transistor and a fifth terminal of the logic module, the drain of the fifth transistor being grounded, and a second terminal of the first resistor, as well as the source and body of the fifth transistor, being connected to a negative voltage node.

[0016] In one possible implementation of the first aspect, the fifth transistor is an NMOS transistor.

[0017] In one possible implementation of the first aspect, the capacitor module includes a first capacitor, a first terminal of which is connected to a third terminal of the logic module, and a second terminal of which is used for grounding or for connection to a negative voltage node.

[0018] Secondly, embodiments of this application provide a negative voltage power supply, including the discharge circuit described in any one of the first aspects.

[0019] Thirdly, embodiments of this application provide an electronic device including the negative voltage power supply described in any one of the second aspects.

[0020] The beneficial effects of the embodiments in this application compared with the prior art are:

[0021] This application provides a discharge circuit including a logic module, a switch module, and a capacitor module. The first terminal of the logic module is used to receive a power supply voltage, the second terminal of the logic module is used to receive an enable signal, the third terminal of the logic module is connected to the first terminal of the capacitor module, the fourth terminal of the logic module and the first terminal of the switch module are both grounded, the fifth terminal of the logic module is connected to the second terminal of the switch module, the third terminal of the switch module is used to connect to a negative voltage node, and the second terminal of the capacitor module is used to ground or to connect to a negative voltage node.

[0022] When the second terminal of the capacitor module is grounded and the enable signal is high, the system is operating normally. At this time, the logic module connects the first terminal of the capacitor module to the power supply voltage according to the enable signal, thereby charging the capacitor module. Simultaneously, the logic module also disconnects the first terminal of the capacitor module from the second terminal of the switch module according to the enable signal, and the switch module is turned off due to the negative voltage node. Therefore, when the system is operating normally, the switch module is in the off state, the discharge circuit does not generate static current, achieving zero static power consumption; at the same time, it charges the capacitor module, ensuring sufficient energy is stored before the discharge operation, preparing for subsequent rapid discharge.

[0023] When the enable signal goes low, it indicates a system power failure. At this time, the logic module disconnects the first terminal of the capacitor module from the power supply voltage based on the enable signal, and simultaneously connects the first terminal of the capacitor module to the second terminal of the switch module. This allows the charge stored in the capacitor module to be transferred to the switch module, controlling the switch module to turn on. After the switch module turns on, a low-resistance discharge path is formed between the negative voltage node and ground, thereby achieving rapid and complete discharge of the voltage at the negative voltage node.

[0024] In summary, the discharge circuit provided in this application achieves rapid and complete discharge of the negative voltage node voltage, while achieving zero static power consumption. It solves the problems of slow discharge speed, high power consumption, and inability to achieve complete discharge in existing negative voltage discharge schemes, thereby improving the reliability of the system.

[0025] It is understood that the beneficial effects of the second and third aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a circuit connection diagram for a passive resistor discharge scheme;

[0028] Figure 2 This is a circuit connection diagram based on the discharge scheme of PMOS transistors;

[0029] Figure 3 Based on Figure 2 A circuit connection diagram of an improved bleedering scheme;

[0030] Figure 4 This is a schematic diagram of a discharge circuit provided in an embodiment of this application;

[0031] Figure 5 This is a schematic diagram of a discharge circuit provided in another embodiment of this application;

[0032] Figure 6 This is a circuit connection diagram of a discharge circuit provided in an embodiment of this application;

[0033] Figure 7 This is a circuit connection diagram of a discharge circuit provided in another embodiment of this application;

[0034] Figure 8 This is a circuit connection diagram of a discharge circuit provided in another embodiment of this application.

[0035] In the diagram: 10, logic module; 20, switch module; 30, capacitor module. Detailed Implementation

[0036] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0037] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0038] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0039] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [the described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [the described condition or event] is detected," or "in response to detection of [the described condition or event]."

[0040] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0041] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0042] Figure 1 The circuit connection diagram of the passive bleeder scheme is shown, as follows: Figure 1 As shown, the passive discharge scheme uses a large-value resistor R with a resistance of tens to hundreds of kiloohms. 101 Connect negative pressure node V NEG With Earth V SS When the system is turned off, negative charges pass through resistor R. 101 Slow release.

[0043] This solution has the following drawbacks: extremely slow discharge speed, large discharge time constant, requiring a discharge time of hundreds of microseconds or even longer, which cannot meet the fast reset requirements of high-speed systems; and unsuitable for low-power applications, where, under normal operating conditions, resistor R... 101It will continuously consume negative charge, leading to increased system power consumption; it affects system reliability. In scenarios with frequent power-on and power-off, negative charge accumulates due to slow discharge, causing incomplete system reset, which can easily lead to timing errors or startup failure.

[0044] Figure 2 and Figure 3 A circuit connection diagram of a PMOS-based bleedering scheme is shown, as follows: Figure 2 and Figure 3 As shown, the enable signal ena is high when the system is working normally. This is achieved through resistor R. 101 Apply current to M, so that 101 The gate voltage of the transistor is maintained at ground V. SS Nearby, M 101 The transistor is in the off state. When the system loses power or the enable signal ena is pulled low, M... 101 The gate voltage of the transistor is through resistor R 101 Reduced to -|V TH |Below, M 101 The tube is turned on to discharge negative charges. Wherein, V TH For M 101 The threshold voltage of the tube.

[0045] This scheme has the following drawbacks: the discharge speed is slow, requiring waiting for M... 101 The gate voltage of the transistor is passed through a large resistance resistor R. 101 Reduced to -|V TH |After that, M 101 The tube has just begun to conduct and discharge; the discharge speed gradually decreases during the process, and as the discharge continues, the voltage at the negative voltage node gradually increases, M 101 The gate voltage of the transistor synchronously approaches ground V. SS This led to M 101 The conductivity of the tube decreases; complete discharge cannot be achieved when the voltage at the negative voltage node discharges to -|V. TH |At that time, M 101 The tube will shut off, preventing the negative voltage node voltage from discharging to ground. SS .

[0046] A slow discharge process can trigger a series of systemic problems. For loads that require strict power-on and power-off sequences (such as LCD screens), if the negative voltage node voltage fails to discharge to zero potential quickly within the time specified in its datasheet, it may cause display abnormalities, such as screen flickering, screen distortion, or brief afterimages.

[0047] In applications such as radio frequency chips, slow discharge of negative voltage nodes can lead to incomplete reset of internal circuits. If power is restored before the negative charge is fully discharged, it may cause abnormal system startup, malfunction, or even system crash, seriously affecting product reliability and user experience.

[0048] Therefore, existing negative voltage discharge schemes have drawbacks such as slow discharge speed, high power consumption, and inability to achieve complete discharge.

[0049] To address the aforementioned problems, this application provides a discharge circuit comprising a logic module, a switch module, and a capacitor module. The first terminal of the logic module receives the power supply voltage, the second terminal receives an enable signal, the third terminal is connected to the first terminal of the capacitor module, the fourth terminal of the logic module and the first terminal of the switch module are both grounded, the fifth terminal of the logic module is connected to the second terminal of the switch module, the third terminal of the switch module is connected to a negative voltage node, and the second terminal of the capacitor module is either grounded or connected to a negative voltage node. When the second terminal of the capacitor module is grounded and the enable signal is high, the system is operating normally. At this time, the logic module connects the first terminal of the capacitor module to the power supply voltage according to the enable signal, thereby charging the capacitor module. Simultaneously, the logic module also disconnects the first terminal of the capacitor module from the second terminal of the switch module according to the enable signal, and the switch module is turned off due to the negative voltage node voltage. As can be seen, when the system is operating normally, the switch module is in the off state, the discharge circuit does not generate static current, achieving zero static power consumption; at the same time, it charges the capacitor module, ensuring that sufficient energy is stored before the discharge operation, preparing for subsequent rapid discharge. When the enable signal goes low, it indicates a system power failure. At this time, the logic module disconnects the first terminal of the capacitor module from the power supply voltage based on the enable signal, and simultaneously connects the first terminal of the capacitor module to the second terminal of the switch module. This allows the charge stored in the capacitor module to be transferred to the switch module, controlling the switch module to turn on. After the switch module turns on, a low-resistance discharge path is formed between the negative voltage node and ground, thereby achieving rapid and complete discharge of the voltage at the negative voltage node.

[0050] In summary, the discharge circuit provided in this application achieves rapid and complete discharge of the negative voltage node voltage, while achieving zero static power consumption. It solves the problems of slow discharge speed, high power consumption, and inability to achieve complete discharge in existing negative voltage discharge schemes, thereby improving the reliability of the system.

[0051] To illustrate the technical solution described in this application, specific embodiments are provided below.

[0052] Figure 4 and Figure 5 A schematic diagram of the discharge circuit provided in this application is shown, as follows. Figure 4 and Figure 5 As shown, the discharge circuit includes a logic module 10, a switch module 20, and a capacitor module 30. The first terminal of the logic module 10 is used to receive the power supply voltage V. DDThe second terminal of logic module 10 is used to receive the enable signal ena. The third terminal of logic module 10 is connected to the first terminal of capacitor module 30. The fourth terminal of logic module 10 and the first terminal of switch module 20 are both used to ground V. SS The fifth terminal of logic module 10 is connected to the second terminal of switch module 20, and the third terminal of switch module 20 is used to connect to the negative pressure node V. NEG The second terminal of capacitor module 30 is used for grounding (e.g., Figure 4 (as shown) or used with negative pressure node V NEG Connections (such as) Figure 5 (As shown).

[0053] Specifically, when the second terminal of capacitor module 30 is grounded V SS When the enable signal ena is high, it indicates that the system is working normally. At this time, the logic module 10 connects the first terminal of the capacitor module 30 to the power supply voltage V according to the enable signal ena. DD The connection is made conductive, thereby increasing the power supply voltage V. DD The capacitor module 30 is charged; simultaneously, the logic module 10 disconnects the first terminal of the capacitor module 30 from the second terminal of the switch module 20 according to the enable signal ena, and the switch module 20 is turned off due to the negative voltage node. As can be seen, when the system is working normally, the switch module 20 is in the off state, the discharge circuit does not generate static current, achieving zero static power consumption; at the same time, the capacitor module 30 is charged to ensure that sufficient energy is stored before the discharge operation, preparing for the subsequent rapid discharge action.

[0054] When the enable signal ena goes low, it indicates that the system has lost power. At this time, logic module 10 connects the first terminal of capacitor module 30 to the power supply voltage V according to the enable signal ena. DD Disconnecting the capacitor module 30 simultaneously connects the first terminal of the capacitor module 30 to the second terminal of the switch module 20, thereby transferring the charge stored in the capacitor module 30 to the switch module 20 and turning it on. After the switch module 20 is turned on, at the negative voltage node V... NEG With Earth V SS A low-resistance discharge path is formed between them, thereby achieving rapid and thorough discharge of the negative voltage node voltage.

[0055] In summary, the discharge circuit provided in this application achieves rapid and complete discharge of the negative voltage node voltage, while achieving zero static power consumption. It solves the problems of slow discharge speed, high power consumption, and inability to achieve complete discharge in existing negative voltage discharge schemes, thereby improving the reliability of the system.

[0056] In one embodiment of this application, when the second terminal of the capacitor module 30 is used to connect with the negative voltage node V NEGWhen the connection is established and the enable signal ena is high, it indicates that the system is operating normally. At this time, logic module 10 connects the first terminal of capacitor module 30 to the power supply voltage V according to the enable signal ena. DD The connection is made conductive, thereby increasing the power supply voltage V. DD The capacitor module 30 is charged; simultaneously, the logic module 10 disconnects the first terminal of the capacitor module 30 from the second terminal of the switch module 20 according to the enable signal ena, and the switch module 20 is turned off due to the negative voltage node. As can be seen, when the system is working normally, the switch module 20 is in the off state, the discharge circuit does not generate static current, achieving zero static power consumption; at the same time, the capacitor module 30 is charged to ensure that sufficient energy is stored before the discharge operation, preparing for the subsequent rapid discharge action.

[0057] When the enable signal ena goes low, it indicates that the system has lost power. At this time, logic module 10 connects the first terminal of capacitor module 30 to the power supply voltage V according to the enable signal ena. DD Disconnecting the capacitor module 30 simultaneously connects the first terminal of the capacitor module 30 to the second terminal of the switch module 20, thereby transferring the charge stored in the capacitor module 30 to the switch module 20 and turning it on. After the switch module 20 is turned on, at the negative voltage node V... NEG With Earth V SS A low-resistance discharge path is formed between them, thereby achieving rapid and thorough discharge of the negative voltage node voltage.

[0058] During the discharge process of the negative voltage node, since the voltage across capacitor module 30 cannot change abruptly, the increase in the negative voltage node, through the coupling effect of capacitor module 30, will raise the voltage at the first terminal of capacitor module 30, thereby increasing the conduction degree of switch module 20 and forming a positive feedback accelerated discharge effect. Utilizing this voltage rise effect, the capacitance requirement of capacitor module 30 can be reduced while achieving the same discharge speed, which is beneficial for optimizing the area of ​​integrated circuits.

[0059] In one embodiment of this application, such as Figure 6 As shown, logic module 10 includes a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4. The source and body terminals of the first transistor M1 are both used to receive the power supply voltage V. DDThe gates of the first transistor M1, the second transistor M2, and the third transistor M3 are all used to receive the enable signal ena. The drain of the first transistor M1 is connected to the body of the fourth transistor M4, the source and body of the second transistor M2, and the first terminal of the capacitor module 30, respectively. The drain of the second transistor M2 is connected to the drain of the third transistor M3 and the source of the fourth transistor M4, respectively. The drain of the fourth transistor M4 is connected to the second terminal of the switching module 20. The gate of the fourth transistor M4 and the source and body of the third transistor M3 are all grounded. In this embodiment, the first transistor M1 and the third transistor M3 are NMOS transistors, and the second transistor M2 and the fourth transistor M4 are PMOS transistors.

[0060] Specifically, when the enable signal ena is high, it indicates that the system is operating normally. At this time, the first transistor M1 and the third transistor M3 are turned on, and the second transistor M2 is turned off. After the first transistor M1 is turned on, the power supply voltage V... DD The capacitor module 30 is charged; when the third transistor M3 is turned on, the source of the fourth transistor M4 is pulled to ground V. SS This puts the fourth transistor M4 in the off state, meaning that the first terminal of the capacitor module 30 is disconnected from the second terminal of the switch module 20.

[0061] When the enable signal ena goes low, it indicates that the system is powered down. At this time, the first transistor M1 and the third transistor M3 are turned off, and the second transistor M2 is turned on. After the second transistor M2 is turned on, it connects the first terminal of the capacitor module 30 to the source of the fourth transistor M4, causing the fourth transistor M4 to enter the conducting state, thereby connecting the first terminal of the capacitor module 30 to the second terminal of the switch module 20.

[0062] In one embodiment of this application, such as Figure 7 As shown, logic module 10 includes a first diode D1, a second transistor M2, a third transistor M3, and a fourth transistor M4. The anode of the first diode D1 is used to receive the power supply voltage V. DD The cathode of the first diode D1 is connected to the body terminal of the fourth transistor M4, the source and body terminal of the second transistor M2, and the first terminal of the capacitor module 30, respectively. The gates of the second transistor M2 and the third transistor M3 are both used to receive the enable signal ena. The drain of the second transistor M2 is connected to the drain of the third transistor M3 and the source of the fourth transistor M4, respectively. The drain of the fourth transistor M4 is connected to the second terminal of the switch module 20. The gate of the fourth transistor M4 and the source and body terminal of the third transistor M3 are both used to ground V. SS .

[0063] Specifically, the first diode D1 replaces the first transistor M1. When the enable signal ena is high, the first diode D1 is forward-biased, and the power supply voltage V... DD The capacitor module 30 is charged. When the enable signal ena goes low, the first diode D1 is reverse-biased and cut off, which is the same as the turn-off function of the first transistor M1.

[0064] In one embodiment of this application, such as Figure 6 As shown, the switching module 20 includes a first resistor R1 and a fifth transistor M5. The first terminal of the first resistor R1 is connected to the gate of the fifth transistor M5 and the fifth terminal of the logic module 10, respectively. The drain of the fifth transistor M5 is grounded. SS The second terminal of the first resistor R1 and the source and body terminals of the fifth transistor M5 are both used to connect to the negative voltage node V. NEG Connection. In this embodiment, the fifth transistor M5 is an NMOS transistor.

[0065] Specifically, when the enable signal ena is high, it indicates that the system is operating normally. At this time, the first transistor M1 and the third transistor M3 are turned on, and the second transistor M2 is turned off. After the first transistor M1 is turned on, the power supply voltage V... DD The capacitor module 30 is charged; when the third transistor M3 is turned on, the source of the fourth transistor M4 is pulled to ground V. SS This puts the fourth transistor M4 in the off state, meaning the first terminal of capacitor module 30 is disconnected from the gate of the fifth transistor M5. Simultaneously, the gate of the fifth transistor M5 is connected to the negative voltage node V through the first resistor R1. NEG Therefore, the fifth transistor M5 is also in the off state. In this operating mode, the discharge circuit does not generate quiescent current, achieving zero quiescent current; at the same time, it charges the capacitor module 30 to ensure that sufficient energy is stored before the discharge operation is performed, preparing for the subsequent rapid discharge action.

[0066] When the enable signal ena goes low, it indicates a system power outage. At this time, the first transistor M1 and the third transistor M3 are turned off, and the second transistor M2 is turned on. After the second transistor M2 turns on, it connects the first terminal of the capacitor module 30 to the source of the fourth transistor M4, causing the fourth transistor M4 to enter the conducting state. This, in turn, connects the first terminal of the capacitor module 30 to the gate of the fifth transistor M5. The charge stored in the capacitor module 30 is transferred to the gate of the fifth transistor M5. Due to the large resistance of the first resistor R1, the charge accumulation will rapidly raise the gate voltage of the fifth transistor M5, causing the fifth transistor M5 to turn on. After the fifth transistor M5 turns on, at the negative voltage node V... NEG With Earth V SSA low-resistance discharge path is formed between them, thereby achieving rapid discharge of the negative voltage node voltage. By properly setting the capacitance value of capacitor module 30 and the resistance value of the first resistor R1, it can be ensured that the negative voltage node voltage is completely released to ground potential without residual voltage, thereby improving the reliability of the system.

[0067] In one embodiment of this application, such as Figure 6 and Figure 8 As shown, the capacitor module 30 includes a first capacitor C1. The first terminal of the first capacitor C1 is connected to the third terminal of the logic module 10, and the second terminal of the first capacitor C1 is used to ground V. SS (like Figure 6 (as shown) or used with negative pressure node V NEG Connections (such as) Figure 8 (As shown).

[0068] Specifically, when the second terminal of the first capacitor C1 is used to ground V SS When the enable signal ena is high, it indicates that the system is working normally. At this time, the first transistor M1 and the third transistor M3 are turned on, and the second transistor M2 is turned off. After the first transistor M1 is turned on, the power supply voltage V... DD The first capacitor C1 is charged; when the third transistor M3 is turned on, the source of the fourth transistor M4 is pulled to ground V. SS This puts the fourth transistor M4 in the off state, meaning the first terminal of the first capacitor C1 is disconnected from the gate of the fifth transistor M5. Simultaneously, the gate of the fifth transistor M5 is connected to the negative voltage node V through the first resistor R1. NEG Therefore, the fifth transistor M5 is also in the off state. In this operating mode, the discharge circuit does not generate quiescent current, achieving zero quiescent current; at the same time, it charges the first capacitor C1 to ensure that enough energy is stored before the discharge operation is performed, preparing for the subsequent rapid discharge action.

[0069] When the enable signal ena goes low, it indicates a system power failure. At this time, the first transistor M1 and the third transistor M3 are turned off, and the second transistor M2 is turned on. After the second transistor M2 turns on, it connects the first terminal of the first capacitor C1 to the source of the fourth transistor M4, causing the fourth transistor M4 to enter the conducting state. This, in turn, connects the first terminal of the first capacitor C1 to the gate of the fifth transistor M5. The charge stored in the first capacitor C1 is transferred to the gate of the fifth transistor M5. Due to the large resistance of the first resistor R1, the charge accumulation will rapidly raise the gate voltage of the fifth transistor M5, causing the fifth transistor M5 to turn on. After the fifth transistor M5 turns on, at the negative voltage node V... NEG With Earth V SSA low-resistance discharge path is formed between them, thereby achieving rapid discharge of the negative voltage node voltage. By properly setting the capacitance value of the first capacitor C1 and the resistance value of the first resistor R1, it can be ensured that the negative voltage node voltage is completely released to ground potential without residual voltage, thereby improving the reliability of the system.

[0070] When the second terminal of the first capacitor C1 is used with the negative voltage node V NEG When the connection is established and the enable signal ena is high, it indicates that the system is operating normally. At this time, the first transistor M1 and the third transistor M3 are turned on, and the second transistor M2 is turned off. After the first transistor M1 is turned on, the power supply voltage V... DD The first capacitor C1 is charged; when the third transistor M3 is turned on, the source of the fourth transistor M4 is pulled to ground V. SS This puts the fourth transistor M4 in the off state, meaning the first terminal of the first capacitor C1 is disconnected from the gate of the fifth transistor M5. Simultaneously, the gate of the fifth transistor M5 is connected to the negative voltage node V through the first resistor R1. NEG Therefore, the fifth transistor M5 is also in the off state. In this operating mode, the discharge circuit does not generate quiescent current, achieving zero quiescent current; at the same time, it charges the first capacitor C1 to ensure that enough energy is stored before the discharge operation is performed, preparing for the subsequent rapid discharge action.

[0071] When the enable signal ena goes low, it indicates a system power failure. At this time, the first transistor M1 and the third transistor M3 are turned off, and the second transistor M2 is turned on. After the second transistor M2 turns on, it connects the first terminal of the first capacitor C1 to the source of the fourth transistor M4, causing the fourth transistor M4 to enter the conducting state. This, in turn, connects the first terminal of the first capacitor C1 to the gate of the fifth transistor M5. The charge stored in the first capacitor C1 is transferred to the gate of the fifth transistor M5. Due to the large resistance of the first resistor R1, the charge accumulation will rapidly raise the gate voltage of the fifth transistor M5, causing the fifth transistor M5 to turn on. After the fifth transistor M5 turns on, at the negative voltage node V... NEG With Earth V SS A low-resistance discharge path is formed between them, thereby achieving rapid discharge of the negative voltage node voltage. By properly setting the capacitance value of the first capacitor C1 and the resistance value of the first resistor R1, it can be ensured that the negative voltage node voltage is completely released to ground potential without residual voltage, thereby improving the reliability of the system.

[0072] During the discharge process of the negative voltage node, since the voltage across the capacitor cannot change abruptly, the increase in the negative voltage node, through the coupling effect of the first capacitor C1, will raise the voltage at the first terminal of the first capacitor C1, i.e., the voltage at node A. This further raises the gate voltage of the fifth transistor M5, increasing its conduction level and forming a positive feedback accelerated discharge effect. Utilizing this voltage boosting effect, the capacitance requirement of the first capacitor C1 can be reduced while achieving the same discharge rate, which is beneficial for optimizing the area of ​​the integrated circuit.

[0073] In summary, the discharge circuit provided in this application embodiment achieves rapid and complete discharge: by charging the first capacitor C1 to pre-store energy, and instantly raising the gate voltage of the fifth transistor M5 when discharge is needed, it quickly turns on, at the negative voltage node V NEG With Earth V SS A low-impedance path is established between them. This shortens the discharge process to the microsecond level and ensures that the negative voltage node voltage is completely released to ground potential without any residual voltage. This is crucial for systems that require strict power-on and power-off timing (such as LCD screens and RF chips), effectively preventing problems such as abnormal system restarts, display distortion, or functional malfunctions caused by incomplete negative charge discharge.

[0074] Zero static power consumption is achieved: During normal system operation, the enable signal ena completely shuts off the discharge path, and the gate of the fifth transistor M5 is reliably clamped at the off potential. Therefore, no static current flows through the discharge circuit during normal system operation, achieving true zero static power consumption. This characteristic is significant for power-sensitive applications such as battery-powered portable electronic devices and IoT devices that are constantly in standby mode, as it can greatly extend the device's battery life.

[0075] The circuit structure is simple and reliable: This application uses capacitors, a few MOSFETs, and a large resistor as core components, and achieves its function through ingenious connection and control logic, eliminating the need for complex level shifting circuits or additional negative voltage power supplies. This concise structure reduces the difficulty of circuit design and implementation, which helps to reduce costs and improve circuit reliability.

[0076] Introducing a positive feedback mechanism to accelerate discharge: Connecting the second terminal of the first capacitor C1 to the negative voltage node V NEG The connection cleverly utilizes the characteristic that the voltage across a capacitor cannot change abruptly. During discharge, the increase in voltage at the negative voltage node automatically raises the voltage at node A through the coupling effect of the capacitor, thus forming a positive feedback effect that further accelerates the conduction and discharge process of the fifth transistor M5. This mechanism can further improve the discharge speed without adding additional complex components, or allow the use of smaller capacitance values ​​to achieve the same discharge speed requirement, thereby further optimizing the chip area.

[0077] Improving System Reliability: This application provides a fast, thorough, and zero-static-power discharge circuit, fundamentally solving the problems of slow response, residual turn-off potential, or high power consumption in traditional discharge circuits (such as those using only large resistors). This ensures that electronic systems using the discharge circuit provided in this application are more stable and reliable during the system turn-off phase, avoiding potential risks and improving the overall product quality and user experience.

[0078] This application also provides a negative voltage power supply, including the discharge circuit described above. Since the negative voltage power supply provided in this application adopts all the technical solutions of all the above embodiments, it possesses at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be elaborated further here.

[0079] This application also provides an electronic device, including the negative voltage power supply described above. Since the electronic device provided in this application adopts all the technical solutions of all the above embodiments, it possesses at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be elaborated upon here.

[0080] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0081] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A discharge circuit, characterized in that, It includes a logic module, a switch module, and a capacitor module. The first terminal of the logic module is used to receive the power supply voltage, the second terminal of the logic module is used to receive the enable signal, the third terminal of the logic module is connected to the first terminal of the capacitor module, the fourth terminal of the logic module and the first terminal of the switch module are both used for grounding, the fifth terminal of the logic module is connected to the second terminal of the switch module, the third terminal of the switch module is used to connect to the negative voltage node, and the second terminal of the capacitor module is used for grounding or for connecting to the negative voltage node. When the second terminal of the capacitor module is grounded and the enable signal is high, the logic module is used to connect the first terminal of the capacitor module to the power supply voltage according to the enable signal, thereby charging the capacitor module with the power supply voltage, and simultaneously disconnecting the first terminal of the capacitor module from the second terminal of the switch module; the switch module is used to turn off according to the negative voltage node voltage; When the enable signal goes low, the logic module is used to disconnect the first terminal of the capacitor module from the power supply voltage according to the enable signal, and connect the first terminal of the capacitor module to the second terminal of the switch module, thereby transferring the charge stored on the capacitor module to the switch module, controlling the switch module to conduct, and realizing the discharge of the negative voltage node voltage. When the second terminal of the capacitor module is connected to the negative voltage node and the enable signal is high, the logic module is used to connect the first terminal of the capacitor module to the power supply voltage according to the enable signal, thereby charging the capacitor module with the power supply voltage, and simultaneously disconnecting the first terminal of the capacitor module from the second terminal of the switch module; the switch module is used to turn off according to the negative voltage node voltage; When the enable signal goes low, the logic module is used to disconnect the first terminal of the capacitor module from the power supply voltage according to the enable signal, and connect the first terminal of the capacitor module to the second terminal of the switch module, thereby transferring the charge stored on the capacitor module to the switch module, controlling the switch module to conduct, and realizing the discharge of the negative voltage node voltage. During the discharge process of the negative voltage node, the increase in the negative voltage node will raise the voltage at the first terminal of the capacitor module through the coupling effect of the capacitor module, thereby increasing the conduction degree of the switch module.

2. The discharge circuit according to claim 1, characterized in that, The logic module includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The source and body of the first transistor are used to receive power supply voltage. The gates of the first transistor, the second transistor, and the third transistor are used to receive enable signals. The drain of the first transistor is connected to the body of the fourth transistor, the source and body of the second transistor, and the first terminal of the capacitor module, respectively. The drain of the second transistor is connected to the drain of the third transistor and the source of the fourth transistor, respectively. The drain of the fourth transistor is connected to the second terminal of the switching module. The gate of the fourth transistor and the source and body of the third transistor are all grounded.

3. The discharge circuit according to claim 2, characterized in that, The first transistor and the third transistor are NMOS transistors, and the second transistor and the fourth transistor are PMOS transistors.

4. The discharge circuit according to claim 1, characterized in that, The logic module includes a first diode, a second transistor, a third transistor, and a fourth transistor. The anode of the first diode is used to receive the power supply voltage. The cathode of the first diode is connected to the body terminal of the fourth transistor, the source and body terminal of the second transistor, and the first terminal of the capacitor module. The gates of the second transistor and the third transistor are both used to receive enable signals. The drain of the second transistor is connected to the drain of the third transistor and the source of the fourth transistor. The drain of the fourth transistor is connected to the second terminal of the switching module. The gate of the fourth transistor and the source and body terminal of the third transistor are all grounded.

5. The discharge circuit according to claim 1, characterized in that, The switching module includes a first resistor and a fifth transistor. The first end of the first resistor is connected to the gate of the fifth transistor and the fifth terminal of the logic module, respectively. The drain of the fifth transistor is grounded. The second end of the first resistor, as well as the source and body of the fifth transistor, are all connected to a negative voltage node.

6. The discharge circuit according to claim 5, characterized in that, The fifth transistor is an NMOS transistor.

7. The discharge circuit according to claim 1, characterized in that, The capacitor module includes a first capacitor, a first terminal of which is connected to a third terminal of the logic module, and a second terminal of which is used for grounding or for connection to a negative voltage node.

8. A negative voltage power supply, characterized in that, Includes the discharge circuit described in any one of claims 1-7.

9. An electronic device, characterized in that, Includes the negative voltage power supply as described in claim 8.

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