Stacked power amplifier based on transformer synthesis

Abstract

The invention discloses a stacked power amplifier based on transformer synthesis, and aims to solve the problem that the output power, synthesis efficiency and dynamic reliability of a power amplifier are difficult to synergistically improve under a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) process. The amplifier adopts a symmetrical double-branch architecture and comprises a T-shaped power distribution network, two power amplification branches and a T-shaped power synthesis network. The power amplifier is characterized in that each power amplification branch comprises an amplifier adopting a multi-transistor stacking topology, and grids of stacked transistors are biased or coupled through a series capacitor so as to realize dynamic voltage distribution in a radio frequency period; the T-type transformer distribution / synthesis network and the stacked amplification branch adopting the capacitor dynamic voltage division work cooperatively, and unification of high output power, high synthesis efficiency and high working reliability is achieved jointly. Through the collaborative design of the architecture and the circuit level, the performance bottleneck in the traditional design is effectively broken through, and the method is suitable for high-frequency and high-power wireless communication systems such as 5G, Internet of Things and the like.

Description

Technical Field

[0001] This invention relates to the field of high-frequency radio frequency communication technology, and is particularly applicable to wireless communication systems such as 5G and the Internet of Things. Specifically, it relates to a stacked power amplifier based on transformer synthesis. Background Technology

[0002] In wireless communication systems, the power amplifier (PA) is a core component of the transmitter, and its output power, efficiency, and reliability directly determine the signal transmission distance, coverage, and communication quality. As 5G and the Internet of Things evolve towards higher frequencies and higher power, CMOS technology has become the mainstream choice for power amplifiers due to its advantages of low cost, high integration, and digital compatibility. However, due to limitations in the voltage withstand characteristics and parasitic parameters of the devices, insufficient output power remains a core technological bottleneck.

[0003] The power limitations of existing CMOS power amplifiers mainly stem from three aspects: First, CMOS transistors have low breakdown voltages, limiting the voltage swing of a single transistor. Although traditional common-source cascode topologies can improve the withstand voltage, the gate-grounded design of quasi-cascode transistors further constrains the voltage swing, limiting the saturated output power. Second, traditional stacked structures rely on bias resistor voltage division, resulting in low accuracy and narrow dynamic range. Under strong signals, single transistors are prone to overvoltage damage. Furthermore, traditional power combining networks (such as resistor and transmission line combining) have poor impedance matching, high reflection loss, and low combining efficiency, limiting the power amplifier bandwidth. Third, traditional distribution and combining networks have high insertion loss, which, combined with device nonlinear losses, leads to low link energy utilization efficiency, making it difficult to meet low power consumption requirements.

[0004] Therefore, it is urgent to overcome the dual limitations of device voltage withstand and synthesis efficiency under CMOS technology, optimize voltage distribution by stacking transistor power stages, and improve the power and voltage withstand of single-channel power amplifiers; coupled with a low-loss, high-precision transformer-type two-channel power combining network, signal loss is reduced while power is superimposed, and finally "high output power + high efficiency + low loss" is achieved to meet the needs of high-frequency and high-power communication scenarios. Summary of the Invention

[0005] The technical problem this invention aims to solve is that CMOS process power amplifiers have limited output power, making it difficult to meet the demands of high-frequency, high-power communication scenarios. Specifically, this includes: CMOS transistors have low withstand voltage and limited voltage swing per transistor; traditional cascode topologies further constrain voltage swing; existing stacked structures rely on bias resistor voltage division, resulting in low accuracy and susceptibility to single-transistor overvoltage damage under strong signals; traditional power combining networks suffer from insufficient impedance matching accuracy, high reflection loss, and low combining efficiency; and significant insertion loss and nonlinear losses in power distribution and combining networks lead to low link energy utilization efficiency. To address these problems, this invention provides a stacked power amplifier based on transformer combining.

[0006] The object of this invention is achieved in the following manner: A stacked power amplifier based on transformer combining adopts a symmetrical dual-branch architecture, including: an input tuning matching unit, a T-type power distribution network, two power amplification branches, a T-type power combining network, and an output tuning matching unit; The input tuning matching unit includes a parallel tuning capacitor C0, whose first end is electrically connected to the radio frequency signal input terminal RFin and the second end is grounded, and is used for pre-matching the input impedance; The common input terminal of the T-type power distribution network is electrically connected to the first terminal of the parallel tuning capacitor C0, which is used to convert the pre-matched input signal into two symmetrical differential signals and output them to the two power amplification branches respectively. Each power amplifier branch includes, in sequence, an input matching transformer, a driver stage amplifier (DA), an interstage matching transformer, a power stage amplifier (PA), and an output matching transformer; wherein, the power stage amplifier adopts a differential cascode topology with 3 stacked transistors; The input terminal of the T-type power combining network is electrically connected to the secondary winding of the output matching transformer of the two power amplification branches, respectively, for performing equal-amplitude and in-phase power combining of the amplified signals from the two branches. The output tuning matching unit includes a parallel tuning capacitor C5, whose first end is electrically connected to the output end of the T-type power combining network and whose second end is grounded. It is used to perform output impedance matching on the combined signal and output it from the RF signal output end RFout.

[0007] The T-type power distribution network includes two transformers and a tuning capacitor connected between them, which can stably output two differential signals with equal amplitude and consistent phase to the primary side of the input matching transformer of the power amplification branch.

[0008] The input matching transformer is a high-frequency differential transformer TF1. One end of its primary coil is connected to the output signal of the T-type power distribution network, and the other end is grounded. The secondary coil has a differential structure, with its two ends connected to the differential input terminals IN1+ and IN1- of the driver stage amplifier, respectively. The center tap of the secondary coil is connected to the gate bias voltage VB1, which is used to provide a static operating point for the driver stage amplifier.

[0009] The driver amplifier (DA) adopts a differential common-source topology, including a first enhancement-mode NMOS transistor M1 and a second enhancement-mode NMOS transistor M2; The gate of M1 is connected to IN1+, and the gate of M2 is connected to IN1-; the sources of M1 and M2 are grounded; the drain of M1 is the differential output terminal OUT1-, and the drain of M2 is the differential output terminal OUT1+. The driver stage amplifier also includes two neutralizing capacitors Cx1: the first neutralizing capacitor Cx1 is connected between the drain of M1 and the gate of M2, and the second neutralizing capacitor Cx1 is connected between the drain of M2 and the gate of M1, for neutralizing the gate-drain parasitic capacitance of M1 and M2.

[0010] The interstage matching transformer is a high-frequency differential transformer TF2; The two ends of its primary coil are electrically connected to the differential output terminals OUT1- and OUT1+ of the driver stage amplifier, respectively, and the center tap of its primary coil is connected to the driver stage power supply VDD1. The secondary coil has a differential structure, with its two ends connected to the differential input terminals IN2+ and IN2- of the power stage amplifier, respectively. The center tap of the secondary coil is connected to the gate bias voltage VB2, which is used to provide bias for the bottom transistor of the power stage amplifier.

[0011] The power amplifier (PA) is a differential structure, with each differential branch consisting of three enhancement-mode NMOS transistors stacked in series: The bottom layer transistors, including the third NMOS transistor M3 and the fourth NMOS transistor M4, have their gates connected to the secondary differential terminal of the interstage matching transformer TF2 through bias resistors, their sources grounded, and their drains connected to the sources of the intermediate transistors respectively. The intermediate transistors, including the fifth NMOS transistor M5 and the sixth NMOS transistor M6, have their gates connected to the intermediate transistor bias voltage VB3 through the first voltage divider capacitor Cg1 and the first gate resistor Rg1, and their drains are connected to the source of the top layer transistor. The top-level transistors, including the seventh NMOS transistor M7 and the eighth NMOS transistor M8, have their gates connected to the top-level transistor bias voltage VB4 through the second voltage divider capacitor Cg2 and the second gate resistor Rg2. Their drains serve as the differential output terminals OUT2- and OUT2+ of the power amplification branch.

[0012] A shunt capacitor Cf is connected between the source and drain of the top-level transistors M7 and M8, respectively, to optimize the voltage distribution of the top-level transistors and shunt high-frequency parasitic current.

[0013] The power stage amplifier also includes a neutralizing capacitor Cx2: a first neutralizing capacitor Cx2 is connected between the gate of M3 and the source of M6, and a second neutralizing capacitor Cx2 is connected between the gate of M4 and the source of M5, to counteract the effect of the transistor gate-drain capacitance.

[0014] The output matching transformer is a high-frequency differential transformer TF3; The two ends of its primary coil are electrically connected to the differential output terminals OUT2- and OUT2+ of the power stage amplifier, respectively, and the center tap of its primary coil is connected to the power stage power supply VDD2. The secondary coil has one end grounded and the other end connected to the power combining node Z1 of the T-type power combining network to achieve differential-to-single-ended signal conversion and impedance matching.

[0015] The T-type power combining network includes a transformer and a tuning capacitor, which are used to superimpose the single-ended signals from the two branches after being transformed by the output matching transformer TF3 at node Z1. The output matching transformer TF3 matches the output impedance of the power stage amplifier to 2Z1. After the two branches are combined by the T-type power combining network, the impedance at node Z1 becomes Z1. Then, through the tuning of the parallel tuning capacitor C5, it is finally matched to the standard load impedance.

[0016] The beneficial effects of this invention are as follows: This invention combines a symmetrical dual-branch architecture with transformer synthesis technology, along with a stacked transistor differential cascode topology and precise voltage division and parasitic suppression design. This achieves uniform distribution of drain-source voltage among transistors, avoiding the risk of overvoltage damage, breaking through the voltage withstand bottleneck of CMOS transistors, and improving device reliability. Furthermore, by leveraging the signal swing advantage of the differential topology and an optimized high-frequency differential transformer and T-type distribution / synthesis network, it significantly improves output power and synthesis efficiency, reduces losses, and solves the problem of low efficiency in traditional synthesis networks. Simultaneously, by using shunt capacitors to offset parasitic capacitance and neutralizing capacitors to suppress high-frequency feedback, it improves broadband energy conversion efficiency. Combined with a broadband adaptation design, it ensures flat gain and stable impedance. In addition, the fully differential topology ensures excellent linearity, the compact layout of core components balances integration and practicality, and the architecture can be flexibly expanded to multi-channel synthesis, compatible with mainstream processes. Ultimately, it achieves synergistic optimization of high power, high efficiency, and high stability, meeting the requirements of high-frequency, high-power wireless communication systems, and possesses good engineering application value and scalability. Attached Figure Description

[0017] Figure 1 This is a structural block diagram of a stacked power amplifier based on transformer synthesis provided in an embodiment of the present invention; Figure 2 The schematic diagram of the driver stage amplifier circuit provided in the embodiment of the present invention; Figure 3 This is a schematic diagram of a stacked power stage amplifier circuit provided in an embodiment of the present invention; Figure 4 A schematic diagram of a stacked amplifier circuit with feedback capacitor provided in an embodiment of the present invention; Figure 5 A three-dimensional model diagram of a transformer-type input power distribution network provided in an embodiment of the present invention; Figure 6 A three-dimensional model diagram of the interstage matching transformer TF2 provided in an embodiment of the present invention; Figure 7A three-dimensional model diagram of a transformer-type output power combining network provided in an embodiment of the present invention; Figure 8 The output power of the stacked power amplifier based on transformer synthesis at 24 GHz provided in the embodiments of the present invention is shown in the simulation. Figure 9 Additional efficiency in power amplifier simulation at 24 GHz provided in this embodiment of the invention; Figure 10 S21 simulation curves of a 22-26GHz power amplifier provided for embodiments of the present invention; Figure 11 S11 simulation curves of a 22-26GHz power amplifier provided for embodiments of the present invention; Figure 12 The simulation curve of the 1dB compression point of the power amplifier at 24GHz is provided for the embodiment of the present invention. Detailed Implementation

[0018] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0019] It should be noted that the following detailed descriptions are exemplary and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same technical meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0020] like Figure 1 As shown, the present invention provides a stacked power amplifier based on transformer combining, which adopts a symmetrical dual-branch architecture and includes: an input tuning matching unit, a T-type power distribution network, two power amplification branches, a T-type power combining network, and an output tuning matching unit; The input tuning matching unit includes a parallel tuning capacitor C0, whose first end is electrically connected to the radio frequency signal input terminal RFin and the second end is grounded, and is used for pre-matching the input impedance; The common input terminal of the T-type power distribution network is electrically connected to the first terminal of the parallel tuning capacitor C0, which is used to convert the pre-matched input signal into two symmetrical differential signals and output them to the two power amplification branches respectively. Each power amplifier branch includes, in sequence, an input matching transformer, a driver stage amplifier (DA), an interstage matching transformer, a power stage amplifier (PA), and an output matching transformer; wherein, the power stage amplifier adopts a differential cascode topology with 3 stacked transistors; The input terminal of the T-type power combining network is electrically connected to the secondary winding of the output matching transformer of the two power amplification branches, respectively, for performing equal-amplitude and in-phase power combining of the amplified signals from the two branches. The output tuning matching unit includes a parallel tuning capacitor C5, whose first end is electrically connected to the output end of the T-type power combining network and whose second end is grounded. It is used to perform output impedance matching on the combined signal and output it from the RF signal output end RFout.

[0021] The T-type power distribution network includes two transformers and a tuning capacitor connected between them, which can stably output two differential signals with equal amplitude and consistent phase to the primary side of the input matching transformer of the power amplification branch.

[0022] The input matching transformer is a high-frequency differential transformer TF1. One end of its primary coil is connected to the output signal of the T-type power distribution network, and the other end is grounded. The secondary coil has a differential structure, with its two ends connected to the differential input terminals IN1+ and IN1- of the driver stage amplifier, respectively. The center tap of the secondary coil is connected to the gate bias voltage VB1, which is used to provide a static operating point for the driver stage amplifier.

[0023] The driver amplifier (DA) adopts a differential common-source topology, including a first enhancement-mode NMOS transistor M1 and a second enhancement-mode NMOS transistor M2; The gate of M1 is connected to IN1+, and the gate of M2 is connected to IN1-; the sources of M1 and M2 are grounded; the drain of M1 is the differential output terminal OUT1-, and the drain of M2 is the differential output terminal OUT1+. The driver stage amplifier also includes two neutralizing capacitors Cx1: the first neutralizing capacitor Cx1 is connected between the drain of M1 and the gate of M2, and the second neutralizing capacitor Cx1 is connected between the drain of M2 and the gate of M1, for neutralizing the gate-drain parasitic capacitance of M1 and M2.

[0024] The interstage matching transformer is a high-frequency differential transformer TF2; The two ends of its primary coil are electrically connected to the differential output terminals OUT1- and OUT1+ of the driver stage amplifier, respectively, and the center tap of its primary coil is connected to the driver stage power supply VDD1. The secondary coil has a differential structure, with its two ends connected to the differential input terminals IN2+ and IN2- of the power stage amplifier, respectively. The center tap of the secondary coil is connected to the gate bias voltage VB2, which is used to provide bias for the bottom transistor of the power stage amplifier.

[0025] The power amplifier (PA) is a differential structure, with each differential branch consisting of three enhancement-mode NMOS transistors stacked in series: The bottom layer transistors, including the third NMOS transistor M3 and the fourth NMOS transistor M4, have their gates connected to the secondary differential terminal of the interstage matching transformer TF2 through bias resistors, their sources grounded, and their drains connected to the sources of the intermediate transistors respectively. The intermediate transistors, including the fifth NMOS transistor M5 and the sixth NMOS transistor M6, have their gates connected to the intermediate transistor bias voltage VB3 through the first voltage divider capacitor Cg1 and the first gate resistor Rg1, and their drains are connected to the source of the top layer transistor. The top-level transistors, including the seventh NMOS transistor M7 and the eighth NMOS transistor M8, have their gates connected to the top-level transistor bias voltage VB4 through the second voltage divider capacitor Cg2 and the second gate resistor Rg2. Their drains serve as the differential output terminals OUT2- and OUT2+ of the power amplification branch.

[0026] A shunt capacitor Cf is connected between the source and drain of the top-level transistors M7 and M8, respectively, to optimize the voltage distribution of the top-level transistors and shunt high-frequency parasitic current.

[0027] The power stage amplifier also includes a neutralizing capacitor Cx2: a first neutralizing capacitor Cx2 is connected between the gate of M3 and the source of M6, and a second neutralizing capacitor Cx2 is connected between the gate of M4 and the source of M5, to counteract the effect of the transistor gate-drain capacitance.

[0028] The output matching transformer is a high-frequency differential transformer TF3; The two ends of its primary coil are electrically connected to the differential output terminals OUT2- and OUT2+ of the power stage amplifier, respectively, and the center tap of its primary coil is connected to the power stage power supply VDD2. The secondary coil has one end grounded and the other end connected to the power combining node Z1 of the T-type power combining network to achieve differential-to-single-ended signal conversion and impedance matching.

[0029] The T-type power combining network includes a transformer and a tuning capacitor, which are used to superimpose the single-ended signals from the two branches after being transformed by the output matching transformer TF3 at node Z1. The output matching transformer TF3 matches the output impedance of the power stage amplifier to 2Z1. After the two branches are combined by the T-type power combining network, the impedance at node Z1 becomes Z1. Then, through the tuning of the parallel tuning capacitor C5, it is finally matched to the standard load impedance.

[0030] like Figure 1As shown, the stacked power amplifier based on transformer combining provided by this invention adopts a symmetrical dual-branch architecture. Based on 65nm CMOS process, it is adapted to the 22-26GHz wideband operating requirements. The core relies on transformer combining technology to achieve efficient power superposition. The whole includes a T-type power distribution network, two power amplification branches with the same parameters, a T-type transformer power combining network, and an input / output tuning matching unit. After the radio frequency signal is input from the RFin terminal, it is first pre-matched to the input impedance by the parallel tuning capacitor C0 to suppress signal reflection. Then, it is converted into two differential signals with equal amplitude and consistent phase by the T-type power distribution network, which are respectively input to the two power amplification branches. Each power amplification branch is electrically connected in sequence along the signal flow direction to the input matching transformer TF1, the driver stage amplifier (DA), the interstage matching transformer TF2, the power stage amplifier PA with a 3-stacked transistor topology, and the output matching transformer TF3. The output signals of the two branches are combined with equal amplitude and in phase by the T-type transformer power combining network, and then the output impedance is matched by the parallel tuning capacitor C5. Finally, the amplified radio frequency signal is output from the RFout terminal.

[0031] like Figure 2 As shown, the driver stage amplifier DA adopts a differential common-source topology, with enhancement-mode NMOS transistors M1 and M2 as its core. The gate of M1 is connected to the secondary terminal IN1+ of the input matching transformer TF1, and the gate of M2 is connected to the secondary terminal IN1-. The sources of both are grounded, and their drains are the differential output terminals OUT1- and OUT1+, respectively. The driver stage is also equipped with two neutralizing capacitors Cx1, which are connected across the drain of M1 and the gate of M2, and the drain of M2 and the gate of M1, respectively. These are used to neutralize the gate-drain parasitic capacitance Cgd of M1 and M2, suppress high-frequency parasitic feedback, and improve gain flatness, providing a stable signal foundation for subsequent transformer synthesis.

[0032] like Figure 3 , Figure 4 As shown, the power stage amplifier (PA) adopts a differential cascode topology with three stacked transistors. Each differential branch includes three series-stacked enhancement-mode NMOS transistors: bottom-level transistors M3 / M4, middle transistors M5 / M6, and top-level transistors M7 / M8. The design of the core capacitors Cg1 and Cg2, shunt capacitor Cf, and neutralizing capacitor Cx2 fully integrates core technologies such as wideband voltage division, parasitic suppression, and power matching, forming a synergistic optimization with the transformer synthesis network. The gate of the bottom-level transistor (common-source transistor) is connected to the secondary terminal of the interstage matching transformer TF2 via a bias resistor, the source is grounded, and the drain is connected to the source of the middle transistor. The gate of the intermediate transistor (voltage divider) is connected to the bias voltage VB3 via a parallel voltage divider capacitor Cg1 and a series resistor Rg1. The core design of Cg1 is based on the 22-26GHz wideband voltage divider principle. The final simulation optimization is adapted to the 22-26GHz frequency band. This capacitor and the gate-source capacitor Cgs of the intermediate transistor are connected in series to form a high-frequency capacitive voltage divider. This not only achieves a uniform distribution of the AC voltage swing between the drain and source of the intermediate transistor and the bottom transistor, but also compensates for the parasitic capacitance of the stacked structure nodes, cancels the parasitic inductance caused by PCB vias and wiring, ensures phase consistency in the wideband, and ensures the amplitude and phase synchronization during transformer synthesis. The gate of the top-layer transistor (common-gate transistor) is connected to the bias voltage VB4 via a parallel voltage divider capacitor Cg2 and a series resistor Rg2. Cg2 and the gate-source capacitor Cgs of the top-layer transistor form a secondary voltage divider mechanism. After wideband impedance matching optimization, its capacitance value forms a synergistic voltage divider effect with Cg1, so that the total drain-source voltage swing of the three stacked transistors (close to the power supply voltage VDD2) is evenly distributed in the 22-26GHz full frequency band. This ensures that the drain-source voltage of a single transistor is always controlled within the rated withstand voltage range (≤1.2V) of the 65nm CMOS process, effectively avoiding the breakdown risk caused by wideband signal fluctuations and improving long-term operational reliability. Meanwhile, a shunt capacitor Cf is connected between the source and drain of the top-layer transistor. This capacitor is a core optimization component for 22-26GHz wideband parasitic suppression: In the 22-26GHz wideband range, the parasitic capacitance of the intermediate node of the stacked structure will cause the drain voltage swing phase of each stacked transistor to be inconsistent, which will not only reduce power performance, but may also cause the drain-source voltage to exceed the breakdown voltage. Cf uses the Miller effect to generate a negative capacitance of (1-A)×Cf at the source of the top-layer transistor, where A is the voltage gain of the top-layer transistor, and A>1), which can accurately cancel the parasitic capacitance of the source of the top-layer transistor and align the drain voltage swing phase of each stacked transistor. This design works in deep collaboration with the output matching transformer and T-type synthesis network, which not only suppresses wideband parasitic effects, but also improves the peak power added efficiency (PAE) of the amplifier to 32.55% in the entire frequency band. Compared with the traditional structure without Cf, the wideband efficiency is improved by 3-5 percentage points, and no large area is required, which effectively reduces the core area of ​​the chip. The power stage is also equipped with neutralizing capacitors Cx2, which are connected across the gate of M3 and the source of M6, and the gate of M4 and the source of M5, respectively. This capacitor is designed with transistor parasitic parameters optimized by 65nm CMOS process. In addition to offsetting the high-frequency parasitic feedback caused by Miller capacitance Cgd, it also suppresses parasitic feedback drift in a wide frequency band by working together with the capacitance values ​​of Cg1 and Cg2, ensuring that the gain flatness in the 22-26GHz band is ≤0.79dB. At the same time, its layout is close to the gate and drain of the transistor, reducing the parasitic inductance of PCB wiring, and further enhancing the impedance matching accuracy of the stacked structure and the input / stage matching transformer. Furthermore, the cascaded interconnect architecture of the three stacked transistors in this topology differs from that of traditional common-source common-gate amplifiers. Its gate bias circuit (Rg1, Rg2 and VB3, VB4) adopts a wideband stability design. By adjusting the gate resistor value, the stacked transistors operate in the saturation region within a wide frequency range of 22-26GHz, avoiding bias drift caused by frequency changes. This design, together with the T-type power distribution network, differential transformer matching network, and T-type transformer synthesis network, forms an integrated synergy to ensure that the amplifier simultaneously achieves high power output, high efficiency, and high linearity within the 22-26GHz wideband.

[0033] like Figure 5 , Figure 6 , Figure 7 As shown, the input matching transformer TF1, interstage matching transformer TF2, and output matching transformer TF3 all adopt high-frequency differential transformers with helical coil structures, which are the core support for transformer synthesis technology: the primary coil of the input matching transformer TF1 is connected to the output of the T-type distribution network at one end and grounded at the other end. The secondary is a differential structure connected to the input of the driver stage, and the center tap is connected to the bias voltage VB1 to provide gate bias for the driver stage. The interstage matching transformer TF2 achieves impedance conjugate matching between the driver stage and the power stage through the T-type equivalent network and the tuning capacitor. The primary is connected to the output of the driver stage, and the center tap is connected to the power supply VDD1. The secondary is connected to the input of the power stage, and the center tap is connected to the bias voltage VB2 to provide bias for the bottom transistor of the power stage. The output matching transformer TF3 matches the output impedance of the power stage to 2Z1. The primary is connected to the output of the power stage, and the center tap is connected to the power supply VDD2. One end of the secondary is grounded, and the other end is connected to the synthesis point Z1 of the T-type transformer synthesis network, realizing differential to single-ended signal conversion and impedance matching, laying the foundation for efficient power synthesis of the two branch signals.

[0034] Figure 8 The simulated output power of the stacked power combining amplifier at 24 GHz provided in this embodiment of the invention shows that the saturated output power is 27 dBm, which has a high saturated output power and meets the high output power requirement. Figure 9 The additional efficiency of the stacked power combining amplifier at 24 GHz provided in the embodiment of the present invention is 32.55% under simulation, which meets the high-efficiency design requirements; Figure 10 The S21 simulation curve of the stacked power combining amplifier in the 22-26GHz band provided in this embodiment of the invention shows a gain of 29dB and a gain flatness of less than 1dB, indicating that the power gain is stable in the target frequency band and meets the high gain requirement. Figure 11The S11 simulation curve of the stacked power combining amplifier in the 22-26GHz band provided in the embodiment of the present invention shows that S11 is less than -10dB, indicating good input impedance matching. Figure 12 The simulation curve of the 1dB compression point of the stacked power combining amplifier at 24GHz provided in the embodiment of the present invention shows that the 1dB compression point is 24.1dBm, which shows excellent linear performance.

[0035] This invention employs a symmetrical dual-branch architecture and 65nm CMOS process, adapting to the 22-26GHz wideband operating requirements. Its core relies on transformer synthesis technology and a 3-stacked transistor differential cascode topology. Through the coordinated design of voltage divider capacitors Cg1 / Cg2, shunt capacitor Cf, neutralizing capacitor Cx2, and a stable bias circuit, it specifically addresses the core technical challenges faced by CMOS process power amplifiers. To address the issues of low voltage withstand capability, limited voltage swing of a single transistor, constraints of traditional cascode topologies, low voltage division accuracy of existing stacked structures relying on bias resistors, and susceptibility to overvoltage damage of a single transistor under strong signals, Cg1 / Cg2, together with the gate-source capacitor of the transistor, forms a high-frequency voltage divider. This precisely distributes the drain-source voltage swing, ensuring that the voltage withstand capability of a single transistor is ≤1.2V, thus overcoming the voltage swing limitation while avoiding overvoltage damage. To address the issues of insufficient impedance matching accuracy, high reflection loss, and low combining efficiency in traditional power combining networks, a differential transformer matching network and a T-type transformer power distribution / combining architecture are adopted to significantly improve impedance matching accuracy and combining efficiency while reducing reflection loss. To address the significant insertion loss and nonlinear losses of devices in power distribution and combining networks, as well as low link energy utilization efficiency, Cf utilizes the Miller effect to offset the parasitic capacitance of the top-layer transistor, and Cx2 suppresses high-frequency parasitic feedback. Combined with the low-loss design of the stacked topology and transformer network, link insertion loss and nonlinear losses are reduced, thereby improving energy utilization efficiency.

[0036] Ultimately, this invention achieves 27dBm saturated output power, 24.3% peak PAE, ≤0.79dB gain flatness, and a 1dB compression point above 24.8dBm in the 22-26GHz frequency band. It also features excellent impedance matching performance and linearity. It can overcome the bottleneck of limited output power of CMOS process power amplifiers without occupying a large area, meet the needs of high-frequency and high-power communication scenarios, and adapt to the high-power and wide-bandwidth application requirements of 5G millimeter-wave phased array system RF front-end.

[0037] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several changes and improvements without departing from the overall concept of the present invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A stacked power amplifier based on transformer synthesis, characterized by: The symmetric double-branch architecture comprises an input tuning matching unit, a T-shaped power distribution network, two power amplification branches, a T-shaped power synthesis network and an output tuning matching unit. The input tuning matching unit comprises a parallel tuning capacitor C0, a first end of which is electrically connected to a radio frequency signal input end RFin, and a second end of which is grounded, for pre-matching the input impedance. A common input end of the T-shaped power distribution network is electrically connected to the first end of the parallel tuning capacitor C0, for converting the pre-matched input signal into two symmetric differential signals, and outputting the two symmetric differential signals to the two power amplification branches respectively. Each of the power amplification branches comprises an input matching transformer, a driver stage amplifier (DA), an inter-stage matching transformer, a power stage amplifier (PA) and an output matching transformer in sequence, wherein the power stage amplifier adopts a differential common-gate topology of three stacked transistors. Input ends of the T-shaped power synthesis network are electrically connected to secondary sides of the output matching transformers of the two power amplification branches respectively, for performing equal-amplitude and in-phase power synthesis on the signals amplified by the two branches. The output tuning matching unit comprises a parallel tuning capacitor C5, a first end of which is electrically connected to an output end of the T-shaped power synthesis network, and a second end of which is grounded, for performing output impedance matching on the synthesized signal, and outputting the signal from a radio frequency signal output end RFout.

2. The transformer synthesis based stacked power amplifier of claim 1, wherein: The T-shaped power distribution network comprises two transformers and tuning capacitors connected therebetween, and is capable of stably outputting two differential signals with equal amplitude and consistent phase to primary sides of the input matching transformers of the power amplification branches.

3. The transformer synthesis based stacked power amplifier of claim 1, wherein: The input matching transformer is a high-frequency differential transformer TF1, one end of a primary coil of which is connected to an output signal of the T-shaped power distribution network, and the other end of the primary coil is grounded; a secondary coil of the input matching transformer is in a differential structure, and two ends of the secondary coil are connected to differential input ends IN1+ and IN1- of the driver stage amplifier respectively; a center tap of the secondary coil is connected to a gate bias voltage VB1, for providing a static working point for the driver stage amplifier.

4. The transformer synthesis based stacked power amplifier of claim 3, wherein: The driver stage amplifier (DA) adopts a differential common-source topology, and comprises a first enhancement-mode NMOS transistor M1 and a second enhancement-mode NMOS transistor M2. A gate of the M1 is connected to IN1+, and a gate of the M2 is connected to IN1-; source electrodes of the M1 and the M2 are commonly grounded; a drain electrode of the M1 is a differential output end OUT1-, and a drain electrode of the M2 is a differential output end OUT1+. The driver stage amplifier further comprises two neutralizing capacitors Cx1: a first neutralizing capacitor Cx1 is connected between the drain electrode of the M1 and the gate of the M2, and a second neutralizing capacitor Cx1 is connected between the drain electrode of the M2 and the gate of the M1, for neutralizing gate-drain parasitic capacitances of the M1 and the M2.

5. The transformer synthesis based stacked power amplifier of claim 4, wherein: The inter-stage matching transformer is a high-frequency differential transformer TF2. Two ends of a primary coil of the inter-stage matching transformer are electrically connected to the differential output ends OUT1- and OUT1+ of the driver stage amplifier respectively, and a center tap of the primary coil of the inter-stage matching transformer is connected to a driver stage power supply VDD1. The secondary coil is a differential structure, and two ends are respectively connected to the differential input terminals IN2+ and IN2- of the power stage amplifier, and the center tap of the secondary coil is connected to the gate bias voltage VB2, which is used to provide bias for the bottom transistor of the power stage amplifier.

6. The transformer synthesis based stacked power amplifier of claim 5, wherein: The power stage amplifier (PA) is a differential structure, and each differential branch includes three enhancement mode NMOS tubes stacked in series: The bottom tube includes the third NMOS tube M3 and the fourth NMOS tube M4, the gate of which is connected to the secondary differential end of the inter-stage matching transformer TF2 through a bias resistor, the source is grounded, and the drain is respectively connected to the source of the middle tube; The middle tube includes the fifth NMOS tube M5 and the sixth NMOS tube M6, the gate of which is connected to the middle tube bias voltage VB3 through the first voltage dividing capacitor Cg1 and the first gate resistor Rg1, and the drain is respectively connected to the source of the top tube; The top tube includes the seventh NMOS tube M7 and the eighth NMOS tube M8, the gate of which is connected to the top tube bias voltage VB4 through the second voltage dividing capacitor Cg2 and the second gate resistor Rg2, and the drain is used as the differential output terminal OUT2- and OUT2+ of the power amplifier branch.

7. The transformer synthesis based stacked power amplifier of claim 6, wherein: Between the source and the drain of the top tube M7 and M8, there is a shunt capacitor Cf connected across, which is used to optimize the voltage distribution of the top tube and shunt the high-frequency parasitic current.

8. Transformer synthesis based stacked power amplifier according to any of claims 6 or 7, characterized in that: The power stage amplifier further includes neutralizing capacitors Cx2: the first neutralizing capacitor Cx2 is connected between the gate of M3 and the source of M6, and the second neutralizing capacitor Cx2 is connected between the gate of M4 and the source of M5, which is used to offset the influence of the transistor gate-drain capacitance.

9. The transformer synthesis based stacked power amplifier of claim 6, wherein: The output matching transformer is a high-frequency differential transformer TF3; Two ends of the primary coil of the output matching transformer are respectively electrically connected to the differential output terminals OUT2- and OUT2+ of the power stage amplifier, and the center tap of the primary coil is connected to the power stage power supply VDD2; One end of the secondary coil is grounded, and the other end is connected to the power synthesis node Z1 of the T-type power synthesis network, which is used to realize differential-to-single-ended signal conversion and impedance matching.

10. The transformer synthesis based stacked power amplifier of claim 9, wherein: The T-type power synthesis network includes a transformer and a tuning capacitor, which is used to power add the single-ended signals from the two branches at node Z1 after being transformed by the output matching transformer TF3; the output matching transformer TF3 matches the output impedance of the power stage amplifier to 2Z1, and after two-way synthesis through the T-type power synthesis network, the impedance at node Z1 becomes Z1, and finally matches to the standard load impedance through the tuning of the parallel tuning capacitor C5.

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