Terminal, clock synchronization circuit, system, method and storage medium

Abstract

The application provides a terminal, a clock synchronization circuit, a system, a method and a storage medium. The clock synchronization circuit comprises: a crystal oscillator which is started to provide a first clock signal in a working state of the terminal; an RC oscillator which is started to provide a second clock signal different from the first clock signal in a sleep state of the terminal; a timer which is connected to the RC oscillator and is started to time based on the second clock signal in the sleep state of the terminal; the timing time reaches a preset time, the terminal is in the working state, the crystal oscillator is started, and the RC oscillator is kept started; a calibrator which is connected to the crystal oscillator and the RC oscillator, detects the first clock signal and the second clock signal in the working and sleep states, and judges whether a preset condition is met, and if not, calibrates the second clock signal based on the first clock signal; and a controller which is connected to and controls the crystal oscillator, the RC oscillator, the timer and the calibrator to start or stop and controls the terminal to switch between the working state and the sleep state, so that a trade-off among low cost, low power consumption and clock accuracy is realized.

Description

Technical Field

[0001] This invention relates generally to the field of electronic circuit technology, and more particularly to a terminal, clock synchronization circuit, system, method and storage medium. Background Technology

[0002] With the continuous development of the Internet of Things (IoT), time synchronization is crucial. Existing time synchronization solutions employ high-frequency clocks, which are costly and power-consuming, failing to meet the demands for low cost and low power consumption. Therefore, a new technical solution is urgently needed to address these issues.

[0003] The content of the background section is merely the technology known to the inventor and does not necessarily represent the prior art in this field. Summary of the Invention

[0004] In view of one or more of the problems existing in the prior art, the present invention provides a terminal, clock synchronization circuit, system, method and storage medium that can reduce cost and power consumption.

[0005] According to a first aspect of the present invention, a clock synchronization circuit is provided. The clock synchronization circuit includes:

[0006] A crystal oscillator is configured to be activated when the terminal is in an operational state to provide a first clock signal to the terminal.

[0007] An RC oscillator is configured to be activated when the terminal is in a sleep state to provide the terminal with a second clock signal, the second clock signal being different from the first clock signal;

[0008] A timer, connected to the RC oscillator and configured to be started when the terminal is in sleep mode, performs timing based on the second clock signal; when the timing reaches a preset time, the terminal is in the working state, the crystal oscillator is started, and the RC oscillator remains started;

[0009] A calibrator, connected to the crystal oscillator and the RC oscillator, is configured to be activated when the terminal is in an operational state, detect the first clock signal and the second clock signal, and determine whether the first clock signal and the second clock signal meet a preset condition. If the preset condition is not met, the calibrator performs calibration on the second clock signal based on the first clock signal; and

[0010] The controller, connected to the crystal oscillator, the RC oscillator, the timer, and the calibrator, is configured to control the crystal oscillator, the RC oscillator, the timer, and the calibrator to start or stop, and to control the terminal to switch between working and sleeping states.

[0011] Optionally, the clock synchronization circuit further includes a phase-locked loop (PLL) connected to the crystal oscillator and the controller, configured to be activated by the controller when the terminal is in the operating state, and to process the first clock signal.

[0012] Optionally, the controller is configured to shut down the crystal oscillator and the phase-locked loop when the terminal is in the sleep state.

[0013] Optionally, the first clock signal has a first period and a first frequency, and the second clock signal has a second period and a second frequency, wherein the second period is greater than the first period and the second frequency is lower than the first frequency.

[0014] Optionally, the calibrator is configured to count the number of first clock signals under a preset number of second clock signals, and determine whether the number is equal to the preset number. If the number is not equal to the preset number, the second clock signal is calibrated based on the first clock signal.

[0015] Optionally, the calibrator is configured to detect that the number is greater than the preset number, and then decrease the second period or increase the second frequency, wherein the second frequency is the reciprocal of the second period.

[0016] Optionally, the calibrator is configured to increase the second period or decrease the second frequency if it detects that the number is less than the preset number.

[0017] According to a second aspect of the present invention, a terminal is provided. The terminal includes a clock synchronization circuit as described above, and the terminal includes a fire alarm terminal.

[0018] According to a third aspect of the present invention, a clock synchronization system is provided. The clock synchronization system includes:

[0019] Gateway; and

[0020] One or more terminals include a clock synchronization circuit, the clock synchronization circuit including a crystal oscillator, an RC oscillator, a timer, a calibrator, and a controller, the timer being connected to the RC oscillator; the calibrator being connected to the crystal oscillator and the RC oscillator; the controller being connected to the crystal oscillator, the RC oscillator, the timer, and the calibrator.

[0021] The gateway is configured to generate a time slot signal and send a time synchronization signal based on the number of terminal nodes registered on the network.

[0022] The terminal is configured to switch to the working state, start the crystal oscillator, receive the time synchronization signal, synchronize the first clock signal based on the time synchronization signal, and send an uplink signal to the gateway.

[0023] The gateway is configured to receive the uplink signal and send the downlink signal to the terminal;

[0024] The terminal is configured to switch to a sleep state, start the RC oscillator and the timer, and turn off the crystal oscillator. The RC oscillator is configured to provide a second clock signal, which is different from the first clock signal. The terminal is configured to synchronize based on the second clock signal. The timer is configured to time based on the second clock signal. When the timer reaches a preset time, the terminal is configured to switch to the working state, start the crystal oscillator and the calibrator, and keep the RC oscillator running. The calibrator is configured to detect the first clock signal and the second clock signal, and determine whether the first clock signal and the second clock signal meet preset conditions. If the preset conditions are not met, the second clock signal is calibrated based on the first clock signal.

[0025] Optionally, the clock synchronization circuit further includes a phase-locked loop (PLL) connected to the crystal oscillator and the controller, configured to be activated by the controller when the terminal is in the operating state, and to process the first clock signal.

[0026] Optionally, the controller is configured to shut down the crystal oscillator and the phase-locked loop when the terminal is in the sleep state.

[0027] Optionally, the first clock signal has a first period and a first frequency, and the second clock signal has a second period and a second frequency, wherein the second period is greater than the first period and the second frequency is lower than the first frequency.

[0028] Optionally, the calibrator is configured to count the number of first clock signals under a preset number of second clock signals, and determine whether the count is equal to the preset number. If the count is not equal to the preset number, the second clock signal is calibrated based on the first clock signal. Optionally, the calibrator is configured to, upon detecting that the count is greater than the preset number, decrease the second period or increase the second frequency, where the second frequency is the reciprocal of the second period.

[0029] Optionally, the calibrator is configured to increase the second period or decrease the second frequency if it detects that the number is less than the preset number.

[0030] According to a fourth aspect of the present invention, a clock synchronization method is provided, performed by the clock synchronization system described above. The clock synchronization method includes:

[0031] The gateway generates time slot signals based on the number of terminal nodes registered on the network and sends time synchronization signals.

[0032] The terminal switches to the working state, starts the crystal oscillator, receives the time synchronization signal, synchronizes the first clock signal based on the time synchronization signal, and sends an uplink signal to the gateway.

[0033] The gateway receives the uplink signal and sends the downlink signal to the terminal.

[0034] The controller switches the terminal to sleep mode, starts the RC oscillator and the timer, and shuts down the crystal oscillator. The RC oscillator provides a second clock signal, which is different from the first clock signal. The terminal synchronizes based on the second clock signal. The timer performs timing based on the second clock signal. When the timing reaches a preset time, the controller switches the terminal to working mode, starts the crystal oscillator and the calibrator, and keeps the RC oscillator running. The calibrator detects the first clock signal and the second clock signal and determines whether they meet preset conditions. If they do not meet the preset conditions, the second clock signal is calibrated based on the first clock signal.

[0035] Optionally, the clock synchronization method further includes: starting a phase-locked loop when the terminal is in the working state and processing the first clock signal; and turning off the crystal oscillator and the phase-locked loop when the terminal is in the sleep state.

[0036] Optionally, the first clock signal has a first period and a first frequency, and the second clock signal has a second period and a second frequency, wherein the second period is greater than the first period and the second frequency is lower than the first frequency.

[0037] Optionally, the clock synchronization method further includes: counting the number of first clock signals under a preset number of second clock signals using the calibrator, and determining whether the number is equal to the preset number; if the number is not equal to the preset number, calibrating the second clock signal based on the first clock signal.

[0038] Optionally, if the preset conditions are not met, calibrating the second clock signal based on the first clock signal includes: if the number is greater than the preset number, then reducing the second period or increasing the second frequency, where the second frequency is the reciprocal of the second period.

[0039] Optionally, if the preset conditions are not met, calibrating the second clock signal based on the first clock signal includes: if the number is less than the preset number, increasing the second period or decreasing the second frequency.

[0040] According to a fifth aspect of the present invention, a computer-readable storage medium is provided. The computer-readable storage medium includes computer-executable instructions stored thereon, which, when executed by a processor, implement the clock synchronization method described above.

[0041] The clock synchronization circuit of this invention, by setting up an RC oscillator, a timer, and a calibrator, can replace a 32.768kHz frequency crystal oscillator, reducing cost and power consumption. In other words, this invention achieves a low-cost replacement of the 32.768kHz frequency crystal oscillator while maintaining low power consumption. When the terminal is in working mode, the crystal oscillator is activated, providing the terminal with a high-precision and high-stability first clock signal. When the terminal is in sleep mode, the crystal oscillator is turned off to save power, and the RC oscillator and timer are activated. The RC oscillator provides the terminal with a second clock signal. The timer performs timing based on the second clock signal. When the timing reaches a preset time, the terminal switches to working mode, the RC oscillator remains on, and the crystal oscillator and calibrator are activated. The calibrator detects the first and second clock signals and determines whether the first and second clock signals meet preset conditions. If the preset conditions are not met, the second clock signal is calibrated based on the first clock signal. The clock synchronization circuit of this invention achieves a trade-off between low cost, low power consumption, and clock accuracy. Attached Figure Description

[0042] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0043] Figure 1 A schematic diagram of a clock synchronization circuit according to some embodiments of the present invention is shown.

[0044] Figure 2 A schematic diagram of a terminal according to some embodiments of the present invention is shown.

[0045] Figure 3A A partial circuit diagram of an RC oscillator according to some embodiments of the present invention is shown.

[0046] Figure 3B A partial circuit diagram of an RC oscillator according to some embodiments of the present invention is shown.

[0047] Figure 4 A schematic diagram of a clock synchronization circuit according to some embodiments of the present invention is shown.

[0048] Figure 5 A schematic diagram illustrating whether a first clock signal and a second clock signal satisfy preset conditions according to some embodiments of the present invention.

[0049] Figure 6 A schematic diagram of a terminal according to some embodiments of the present invention is shown.

[0050] Figure 7 A schematic diagram of a clock synchronization system according to some embodiments of the present invention is shown.

[0051] Figure 8 A schematic diagram of a frame period slot structure for a gateway frame in TDMA mode according to some embodiments of the present invention is shown.

[0052] Figure 9 A schematic diagram illustrating communication between a terminal and a gateway in a TDMA system according to some embodiments of the present invention is shown.

[0053] Figure 10 A flowchart illustrating a clock synchronization method performed by a clock synchronization system according to some embodiments of the present invention is shown. Detailed Implementation

[0054] In the following description, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of the invention. Therefore, the drawings and description are considered to be exemplary in nature and not restrictive.

[0055] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0056] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "coupling" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows for communication; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0057] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0058] The following provides many different embodiments or examples for implementing various structures of the invention. To simplify the invention, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the invention. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, examples of various specific processes and materials are provided in this invention, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0059] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0060] This invention provides a clock synchronization circuit. This invention also provides a terminal. Figure 1 A schematic diagram of a clock synchronization circuit 10 according to some embodiments of the present invention is shown. Figure 2 A schematic diagram of a terminal 20 according to some embodiments of the present invention is shown. Figure 1 and Figure 2 As shown, the clock synchronization circuit 10 includes a crystal oscillator 11, an RC oscillator 12, a timer 13, a calibrator 14, and a controller 15. Terminal 20 includes the clock synchronization circuit 10. Terminal 20 may include a fire alarm terminal. For example, a fire alarm terminal may include a smoke detector, a heat detector, a flame detector, a gas detector, a composite detector, etc.

[0061] Crystal oscillator 11 is used to provide a first clock signal CLK1 with high precision and high stability. In some embodiments, crystal oscillator 11 is configured to be activated when terminal 20 is in an operating state, providing the first clock signal CLK1 to terminal 20. The first clock signal CLK1 has a first period T1 and a first frequency f1. The first frequency f1 is the reciprocal of the first period T1. That is, f1 = 1 / T1. For example, the first clock signal CLK1 can be 26MHz, 32MHz, 36MHz, etc. In some embodiments, crystal oscillator 11 is configured to be turned off when terminal 20 is in a sleep state to save power. For example, crystal oscillator 11 can include a non-temperature compensated crystal oscillator, a temperature compensated crystal oscillator, a voltage-controlled crystal oscillator, a temperature-controlled crystal oscillator, and a digitally compensated crystal oscillator, etc. It should be noted that the present invention does not limit the specific implementation and frequency of crystal oscillator 11; in practical applications, it can be configured according to requirements.

[0062] The RC oscillator 12 is low-cost, small-sized, and has a fast startup speed, and is used to provide the second clock signal CLK2. In some embodiments, the RC oscillator 12 is configured to be started when the terminal 20 is in a sleep state to provide the second clock signal CLK2 to the terminal 20. In some embodiments, the RC oscillator 12 is configured to remain started when the terminal 20 is in an operating state for clock calibration. In some embodiments, the RC oscillator 12 is configured to be turned off when the terminal 20 is in an operating state to save power. The second clock signal CLK2 has a second period T2 and a second frequency f2. The second frequency f2 is the reciprocal of the second period T2, that is, f2 = 1 / T2. The second clock signal CLK2 is different from the first clock signal CLK1. In some embodiments, the second period T2 is greater than the first period T1. The second frequency f2 is lower than the first frequency f1. For example, the second clock signal CLK2 can be 32.768kHz.

[0063] The RC oscillator 12 includes an oscillation circuit that generates periodic voltage changes through the charging and discharging process of a capacitor, thereby achieving oscillation.

[0064] Figure 3A and Figure 3B Partial circuit diagrams of RC oscillators according to some embodiments of the present invention are shown. Figure 3A and Figure 3B As shown, the RC oscillator 12 includes a first comparator CMP1, a second comparator CMP2, an RS flip-flop, a first P-type MOS transistor PMOS1, a first N-type MOS transistor NMOS1, a first capacitor C1, a second P-type MOS transistor PMOS2, a second N-type MOS transistor NMOS2, and a second capacitor C2. In some embodiments, the first capacitor C1 and the second capacitor C2 are charged and discharged alternately. The capacitance values ​​of the first capacitor C1 and the second capacitor C2 can be the same. In some embodiments, the circuit structures of the first comparator CMP1 and the second comparator CMP2 can be the same. The width-to-length ratios of PMOS1 and PMOS2 can be the same. The width-to-length ratios of NMOS1 and NMOS2 can be the same. It should be noted that this is only an exemplary description, and the present invention is not limited thereto. In practical applications, appropriate devices and specifications can be configured accordingly.

[0065] like Figure 3A and Figure 3BAs shown, the positive input of the first comparator CMP1 is connected to the upper plate node of the first capacitor C1 (hereinafter referred to as the first voltage node N1 for ease of description), and the negative input is connected to a reference voltage source, which provides a reference voltage Vref. The positive input of the second comparator CMP2 is connected to the upper plate node of the second capacitor C2 (hereinafter referred to as the second voltage node N2), and the negative input is also connected to the reference voltage Vref. The output of the first comparator CMP1 is connected to the set terminal S of the RS flip-flop, and the output of the second comparator CMP2 is connected to the reset terminal R of the RS flip-flop. The first output CH1 of the RS flip-flop is connected to the gate G of PMOS1 and NMOS1. The second output CH2 of the RS flip-flop is connected to the gate G of PMOS2 and NMOS2. The first output CH1 and the second output CH2 are complementary outputs of the RS flip-flop, and their states are always opposite.

[0066] like Figure 3A and Figure 3B As shown, the source S of PMOS1 is connected to the positive terminal of the power supply (or a reference current source, which can provide a reference current Iref), and its drain D is connected to the first voltage node N1. The drain D of NMOS1 is connected to the first voltage node N1, and its source S is grounded to VSS. The first capacitor C1 is connected between the first voltage node N1 and ground VSS. PMOS1, NMOS1, the first voltage node N1, and the first capacitor C1 together form the first charging and discharging path. It can be understood that the voltage Vp of the first voltage node N1 is the voltage across the first capacitor C1. The output state of the first comparator CMP1 affects the RS flip-flop, determines the state of the first output terminal CH1, and thus controls the on / off state of PMOS1 and NMOS1, thereby determining whether the first capacitor C1 is in a charging or discharging state.

[0067] like Figure 3A and Figure 3B As shown, the source S of PMOS2 is connected to the positive terminal of the power supply (or a reference current source, which can provide a reference current Iref), and its drain D is connected to the second voltage node N2. The drain D of NMOS2 is connected to the second voltage node N2, and its source S is grounded to VSS. The second capacitor C2 is connected between the second voltage node N2 and ground VSS. PMOS2, NMOS2, the second voltage node N2, and the second capacitor C2 together form the second charging and discharging path. It can be understood that the voltage VN of the second voltage node N2 is the voltage across the second capacitor C2. The output state of the second comparator CMP2 affects the RS flip-flop, determines the state of the second output terminal CH2, and thus controls the on / off state of PMOS2 and NMOS2 and the charging and discharging state of the second capacitor C2.

[0068] For example, when the voltage across the first capacitor C1 is lower than the reference voltage Vref (i.e., Vp < Vref), the first comparator CMP1 outputs a low level (state 0), and the RS flip-flop is reset (state 0). The first output CH1 outputs a low level (state 0), and the second output CH2 outputs a high level (state 1). PMOS1 is turned on, NMOS1 is turned off, Vp voltage increases, and the first capacitor C1 is charged through NMOS1. At the same time, PMOS2 is turned off, NMOS2 is turned on, VN voltage decreases, and the second capacitor C2 is discharged through NMOS2.

[0069] For example, when the voltage Vp across the first capacitor C1 rises above the reference voltage Vref (i.e., Vp > Vref), the output state of the first comparator CMP1 flips to high (state 1), and the RS flip-flop is set (state 1). This causes the output state of the first output terminal CH1 to flip to high (state 1), and the output state of the second output terminal CH2 to low (state 0). After the state switch, PMOS1 is turned off, NMOS1 is turned on, the Vp voltage drops, and the first capacitor C1 discharges through NMOS1. At the same time, PMOS2 is turned on, NMOS2 is turned off, the VN voltage rises, and the second capacitor C2 is charged through NMOS2.

[0070] One charging and discharging cycle of either capacitor C1 or capacitor C2 constitutes one oscillator cycle. Thus, controlled by an RS flip-flop and two comparators, the charging and discharging processes of capacitors C1 and C2 are precisely alternated and compared, generating a precisely periodic oscillation signal (i.e., the second clock signal CLK2). This dual-path symmetrical structure effectively counteracts the effect of the propagation delay of a single comparator on the oscillation period.

[0071] In some traditional solutions, the RC oscillator adopts a single-channel structure, where the charging and discharging of the capacitor are both judged by the same comparator. The inherent propagation delay of the comparator will affect the switching time of the two stages of charging and discharging, resulting in an uncontrollable delay time in the oscillation period. This causes the frequency to vary with process, voltage and temperature, resulting in poor robustness and insufficient stability and reliability.

[0072] Unlike traditional solutions, the RC oscillator in this application employs a two-way symmetrical structure, which can effectively mitigate or even eliminate the adverse effects of comparator propagation delay on the oscillation period accuracy, thereby obtaining an oscillation signal with higher accuracy and stability. Figure 3A , Figure 3BThe dual-channel structure shown features two capacitors (C1 and C2) and switching transistors (PMOS1, NMOS1, PMOS2, NMOS2) that operate alternately under the control of an RS flip-flop. When one capacitor is charging (e.g., C1 charging) and about to trigger the comparator, the other capacitor is discharging (e.g., C2 discharging). This periodic charging and discharging not only shuts off the charging path of one capacitor (e.g., C1) and initiates its discharge, but also immediately starts the charging process of the other capacitor (e.g., C2). In this way, the delay time of the comparator (e.g., CMP1) is "hidden" during the charging start-up process of the other capacitor (e.g., C2). The length of the oscillation period (i.e., the second period T2) is primarily determined by the precise time required for the two capacitors to charge from their discharge state voltage to the reference voltage Vref (this time is precisely set by the reference current Iref, capacitor C, and reference voltage Vref). This allows for precise control of the frequency (i.e., the second frequency f2), ensuring that the frequency remains independent of process, voltage, and temperature variations, exhibiting good robustness and stability.

[0073] In an RC oscillator, the oscillation frequency f2 is determined by the RC time constant and the reference voltage Vref. R is the equivalent resistance implemented through a current source. C is the capacitance of either the first capacitor C1 or the second capacitor C2. Because the circuit employs a dual-path symmetrical structure, the two capacitors alternately charge and discharge, and the discharge process is rapidly completed through a low-resistance path, with a time much shorter than the charging time. Therefore, the oscillation period is mainly determined by the constant-current charging time of a single capacitor, which can be approximated as twice the charging time of a single capacitor.

[0074] The charging time Tcharge for a single capacitor is:

[0075] Tcharge = C*Vref / Iref. Since the two capacitors work alternately, the entire oscillator period (i.e., the second period T2) is twice the charging time of a single capacitor.

[0076] T2 = 2*Tcharge = 2*C*Vref / Iref.

[0077] The corresponding oscillation frequency (i.e., the second frequency f2) is:

[0078] f2=1 / T2=Iref / (2*C*Vref)……(Equation 1).

[0079] In some embodiments, the reference current source can be a variable constant current source. The variable constant current source can provide a variable reference current lref. The first capacitor C1 and the second capacitor C2 can include an adjustable capacitor array with adjustable capacitance values. By adjusting the reference current lref or the capacitance value C of the first capacitor C1 or the second capacitor C2, the second frequency f2 can be precisely controlled. For example, the second frequency f2 can be increased by increasing lref or decreasing C. For example, the second frequency f2 can be decreased by decreasing lref or increasing C.

[0080] Timer 13 is connected to RC oscillator 12 and configured to be started when terminal 20 is in sleep mode, timing based on the second clock signal CLK2. When the preset time is reached, terminal 20 enters the working state, and timer 13 can be turned off to save power. Crystal oscillator 11 is started, while RC oscillator 12 remains on for clock calibration. It should be noted that this invention does not limit the specific implementation of the timer. The timer can be implemented in hardware, software, or a combination of both, as long as timing is achieved. In practical applications, a suitable implementation method can be configured according to requirements.

[0081] The calibrator 14 is connected to the crystal oscillator 11 and the RC oscillator 12, and is configured to be activated when the terminal 20 is in the working state. It detects a first clock signal CLK1 and a second clock signal CLK2, and determines whether the first clock signal CLK1 and the second clock signal CLK2 meet preset conditions. If the preset conditions are not met, the second clock signal CLK2 is calibrated based on the first clock signal CLK1. For example, the calibrator 14 may include a processor. The processor may be the same as or similar to the controller 15. For example, the calibrator 14 may be integrated with the controller 15 or set up independently. For example, the calibrator 14 may be implemented in software. It should be noted that the present invention does not limit the specific implementation of the calibrator. The calibrator can be implemented in hardware, software, or a combination of both. In practical applications, a suitable implementation method can be configured according to requirements.

[0082] Controller 15 connects to crystal oscillator 11, RC oscillator 12, timer 13, and calibrator 14. In some embodiments, crystal oscillator 11 may be housed on a single chip. RC oscillator 12, timer 13, and calibrator 14 may be integrated into another chip. This maintains clock independence and helps improve reliability. In some embodiments, controller 15 may be configured separately, integrated into crystal oscillator 11, or integrated into RC oscillator 12, timer 13, and calibrator 14. In practical applications, the configuration can be tailored to specific requirements.

[0083] The controller 15 is configured to control the crystal oscillator 11, RC oscillator 12, timer 13 and calibrator 14 to start or stop, and to control the terminal to switch between working state and sleep state.

[0084] In some embodiments, controller 15 can control the crystal oscillator 11, RC oscillator 12, timer 13, and calibrator 14 to start or stop based on enable signals. For example, controller 15 controls the crystal oscillator 11 to start or stop based on a first enable signal. For example, controller 15 controls the RC oscillator 12 to start or stop based on a second enable signal. For example, controller 15 controls the timer 13 to start or stop based on a third enable signal. For example, controller 15 controls the calibrator 14 to start or stop based on a fourth enable signal. The first, second, third, and fourth enable signals are all different from each other.

[0085] In some embodiments, the controller 15 can control the terminal 20 to switch between a working state and a sleep state based on a control signal. For example, the controller 15 controls the terminal 20 to switch to a working state (also known as working mode) Mode1 based on a first control signal. For example, the controller 15 controls the terminal 20 to switch to a sleep state (also known as sleep mode, non-working state, or non-working mode) Mode2 based on a second control signal. The first control signal is different from the second control signal. In some embodiments, the controller 15 can control the terminal 20 to periodically switch between a working state and a sleep state. In some embodiments, the controller 15 can control the terminal 20 to switch between a working state and a sleep state based on whether the terminal 20 receives a gateway signal. For example, if the terminal 20 receives a gateway signal, the controller 15 controls the terminal 20 to be in a working state. For example, if the terminal 20 does not receive a gateway signal, the controller 15 controls the terminal 20 to be in a sleep state.

[0086] In some embodiments, the controller 15 may include control circuitry, a central processing unit (CPU), a micro control unit (MCU), a digital signal processor (DSP), other general-purpose processors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, and other components or circuits.

[0087] In some embodiments, the calibrator 14 can count the number of first clock signals CLK1 under a preset number (e.g., n) of second clock signals CLK2 (e.g., m), and determine whether the number (e.g., m) is equal to the preset number m0.

[0088] m0 = n*T2 / T1……(Equation 2)

[0089] If the number of clock signals equals the preset number (m = m0), it indicates that the first clock signal CLK1 and the second clock signal CLK2 meet the preset conditions, meaning that the second clock signal CLK2 has no clock deviation (or the deviation is below the deviation threshold), and calibration is not required. Conversely, if the number of clock signals does not equal the preset number (m ≠ m0), it indicates that the first clock signal CLK1 and the second clock signal CLK2 do not meet the preset conditions, meaning that the second clock signal CLK2 has a clock deviation (or the deviation is not below the deviation threshold), and calibration is required.

[0090] In some embodiments, if the number is not equal to the preset number, i.e., m≠m0, the calibrator 14 can calibrate the second clock signal CLK2 based on the first clock signal CLK1.

[0091] In some embodiments, the calibrator 14 is configured to detect that the number is less than the preset number, i.e., m < m0, or m < n*T2 / T1, indicating that T2 is too small, and the second period T2 can be increased or the second frequency f2 can be decreased. In other words, when m < m0, the calibrator 14 can increase the second period T2 by decreasing the second frequency f2 until the preset condition (m = m0) is met, and obtain the calibrated clock signal CLK2'.

[0092] In some embodiments, the calibrator 14 is configured to detect that the number is greater than the preset number, i.e., m > m0, or m > n*T2 / T1, indicating that T2 is too large, and the second period T2 can be reduced or the second frequency f2 can be increased. In other words, when m > m0, the calibrator 14 can shorten the second period T2 by increasing the second frequency f2 until the preset condition (m = m0) is met, and obtain the calibrated clock signal CLK2'.

[0093] Figure 5 A schematic diagram illustrating whether the first clock signal CLK1 and the second clock signal CLK2 satisfy preset conditions according to some embodiments of the present invention is shown. Figure 5 As shown in part (a), the first clock signal CLK1 and the second clock signal CLK2 satisfy a preset condition, and the second clock signal CLK2 has no clock deviation. Figure 5As shown in part (b), if the number of detected first clock signals CLK1 is less than the preset number, it indicates that T2 is too small, and the first clock signal CLK1 and the second clock signal CLK2 do not meet the preset condition, so the second period T2 can be lengthened. Figure 5 As shown in part (c), if the number of first clock signals CLK1 is greater than the preset number, it means that T2 is too large. The first clock signal CLK1 and the second clock signal CLK2 do not meet the preset conditions, and the second period T2 can be shortened.

[0094] In some embodiments, the first period T1 and the second period T2 have a preset multiple relationship. The calibrator 14 can calculate the deviation ratio between the two by detecting the multiple relationship between the first period T1 and the second period T2. For example, the deviation ratio is the deviation between the number m of CLK1 under n CLK2 cycles and a preset number m0. For instance, if n is 10, f2 is 13kHz, f1 is 26MHz, the calibrator 14 can count the number m of CLK1 cycles under 10 CLK2 cycles, where m is the actual count, and the preset number m0 is 10*26M / 13k = 20000 cycles. Then the deviation ratio is dm = (m-m0) / m0 = (m-20000) / 20000. It should be noted that this is only an illustrative example, and the invention is not limited thereto. After determining the deviation ratio dm, the calibrator 14 can adjust the RC value of the RC oscillator 12 according to the deviation ratio dm. The relationship between the deviation ratio dm and the RC value can be obtained through simulation, and the mapping relationship between the two can be stored in memory in tabular form. During real-time calibration, the calibrator 14 looks up the RC value corresponding to the calculated deviation ratio dm by looking up the table, and calibrates the second period T2 (or the second frequency f2) based on the RC value, thereby calibrating the second clock signal CLK2 and obtaining the calibrated clock signal CLK2'.

[0095] In some embodiments, the memory may include random access memory (RAM) or non-volatile memory (NVM). Further, the memory may include at least one of phase-change random access memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), read-only memory (ROM), and electrically erasable programmable read-only memory (EEPROM). In some embodiments, the memory may include cloud storage.

[0096] In some embodiments, referring to (Equation 1), if Vref remains constant, the calibrator 14 can adjust the second frequency f2 by adjusting lref or C. For example, the calibrator 14 can increase the second frequency f2 by increasing Iref and / or decreasing C. For example, the calibrator 14 can decrease the second frequency f2 by decreasing Iref and / or increasing C.

[0097] In some traditional solutions, the terminal operates and times itself based on the crystal oscillator frequency, regardless of whether it is in active or sleep mode. For example, they often use an RTC chip with a 32.768kHz crystal oscillator. This solution is costly and consumes a lot of power.

[0098] Unlike traditional solutions, the clock synchronization circuit 10 of this invention, by setting up an RC oscillator 12, a timer 13, and a calibrator 14, can replace the 32.768kHz frequency crystal oscillator, reducing cost and power consumption. In other words, this invention achieves a low-cost replacement of the 32.768kHz frequency crystal oscillator while maintaining low power consumption. When the terminal 20 is in the working state, the crystal oscillator 11 is activated, providing the terminal 20 with a high-precision and high-stability first clock signal CLK1. When the terminal 20 is in the sleep state, the crystal oscillator 11 is turned off to save power, and the RC oscillator 12 and timer 13 are activated. The RC oscillator 12 can provide the terminal 20 with a second clock signal CLK2, and the timer 13 can perform timing based on the second clock signal CLK2. When the preset time is reached, terminal 20 switches to working state. RC oscillator 12 remains on, while crystal oscillator 11 and calibrator 14 are activated. Calibrator 14 detects the first clock signal CLK1 and the second clock signal CLK2, and determines whether they meet preset conditions. If not, it calibrates the second clock signal CLK2 based on the first clock signal CLK1. The clock synchronization circuit 10 of this invention achieves a balance between low cost, low power consumption, and clock accuracy.

[0099] Figure 4 A schematic diagram of a clock synchronization circuit 10 according to some embodiments of the present invention is shown. Figure 6 A schematic diagram of a terminal 20 according to some embodiments of the present invention is shown. Figure 4 and Figure 6 As shown, the clock synchronization circuit 10 also includes a phase-locked loop (PLL) 16. The terminal 20 also includes a radio frequency (RF) module 21 and a baseband module 22. The PLL 16 connects the crystal oscillator 11 and the controller 15. The PLL 16 processes the first clock signal CLK1 and outputs a stable clock signal CLK1' to the RF module 21 and the baseband module 22. The RF module 21 and the baseband module 22 operate based on the clock signal CLK1'. The RF module 21 includes an RF antenna and can transmit and receive signals based on the clock signal CLK1'. The baseband module 22 includes a baseband processor that can process the signals transmitted and received by the RF module 21, including but not limited to modulation and demodulation. The PLL 16 achieves phase synchronization between the clock signal CLK1' and the first clock signal CLK1 through a closed-loop feedback mechanism, ensuring that the system maintains a stable phase-locked state under dynamic changes, thus ensuring reliable and stable communication.

[0100] In some embodiments, the controller 15 is configured to start the crystal oscillator 11 and the phase-locked loop 16 when the terminal 20 is in an active state. That is, the phase-locked loop 16 can be started by the controller 15 when the terminal 20 is in an active state. In some embodiments, the controller 15 is configured to shut down the crystal oscillator 11 and the phase-locked loop 16 when the terminal 20 is in a sleep state. For example, the controller 15 controls the crystal oscillator 11 to start or shut down based on a first enable signal. For example, the controller 15 controls the phase-locked loop 16 to start or shut down based on a fifth enable signal. The fifth enable signal is different from the first, second, third, and fourth enable signals.

[0101] In some embodiments, when the terminal 20 is in an active state, the controller 15 can control the radio frequency module 21 and the baseband module 22 to operate. In some embodiments, when the terminal 20 is in a sleep state, the controller 15 can control the radio frequency module 21 and the baseband module 22 to sleep in order to save power consumption.

[0102] The clock synchronization circuit 10 of this invention, and the controller 15, can selectively enable or disable the crystal oscillator 11, RC oscillator 12, timer 13, calibrator 14, and phase-locked loop 16 via a first enable signal, a second enable signal, a third enable signal, a fourth enable signal, and a fifth enable signal. This allows for flexible control of system functions and resource usage, effectively reduces system power consumption, improves energy efficiency, protects the system or equipment from erroneous operation or adverse conditions, prevents system failure or damage due to inappropriate input, and contributes to improved reliability.

[0103] The present invention also provides a clock synchronization system. The clock synchronization system includes a gateway and one or more terminals. Figure 7 A schematic diagram of a clock synchronization system 30 according to some embodiments of the present invention is shown. Figure 7 As shown, the clock synchronization system 30 includes a gateway 31 and multiple terminals 20. Terminals 20 and gateway 31 can communicate with each other. For example, gateway 31 may include an industrial-grade IoT gateway, etc. Terminals 20 may include fire-fighting terminals. For example, fire-fighting terminals may include smoke detectors, heat detectors, flame detectors, gas detectors, composite detectors, etc. This invention does not limit the specific number and type of terminals 20; in practical applications, they can be configured according to requirements. Terminals 20 include a clock synchronization circuit 10, which can reduce cost and power consumption while maintaining clock accuracy and reliability.

[0104] Figure 8 A schematic diagram of a frame period slot structure for a gateway frame in TDMA mode according to some embodiments of the present invention is shown. Figure 9A schematic diagram illustrating communication between a terminal and a gateway in a TDMA system according to some embodiments of the present invention is shown.

[0105] like Figures 1 to 9 As shown, gateway 31 generates a timeslot signal based on the number of registered terminal nodes and sends a time synchronization signal. The time synchronization signal includes the terminal's ID and communication timeslot. For example, refer to... Figure 8 The orange section shows the synchronization time slices 1-N.

[0106] Terminal 20 switches to working mode, starts crystal oscillator 11, receives time synchronization signal, synchronizes with first clock signal CLK1 based on time synchronization signal, and sends uplink signal to gateway 31. (See example for details.) Figure 8 The green section shows the node's uplink time slice 1-M. Figure 8 The example shows node 1 sending uplink time slices to gateway 31 for the 1st, 2nd, 3rd, 4th, and 5th times.

[0107] Gateway 31 receives uplink signals and sends downlink signals to terminal 20. See example [link to example]. Figure 8 As shown in yellow, the gateway sends downlink time slices 1-K.

[0108] Terminal 20 switches to sleep mode, starts RC oscillator 12 and timer 13, and shuts down crystal oscillator 11. RC oscillator 12 provides a second clock signal CLK2, which is different from the first clock signal CLK1. Terminal 20 synchronizes based on the second clock signal CLK2. Timer 13 performs timing based on the second clock signal CLK2.

[0109] When the preset time is reached, terminal 20 switches to working state, starts crystal oscillator 11 and calibrator 14, keeps RC oscillator 12 running, and timer 13 can be turned off.

[0110] The calibrator 14 detects a first clock signal CLK1 and a second clock signal CLK2, and determines whether the first clock signal CLK1 and the second clock signal CLK2 meet preset conditions. If the preset conditions are not met, the second clock signal CLK2 is calibrated based on the first clock signal CLK1. The calibrator 14 is configured to count the number of first clock signals CLK1 under a preset number of second clock signals CLK2, and determine whether the count is equal to a preset number. If the count is not equal to the preset number, the second clock signal CLK2 is calibrated based on the first clock signal CLK1. If the calibrator 14 detects that the count is greater than the preset number, it can reduce the second period or increase the second frequency. If the calibrator 14 detects that the count is less than the preset number, it can increase the second period or decrease the second frequency. Examples similar to those described above will not be repeated here.

[0111] With the continuous development of the Internet of Things (IoT), large-scale terminal devices often require real-time communication such as wake-up and reporting. In wireless systems, TDMA and FDMA are two very important access methods, both of which require reliable time synchronization for communication. In TDMA mode, the gateway typically first sends a time synchronization beacon periodically, and the terminal opens a receiving window at a specified period to complete time synchronization.

[0112] Some time synchronization solutions incorporate temperature compensation at the terminal and improve robustness by adding a threshold for missed time occurrences. Others combine terminal channel activity detection (CAD) technology with dynamic calibration strategies, employing a gradual, dynamic adjustment of the hardware RTC clock compensation value. These techniques often utilize a 32.768kHz crystal oscillator, resulting in high cost and power consumption.

[0113] The clock synchronization system of this invention includes a clock synchronization circuit for each terminal. By using an RC oscillator, a timer, and a calibrator, a 32.768kHz crystal oscillator can be replaced, reducing cost and power consumption. The calibrator can calibrate each terminal's second clock signal based on its own first clock signal. The first clock signal is synchronized based on a time synchronization signal sent from the gateway. This allows for low-cost clock consistency across different terminals, improving system communication real-time performance, stability, effectiveness, and reliability, while also achieving low cost and low power consumption.

[0114] The present invention also provides a clock synchronization method performed by a clock synchronization system. Figure 10 A flowchart illustrating a clock synchronization method 40 performed by a clock synchronization system 30 according to some embodiments of the present invention is shown. Figure 10 As shown, clock synchronization method 40 includes steps S41-S46. Refer to the following... Figures 1 to 10 introduce.

[0115] Step S41: Gateway 31 generates a timeslot signal based on the number of registered terminal nodes and sends a time synchronization signal. The time synchronization signal includes the terminal's ID and communication timeslot. For example, refer to... Figure 8 The orange section shows the synchronization time slices 1-N.

[0116] Step S42: Switch to working state via terminal 20, start crystal oscillator 11, receive time synchronization signal, synchronize the first clock signal CLK1 based on the time synchronization signal, and send uplink signal to gateway 31. For example, refer to... Figure 8 The green section shows the node's uplink time slice 1-M. Figure 8 The example shows node 1 sending uplink time slices to gateway 31 for the 1st, 2nd, 3rd, 4th, and 5th times.

[0117] Step S43: Receive uplink signals through gateway 31 and send downlink signals to terminal 20. For example, refer to... Figure 8 As shown in yellow, the gateway sends downlink time slices 1-K.

[0118] In step S44, the terminal 20 is switched to sleep mode by the controller 15, the RC oscillator 12 and the timer 13 are started, the crystal oscillator 11 is turned off, and the second clock signal CLK2 is provided by the RC oscillator 12. The second clock signal CLK2 is different from the first clock signal CLK1. The terminal 20 is synchronized based on the second clock signal CLK2. The timer 13 is used for timing based on the second clock signal CLK2.

[0119] In step S45, when the preset time is reached, the controller 15 switches the terminal 20 to the working state, starts the crystal oscillator 11 and calibrator 14, keeps the RC oscillator 12 running, and the timer 13 can be turned off. It should be understood that the time synchronization signal includes the terminal's ID and the communication time slot. Upon receiving the time synchronization signal, the terminal 20 can determine the arrival time of its own communication time slot, and the timer 13 can perform timing based on the arrival time of the communication time slot. When the preset time is reached, i.e., when the timing reaches the arrival time of the communication time slot, it indicates that the communication time slot allocated to the terminal 20 by the gateway 31 has arrived. At this time, the timer 13 can be turned off to save power. The terminal 20 switches to the working state, the crystal oscillator 11 and calibrator 14 are started, and the RC oscillator 12 remains running. The calibrator 14 can detect and calibrate the second clock signal CLK2 generated by the RC oscillator 12.

[0120] Step S46: The calibrator 14 detects the first clock signal CLK1 and the second clock signal CLK2, and determines whether the first clock signal CLK1 and the second clock signal CLK2 meet preset conditions. If the preset conditions are not met, the second clock signal CLK2 is calibrated based on the first clock signal CLK1. In some embodiments, the first clock signal has a first period and a first frequency, and the second clock signal has a second period and a second frequency, wherein the second period is greater than the first period and the second frequency is lower than the first frequency.

[0121] In some embodiments, the clock synchronization method 40 further includes: counting the number of first clock signals CLK1 under a preset number of second clock signals CLK2 using a calibrator 14, and determining whether the number is equal to a preset number; if the number is not equal to the preset number, calibrating the second clock signal CLK2 based on the first clock signal CLK1. In some embodiments, if a preset condition is not met, calibrating the second clock signal based on the first clock signal includes: if the number is greater than the preset number, decreasing the second period or increasing the second frequency, where the second frequency is the reciprocal of the second period. In some embodiments, if a preset condition is not met, calibrating the second clock signal based on the first clock signal includes: if the number is less than the preset number, increasing the second period or decreasing the second frequency. Similar to the aforementioned embodiments, further details are omitted here.

[0122] In some embodiments, the clock synchronization method 40 further includes: starting the phase-locked loop 16 when the terminal 20 is in an operating state, and processing the first clock signal CLK1. When the terminal 20 is in a sleep state, the crystal oscillator 11 and the phase-locked loop 16 are turned off. The crystal oscillator 11, calibrator 14, phase-locked loop 16, radio frequency module 21, and baseband module 22 are in the same on or off state. The clock synchronization method of the present invention, executed by a clock synchronization system, achieves clock consistency between different terminals in a low-cost manner, which helps to improve the real-time performance, stability, effectiveness, and reliability of system communication.

[0123] The present invention also provides a computer-readable storage medium. The computer-readable storage medium includes computer-executable instructions stored thereon, which, when executed by a processor, implement the clock synchronization method 40 as described above. The processor may be the same as or similar to the controller 15.

[0124] In some embodiments, the present invention may take the form of a computer program product implemented on one or more storage media containing program code. Computer-usable storage media include permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information may be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to: PRAM, SRAM, DRAM, other types of RAM, ROM, EEPROM, flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital video disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transfer medium that can be used to store information accessible by a computing device.

[0125] It should be noted that this specification provides method operation steps as shown in the embodiments or diagrams, but based on conventional or non-inventive labor, more or fewer operation steps may be included. The order of steps listed in the embodiments is merely one possible execution order among many steps and does not represent the only execution order. In actual system or device products, the methods shown in the embodiments or flowcharts can be executed sequentially or in parallel.

[0126] It should be noted that although several modules of clock synchronization circuits, terminals, and clock synchronization systems have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of the present invention, the features and functions of two or more modules described above can be implemented in one module. Conversely, the features and functions of one module described above can be further divided and embodied by multiple modules. Furthermore, the various modules mentioned in this invention can be implemented in hardware, in software, or a combination of hardware and software.

[0127] It should be noted that the present invention may include Figure 1-10 Any one or more features of any one or more embodiments. In other words, not all features shown in the figures need to be implemented simultaneously in the clock synchronization circuit, terminal, clock synchronization system, or computer-readable storage medium of the present invention. Figure 1-10 Any one or more features of any one or more embodiments can be arbitrarily combined or applied to each other.

[0128] Finally, it should be noted that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A clock synchronization circuit, characterized in that, include: A crystal oscillator is configured to be activated when the terminal is in an operational state to provide the terminal with a first clock signal having a first period and a first frequency. An RC oscillator is configured to be activated when the terminal is in a sleep state to provide the terminal with a second clock signal having a second period and a second frequency, the second clock signal being different from the first clock signal; A timer, connected to the RC oscillator and configured to be started when the terminal is in sleep mode, performs timing based on the second clock signal; when the timing reaches a preset time, the terminal is in the working state, the crystal oscillator is started, and the RC oscillator remains started; The calibrator, connected to the crystal oscillator and the RC oscillator, is configured to be activated when the terminal is in the working state, detect the first clock signal and the second clock signal, and determine whether the first clock signal and the second clock signal meet a preset condition. If the preset condition is not met, the second clock signal is calibrated based on the first clock signal. and The controller, connected to the crystal oscillator, the RC oscillator, the timer, and the calibrator, is configured to control the crystal oscillator, the RC oscillator, the timer, and the calibrator to start or stop, and to control the terminal to switch between working and sleeping states; The calibrator is configured to count the number of first clock signals under a preset number of second clock signals, and determine whether the number is equal to the preset number. If the number is not equal to the preset number, the second clock signal is calibrated based on the first clock signal. The calibrator is configured to detect that the number is greater than the preset number, and then decrease the second period or increase the second frequency, wherein the second frequency is the reciprocal of the second period; The calibrator is configured to increase the second period or decrease the second frequency if it detects that the number is less than the preset number.

2. The clock synchronization circuit according to claim 1, characterized in that, Also includes: A phase-locked loop, connecting the crystal oscillator and the controller, is configured to be activated by the controller when the terminal is in the operating state, and to process the first clock signal.

3. The clock synchronization circuit according to claim 2, characterized in that, The controller is configured to shut down the crystal oscillator and the phase-locked loop when the terminal is in the sleep state.

4. The clock synchronization circuit according to claim 1, characterized in that, The second period is longer than the first period, and the second frequency is lower than the first frequency.

5. A terminal, characterized in that, include: The clock synchronization circuit as described in any one of claims 1-4, wherein the terminal includes a fire terminal.

6. A clock synchronization system, characterized in that, include: Gateway; and One or more terminals include a clock synchronization circuit, the clock synchronization circuit including a crystal oscillator, an RC oscillator, a timer, a calibrator, and a controller, the timer being connected to the RC oscillator; the calibrator being connected to the crystal oscillator and the RC oscillator; the controller being connected to the crystal oscillator, the RC oscillator, the timer, and the calibrator. The gateway is configured to generate a time slot signal and send a time synchronization signal based on the number of terminal nodes registered on the network. The terminal is configured to switch to the working state, start the crystal oscillator, receive the time synchronization signal, synchronize the first clock signal based on the time synchronization signal, and send an uplink signal to the gateway. The first clock signal has a first period and a first frequency. The gateway is configured to receive the uplink signal and send the downlink signal to the terminal; The terminal is configured to switch to a sleep state, start the RC oscillator and the timer, and turn off the crystal oscillator. The RC oscillator is configured to provide a second clock signal, which has a second period and a second frequency, and is different from the first clock signal. The terminal is configured to synchronize based on the second clock signal. The timer is configured to time based on the second clock signal. When the timer reaches a preset time, the terminal is configured to switch to the working state, start the crystal oscillator and the calibrator, and keep the RC oscillator running. The calibrator is configured to detect the first clock signal and the second clock signal, and determine the first clock signal... If the first clock signal and the second clock signal meet a preset condition, and if the preset condition is not met, the second clock signal is calibrated based on the first clock signal; the calibrator is configured to count the number of first clock signals under a preset number of second clock signals, and determine whether the number is equal to the preset number; if the number is not equal to the preset number, the second clock signal is calibrated based on the first clock signal; the calibrator is configured to, if the number is greater than the preset number, decrease the second period or increase the second frequency, where the second frequency is the reciprocal of the second period; if the number is less than the preset number, increase the second period or decrease the second frequency.

7. The clock synchronization system according to claim 6, characterized in that, The clock synchronization circuit also includes: A phase-locked loop, connecting the crystal oscillator and the controller, is configured to be activated by the controller when the terminal is in the operating state, and to process the first clock signal.

8. The clock synchronization system according to claim 7, characterized in that, The controller is configured to shut down the crystal oscillator and the phase-locked loop when the terminal is in the sleep state.

9. The clock synchronization system according to claim 6, characterized in that, The second period is longer than the first period, and the second frequency is lower than the first frequency.

10. A clock synchronization method executed by the clock synchronization system according to any one of claims 6-9, characterized in that, include: The gateway generates time slot signals based on the number of terminal nodes registered on the network and sends time synchronization signals. The terminal switches to the working state, starts the crystal oscillator, receives the time synchronization signal, synchronizes the first clock signal based on the time synchronization signal, and sends an uplink signal to the gateway. The first clock signal has a first period and a first frequency. The gateway receives the uplink signal and sends the downlink signal to the terminal. The controller switches the terminal to sleep mode, starts the RC oscillator and the timer, and shuts down the crystal oscillator. The RC oscillator provides a second clock signal with a second period and a second frequency, which is different from the first clock signal. The terminal then synchronizes based on the second clock signal. Timing is performed using the timer based on the second clock signal; When the preset time is reached, the controller switches the terminal to the working state, starts the crystal oscillator and the calibrator, and keeps the RC oscillator running. The calibrator detects the first clock signal and the second clock signal and determines whether the first clock signal and the second clock signal meet the preset conditions. If the preset conditions are not met, the second clock signal is calibrated based on the first clock signal. The calibrator counts the number of first clock signals under a preset number of second clock signals and determines whether the number is equal to the preset number. If the number is not equal to the preset number, the second clock signal is calibrated based on the first clock signal. If the number is greater than the preset number, then the second period is reduced or the second frequency is increased, where the second frequency is the reciprocal of the second period; If the number is less than the preset number, then the second period is increased or the second frequency is decreased.

11. The clock synchronization method according to claim 10, characterized in that, Also includes: When the terminal is in the working state, the phase-locked loop is started, and the first clock signal is processed; When the terminal is in the sleep state, the crystal oscillator and the phase-locked loop are turned off.

12. The clock synchronization method according to claim 10, characterized in that, The second period is longer than the first period, and the second frequency is lower than the first frequency.

13. A computer-readable storage medium, characterized in that, It includes computer-executable instructions stored thereon, which, when executed by a processor, implement the clock synchronization method as described in any one of claims 10-12.

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