SiC MOS device structure and preparation method thereof

Abstract

The invention discloses a SiC MOS device structure and a preparation method thereof. The SiC MOS device structure comprises an N + substrate layer, an N-epitaxial layer, an interlayer dielectric layer, a drain electrode, a source electrode, a symmetrical P-Well region, an N + doped region and a P + doped region, wherein the N + doped region and the P + doped region are arranged in the P-Well region; a gate oxide layer and a plane split polycrystalline silicon gate are formed above an epitaxial layer, a shallow trench structure is arranged in a JFET region between P-Well regions on two sides, the trench is filled with an interlayer dielectric layer and the gate oxide layer, and the split gate forms physical isolation above the JFET trench region. The depth of the JFET trench region is smaller than that of the P-Well region, and the JFET trench region is located in the middle of the P-Well region and is not in contact with the P-Well region. Through groove isolation and a split gate structure, gate-drain coupling capacitance (Cgd) is reduced, gate misconduction in a turn-off process is suppressed, electric field distribution of a gate sharp corner is optimized, and switching performance and reliability of a device are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to a device structure and a preparation method thereof, in particular to a SiC MOS device structure and a preparation method thereof, and belongs to the field of semiconductor device preparation. BACKGROUND

[0002] SiC MOS has significant advantages in the high-frequency field due to its high switching frequency, low switching loss, high temperature resistance and other characteristics, and can effectively solve the problems of low efficiency, serious heating and large volume of traditional silicon devices at high frequency. It is currently widely used in high-frequency power and power conversion, radio frequency and microwave power applications, new energy and power grid high-frequency equipment and other fields. However, during the off process of SiC MOS, due to its fast working frequency, the large dV / dt under the Cgd coupling effect causes the gate to pass through a large transient current, and further generates an induced voltage Vg under the action of the gate resistance Rg. If this induced voltage is large enough, even if the drive circuit has sent an off signal at this time, the actual voltage of the gate will still be lifted to above Vth, causing the gate of the MOS to misdirect. The gate misdirecting will increase the power consumption of the device, aggravate the degradation of the gate oxide layer, and increase the electromagnetic interference. It is a problem that needs to be avoided in the application of SiC MOS. It not only worsens the performance of the device, but also can directly cause damage to the device or system failure. Therefore, the suppression of misdirecting is a key design goal to improve the reliability of SiC MOS.

[0003] To avoid such misdirecting, the gate structure should be optimized in device design to reduce the gate-drain coupling capacitance Cgd as much as possible. The current commonly used methods include planar split gate, raised gate and recessed gate structure. Among them, the raised gate structure is designed in a raised form near the gate position of the JFET area, and the gate oxide layer in this area is locally thickened to reduce the coupling capacitance Cgd between the gate and the drain. However, due to the uniformity problem of the local oxide layer, it is easy to cause fluctuations in the quality of the gate oxide layer, affecting the reliability of the device. The recessed gate structure recesses the gate into the SiC substrate, extending the overlapping area of the gate and the drain in the longitudinal direction, reducing the equivalent Cgd by changing the geometric distribution of the gate-drain capacitance. However, the recess depth and doping concentration need to be accurately controlled, otherwise the Cgd will be raised due to the increase in the length of the gate. The current mainstream planar split gate structure splits the single gate into a main gate and an auxiliary gate. The main gate is close to the source and is responsible for the control of the channel conduction, and the auxiliary gate is close to the JFET area, reducing the Cgd by reducing the overlapping area of the gate and the drain. However, it is easy to cause the concentration of the electric field at the sharp corner of the gate near the JFET area, causing the breakdown voltage of the drain-source to decrease and the gate oxide reliability problem. SUMMARY

[0004] In order to solve the defects existing in the prior art, the structure of the present application is a planar split gate structure with a JFET area shallow trench, and a specific disclosure of a SiC MOS device structure is as follows:

[0005] N+ doped substrate layer (102);

[0006] N- doped epitaxial layer (103) above the substrate layer (102);

[0007] Drain electrode (101) below the substrate layer (102);

[0008] P-Well region (104) in the epitaxial layer (103) symmetrically located on the left and right sides;

[0009] N+ doped region (105) in the P-Well region (104);

[0010] P+ doped region (106) in the P-Well region (104);

[0011] JFET trench region (107) in the center of the epitaxial layer (103) between the two P-Well regions (104);

[0012] Gate oxide layer (108) above the epitaxial layer (103) and the sidewalls and bottom of the JFET trench region (107);

[0013] Left and right polysilicon gates (109) above the gate oxide layer (108);

[0014] Interlayer dielectric layer (110) covering the gate oxide layer (108) and polysilicon gate (109) and filling the JFET trench region (107);

[0015] Source electrode (111) above the epitaxial layer (103) and interlayer dielectric layer (110);

[0016] Wherein, the JFET trench region (107) is filled by the interlayer dielectric layer (110) and gate oxide layer (108), the gate oxide layer (108) and the polysilicon gate (109) form a planar MOS structure above the P-Well region (104) and a separate structure above the JFET trench region (107);

[0017] The depth of the JFET trench region (107) is less than the depth of the P-Well region (104), is located in the middle of the left and right P-Well regions (104), and does not contact the P-Well region (104).

[0018] The application also discloses a preparation method of the SiC MOS device structure, characterized by comprising the following steps:

[0019] S1: providing a SiC substrate wafer (102) and epitaxially growing a SiC epitaxial layer (103) on the substrate wafer;

[0020] S2: forming alignment marks on the surface of the epitaxial layer (103) by photolithography and etching;

[0021] S3: depositing a hard mask layer on the surface of the epitaxial layer (103), forming a P-Well implantation window by photolithography and etching, and then performing ion implantation to form a P-Well region (104);

[0022] S4: depositing a hard mask layer on the surface of the epitaxial layer (103), opening a window at the position where the N+ doped region is planned to be formed by photolithography and etching, and forming an N+ doped region implantation window;

[0023] S5: after removing the surface photoresist, using the remaining hard mask layer as a mask, performing high-temperature ion implantation of N-type impurities to form an N+ doped region (105) in the P-Well region (104);

[0024] S6: after removing all surface hard mask layers, performing P+ doped region photolithography and etching according to step S4 to form a P+ doped region implantation window, and then performing ion implantation to form a P+ doped region (106);

[0025] S7: defining a JFET implantation window, adjusting the doping concentration of the JFET region by ion implantation, and removing all hard mask layers;

[0026] S8: depositing a carbon film as a protective layer on the surface of the wafer; then performing high-temperature annealing to activate the doping impurities of each implanted region; and finally removing the carbon film;

[0027] S9: etching the JFET region in the center of the epitaxial layer (103) to form a JFET trench region (107), the trench depth does not exceed the depth of the P-Well region (104), and is located in the middle of the left and right P-Well regions (104), and does not contact the P-Well region (104);

[0028] S10: performing high-temperature oxidation treatment on the wafer to form a sacrificial oxide layer to remove surface damage, and removing the sacrificial oxide layer;

[0029] S11: generating a gate oxide layer (108) and a polysilicon gate layer on the surface of the epitaxial layer (103) and the JFET trench (107) to a certain thickness, and etching the polysilicon gate layer to form a split polysilicon gate (109);

[0030] S12: depositing a certain thickness of interlayer dielectric material USG+BPSG on the surface of the epitaxial layer (103), gate oxide layer (108) and polysilicon gate (109) to form an interlayer dielectric layer (110);

[0031] S13: etching the interlayer dielectric layer (110) to expose the upper surfaces of the N+ doped region (105), P+ doped region (106) and P-Well region (104), depositing an ohmic contact metal layer and performing rapid thermal treatment to form an ohmic contact layer;

[0032] S14: removing the unreacted metal and depositing a metal layer on the surface of the epitaxial layer (103) and interlayer dielectric layer (110) as a source electrode (111).

[0033] S15: depositing a PA passivation dielectric layer on the surface of the wafer, and opening the electrode lead-out area through a photolithography and etching process;

[0034] S16: coating a PI passivation layer on the surface of the wafer, and opening the PI layer to form a PAD electrode contact area through a photolithography process;

[0035] S17: performing a thinning process on the back surface of the wafer, depositing an ohmic contact layer at the bottom of the substrate layer (102), and depositing a metal layer as a drain electrode (101) after annealing.

[0036] The application also discloses a power electronic conversion device, characterized by comprising a SiC MOS device structure and the SiC MOS device structure prepared by the method.

[0037] Preferably, the device is at least one of a DC-DC converter, a DC-AC inverter or an AC-DC rectifier.

[0038] The application also discloses a method for inhibiting gate mis-conduction of a SiC MOS device, wherein the SiC MOS device is the SiC MOS device structure, and the method comprises the following steps: forming a shallow trench in a JFET region of the SiC MOS device, the shallow trench being filled with an interlayer dielectric and a gate oxide layer, and forming split polysilicon gates above P-Well regions on both sides of the shallow trench; wherein the depth of the shallow trench is less than the depth of the P-Well regions, and the shallow trench is located in the middle of the P-Well regions without contacting the P-Well regions, so as to reduce a gate-drain coupling capacitance Cgd and optimize the distribution of the gate edge electric field.

[0039] Advantages

[0040] (1) The parasitic parameters are more optimal, the trench isolation reduces the overlapping capacitance between gates, the gate-drain coupling capacitance (Cgd) is smaller than that of a traditional planar structure, the switching loss is lower, and the anti-mis-conduction ability is stronger under high frequency.

[0041] (2) Threshold voltage is more stable, trench isolation avoids electric field crosstalk between gates, control gate and channel coupling is more accurate, Vth dispersion is small, the probability of false triggering caused by noise interference is reduced.

[0042] (3) On-resistance and reliability balance, retain the low electric field concentration advantage of planar structure, while trench isolation optimizes current distribution, slightly lower than traditional planar split gate Ron, low loss and long life.

[0043] (4) Strong dv / dt interference ability, trench structure enhances the electric field shielding effect of the gate and the drain, reduces the coupling interference of rapid voltage change on the gate, further suppresses the false conduction. BRIEF DESCRIPTION OF DRAWINGS

[0044] Figure 1 A schematic diagram of a new SiC MOS device structure is shown.

[0045] Figure 2-1 A schematic diagram of an epitaxial process is shown.

[0046] Figure 2-2 A schematic diagram of P-Well area lithography and implantation process is shown.

[0047] Figure 2-3 A schematic diagram of N+ doped region lithography and process one is shown.

[0048] Figure 2-4 A schematic diagram of N+ doped region lithography and implantation process two is shown.

[0049] Figure 2-5 A schematic diagram of P+ doped region lithography and implantation process is shown.

[0050] Figure 2-6 A schematic diagram of JFET trench area etching process is shown.

[0051] Figure 2-7 A schematic diagram of gate oxide layer and polysilicon gate layer generation process is shown.

[0052] Figure 2-8 A schematic diagram of split polysilicon gate etching process is shown.

[0053] Figure 2-9 A schematic diagram of interlayer dielectric layer deposition process is shown.

[0054] Figure 2-10 A schematic diagram of contact hole etching and ohmic contact formation process is shown.

[0055] Figure 2-11 A schematic diagram of source electrode and drain electrode generation process is shown.

[0056] Figure 3 A flowchart of the preparation method is shown. Detailed Implementation

[0057] Example 1

[0058] This embodiment proposes a SiC MOS device structure, such as... Figure 1 As shown, the structure includes an N+ doped substrate (102), an N- doped epitaxial layer (103) above the substrate, a drain electrode (101) below the substrate, symmetrical P-Well regions (104) on both sides of the epitaxial layer, an N+ doped region (105) and a P+ doped region (106) within the P-Well regions, a JFET trench region (107) between the P-Well regions on both sides of the center of the epitaxial layer, a gate oxide layer (108) above the epitaxial layer and at the bottom and sidewalls of the JFET trench region, left and right polysilicon gates (109) above the gate oxide layer, an interlayer dielectric layer (110) covering the gate oxide layer and the polysilicon gates and filling the JFET trench region, and a source electrode (111) above the epitaxial layer and the interlayer dielectric layer. The JFET trench region is filled by the gate oxide layer and the interlayer dielectric layer. The gate oxide layer and the polysilicon gate form a normal planar MOS structure above the P-Well region and a separated structure above the JFET trench region. The depth of the JFET trench region in the epitaxial layer is less than the depth of the P-Well region, it is located in the middle of the left and right P-Well regions and is not in close contact with the P-Well region.

[0059] In this embodiment, SiC is used as the substrate. Symmetrical gates are distributed on both sides of the JFET trench region, and a split gate structure is achieved using trenches that extend longitudinally into the epitaxial layer. This reduces the coupling area between the gate and the channel. The thickness of the interlayer dielectric layer above the polysilicon gate is much greater than the thickness of the gate oxide layer below it, reducing the impact of Cgd. The advantages of the above technical solution are that it reduces Cgd and suppresses mis-conduction using the split gate structure, and solves the problem of electric field concentration at the sharp corners of the traditional planar split gate through the JFET trench.

[0060] Example 2

[0061] The following is in conjunction with the appendix Figure 3 and appendix Figure 2-1 To be continued Figure 2-11 The fabrication method of the SiC MOS device structure disclosed in Example 1 is illustrated below:

[0062] Step S1: Select a SiC substrate wafer 102 with appropriate size, thickness and resistivity according to the product specifications, and epitaxially grow a SiC epitaxial layer 103 with a certain thickness and doping concentration on the substrate wafer; preferably: the epitaxial layer thickness is 5-50 μm and the doping concentration is 1e15-1e17 cm⁻³.

[0063] Step S2: Forming a pattern on the wafer surface by lithography and etching a certain thickness of SiC layer, which can provide alignment marks for subsequent lithography steps.

[0064] Step S3: Depositing a hard mask layer 201 on the surface of the SiC wafer epitaxial layer 103, which can be silicon dioxide, silicon nitride, polysilicon or a combination thereof, etc. Forming a P-Well implantation window on the wafer surface by lithography and etching hard mask layer process steps, after stripping, high-temperature ion implantation of B or Al is performed to form a P-Well region 104 in the epitaxial layer, as shown in Figure 2-2 .

[0065] Preferably, the ion implantation temperature is 500-1000°C, and the implantation dose is 1e13-1e15 cm⁻²;

[0066] Step S4: According to the design requirements of the channel length, continue to deposit a certain thickness of hard mask layer 301 on the wafer surface after the previous step, and use lithography development to retain the photoresist above the N+ doped region, as shown in Figure 2-3 . After etching a certain thickness of hard mask layer by self-aligned process, the hard mask layer under the photoresist 302 is retained, as shown in Figure 2-4 .

[0067] Step S5: After removing the photoresist 302 on the wafer surface, high-temperature ion implantation of N or P is performed, and under the shielding effect of the hard mask layers 201 and 301, N+ doped region 105 is selectively implanted in the P-Well region 104.

[0068] Step S6: After removing all hard mask layers on the wafer surface, re-depositing a hard mask layer and performing P+ lithography etching to form a P+ implantation window according to step S4, after stripping, high-temperature ion implantation of B or Al is performed to selectively implant P+ doped region 106 in the P-Well region 104, as shown in Figure 2-5 .

[0069] Step S7: Defining the JFET implantation window, after stripping, ion implantation of N or P at room temperature or high temperature is performed to adjust the doping concentration of the JFET region 501, and then all hard mask layers on the wafer surface are removed.

[0070] Step S8: Depositing a carbon film on the wafer surface and performing high-temperature ion activation (preferably: high-temperature activation temperature is 1500-1700°C) of the dopant in each implantation region, and removing the carbon film on the wafer surface.

[0071] Step S9: By etching process, etching a trench structure 107 in the center of the epitaxial layer, the depth of the JFET region 501 does not exceed the P-Well region, and the width is kept a certain distance (for example, 0.1-1.0 μm, to avoid electrical short circuit) from the P-Well region, as shown in Figure 2-6 .

[0072] Preferably, the center JFET region of the epitaxial layer is etched to form a trench with a depth of 0.5-2.0 μm and a width of 1-5 μm, the trench depth is less than the P-Well region junction depth, and is located in the middle of the left and right P-Well regions, and is spaced apart from the P-Well region by 0.1-1.0 μm.

[0073] Step S10: high-temperature oxidation treatment is performed on the wafer, the surface layer SiC with a certain damage on the wafer surface is oxidized and consumed, and the sacrificial oxide layer is removed through an etching process to expose a SiC surface layer with fewer defects.

[0074] Step S11: a gate oxide layer 108 and a heavily doped polysilicon layer 701 are generated on the wafer surface by oxidation, as shown in FIG. 7A. Figure 2-7 The polysilicon layer 701 is photolithographically etched to form a split polysilicon gate 109 symmetrically left and right, as shown in FIG. 7B. Figure 2-8

[0075] Step S12: an interlayer dielectric layer material, generally USG+BPSG, is deposited on the wafer surface to form an interlayer dielectric layer 110, and the thickness of the interlayer dielectric layer 110 is much greater than the thickness of the gate oxide layer 108, as shown in FIG. 7C. Figure 2-9 Preferably, the interlayer dielectric material USG+BPSG is deposited above the polysilicon gate and the gate oxide layer to form the interlayer dielectric layer 110, and the thickness of the interlayer dielectric layer 110 is 500-1000 nm.

[0076] Step S13: the interlayer dielectric layer ILD 110 is etched using photoresist as a mask to expose the N+ doped region, the P+ doped region and the P-Well region to a sufficient length of contact hole, and after the photoresist is removed, an ohmic contact layer metal (generally a Ni metal layer) is deposited and rapid thermal treatment is performed, and the ohmic contact metal forms an ohmic contact layer with SiC in the contact hole area.

[0077] Preferably, the rapid thermal treatment is performed at a temperature of 900-1100°C for 1-5 minutes.

[0078] Step S14: after the metal that reacts in other regions is removed, a layer of metal is deposited as a source electrode 111, as shown in FIG. 7E. Figure 2-10

[0079] Step S15: a PA passivation layer, generally SiO2 or SiN, is deposited on the wafer surface, the passivation layer is opened by photolithography and etching, and then the photoresist is removed.

[0080] Step S16: a PI passivation layer is applied to the wafer surface, the PI layer is opened by photolithography to form a PAD electrode contact area, and then solidification treatment is performed.

[0081] ​​Step S17: thinning the back surface of the wafer to reduce the on-resistance of the device, and depositing an ohmic contact layer (typically a Ni metal layer) on the back surface of the wafer, and then depositing a back surface drain electrode metal composite layer (typically Ti / Ni / Ag) after laser annealing, to form a drain electrode 101, as shown in Figure 2-11

[0082] The present application provides a novel SiC MOS device structure and a preparation method, which changes the traditional planar split gate structure design, and realizes the physical isolation of the split gate by forming a shallow trench structure in the JFET region of the SiC MOS. The planar gate with gate trench separation can effectively modulate the gate corner electric field distribution, protect the gate oxide, so that the gate oxide layer at the edge of the split gate is not easy to be broken down, and the on-state performance of the traditional planar split gate device is improved. And further improve the characteristics of reducing Cgd of the planar split gate, which can effectively avoid the gate mis-conduction of the SiC MOS when it is turned off.

[0083] Embodiment 3

[0084] This embodiment discloses a power electronic conversion device, which comprises the SiC MOS device structure disclosed in embodiment 1 and the preparation method for preparing the SiC MOS device structure disclosed in embodiment 2; and the device is at least one of a DC-DC converter, a DC-AC inverter or an AC-DC rectifier.

[0085] Embodiment 4

[0086] This embodiment discloses a method for inhibiting the gate mis-conduction of a SiC MOS device, wherein the SiC MOS device is the SiC MOS device structure disclosed in embodiment 1, and the method comprises: forming a shallow trench in the JFET region of the SiC MOS device, the shallow trench being filled with an interlayer dielectric layer and a gate oxide layer, and forming split polysilicon gates above the P-Well regions on both sides of the shallow trench; wherein the depth of the shallow trench is less than the depth of the P-Well regions, and the shallow trench is located in the middle of the P-Well regions without contacting the P-Well regions, so as to reduce the gate-drain coupling capacitance Cgd and optimize the gate edge electric field distribution.

[0087] The basic principles, main features and advantages of the present application are shown and described above. It should be understood by those skilled in the art that the present application is not limited by the above embodiments, and the above embodiments and descriptions in the specification are only the principles of the present application. Without departing from the spirit and scope of the present application, various changes and improvements can be made to the present application, and these changes and improvements all fall within the scope of the claimed present application. The scope of protection of the present application is defined by the appended claims and their equivalents.​

Claims

1. A SiC MOS device structure, characterized by, Comprise: N+ doped substrate layer (102); N- doped epitaxial layer (103) above the substrate layer (102); Drain electrode (101) below the substrate layer (102); P-Well region (104) symmetrically located in the left and right of the epitaxial layer (103); N+ doped region (105) in the P-Well region (104); P+ doped region (106) in the P-Well region (104); JFET trench region (107) in the center of the epitaxial layer (103) between the two P-Well regions (104); Gate oxide layer (108) above the epitaxial layer (103) and the sidewall and bottom of the JFET trench region (107); Left and right polysilicon gates (109) above the gate oxide layer (108); Interlayer dielectric layer (110) covering the gate oxide layer (108) and polysilicon gate (109) and filling the JFET trench region (107); Source electrode (111) above the epitaxial layer (103) and interlayer dielectric layer (110); Wherein, the JFET trench region (107) is filled with the interlayer dielectric layer (110) and the gate oxide layer (108), the gate oxide layer (108) and the polysilicon gate (109) form a planar MOS structure above the P-Well region (104) and a separate structure above the JFET trench region (107); The depth of the JFET trench region (107) is less than the depth of the P-Well region (104), located in the middle of the left and right P-Well regions (104), and does not contact the P-Well region (104).

2. The SiC MOS device structure of claim 1, wherein, The material of the interlayer dielectric layer (110) is USG+BPSG.

3. The SiC MOS device structure of claim 1, wherein, The polysilicon gate (109) is symmetrically distributed and located above the gate oxide layer (108); the thickness of the interlayer dielectric layer (110) above the polysilicon gate (109) is greater than the thickness of the gate oxide layer (108).

4. The SiC MOS device structure of claim 1, wherein, The spacing between the JFET trench region (107) and the P-Well region (104) is 0.1-1.0μm; the depth of the JFET trench region (107) is 0.5-2.0μm, and the width is 1-5μm.

5. A method of fabricating a SiC MOS device structure, characterized by, Comprise the following steps: S1: provide a SiC substrate wafer (102) and epitaxially grow a SiC epitaxial layer (103) on the substrate wafer; S2: form alignment marks on the surface of the epitaxial layer (103) by lithography and etching; S3: deposit a hard mask layer on the surface of the epitaxial layer (103), form P-Well implantation windows by lithography and etching, and then perform ion implantation to form P-Well regions (104); S4: deposit a hard mask layer on the surface of the epitaxial layer (103), open windows at the planned N+ doped region by lithography development and etching process, and form N+ doped region implantation windows; S5: After removing the surface photoresist, high temperature ion implantation of N-type impurities is performed with the remaining hard mask layer as a mask to form an N+ doped region (105) in the P-Well region (104); S6: After removing all the surface hard mask layers, P+ doped region lithography and etching are performed according to the step S4 to form a P+ doped region implantation window, and then ion implantation is performed to form a P+ doped region (106); S7: A JFET implantation window is defined, ion implantation is performed to adjust the doping concentration of the JFET region, and all the hard mask layers are removed; S8: A carbon film is deposited on the wafer surface as a protective layer; then high temperature annealing is performed to activate the doping impurities of each implantation region; and finally the carbon film is removed; S9: The JFET region in the center of the epitaxial layer (103) is etched to form a JFET trench region (107), the depth of the trench does not exceed the depth of the P-Well region (104), and is located in the middle of the left and right P-Well regions (104) and does not contact the P-Well region (104); S10: High temperature oxidation treatment is performed on the wafer to form a sacrificial oxide layer to remove surface damage, and the sacrificial oxide layer is removed; S11: A gate oxide layer (108) and a polysilicon gate layer of a certain thickness are formed on the surface of the epitaxial layer (103) and the JFET trench (107), and the polysilicon gate layer is etched to form a split polysilicon gate (109); S12: An interlayer dielectric material USG+BPSG of a certain thickness is deposited on the surface of the epitaxial layer (103), the gate oxide layer (108), and the polysilicon gate (109) to form an interlayer dielectric layer (110); S13: The interlayer dielectric layer (110) is etched to expose the upper surfaces of the N+ doped region (105), the P+ doped region (106), and the P-Well region (104), an ohmic contact metal is deposited, and rapid thermal treatment is performed to form an ohmic contact layer; S14: The unreacted metal is removed, and a layer of metal is deposited on the surface of the epitaxial layer (103) and the interlayer dielectric layer (110) as a source electrode (111); S15: A PA passivation dielectric layer is deposited on the wafer surface, and the electrode lead-out area is opened through lithography and etching processes; S16: A PI passivation layer is applied on the wafer surface, and the PAD electrode contact area is formed by opening the PI layer through a lithography process; S17: The wafer back is thinned, an ohmic contact layer is deposited at the bottom of the substrate layer (102), and a layer of metal is deposited as a drain electrode (101) after annealing.

6. The production method according to claim 5, wherein The thickness of the epitaxial layer (103) in step S1 is 5-50 μm, and the doping concentration is 1 x 1018- 1 x 1020cm-3. 5 1 x 1018 7 cm-3 -³ The ion implantation in steps S3, S5, S6 includes boron or aluminum implantation for P-Well region (104), P+ doped region (106), and nitrogen or phosphorus implantation for N+ doped region (105), and the implantation temperature is 500-1000°C; and the high temperature activation in step S8 is at a temperature of 1500-1700°C.

7. The preparation method according to claim 5, characterized in that, The depth of the JFET trench region (107) in step S9 is 0.5-2.0 μm, the width is 1-5 μm, and the spacing from the P-Well region (104) is 0.1-1.0 μm; the material of the gate oxide layer (108) in step S11 is silicon dioxide, and the thickness is 30-200 nm; the material of the interlayer dielectric layer (110) in step S12 is USG+BPSG, and the thickness is 500-1000 nm.

8. A power electronic conversion device, characterized by, The SiC MOS device structure according to claim 1 and the SiC MOS device structure prepared by the method according to claim 5.

9. The power electronic conversion device of claim 8, wherein, The device is at least one of a DC-DC converter, a DC-AC inverter, or an AC-DC rectifier.

10. A method of suppressing gate mis-turn-on of a SiC MOS device, the SiC MOS device being the SiC MOS device structure of claim 1, characterized in that, Comprising: Forming a shallow trench in a JFET region of the SiC MOS device; Filling the shallow trench with an interlayer dielectric layer and a gate oxide layer; forming split polysilicon gates over the P-Well regions on both sides of the shallow trench; wherein the depth of the shallow trench is less than the depth of the P-Well regions and is located in the middle of the P-Well regions without contacting them.

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