A semiconductor device and a manufacturing method thereof

Abstract

This application provides a semiconductor device and a method for manufacturing the same. The manufacturing method includes: providing a semiconductor structure including a substrate having a PMOS region and an NMOS region, with a gate and a sidewall material layer including a first material layer and a second material layer disposed on the substrate; forming a first mask layer covering the surface of the semiconductor structure; forming an anti-reflective layer and a second mask layer and an opening on the first mask layer, the opening exposing a portion of the first mask layer; removing the exposed first mask layer; removing the second mask layer and a portion of the anti-reflective layer in the NMOS region; forming trenches on both sides of the gate in the PMOS region, and removing the exposed portion of the first mask layer and a portion of the second material layer in the NMOS region; forming a stress semiconductor layer in the trenches to fill the trenches; etching to remove the remaining first mask layer and the sidewall material layer on the top surface of the gate, and forming sidewall layers on both sides of the gate. This application eliminates the need to separately remove the hard mask layer in the NMOS region, saving production costs.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] In the field of semiconductor technology, with the increasing integration of CMOS technology and the shrinking of key dimensions, the stress-stretching method used in traditional CMOS processes can no longer meet the requirements of devices for PMOS drive current. To address this, related technologies use silicon-germanium epitaxy to increase the compressive stress of PMOS in order to improve the overall response speed of the device.

[0003] In silicon-germanium epitaxy, silicon-germanium trenches are first formed, and then silicon-germanium is epitaxially grown to fill the silicon-germanium trenches to form a silicon-germanium layer in the PMOS region. When forming the silicon-germanium trenches, a hard mask layer covers the entire wafer surface. After the silicon-germanium layer in the PMOS region is formed, a separate process is needed to remove the hard mask layer in the NMOS region. However, the process of removing the hard mask layer in the NMOS region does not form a substantial pattern or structure, but it adds corresponding process steps, thereby increasing the corresponding economic and time costs. Summary of the Invention

[0004] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This summary section is not intended to limit the key and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0005] To address the existing problems, this application provides a method for manufacturing a semiconductor device, the method comprising:

[0006] A semiconductor structure is provided, the semiconductor structure including a substrate, the substrate including at least one PMOS region and at least one NMOS region, a gate and a sidewall material layer covering the gate are disposed on the substrate of the PMOS region and the NMOS region, the sidewall material layer including a first material layer and a second material layer stacked from bottom to top;

[0007] A first mask layer is formed to conformally cover the surface of the semiconductor structure;

[0008] An anti-reflection layer and a second mask layer are sequentially formed on the first mask layer, and an opening penetrating the second mask layer and the anti-reflection layer is formed, the opening also exposing a portion of the first mask layer located in the PMOS region;

[0009] Remove the first mask layer exposed in the opening;

[0010] At least the second mask layer and a portion of the anti-reflective layer on the gate of the NMOS region are removed to expose at least a portion of the first mask layer on the top surface of the gate of the NMOS region;

[0011] Trenches are formed in the substrate on both sides of the gate of the PMOS region by etching process, and a portion of the first mask layer and a portion of the second material layer located in the NMOS region are removed, so that a portion of the first material layer on the top surface of the gate of the NMOS region is exposed.

[0012] A stress semiconductor layer is formed in the trench to fill the trench, and the top surface of the stress semiconductor layer protrudes from the surface of the substrate;

[0013] The remaining first mask layer is etched away, and at least the sidewall material layer on the top surface of the gate is etched away to form sidewall layers on both sides of the gate in the PMOS region and on both sides of the gate in the NMOS region.

[0014] In one embodiment, trenches are formed in the substrate on both sides of the gate of the PMOS region by an etching process, including:

[0015] An initial trench is formed in the substrate on both sides of the gate of the PMOS region by a first etching process, while removing a portion of the first mask layer and a portion of the second material layer exposed in the NMOS region, so that a portion of the first material layer on the gate of the NMOS region is exposed.

[0016] Remove the remaining anti-reflective layer and perform a second etching process on the initial trench to expand it into the final trench.

[0017] In one embodiment, a sacrificial layer is further formed between the first mask layer and the substrate, and the initial trench is formed in the substrate on both sides of the gate of the PMOS region by the first etching process, including:

[0018] Etching removes a portion of the sacrificial layer on the substrate to expose portions of the substrate on either side of the gate of the PMOS region;

[0019] The substrate is etched to form the initial trench.

[0020] In one embodiment, the second mask layer includes a photoresist layer, the first mask layer and the first material layer are made of silicon nitride, and the sacrificial layer and the second material layer are made of silicon oxide.

[0021] In one embodiment, performing a second etching process on the initial trench to expand it into the final trench includes:

[0022] The substrate exposed in the initial trench is etched using a wet etching process to form the Σ-shaped trench.

[0023] In one embodiment, the first mask layer and the first material layer are made of silicon nitride, the second material layer is made of silicon oxide, and the substrate is made of silicon.

[0024] The process gases for the first etching include CF4 and Ar.

[0025] In one embodiment, the first material layer and the first mask layer have the same material, and the first material layer on the top surface of the gate is removed while the remaining first mask layer is etched away.

[0026] In one embodiment, after forming the stress semiconductor layer before etching away the remaining first mask layer, the method further includes:

[0027] Oxidize the exposed surface of the stress semiconductor layer to form an oxide layer.

[0028] After etching away the remaining first mask layer, the process further includes etching away the oxide layer.

[0029] In one embodiment, the stress semiconductor layer includes a silicon-germanium layer, which is formed in the trench using a selective epitaxial growth process.

[0030] This application also provides a semiconductor device, which is manufactured using the above-described manufacturing method.

[0031] The semiconductor device and manufacturing method of the present application embodiment include a PMOS region and an NMOS region on a substrate of a semiconductor structure. A first mask layer is formed on the surface of the semiconductor structure. An anti-reflection layer and a second mask layer are formed on the first mask layer, and an opening penetrating the second mask layer and the anti-reflection layer is formed. The opening exposes a portion of the first mask layer of the PMOS region. Then, the first mask layer exposed by the opening is removed. After removing the first mask layer exposed by the opening, the second hard mask layer and a portion of the anti-reflection layer of the NMOS region are removed to expose a portion of the first mask layer on the top surface of the gate of the NMOS region. Then, the first mask layer on the top surface of the gate of the NMOS region is removed while etching trenches in the PMOS region. Then, conventional processes are used to form a stress semiconductor layer and the gate sidewalls of the PMOS region and the NMOS region. Thus, it is not necessary to remove the hard mask layer of the NMOS region separately during the formation of the stress semiconductor layer of the PMOS region, thereby saving production costs and improving production efficiency. Attached Figure Description

[0032] The following drawings, which are incorporated herein by reference and are used to understand this application, illustrate embodiments of the invention and their descriptions to explain the principles of the invention.

[0033] In the attached image:

[0034] Figures 1A-1F A partial cross-sectional schematic diagram of a semiconductor device obtained when a method for manufacturing silicon-germanium epitaxy is performed sequentially using related techniques is shown.

[0035] Figure 2 A flowchart illustrating a method for manufacturing a semiconductor device according to a specific embodiment of this application is shown;

[0036] Figures 3A-3K This diagram shows a cross-sectional view of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to a specific embodiment of this application. Detailed Implementation

[0037] The present application will now be described more fully with reference to the accompanying drawings, in which embodiments of the present application are illustrated. However, the present application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present application to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0038] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0039] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0040] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0041] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms as defined in commonly used dictionaries shall be interpreted as having a meaning consistent with their meaning in the relevant field and / or the context of this specification, and not as in an ideal or overly formal sense, unless expressly defined herein.

[0042] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0043] In the field of semiconductor technology, with the increasing integration of CMOS technology and the shrinking of key dimensions, the stress-stretching method used in traditional CMOS processes can no longer meet the requirements of devices for PMOS drive current. To address this, related technologies use silicon-germanium epitaxy to increase the compressive stress of PMOS in order to improve the overall response speed of the device.

[0044] In silicon-germanium epitaxy, the main technologies include two parts: silicon-germanium trench etching and silicon-germanium growth for PMOS and removal of the hard mask layer in the NMOS region, in order to form a silicon-germanium layer in the PMOS region. Specifically, firstly, as... Figure 1A As shown, a PMOS region and an NMOS region are formed in the substrate 100. A gate 101 and a sidewall material layer covering the gate 101 are disposed on the substrate of both the PMOS region and the NMOS region. A silicon oxide layer 102, a silicon nitride layer 103, an anti-reflection layer 104, and a patterned photoresist layer 105 are sequentially formed on the substrate 100 to define the PMOS region.

[0045] Next, as Figure 1B As shown, the anti-reflection layer 104, silicon nitride layer 103, oxide layer 102 and part of the substrate 100 in the PMOS region are removed by etching process to form an initial trench in the PMOS region, and the remaining anti-reflection layer is removed.

[0046] Next, as Figure 1C As shown, the substrate 100 exposed in the initial trench is etched by a wet etching process to form a Σ-shaped trench, thereby expanding the initial trench into the final trench.

[0047] Next, as Figure 1D As shown, a silicon-germanium layer 106 is formed in the trench using a selective epitaxial growth process to fill the trench.

[0048] This completes the silicon-germanium trench etching and silicon-germanium growth process for the PMOS region in the relevant technology. Next, the hard mask layer for the NMOS region is removed, i.e., the silicon nitride layer for the NMOS region is removed, as shown below. Figure 1E As shown, an anti-reflection layer 104 and a patterned photoresist layer 105 are formed again on the substrate 100. Notably, the patterned photoresist layer defines the NMOS region at this point, and the anti-reflection layer 104 of the NMOS region is etched using the patterned photoresist layer as a mask; then as... Figure 1F As shown, the silicon nitride layer 103 in the NMOS region is removed by etching, and the anti-reflection layer 104 and photoresist layer 105 are also removed, thereby removing the hard mask layer in the NMOS region.

[0049] Then, subsequent processes are performed, namely, forming an oxide layer to protect the silicon-germanium layer, and finally removing part of the sidewall material layer by wet etching, ultimately forming gate sidewalls on both sides of the gate.

[0050] In related technologies, when forming silicon-germanium trenches, a hard mask layer, i.e., a silicon nitride layer, covers the entire wafer surface, while the silicon-germanium layer is formed in the PMOS region. Therefore, it is only necessary to etch the hard mask layer in the PMOS region to form the silicon-germanium trench. After forming the silicon-germanium layer in the PMOS region, a separate process is required to remove the hard mask layer in the NMOS region. However, the process of removing the hard mask layer in the NMOS region does not form a substantial pattern or structure, but it requires multiple photolithography and wet etching steps, increasing the corresponding process steps and thus increasing the corresponding economic and time costs.

[0051] Therefore, in view of the aforementioned technical problems, this application proposes a method for manufacturing a semiconductor device, such as... Figure 2 As shown, it mainly includes the following steps:

[0052] Step S110: Provide a semiconductor structure, the semiconductor structure includes a substrate, the substrate includes at least one PMOS region and at least one NMOS region, a gate and a sidewall material layer covering the gate are disposed on the substrate of both the PMOS region and the NMOS region, the sidewall material layer includes a first material layer and a second material layer stacked from bottom to top;

[0053] Step S120: A first mask layer is formed to conformally cover the surface of the semiconductor structure;

[0054] Step S130: An anti-reflection layer and a second mask layer are sequentially formed on the first mask layer, and an opening penetrating the second mask layer and the anti-reflection layer is formed. The opening also exposes a portion of the first mask layer located in the PMOS region.

[0055] Step S140: Remove the first mask layer exposed in the opening;

[0056] Step S150: Remove at least the second mask layer and a portion of the anti-reflection layer on the gate of the NMOS region to expose at least a portion of the first mask layer on the top surface of the gate of the NMOS region.

[0057] Step S160: Trenches are formed in the substrate on both sides of the gate of the PMOS region by etching process, and the exposed part of the first mask layer and part of the second material layer located in the NMOS region are removed, so that part of the first material layer on the top surface of the gate of the NMOS region is exposed.

[0058] Step S170: A stress semiconductor layer is formed in the trench to fill the trench, and the top surface of the stress semiconductor layer protrudes from the substrate surface.

[0059] Step S180: Etch away the remaining first mask layer and at least etch away the sidewall material layer on the top surface of the gate to form sidewall layers on both sides of the gate in the PMOS region and on both sides of the gate in the NMOS region.

[0060] The semiconductor device and manufacturing method of the present application embodiment include a PMOS region and an NMOS region on a substrate of a semiconductor structure. A first mask layer is formed on the surface of the semiconductor structure. An anti-reflection layer and a second mask layer, as well as an opening penetrating the second mask layer and the anti-reflection layer, are sequentially formed on the first mask layer. The opening exposes a portion of the first mask layer of the PMOS region. Then, the first mask layer exposed by the opening is removed. After removing the first mask layer exposed by the opening, a second hard mask layer and a portion of the anti-reflection layer of the NMOS region are removed to expose a portion of the first mask layer on the top surface of the gate of the NMOS region. Then, while etching trenches in the PMOS region, the first mask layer on the top surface of the gate of the NMOS region is removed. Then, conventional processes are used to form a stress semiconductor layer and the gate sidewalls of the PMOS region and the NMOS region. Thus, it is not necessary to remove the hard mask layer of the NMOS region separately during the formation of the stress semiconductor layer of the PMOS region, thereby saving production costs and improving production efficiency.

[0061] Below, for reference Figure 2 , Figures 3A to 3K The method for manufacturing the semiconductor device of this application is described in detail, wherein, Figure 2 A flowchart illustrating a method for manufacturing a semiconductor device according to a specific embodiment of this application is shown; Figures 3A-3K The diagram shows a cross-sectional view of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to a specific embodiment of this application.

[0062] For example, the semiconductor structure processing method of this application includes the following steps:

[0063] First, such as Figure 2 As shown, step S110 is performed to provide a semiconductor structure, such as... Figure 3A As shown, the semiconductor structure includes a substrate 200, which includes at least one PMOS region and at least one NMOS region. A gate 201 and a sidewall material layer covering the gate 201 are disposed on both the PMOS and NMOS regions of the substrate 200. The sidewall material layer includes a first material layer 203 and a second material layer 204 stacked from bottom to top. An ion implantation region 215 is also formed in the PMOS region. Exemplarily, the first material layer 203 is made of silicon nitride, and the second material layer 204 is made of silicon oxide.

[0064] The substrate 200 can be any suitable semiconductor substrate, such as a silicon substrate, or at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III / V compound semiconductors, including multilayer structures composed of these semiconductor materials, or silicon-on-insulator (SOI), strained silicon-on-insulator (SSOI), strained silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), or it can be a double-side polished wafer (DSP). Preferably, the substrate 200 is made of single-crystal silicon. In the substrate, an N-type well for a PMOS device and a P-type well for an NMOS device are formed respectively through an ion implantation process, thereby defining the PMOS region and the NMOS region.

[0065] A shallow trench isolation structure is also formed in the substrate, which can be used to isolate different active regions, such as NMOS region and PMOS region.

[0066] In one example, the formation process of gate 201 includes: after completing shallow trench isolation and well implantation, a sacrificial layer 209 and a gate electrode layer are sequentially deposited on the entire substrate surface; subsequently, the gate pattern is defined by photolithography, and the gate electrode layer is patterned by dry etching using photoresist as a mask to form gate 201, while the portion of the sacrificial layer 209 located below gate 201 can subsequently be used as a gate dielectric layer. After gate 201 is formed, a sidewall material layer is conformally deposited on its sidewalls and top, the sidewall material layer including a first material layer 203 and a second material layer 204 stacked from bottom to top. Exemplarily, the first material layer 203 is made of silicon nitride, and the second material layer 204 is made of silicon oxide. Optionally, the material of the sacrificial layer 209 can be the same as that of the second material layer 204, for example, both can include silicon oxide.

[0067] In the PMOS region, ion implantation regions 215 are also formed in the substrate on both sides of the gate 201. These regions are typically formed by ion implantation after gate patterning and before sidewall material layer deposition, and are used to adjust the doping profile of the source and drain extension regions.

[0068] Then, continue as follows Figure 2As shown, in step S120, referring to 3A, a first mask layer 205 is formed. The first mask layer 205 conformally covers the surface of the semiconductor structure so that the sidewall material layer of the gate 201 is also covered by the first mask layer 205. The process for fabricating the first mask layer 205 can be any of physical vapor deposition, chemical vapor deposition, and atomic layer deposition.

[0069] Next, step S130 is performed, in which an anti-reflection layer and a second mask layer are sequentially formed on the first mask layer, and an opening penetrating the second mask layer and the anti-reflection layer is formed, the opening also exposing a portion of the first mask layer located in the PMOS region.

[0070] For example, continue to refer to Figure 3A An antireflective layer 206 is formed on the first mask layer 205 by spin coating or chemical vapor deposition. Next, a second mask material layer (not shown) is formed on the antireflective layer 206 by spin coating or chemical vapor deposition. Then, the second mask material layer is patterned to form a second mask layer 207. The second mask layer 207 defines the position and size of the corresponding PMOS region on the antireflective layer 206. Then, as... Figure 3B As shown, the anti-reflective layer is etched using the second mask layer 207 as a mask to expose a portion of the first mask layer 205 containing the PMOS, thereby forming an opening 208 that penetrates the second mask layer 207 and the anti-reflective layer 206. Exemplarily, the first mask layer is made of silicon nitride, and the second mask layer includes a photoresist layer.

[0071] Next, step S140 is performed to remove the first mask layer exposed in the opening, exemplarily as follows: Figure 3C As shown, an etching process, such as dry etching, is used to remove the first mask layer 205 exposed in the opening 208. This involves removing the first mask layer 205 on the surface of the substrate 200 in the opening 208 region and a portion of the first mask layer 205 on the sidewall material layer of the gate 201. It is worth noting that when removing the first mask layer 205 exposed in the opening 208, the second mask layer 207 is also partially removed.

[0072] Next, step S150 is performed to remove at least the second mask layer and a portion of the anti-reflective layer on the gate of the NMOS region, so as to expose at least a portion of the first mask layer on the top surface of the gate of the NMOS region.

[0073] For example, such as Figure 3D As shown, dry etching is used to remove the second mask layer 207 and part of the anti-reflection layer 206 until the anti-reflection layer 206 is etched to a portion of the first mask layer 205 on the top surface of the gate 201 of the NMOS region, at which point the etching stops.

[0074] Next, step S160 is performed, in which trenches are formed in the substrate on both sides of the gate of the PMOS region by etching process, and the exposed part of the first mask layer and part of the second material layer in the NMOS region are removed, so that part of the first material layer on the top surface of the gate of the NMOS region is exposed.

[0075] For example, such as Figure 3D As shown, a sacrificial layer 209 is formed between the first mask layer 205 and the substrate 200. Trenches are formed in the substrate 200 on both sides of the gate 201 in the PMOS region by an etching process, including the following steps:

[0076] First, an initial trench is formed in the substrate on both sides of the gate of the PMOS region through a first etching process, while removing part of the first mask layer and part of the second material layer exposed in the NMOS region, so that part of the first material layer on the gate of the NMOS region is exposed.

[0077] For example, such as Figure 3E As shown, firstly, a portion of the sacrificial layer 209 on the substrate 200 is etched away, that is, the opening region is etched away, exposing the sacrificial layer 209 of the PMOS region, so as to expose the portion of the substrate 200 on both sides of the gate 201 of the PMOS region. During the etching process, the ion implantation region 215 of the PMOS region is also partially etched. Then, the exposed portion of the substrate 200 is etched further, and the opening of the PMOS region extends towards the substrate 200, as shown. Figure 3F As shown, an initial trench 210 is formed in the PMOS region. During the process of etching away a portion of the sacrificial layer on the substrate 200 to form the initial trench 210 through a first etching process, the first mask layer 205 and the second material layer 204 on the top surface of the gate 201 of the NMOS region are also etched, thereby removing the exposed portion of the first mask layer 205 and the second material layer 204 of the NMOS region, so that a portion of the first material layer 203 on the gate of the NMOS region is exposed. It is worth mentioning that during the etching process to form the initial trench 210, the anti-reflective layer 206 is also thinned due to etching.

[0078] The first etching process may include a dry etching process. The process gas for the first etching process includes CF4 and Ar or other suitable process gases. When the first etching process begins to form the initial trench 210, the outermost layer of the gate 201 in the PMOS region is essentially the second material layer 204, while the outermost layer of the top surface of the gate 201 in the NMOS region is the first mask layer 205. The etching rate of the first mask layer 205 is faster than the etching rate of the second material layer 204. Therefore, although the starting materials at the top of the gates in the two regions are different, the etching process consumes the first mask layer 205 at the top of the NMOS region more quickly. When the etching progresses to form the initial trench of the required depth in the PMOS region, the first mask layer 205 on the top surface of the gate in the NMOS region has been completely removed, and the portion of the second material layer 204 below it is also etched. Thus, after etching using the first etching process, the difference between the sidewall material layer on the gate top surface of the PMOS region and the sidewall material layer on the gate top surface of the NMOS region is small, so that the first material layer 203 on the gate top surface of both the PMOS region and the NMOS region is exposed.

[0079] Next, the remaining anti-reflective layer is removed, and a second etching process is performed on the initial trench to expand it into the final trench.

[0080] For example, such as Figures 3F to 3G As shown, the remaining anti-reflective layer 206 is removed using wet etching or dry etching processes to form a layer as shown. Figure 3G The structure shown, then, as Figure 3H As shown, the substrate 200 exposed in the initial trench 210 is etched by a wet etching process to form a Σ-shaped trench 211, thereby expanding the initial trench 210 into the final trench 211.

[0081] Next, step S170 is performed to form a stress semiconductor layer in the trench to fill the trench, and the top surface of the stress semiconductor layer protrudes from the substrate surface.

[0082] For example, such as Figure 3I As shown, the stress semiconductor layer 212 includes a silicon-germanium layer or other suitable material layer, which is formed in the trench using a selective epitaxial growth process. The top surface of the silicon-germanium layer protrudes from the surface of the substrate 200.

[0083] Next, as Figure 3J As shown, the surface of the stress semiconductor layer 212 is oxidized to form an oxide layer 213 on the stress semiconductor layer 212. For example, the oxide layer 213 is formed by an oxidation process such as rapid thermal oxidation or low-temperature thermal oxidation. The oxide layer can serve as a protective layer in subsequent process steps to prevent the stress semiconductor layer 212 from being etched or contaminated, and passivate dangling bonds and defect states on the surface of the stress semiconductor layer 212 and at its interface with the substrate 200, thereby improving the interface quality.

[0084] Next, step S180 is performed to etch away the remaining first mask layer and at least etch away the sidewall material layer on the top surface of the gate to form sidewall layers on both sides of the gate in the PMOS region and on both sides of the gate in the NMOS region.

[0085] For example, such as Figure 3K As shown, a wet etching process is used to remove the remaining first mask layer 205 and the sidewall material layer on the top surface of the gate 201. It is worth noting that when removing the remaining first mask layer 205, the second material layers 204 on both sides of the gate 201 can also be removed, ultimately forming the sidewall layer 214 with the first material layer 203. For example, the first material layer 203 and the first mask layer 205 have the same material, and the wet etching process can remove the first material layer 203 on the top surface of the gate 201 simultaneously with removing the remaining first mask layer 205.

[0086] In a specific example, both the first mask layer 205 and the first material layer 203 are made of silicon nitride, while the second material layer 204 is made of silicon oxide. Therefore, a wet etching process can be performed using an etchant with high selectivity for silicon nitride (such as hot phosphoric acid). This etching process simultaneously removes the remaining first mask layer 205 covering the semiconductor structure surface, as well as the first material layer 203 located on top of the gate 201. During this process, the second material layer 204 on the gate sidewall has high resistance to the etchant due to its silicon oxide material, and its lateral portion is protected vertically by the underlying first material layer 203, thus allowing it to be retained. The second material layer 204 on the gate sidewall is then etched away; the etching process can be dry etching or wet etching. After etching, the original stacked structure on the gate sidewall, composed of the first material layer 203 and the second material layer 204, is transformed into a single sidewall layer 214 consisting only of the retained first material layer 203. This step not only defines the morphology of the sidewall but also simultaneously removes the remaining first mask layer.

[0087] Then, continue as follows Figure 3K As shown, etching removes the oxide layer 213 on the stress semiconductor layer 212. The removal of the oxide layer 213 can be achieved using dry etching (such as reactive ion etching) or wet etching (such as diluted hydrofluoric acid solution). The process selection must comprehensively consider factors such as selectivity for the underlying stress semiconductor layer 212 (such as silicon-germanium), etching uniformity, and avoiding the introduction of surface damage. After etching, the surface of the stress semiconductor layer 212 is exposed, facilitating subsequent source / drain contact hole formation and metallization processes.

[0088] It is worth mentioning that the second material layer may be removed in this step, thereby forming the final sidewall layer 214 after this step.

[0089] This concludes the description of the key steps in the semiconductor device manufacturing method of this application. The complete semiconductor device manufacturing method may also include other steps, which will not be elaborated here. It is worth mentioning that the order of the above steps can be adjusted without conflict.

[0090] In summary, the semiconductor device manufacturing method of this application embodiment includes a PMOS region and an NMOS region on a substrate of a semiconductor structure. A first mask layer is formed on the surface of the semiconductor structure. An anti-reflection layer and a second mask layer, as well as an opening penetrating the second mask layer and the anti-reflection layer, are formed on the first mask layer. The opening exposes a portion of the first mask layer of the PMOS region. Then, the first mask layer exposed by the opening is removed. After removing the first mask layer exposed by the opening, the second hard mask layer and a portion of the anti-reflection layer of the NMOS region are removed to expose a portion of the first mask layer on the top surface of the gate of the NMOS region. Then, the first mask layer on the top surface of the gate of the NMOS region is removed while etching trenches in the PMOS region. Then, conventional processes are used to form a stress semiconductor layer, the gate sidewall of the PMOS region, and the gate sidewall of the NMOS region. Thus, it is not necessary to remove the hard mask layer of the NMOS region separately during the formation of the stress semiconductor layer of the PMOS region, thereby saving production costs and improving production efficiency.

[0091] This application also provides a semiconductor device that can be prepared by the manufacturing method of the semiconductor device in the foregoing embodiments. The semiconductor device of this application has the same beneficial effects as the manufacturing method of the foregoing semiconductor device, which will not be repeated here.

[0092] Although several embodiments have been described herein, it should be understood that many other modifications and embodiments will arise in the mind of those skilled in the art, all of which will fall within the spirit and scope of the concept disclosed herein. More specifically, various modifications and changes may be made in terms of the arrangement and / or components of the subject matter within the scope of this disclosure, the drawings, and the appended claims. In addition to modifications and changes in the components and / or arrangement, the use of alternative methods will also be obvious to those skilled in the art.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, The manufacturing method includes: A semiconductor structure is provided, the semiconductor structure including a substrate, the substrate including at least one PMOS region and at least one NMOS region, a gate and a sidewall material layer covering the gate are disposed on the substrate of the PMOS region and the NMOS region, the sidewall material layer including a first material layer and a second material layer stacked from bottom to top; A first mask layer is formed to conformally cover the surface of the semiconductor structure; An anti-reflection layer and a second mask layer are sequentially formed on the first mask layer, and an opening penetrating the second mask layer and the anti-reflection layer is formed, the opening also exposing a portion of the first mask layer located in the PMOS region; Remove the first mask layer exposed in the opening; At least the second mask layer and a portion of the thickness of the anti-reflective layer on the gate of the NMOS region are removed to expose at least a portion of the first mask layer on the top surface of the gate of the NMOS region; Trenches are formed in the substrate on both sides of the gate of the PMOS region by etching process, and a portion of the first mask layer and a portion of the second material layer located in the NMOS region are removed, so that a portion of the first material layer on the top surface of the gate of the NMOS region is exposed. A stress semiconductor layer is formed in the trench to fill the trench, and the top surface of the stress semiconductor layer protrudes from the surface of the substrate; The remaining first mask layer is etched away, and at least the sidewall material layer on the top surface of the gate is etched away to form sidewall layers on both sides of the gate in the PMOS region and on both sides of the gate in the NMOS region.

2. The manufacturing method as described in claim 1, characterized in that, Trenches are formed in the substrate on both sides of the gate of the PMOS region by an etching process, including: An initial trench is formed in the substrate on both sides of the gate of the PMOS region by a first etching process, while removing a portion of the first mask layer and a portion of the second material layer exposed in the NMOS region, so that a portion of the first material layer on the gate of the NMOS region is exposed. Remove the remaining anti-reflective layer and perform a second etching process on the initial trench to expand it into the final trench.

3. The manufacturing method as described in claim 2, characterized in that, A sacrificial layer is also formed between the first mask layer and the substrate. The initial trenches are formed in the substrate on both sides of the gate of the PMOS region by the first etching process, including: Etching removes a portion of the sacrificial layer on the substrate to expose portions of the substrate on either side of the gate of the PMOS region; The substrate is etched to form the initial trench.

4. The manufacturing method as described in claim 3, characterized in that, The second mask layer includes a photoresist layer, the first mask layer and the first material layer are made of silicon nitride, and the sacrificial layer and the second material layer are made of silicon oxide.

5. The manufacturing method as described in claim 2, characterized in that, Performing a second etching process on the initial trench to expand it into the final trench includes: The substrate exposed in the initial trench is etched using a wet etching process to form the Σ-shaped trench.

6. The manufacturing method according to any one of claims 2-4, characterized in that, The first mask layer and the first material layer are made of silicon nitride, the second material layer is made of silicon oxide, and the substrate is made of silicon. The process gases for the first etching include CF4 and Ar.

7. The manufacturing method as described in claim 1, characterized in that, The first material layer and the first mask layer have the same material, and the first material layer on the top surface of the gate is removed while the remaining first mask layer is etched away.

8. The manufacturing method as described in claim 7, characterized in that, After forming the stress semiconductor layer, before etching away the remaining first mask layer, the method further includes: Oxidize the exposed surface of the stress semiconductor layer to form an oxide layer. After etching away the remaining first mask layer, the process further includes etching away the oxide layer.

9. The manufacturing method as described in claim 1, characterized in that, The stress semiconductor layer includes a silicon-germanium layer, which is formed in the trench using a selective epitaxial growth process.

10. A semiconductor device, characterized in that, The semiconductor device is manufactured using the manufacturing method described in any one of claims 1-9.

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