Planar film passive equalizer in multi-core-particle integrated system and manufacturing method of planar film passive equalizer

Abstract

The invention provides a planar film passive equalizer in a multi-chip integrated system and a manufacturing method thereof, the planar film passive equalizer comprises a resistor region and a capacitor region, the resistor region and the capacitor region are connected in parallel and then are bridged between two points of an interconnection line to form a parallel R-C equalization structure; wherein the capacitor region and the resistor region are both of a planar multi-layer film stacking structure which is manufactured on the same silicon substrate by adopting film growth, the multi-layer film stacking structure is formed by alternately depositing polar plate layers and dielectric layers from bottom to top, and the polar plate layer is arranged at the top of the multi-layer film stacking structure; in the resistance region, the multiple layers of thin film stacking structures are connected through internal through holes, so that all polar plate layers are connected in parallel to form a planar thin film resistor; and in the capacitance region, the multiple layers of film stacking structures are connected through internal through holes, so that the adjacent polar plate layers are respectively connected to two different end points of the interconnection line, thereby forming a planar parallel polar plate capacitor.

Description

Technical Field

[0001] This invention relates to the field of integrated passive device technology, and in particular to a planar thin-film passive equalizer in a multi-core integrated system and its manufacturing method. Background Technology

[0002] As transistor miniaturization technology approaches its physical limits, the design paradigm for integrated circuits is shifting from single, large-size System-on-a-Chip (SoC) to the integration of multiple small-size chips. In multi-chip integrated systems, the integration density and transmission rate of data interfaces and interconnect networks are crucial for improving overall performance. However, high-density, fine interconnects can cause significant signal integrity problems at high speeds, such as signal attenuation, crosstalk, and inter-symbol interference (ISI).

[0003] To address the aforementioned signal integrity issues, existing technologies primarily employ equalizer solutions, which can be broadly categorized into active equalizers and passive equalizers.

[0004] Active equalizers: These equalizers utilize the switching characteristics and parasitic effects of transistors to achieve low-frequency suppression and high-frequency gain of signals. However, the disadvantage of active equalizers lies in their complex manufacturing process, which requires a large chip area, typically reaching several thousand μm. 2 Furthermore, it consumes a relatively high amount of power during operation. These drawbacks make it more suitable for long-distance critical path balancing than for applications requiring high-density, high-bandwidth parallel interfaces.

[0005] Passive equalizers: These equalizers primarily compensate for signals using passive components such as integrated resistors (R), capacitors (C), and inductors (L). Common structures include parallel RC type, series RL type, and T-bridge equalizers. Although passive equalizers save chip area compared to active solutions, current passive equalizers often employ damascene copper wiring layers in their inductor and capacitor fabrication methods, resulting in a large area on the adapter board and significant space consumption. Therefore, current technologies cannot simultaneously meet the requirements of high integration, low cost, and low power consumption in high-speed circuit equalization solutions. Summary of the Invention

[0006] In view of this, the present invention provides a planar thin-film passive equalizer and a method for manufacturing the same, in order to solve at least one of the problems mentioned above.

[0007] To achieve the above objectives, the present invention adopts the following solution: According to a first aspect of the present invention, an embodiment of the present invention provides a planar thin-film passive equalizer, including a resistive region and a capacitive region, wherein the resistive region and the capacitive region are connected in parallel and then connected across two points of an interconnect line to jointly form a parallel RC equalization structure; The capacitor region and the resistor region are both planar multilayer thin film stacked structures fabricated on the same silicon substrate by thin film growth. The multilayer thin film stacked structure is formed by alternating deposition of electrode layers and dielectric layers from bottom to top, and the top of the multilayer thin film stacked structure is the electrode layer. Within the resistance region, the multilayer thin film stacked structure is connected through internal through holes, so that all or part of the electrode layers are connected in parallel, forming a conductive path with a specific resistance value, thereby constituting a planar thin film resistor. Within the capacitor region, the multilayer thin film stacked structure is connected through internal through-holes, so that adjacent electrode layers are respectively connected to two different ends of the interconnect line, thereby forming a planar parallel electrode capacitor.

[0008] In one embodiment of this application, a silicon dioxide layer is further included between the silicon substrate and the bottom electrode layer.

[0009] In one embodiment of this application, the planar thin-film passive equalizer further includes a copper metal layer connected to the through-hole. The copper metal layer is manufactured by damascus steel and electroplating to complete the internal interconnection of the planar thin-film passive equalizer and to connect to the interconnect line.

[0010] In one embodiment of this application, the thickness of the copper metal layer is 1 μm; the thickness of the interlayer dielectric is 1 μm; the thickness of the electrode layer is 50 nm; the thickness of the dielectric layer is 20 nm; the width of the resistance line of the resistance region is 1 μm; the length of the resistance region is 12 μm; and the side length of the capacitor region is 12 μm.

[0011] In one embodiment of this application, the individual unit size of the planar thin-film passive equalizer is less than 300 μm. 2 .

[0012] In one embodiment of this application, the above-described multilayer thin film stack structure and the vias are covered with silicon dioxide.

[0013] In one embodiment of this application, the conductive material used in the electrode layer is selected from one or more combinations of metals, metal nitrides, or metal alloys; the insulating material used in the dielectric layer is selected from one or more combinations of silicon nitride, metal oxides, or mixed materials.

[0014] In one embodiment of this application, the via is filled with sputtered tungsten metal and the excess tungsten on the surface is removed by a chemical mechanical planarization process.

[0015] In one embodiment of this application, the operating curve of the passive equalizer can be adjusted by adjusting the number and size of the electrode layers.

[0016] According to a second aspect of the present invention, an embodiment of the present invention provides a method for manufacturing a planar thin-film passive equalizer, the method comprising: A first silicon dioxide layer is grown on a silicon substrate to form an insulating layer; On the insulating layer, conductive materials are alternately deposited to form an electrode layer and insulating materials to form a dielectric layer, thereby forming a planar multilayer thin film stack structure; The multilayer thin film stack structure is patterned using photolithography and etching processes to define the resistive and capacitive regions. A second silicon dioxide layer is deposited on the surface of the multilayer thin film stack structure and then planarized. By photolithography, development, and etching of the second silicon dioxide layer, through-hole arrays for connecting the electrode layer are respectively prepared in the resistive region and the capacitor region. Sputtering metallic tungsten fills the through-hole array, and chemical mechanical planarization removes excess metallic tungsten from the surface; A copper metal layer connecting the via array is formed using the damascus process and electroplating to complete the internal interconnection of the resistive region and the capacitor region and connect them to the external interconnection lines.

[0017] The planar thin-film passive equalizer and its manufacturing method proposed in this invention feature a compact and ingenious design, with the physical size of a single unit being less than 300 μm. 2 Compared to traditional inductor-based equalizers, this device reduces size by an order of magnitude. This ultra-small area allows for high-density integration onto silicon interposer boards or silicon interconnect bridges, making it particularly suitable for high-density parallel interface applications. Furthermore, the manufacturing method of this equalizer cleverly utilizes and is fully compatible with existing deep-groove capacitor manufacturing processes. This means that no additional photomask layer is required during production, significantly simplifying the manufacturing process and effectively reducing production costs. Finally, the planar thin-film passive equalizer of this application, by incorporating optimized parameters, can effectively compensate for the attenuation of high-speed signals during transmission. For example, when applied to interconnect channels with a linewidth of 1 micrometer and a pitch of 5 micrometers, it can effectively equalize signals up to 32Gbps NRZ, thereby achieving extremely high transmission bandwidth, such as an edge interconnect bandwidth of 6.4Tbps / mm. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings:

[0019] Figure 1 This is a top view of the planar thin-film passive equalizer in the multi-core integrated system provided in this application embodiment;

[0020] Figure 2 This is a cross-sectional view of the planar thin-film passive equalizer in the multi-core integrated system provided in this application embodiment;

[0021] Figure 3 This is a diagram showing the arrangement of the planar thin-film passive equalizer and transmission lines provided in the embodiments of this application;

[0022] Figure 4 This is a flowchart illustrating the fabrication process of the planar thin-film passive equalizer in the multi-core integrated system provided in this application embodiment. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. Here, the illustrative embodiments of the present invention and their descriptions are used to explain the present invention, but are not intended to limit the present invention.

[0024] As indicated in this application and claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" are not specifically singular and may include plural forms. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements.

[0025] Furthermore, it should be noted that the use of terms such as "first" and "second" to define related concepts is merely for the purpose of distinguishing the corresponding concepts. Unless otherwise stated, these terms have no special meaning and therefore should not be construed as limiting the scope of protection of this application. In addition, although the terminology used in this application is selected from commonly known and used terms, some terms mentioned in this application's specification may have been chosen by the applicant according to his or her judgment, and their detailed meanings are explained in the relevant sections of this description. Moreover, this application should be understood not only through the actual terms used, but also through the meaning implied by each term.

[0026] like Figure 1 The image shown is a top view of a planar thin-film passive equalizer in a multi-core integrated system provided in this application embodiment. Figure 2 This is a cross-sectional view of a planar thin-film passive equalizer. Below, we will combine... Figure 1 and Figure 2 The planar thin-film passive equalizer of this application will be described.

[0027] Depend on Figure 1 As can be seen, the planar thin-film passive equalizer includes a resistor region B and a capacitor region A. The resistor region B and the capacitor region A together form a parallel RC equalization structure. After being connected in parallel, they are connected across two points in the high-speed signal transmission path (i.e., interconnection line 1) to compensate for signal loss during high-frequency transmission.

[0028] In this embodiment, both capacitor region A and resistor region B are planar multilayer thin film stacked structures fabricated on the same silicon substrate 2. This planar multilayer thin film stacked structure is formed by alternating deposition of an electrode layer 3 (conductive material) and a dielectric layer 4 (insulating material) from bottom to top using thin film growth techniques such as atomic layer deposition (ALD) or physical vapor deposition (PVD). The top of the entire stacked structure is an electrode layer. This manufacturing process is fully compatible with existing deep trench capacitor processes, the difference being that the material growth in this application is entirely planar.

[0029] Within the resistance region B, this multilayer thin-film stacked structure is connected through internal through-holes 5, allowing all electrode layers 3 to be connected in parallel, forming a conductive path with a specific resistance value, thus constituting a planar thin-film resistor. For example... Figure 2 As shown in Figure (a), the plate pattern connection method of the resistive region B is given. The four parallel conductor plates are connected in parallel, which reduces the conduction resistance. Of course, in this embodiment, some of the plate layers 3 can also be connected in parallel. That is, when making the through holes 5, only the through holes corresponding to the plate layers 3 need to be selectively made. It can be seen that in this embodiment, the deep trench thin film passive equalizer can achieve the combination of different parameters of the capacitor region A, the resistive region B and the inductor region C by selectively making different through holes 5 when preparing the capacitor region A, the resistive region B and the inductor region C. The preparation process is flexible and controllable.

[0030] Depend on Figure 2 As shown in (a), each electrode layer can be considered an independent resistor. At the entrance of resistor region B, four through-holes and the copper metal layer 8 connect all four electrode layers together. At the exit of resistor region B, another four through-holes similarly connect these four electrode layers together. This is equivalent to connecting the two ends of four independent resistors to the same common point, forming a parallel circuit. Through this parallel connection, the total on-resistance is reduced.

[0031] Within capacitor region A, the multilayer thin-film stacked structure is the same as that of resistor region B. The difference lies in the connection method between the through-hole 5 and the electrode layer 3. Within capacitor region A, adjacent electrode layers 3 are connected to two different endpoints of interconnect line 1 through the internal through-hole 5, thereby forming a planar parallel electrode capacitor.

[0032] A simple parallel-plate capacitor consists of three basic parts: two parallel conducting plates and an insulating dielectric sandwiched between them. When a voltage is applied to the plates, charge is stored on them.

[0033] Depend on Figure 2 As shown in Figure (b), there are multiple electrode layers 3 made of conductive material, with a dielectric layer 4 made of insulating material filling between every two electrode layers. Within capacitor region A, the vias 5 are connected alternately. As shown, the first and third electrode layers are connected to a copper metal layer 8 through vias 5, while the second and fourth electrode layers are connected to another copper metal layer 8 through vias 5.

[0034] This alternating connection method ensures that each pair of adjacent plates connected to different signal terminals (e.g., the first and second layers, the second and third layers, the third and fourth layers) constitutes an independent parallel plate capacitor, forming a parallel connection in the circuit.

[0035] In one embodiment of this application, the operating curve of the passive equalizer can be adjusted by changing the number and size of the electrode layers 3. That is, this embodiment can obtain smaller or larger resistance values ​​by connecting more or fewer electrode layers 3 in parallel. For example, in resistance region B, increasing the number of parallel electrode layers can effectively reduce the total resistance; conversely, reducing the number of layers will increase the resistance. The resistance value is also directly related to the physical dimensions of the resistance region, especially the length of the resistance region and the width of the resistance lines; increasing the length or decreasing the width will increase the resistance value. In capacitance region A, increasing the number of stacked electrode layers and dielectric layers is equivalent to adding multiple parallel-connected planar capacitors, thereby obtaining a larger total capacitance value. Furthermore, the capacitance value is positively correlated with the area of ​​the electrode plates in the capacitance region. By adjusting the electrode dimensions such as the side length of the capacitance region, different capacitance values ​​can be obtained; increasing the side length (i.e., increasing the area) will increase the capacitance value.

[0036] The operating curve (i.e., its frequency response characteristics) of a passive equalizer is determined by the values ​​of its internal resistor (R) and capacitor (C). Therefore, by changing the resistor and capacitor values ​​using the method described above, the attenuation levels of the high-frequency and low-frequency components of the signal can be directly adjusted, thereby adjusting the overall operating curve. This adjustability allows the equalizer design to be adapted to specific conditions, optimized for transmission lines of different lengths and loss characteristics to achieve the best signal equalization effect.

[0037] In another embodiment of this application, a first silicon dioxide layer 6 is further included between the silicon substrate 2 and the bottom electrode layer. This first silicon dioxide layer 6 is prepared on a clean silicon substrate 2 using a thermo-oxidative growth process, and its main function is to achieve insulation of the silicon wafer surface. This first silicon dioxide layer 6 is the foundation of the entire multilayer thin film structure, ensuring complete isolation between all conductive electrode layers on it and the silicon substrate with a certain degree of conductivity, thus avoiding leakage and signal loss.

[0038] As described above, the planar thin-film passive equalizer also includes a copper metal layer 8, which is connected to the through-hole 5. The copper metal layer can be manufactured by damascusing and electroplating, and is used to complete the internal interconnection of the planar thin-film passive equalizer and connect to the interconnect line 1.

[0039] The copper metal layer 8 serves as the final connection and wiring element in the entire planar thin-film passive equalizer. This copper metal layer 8 is connected to specific electrode layers in the multilayer thin-film stacked structure through vias 5 beneath it. Its core function is to bring the corresponding electrodes together at a common electrical node according to the design (e.g., capacitor or resistor regions), thus completing the internal interconnection of the equalizer. After completing the internal interconnection, the copper metal layer 8 extends out to connect to the external circuit interconnects 1, thereby embedding the entire planar thin-film passive equalizer into the high-speed signal transmission path.

[0040] In another embodiment of this application, the aforementioned multilayer thin-film stacked structure and via 5 are covered by a second silicon dioxide layer 7. After the multilayer thin-film stacked structure is completed, the patterns of all conductor plates can be formed by photolithography and etching processes. Subsequently, silicon dioxide is deposited by methods such as physical vapor deposition (PVD) to cover the entire structure. This second silicon dioxide layer 7 fills the etched gaps and unevenness of the structural surface, and then undergoes chemical mechanical planarization (CMP) to obtain a smooth surface. This flat second silicon dioxide layer 7 forms the basis for fabricating the via 5 and the top copper metal layer 8. Next, photolithography and etching are performed on this silicon dioxide layer to fabricate the via 5 connecting to the lower plate.

[0041] In another embodiment of this application, the vias 5 are filled with sputtered tungsten metal, and excess tungsten is removed from the surface using a chemical mechanical planarization (CMP) process. After forming a smooth silicon dioxide surface using physical vapor deposition (PVD) and chemical mechanical planarization (CMP) processes, the next step is to fabricate an array of vias on the silicon dioxide layer using photolithography, development, and etching techniques. The positions and depths of these vias 5 are precisely designed to accurately expose the underlying conductor electrode layers that need to be connected.

[0042] Sputtering is a physical vapor deposition technique that uniformly deposits tungsten metal onto the entire wafer surface, completely filling vias. Tungsten is chosen as the filler material because of its good electrical conductivity, thermal stability, and compatibility with silicon dioxide.

[0043] After the vias are completely filled, the wafer surface is covered with an excess of tungsten. To remove this excess metal and ensure the surface is flat again for subsequent copper wiring layer fabrication, a chemical mechanical planarization (CMP) process is required. CMP precisely removes the tungsten from the surface through the synergistic effect of chemical etching and mechanical polishing until a flat silicon dioxide layer is exposed again, leaving tungsten as conductive pillars inside the vias.

[0044] After completing this step, a structure with a flat surface and vertical electrical connections achieved internally through tungsten metal pillars is obtained, which prepares the final step for manufacturing the top copper metal layer 8.

[0045] In another embodiment of this application, the conductive material used in the electrode layer 3 can be selected from one or more combinations of metals, metal nitrides or metal alloys, such as TiN, TaN, Al, etc. It is required to have good adhesion to the materials of the first silicon dioxide 6 and the dielectric layer 4, which is crucial to ensuring the stability and reliability of the multilayer thin film structure.

[0046] The insulating material used in dielectric layer 4 is selected from one or more combinations of silicon nitride, metal oxide, or mixed materials, such as SiON. x Materials such as Al2O3, HfO2, ZrO2, or TiO2 are used. These materials, especially High-K materials (such as HfO2), help to achieve high capacitance density in a very small area.

[0047] The inventors found that, preferably, the dielectric layer 4 is made of HfO2 and the electrode layer 3 is made of TiN, which has good process compatibility.

[0048] Both the electrode layer 3 and the dielectric layer 4 can be prepared using processes such as atomic layer deposition (ALD) or physical vapor deposition (PVD). By alternating the deposition of these two materials, a multilayer thin-film structure with the desired number of layers can be constructed.

[0049] The aforementioned passive equalizer is specifically designed for high-speed interconnects in multi-core integration and can be integrated into silicon interposer boards or silicon interconnect bridges. These scenarios are characterized by extremely high interconnect density and very stringent size requirements for the equalizer. In this embodiment, when arranged in an interleaved pattern, high-density integration of the equalizer can be achieved, such as... Figure 3 The diagram shows the arrangement of a planar thin-film passive equalizer and transmission lines.

[0050] like Figure 3 As shown, eight independent planar thin-film passive equalizers are placed on eight parallel interconnect lines. They are not placed side-by-side or aligned, but rather in a staggered arrangement. This staggered layout makes full use of the space above and below the transmission lines, allowing the equalizers to be closely packed together, thus integrating as many equalizers as possible within a limited area, achieving high-density integration. Figure 3 The example demonstrates how to effectively integrate eight equalizers with interconnect linewidths of 1 micrometer and line spacing of 5 micrometers. Assuming... Figure 3 The left side of the diagram represents the signal transmitter, and the right side represents the signal receiver. Each equalizer is connected in series in its respective transmission channel to equalize the high-speed signal emitted from the transmitter before the signal is transmitted to the receiver. This design is well-suited for protocols and standards such as UCIe and HBM (High Bandwidth Memory) that require high-speed parallel interconnection.

[0051] When the aforementioned passive equalizer is applied to a multi-core integrated system, by optimizing the design parameters, it can achieve extremely high-density integration while meeting high-performance requirements, effectively solving the signal integrity problem of high-speed parallel interfaces in multi-core systems.

[0052] Table 1 below is an example of parameter design optimization provided in the embodiments of this application:

[0053] Table 1

[0054]

[0055] The explanations for the above parameters can be found in the reference section. Figures 1-3 The corresponding annotations are provided, and further textual descriptions are omitted. Based on the design parameters in Table 1, the individual unit size of the planar thin-film passive equalizer can be reduced to less than 300 μm. 2 The ultra-small area (for example, it can reach 224μm in this embodiment) 2 ), and when this planar thin-film passive equalizer is applied to an 8-channel interconnect with a linewidth of 1 micrometer and a spacing of 5 micrometers (i.e. Figure 3 It can achieve equalization of 32Gbps NRZ signals and achieves an edge interconnect bandwidth of 6.4Tbps / mm.

[0056] As can be seen from the above, the planar thin-film passive equalizer proposed in this invention has a compact and ingenious design, and the physical size of a single unit can be less than 300μm. 2Compared to traditional inductor-based equalizers, this device reduces size by an order of magnitude. This ultra-small area allows for high-density integration onto silicon interposer boards or silicon interconnect bridges, making it particularly suitable for high-density parallel interface applications. Furthermore, the manufacturing method of this equalizer cleverly utilizes and is fully compatible with existing deep-groove capacitor manufacturing processes. This means that no additional photomask layer is required during production, significantly simplifying the manufacturing process and effectively reducing production costs. Finally, the planar thin-film passive equalizer of this application, by incorporating optimized parameters, can effectively compensate for the attenuation of high-speed signals during transmission. For example, when applied to interconnect channels with a linewidth of 1 micrometer and a pitch of 5 micrometers, it can effectively equalize signals up to 32Gbps NRZ, thereby achieving extremely high transmission bandwidth, such as an edge interconnect bandwidth of 6.4Tbps / mm.

[0057] like Figure 4 The diagram shown is a flowchart illustrating a method for manufacturing a planar thin-film passive equalizer in a multi-core integrated system according to an embodiment of this application. The method includes the following steps:

[0058] Step S401: A first silicon dioxide layer is grown on a silicon substrate to form an insulating layer.

[0059] This step lays the electrical isolation foundation for the entire device structure, typically using a high-purity single-crystal silicon wafer as the mechanical support substrate. Through a thermal oxidation process, in a high-temperature, oxygen-containing environment, silicon atoms on the wafer surface react with oxygen to grow a dense, uniform silicon dioxide layer with excellent dielectric properties. This silicon dioxide layer completely isolates all subsequent functional structures from the conductive silicon substrate, preventing current leakage into the substrate and ensuring the equalizer functions accurately as an independent passive device.

[0060] Step S402: On the insulating layer, conductive materials are alternately deposited to form an electrode layer and insulating materials to form a dielectric layer, thereby constituting a planar multilayer thin film stack structure.

[0061] Planar multilayer thin-film stacked structures are sandwich structures composed of conductive electrodes and dielectric layers, forming the basis for capacitance and resistance. This process employs atomic layer deposition (ALD) or physical vapor deposition (PVD) techniques. The advantage of ALD technology lies in its ability to grow at the atomic layer level, enabling extremely precise control over film thickness (e.g., a dielectric layer thickness of 20 nm and an electrode thickness of 50 nm) with excellent conformal properties. This is crucial for fabricating high-quality, high-capacitance-density High-K dielectric layers.

[0062] This process is performed alternately, for example: depositing a conductive material (TiN) layer -> depositing an insulating material (HfO2) layer -> depositing a second conductive material (TiN) layer -> depositing a second insulating material (HfO2) layer... and so on, until the designed number of layers is reached (e.g., a total of 4 electrode layers and 3 dielectric layers). The last layer is the electrode layer.

[0063] Step S403: The multilayer thin film stack structure is patterned using photolithography and etching processes to define the resistive region and the capacitive region.

[0064] This step involves etching circuit patterns onto the aforementioned sandwich structure, clearly defining the resistive and capacitive regions. This is a delicate subtractive process: a layer of photoresist is coated onto the surface of the multilayer thin-film stacked structure. A photomask with a pre-defined pattern (i.e., the shapes of resistive region B and capacitive region A) is then exposed to ultraviolet light, causing changes in the chemical properties of the photoresist in specific areas. The exposed (or unexposed, depending on the photoresist type) photoresist is then washed away with a developer, exposing the underlying multilayer thin-film structure. Dry etching is then used to etch the exposed thin-film material layer by layer downwards. By precisely controlling the etching depth and range, the electrode layers in different regions are shaped into specific interconnection patterns.

[0065] Step S404: Deposit a second silicon dioxide layer on the surface of the multilayer thin film stack structure and perform planarization treatment.

[0066] This step fills in the trenches created after patterning and provides an absolutely flat worktable for subsequent interconnect processes. A layer of silicon dioxide can be deposited over the entire surface using methods such as physical vapor deposition (PVD). This silicon dioxide layer fills all the gaps etched in step S403, serving as protection and interlayer insulation. Then, a chemical mechanical planarization (CMP) process is employed. The CMP equipment acts like a precision polisher, using the synergistic effect of chemical etching solution and abrasive particles to polish the wafer surface to nanometer-level flatness. A flat surface is crucial for the focusing accuracy of subsequent photolithography and the yield of metal wiring.

[0067] Step S405: By photolithography, development, and etching of the second silicon dioxide layer, through-hole arrays for connecting the electrode layers are respectively prepared in the resistive region and the capacitive region.

[0068] The purpose of this step is to drill holes in the insulating silicon dioxide to create vertical conductive channels for connecting the different electrode layers buried deep beneath. This step repeats the "photolithography-development-etching" process, but this time the goal is to operate on the second silicon dioxide layer formed in S404. The etching depth needs to be precisely controlled to ensure that the vias stop precisely on the surface of the target electrode layer to be connected, without piercing through or under-etching.

[0069] Step S406: Sputter tungsten metal to fill the through-hole array, and chemically and mechanically planarize to remove excess tungsten metal from the surface.

[0070] This step involves filling the vias with conductive metal to form conductive pillars (Via). Specifically, a sputtering process is used to uniformly deposit high-melting-point, highly conductive tungsten metal across the entire wafer surface, completely filling all vias. Then, a chemical mechanical planarization (CMP) process is performed again. The goal here is to remove only the tungsten from the wafer surface, retaining the tungsten inside the vias. After this process, the wafer surface is restored to flat silicon dioxide, while embedded tungsten pillars are formed within the vias, creating a reliable vertical electrical connection.

[0071] Step S407: A copper metal layer connecting the via array is formed using the damascus process and electroplating to complete the internal interconnection of the resistive region and the capacitor region and connect them to the external interconnection lines.

[0072] The copper metal layer integrates the various components (resistors and capacitors) inside the equalizer, which are connected via vias, into a complete circuit, and provides connection points for connection to external signal transmission lines. Using the damascus process, an insulating dielectric layer is first deposited on the surface, and then trenches with wiring patterns are etched into it using photolithography and etching. Next, copper is electroplated into the trenches. Finally, CMP (Chemical Mechanical Polishing) removes excess copper from the surface, forming flat copper conductors embedded in the insulating dielectric. These copper conductors are precisely connected to the underlying tungsten vias, ultimately completing the manufacturing of the entire equalizer.

[0073] As can be seen from the above, the manufacturing method of the planar thin-film passive equalizer proposed in this invention results in an equalizer design that is exquisite and compact, with the physical size of a single unit being less than 300 μm. 2 Compared to traditional inductor-based equalizers, this device reduces size by an order of magnitude. This ultra-small area allows for high-density integration onto silicon interposer boards or silicon interconnect bridges, making it particularly suitable for high-density parallel interface applications. Furthermore, the manufacturing method of this equalizer cleverly utilizes and is fully compatible with existing deep-groove capacitor manufacturing processes. This means that no additional photomask layer is required during production, significantly simplifying the manufacturing process and effectively reducing production costs. Finally, the planar thin-film passive equalizer of this application, by incorporating optimized parameters, can effectively compensate for the attenuation of high-speed signals during transmission. For example, when applied to interconnect channels with a linewidth of 1 micrometer and a pitch of 5 micrometers, it can effectively equalize signals up to 32Gbps NRZ, thereby achieving extremely high transmission bandwidth, such as an edge interconnect bandwidth of 6.4Tbps / mm.

[0074] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A planar thin film passive equalizer in a multi-core particle integrated system, characterized by, The parallel R-C equalizer includes a resistance region and a capacitance region, which are connected in parallel and across two points of an interconnection line. The resistance region and the capacitance region are both planar multilayer thin film stack structures grown on the same silicon substrate, which are deposited alternately from bottom to top by electrode plate layers and dielectric layers, and the top of the multilayer thin film stack structure is an electrode plate layer. In the resistance region, the multilayer thin film stack structure is connected by internal vias, so that all or part of the electrode plate layers are connected in parallel, and the whole serves as a conductive path with a specific resistance value, thereby forming a planar thin film resistor. In the capacitance region, the multilayer thin film stack structure is connected by internal vias, so that adjacent electrode plate layers are connected to two different end points of the interconnection line, thereby forming a planar parallel-plate capacitor.

2. The planar thin film passive equalizer in a multi-chiplet integrated system of claim 1, wherein, The silicon substrate and the bottom electrode plate layer further include a silicon dioxide layer.

3. The planar thin film passive equalizer in a multi-chiplet integrated system of claim 2, wherein, The planar thin film passive equalizer further includes a copper metal layer connected with the vias, which is formed by damascene and electroplating methods to complete the internal interconnection of the planar thin film passive equalizer and connect with the interconnection line.

4. The planar thin film passive equalizer in a multi-chiplet integrated system of claim 3, wherein, The thickness of the copper metal layer is 1 μm, the thickness of the interlayer dielectric is 1 μm, the thickness of the electrode plate layer is 50 nm, the thickness of the dielectric layer is 20 nm, the width of the resistance line of the resistance region is 1 μm, the length of the resistance region is 12 μm, and the side length of the capacitance region is 12 μm.

5. The planar thin film passive equalizer in a multi-chiplet integration system of claim 4, wherein, The single cell size of the planar thin film passive equalizer is less than 300 pm 2 .

6. The planar thin film passive equalizer in a multi-chiplet integrated system of claim 1, wherein, The multilayer thin film stack structure and the vias are covered by silicon dioxide.

7. The planar thin film passive equalizer in a multi-chiplet integrated system of claim 1, wherein, The conductive material of the electrode plate layer is selected from one or more combinations of metal, metal nitride or metal alloy, and the insulating material of the dielectric layer is selected from one or more combinations of silicon oxynitride, metal oxide or mixed material.

8. The planar thin film passive equalizer in a multi-chiplet integrated system of claim 1, wherein, The vias are filled with sputtered tungsten and the surface excess tungsten is removed by chemical mechanical planarization process.

9. The planar thin film passive equalizer in a multi-chiplet integrated system of claim 1, wherein, By adjusting the number and size of the electrode plate layers, the working curve of the passive equalizer can be adjusted.

10. A method for manufacturing a planar thin-film passive equalizer in a multi-core integrated system, characterized in that, The method includes: growing a first silicon dioxide layer on a silicon substrate to form an insulating layer; alternately depositing conductive material to form electrode plate layers and insulating material to form dielectric layers on the insulating layer to form a planar multilayer thin film stack structure; performing photolithography and etching on the multilayer thin film stack structure to define a resistance region and a capacitance region; depositing a second silicon dioxide layer on the surface of the multilayer thin film stack structure and performing planarization treatment; performing photolithography, development and etching on the second silicon dioxide layer to prepare via arrays for connecting electrode plate layers in the resistance region and the capacitance region; filling the via arrays with sputtered tungsten and removing the surface excess tungsten by chemical mechanical planarization; forming a copper metal layer connected with the via arrays by damascene and electroplating methods to complete the internal interconnection of the resistance region and the capacitance region and connect them to the external interconnection line.

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