Circuits, chips, and electronic devices for implementing interrupt arbitration in I3C HUB chips.

Abstract

The application discloses a kind of circuit, chip and electronic equipment for realizing interrupt arbitration function in I3C HUB chip, belong to integrated circuit communication technical field.The application is integrated low-level clamping circuit and voltage detection comparator in each slave side port, voltage detection circuit compares SSP SDA pin voltage with reference voltage VREF in real time, when detecting voltage is lower than VREF, it is judged that slave initiates interrupt, and direction control logic is triggered to switch data path direction.The application is used in I3C HUB chip, solves arbitration blind area problem when master and slave drive low level simultaneously by voltage domain real-time comparison, with the advantages of high reliability, simple structure, no external timing control, good compatibility and easy to expand.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit communication technology, and more specifically to a circuit, chip, and electronic device for implementing interrupt arbitration function in an I3C HUB chip. Background Technology

[0002] The I3C (Improved Inter-Integrated Circuit) bus protocol is a next-generation serial communication interface standardized by the MIPI Alliance. While inheriting the basic architecture of the traditional I2C bus (serial data line SDA and serial clock line SCL), it integrates the high-speed characteristics of the SPI bus and some advantages of the UART bus. Compared to traditional I2C, I3C significantly improves data transfer rates, reduces static and dynamic power consumption, and natively supports multi-master operation, dynamic address allocation, and efficient in-band interrupt mechanisms while maintaining pin simplicity and low cost. These features make I3C better suited for modern electronic system applications.

[0003] One of the core innovations of the I3C bus lies in its dynamic hybrid use of open-drain (OD) and push-pull (PP) output modes. During bus startup, address transfer, and arbitration phases, the bus operates in OD mode, utilizing its wired-AND characteristic to achieve multi-master arbitration and interrupt requests; that is, if any device pulls the bus low, the entire bus is at a low level. Once the data payload transfer phase begins, it switches to PP mode, actively driving high and low levels to achieve high-speed data transmission, effectively improving data throughput. This flexible mode-switching mechanism is key to the high performance of the I3C, but it also presents significant challenges to the design of the I3C hub chip.

[0004] In complex I3C-based systems, the hub chip acts as the central node of the communication network. One end connects to the upstream master controller (such as an application processor or microcontroller) via the Master Side Port (MSP), while the other end connects to multiple downstream slave devices via multiple Slave Side Ports (SSPs). The core function of the hub is to efficiently and accurately manage the data flow between the master and slave devices, ensuring the reliability and integrity of communication. Because the I3C bus uses half-duplex communication, data can only be transmitted in one direction at a time. This requires the hub to have intelligent direction switching capabilities. It needs to determine in real time whether the current data flow is from the master's downlink communication (MSP to SSP) or from the slave's uplink communication (SSP to MSP), and promptly connect the corresponding data path while blocking the reverse path to prevent bus conflicts and data corruption.

[0005] Handling in-band interrupt requests initiated by slave devices is a crucial and highly challenging function of the I3C hub. In the I3C protocol, slave devices do not need to wait for host polling as in traditional I2C; instead, they can actively send an interrupt signal to the host by pulling SDA low, requesting communication. This process is called "interrupt arbitration." When the hub detects that a slave device has pulled its connected SSP SDA low to initiate an interrupt, it must respond immediately: first, it must identify the interrupt request; second, it needs to adjudicate the legitimacy of the request; and finally, it must quickly switch the transmission direction of the internal data path from MSP to SSP to SSP to MSP, enabling the interrupting slave device to successfully upload its subsequent data to the host. The entire arbitration and switching process must be completed within a very short time to meet the strict timing requirements of the bus protocol and ensure that communication is not interrupted or damaged.

[0006] In existing technologies, a typical scheme for implementing interrupt arbitration in an I3C hub is based on a fixed-time voltage detection arbitration method. This scheme utilizes the characteristic of the I3C bus being synchronized with SCL, and within a pre-set, fixed time window after the falling edge of SCL, simultaneously samples and compares the level states on MSP SDA and SSP SDA. Its arbitration logic is relatively straightforward: if MSP SDA is detected to be high (indicating the master is not driving the bus low) and SSP SDA is low (indicating the slave is driving the bus low) at this fixed time, then the interrupt arbitration request initiated by the slave is deemed valid, and the hub control logic will then execute a switch in the transmission direction.

[0007] However, this existing technical solution has fundamental flaws that are difficult to overcome: First, when the master and the slave requesting an interrupt simultaneously attempt to pull the bus low (i.e., both MSP SDA and SSP SDA are low), the bus is already at a low level due to the "wired-AND" characteristic of the OD line. The arbitration logic based on level comparison cannot distinguish this situation, causing the arbitration mechanism to fail and potentially leading to bus deadlock or data conflicts. Second, due to the differences in the internal logic of different slaves, the timing of their interrupt requests is asynchronous and unpredictable relative to the SCL clock edge. To ensure that potentially late arbitration signals can be captured, designers are forced to delay the sampling point, but this inevitably encroaches on the setup time of the next data bit, which can easily cause timing violations and data sampling errors at high communication rates. Third, the I3C bus supports multiple data rate modes, and the clock frequencies differ greatly between different modes. The HUB chip must be able to generate a variable sampling clock or delay chain that matches the current rate, which increases the complexity of circuit design, chip area, and power consumption, and also introduces more potential failure points.

[0008] Therefore, there is an urgent need in this field for a new and more fundamental solution that can get rid of the dependence on precise fixed time and fundamentally solve the arbitration problem in the case of level conflict, thereby realizing a more robust, efficient and easy-to-implement interrupt arbitration mechanism. Summary of the Invention

[0009] To alleviate or partially alleviate the above-mentioned technical problems, the solution of the present invention is as follows:

[0010] On one hand, this invention discloses a circuit for implementing interrupt arbitration function in an I3C HUB chip. The circuit for implementing interrupt arbitration function in the I3C HUB chip is integrated into each SSP of the HUB chip, and includes:

[0011] A low-level clamping circuit is used to clamp the voltage of the SSP SDA pin to a preset voltage V-pre when the HUB chip outputs a low level as a host driver SSP SDA pin.

[0012] A voltage detection circuit, connected to the SSP SDA pin, is used to detect the voltage on the SSP SDA pin in real time, compare it with the reference voltage VREF, and output an arbitration decision signal.

[0013] The direction control logic circuit controls the switching of the data path direction in response to the arbitration decision signal;

[0014] Specifically, when the voltage detection circuit detects that the voltage on the SSP SDA pin is lower than the reference voltage VREF, the arbitration decision signal indicates that the slave interrupt arbitration occurs, and the direction control logic circuit switches the data transmission direction from MSP to SSP to SSP to MSP; the preset voltage V-pre=VREF+ΔV, where ΔV is a positive value, to ensure that the preset voltage V-pre is greater than the reference voltage VREF.

[0015] In one embodiment, the low-level clamping circuit includes:

[0016] An amplifier, wherein the inverting input terminal of the amplifier is connected to the preset voltage V-pre, and the non-inverting input terminal of the amplifier is connected to the SSP SDA pin;

[0017] The SSP SDA pull-down driver transistor is connected between the SSP SDA pin and ground, and the gate of the SSP SDA pull-down driver transistor is controlled by the output of the amplifier.

[0018] The amplifier controls the SSP SDA pull-down drive transistor through negative feedback, so that the SSP SDA pin is stabilized at the preset voltage V-pre when the HUB drive is low.

[0019] In one embodiment, the voltage detection circuit includes a comparator, the non-inverting input of which is connected to the SSP SDA pin, the inverting input of which is connected to the reference voltage VREF, and the output of which outputs the arbitration decision signal.

[0020] In one embodiment, the direction control logic circuit includes:

[0021] The first inverter receives the arbitration decision signal at its input terminal and its output terminal is used to control the MSP SDA pull-down drive transistor of the SSP to MSP data path.

[0022] The second inverter has an enable terminal that receives the arbitration decision signal and an output terminal that controls the switching of the MSP to SSP data path.

[0023] Specifically, when the arbitration decision signal is low, the MSP to SSP data path is closed, and the SSP to MSP data path is open.

[0024] In one embodiment, the SSP SDA pull-down driver transistor and the MSP SDA pull-down driver transistor are NMOS transistors.

[0025] In one embodiment, a reference voltage generation circuit is included for generating the reference voltage VREF.

[0026] In one embodiment, the reference voltage generating circuit also generates the preset voltage V-pre.

[0027] In one embodiment, the preset voltage V-pre = VREF + ΔV, where ΔV is a positive value, to ensure that the preset voltage V-pre is greater than the reference voltage VREF.

[0028] In one embodiment, the circuitry implementing the interrupt arbitration function in the I3C HUB chip is further multiplexed to implement at least one of the following functions:

[0029] Clock extension function: The same voltage detection circuit is set on the SSP and SCL pins. When the SCL voltage is detected to be lower than the reference voltage VREF, a clock pause control signal is generated.

[0030] Slave acknowledgment detection function: During the clock cycle corresponding to the ACK bit, it detects whether the SSP SDA voltage is lower than the reference voltage VREF to determine the validity of the ACK signal.

[0031] On the other hand, the present invention discloses an I3C HUB chip, which includes circuitry for implementing interrupt arbitration functionality in the I3C HUB chip as described in any of the preceding claims.

[0032] On the other hand, the present invention discloses an electronic device comprising the aforementioned I3C HUB chip.

[0033] The technical solution of this invention has one or more of the following beneficial technical effects:

[0034] (1) Effectively avoid arbitration failure caused by simultaneous low-level driving of master and slave devices, and achieve highly reliable and timely interrupt arbitration through real-time comparison of voltage domain.

[0035] (2) It can automatically detect slave interrupt requests and intelligently switch data transmission direction without external intervention, simplifying system design.

[0036] (3) It is compatible with the I3C protocol standard and can be reused for clock extension and slave response detection functions, which improves the utilization of hardware resources.

[0037] Furthermore, other beneficial effects of the present invention will be mentioned in the specific embodiments. Attached Figure Description

[0038] Figure 1 This is a schematic diagram of the I3C HUB system applying the present invention;

[0039] Figure 2 This is a circuit diagram illustrating the interrupt arbitration function in one embodiment of the present invention. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0041] To facilitate a clear description of the technical solutions in the embodiments of the present invention, the terms "first" and "second" are used to distinguish identical or similar items with substantially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order.

[0042] The term "clamping" refers to a technique used to limit the voltage of a node in a circuit to a preset range. Specifically, it involves using feedback control to stabilize the output low level at a precise preset voltage V-pre (=VREF+ΔV) above zero potential, instead of pulling it directly to ground.

[0043] The term "VREF" refers to the Reference Voltage. It is a highly stable DC voltage generated by internal circuitry (such as a bandgap reference source) and serves as the voltage reference for the voltage detection circuit to determine whether an interrupt arbitration has occurred.

[0044] The term "V-pre" refers to a preset voltage, the value of which is VREF+ΔV (ΔV is a positive value, such as 10mV-200mV, which can be adjusted according to circuit design needs). It is a specific voltage value generated by the low-level clamping circuit inside the HUB to represent logic '0'. This voltage is higher than the ground level, thus distinguishing it in amplitude from the true low level (~0V) driven by the slave device.

[0045] This invention is applied in I3C networks and involves the following core components:

[0046] Master Side Port IO (MSP): A bidirectional IO port for connecting the I3C HUB to upstream hosts (such as CPUs, MCUs, and other control devices).

[0047] Slave Side Port IO (SSP): A bidirectional IO port for connecting an I2C hub to downstream slave devices (such as sensors, memory, and other controlled devices).

[0048] I3C Hub: As a repeater between a master and multiple slave devices, it forwards data correctly and efficiently between the master and multiple slave devices, and has intelligent data transmission direction judgment and switching capabilities.

[0049] This invention is applied to a typical I3C HUB communication system. Figure 1 This is a schematic diagram of the I3C HUB system applying the present invention, as shown below. Figure 1 As shown, the core of this system is an I3C HUB chip. Figure 1The chip's interconnectivity is clearly depicted: one side of the chip is the host-side port, connected to the upstream host via an I3C bus (including the SCL clock line and SDA data line); the other side of the chip has multiple slave-side ports, each slave-side port (SSP0, SSP1, SSPN) connected to a downstream slave (Slave 0, Slave 1, Slave N, where N is a positive integer) via an independent I3C bus. The core function of the HUB chip is to correctly and efficiently forward data between the host and multiple slaves. Since the I3C bus is half-duplex communication, each I / O is a bidirectional port, capable of both receiving and sending data. However, the SDA data line can only transmit data in one direction at a time. Therefore, the HUB must have intelligent data transmission direction judgment and switching capabilities, especially when handling interrupt arbitration initiated by slaves, requiring rapid and reliable switching of the data flow from "host to slave" to "slave to host". Figure 1 The system shown is the application carrier of the present invention, and the circuit provided by the present invention is built into each slave-side port of the HUB chip.

[0050] This invention discloses a circuit for implementing interrupt arbitration in an I3C hub chip. Its core lies in integrating an arbitration unit consisting of a low-level clamping circuit and a voltage detection circuit into each slave-side port (SSP). The low-level clamping circuit precisely clamps the low-level voltage output by the hub itself to a preset voltage V-pre above a reference voltage VREF, while the voltage detection circuit monitors the voltage on the SDA pin of the SSP in real time and compares it with the reference voltage VREF. The voltage detection circuit is preferably implemented using a comparator. When a slave initiates interrupt arbitration, it pulls the SDA line to a true low level below the reference voltage VREF. At this time, the comparator outputs a transition signal indicating that arbitration has occurred. This signal then controls the internal data path switch of the hub, automatically switching the data transmission direction from master to slave (MSP to SSP) to slave to master (SSP to MSP). This method does not rely on precise timing detection, thus reliably arbitrating all conflict situations, including simultaneous low-level outputs from both the master and slave, achieving efficient and reliable interrupt arbitration.

[0051] Figure 2 This is a schematic diagram of a circuit structure for implementing the interrupt arbitration function in one embodiment of the present invention, as shown below. Figure 2 As shown in the figure, this diagram illustrates a circuit applied to a slave-side port. The circuit mainly comprises several key components: a reference voltage generation circuit, a low-level clamping circuit, a voltage detection circuit, and a direction control logic circuit.

[0052] The reference voltage generation circuit is the foundation of the system. Its function is to generate an accurate and stable reference voltage VREF and a preset voltage V-pre (=VREF+ΔV). ΔV (ΔV is a positive value) is a preset value that has been determined during the circuit design. Its purpose is to ensure that the preset voltage V-pre is above the reference voltage VREF.

[0053] The core component of the low-level clamping circuit is an amplifier. The amplifier's inverting input is connected to the preset voltage V-pre, while its non-inverting input is directly connected to the SSP / SDA pin to monitor its real-time voltage. The amplifier's output is connected to and controls a pull-down driver transistor for the SSP / SDA pin. This forms a precise negative feedback loop. This circuit activates when the I3CHUB needs to send a logic low level "0" to the slave device. The amplifier continuously compares the voltage at the SSP / SDA pin with the preset voltage V-pre. If the SSP / SDA voltage is higher than the preset voltage V-pre, the amplifier increases the conduction of the pull-down driver transistor, pulling the pin voltage lower; conversely, it decreases it. Through this dynamic adjustment process, the output low level on the SSP / SDA pin is ultimately stabilized precisely at VREF + ΔV (= preset voltage V-pre). Therefore, the low-level clamping circuit ensures that any low level actively driven by the HUB is a clamped, known preset voltage V-pre that is higher than the true low level "0", thus creating a recognizable level indicator for subsequent arbitration. In summary, the core function of this low-level clamping circuit is to create a recognizable "pseudo-low level" controlled by the HUB, namely a preset voltage V-pre. This distinguishes it from the "real low level" (close to 0V) driven by the slave device in terms of voltage value.

[0054] The voltage detection circuit mainly consists of a comparator. One input (non-inverting input) of the comparator is connected to the SSP / SDA pin, and the other input (inverting input) is connected to the reference voltage VREF. The output node of the comparator (labeled as node 1 in the diagram) is the decision signal output of the entire arbitration circuit. The function of this voltage detection circuit is to determine in real time whether the voltage on the SSP / SDA pin is higher or lower than VREF. Its decision logic is as follows: as long as the SSP / SDA voltage is higher than the reference voltage VREF, node 1 outputs a logic high level "1" (indicating no arbitration); once the SSP / SDA voltage is lower than the reference voltage VREF, node 1 immediately toggles to a logic low level "0", indicating that an arbitration request has been detected.

[0055] The direction control logic circuit mainly consists of two inverters (a first inverter and a second inverter). It is responsible for receiving the decision signal from node 1 and controlling two critical data paths, path 1 and path 2. Path 1 represents the normal downlink data transmission path from MSPSDA to SSP SDA. The signal from node 1 passes through an inverter (the second inverter), and the output of the second inverter (labeled as node 3 in the diagram) is used to control the opening and closing of path 1 (e.g., ...). Figure 2 (Switch shown). The second inverter converts the arbitration decision result (node ​​1) into an enable signal for data path 1, ensuring that this signal is always opposite to the enable signal for path 2. Path 2 represents the interrupted uplink data transmission path from SSP SDA to MSP SDA. Its key execution component is an MSP SDA pull-down driver transistor. After the signal from node 1 passes through an inverter (first inverter), the output node of the first inverter (labeled as node 2 in the figure) controls the gate of the MSP SDA pull-down driver transistor, directly turning it on. The first inverter enhances the driving capability and shapes the waveform of the control signal generated by the preceding logic to ensure reliable driving of the MSP SDA pull-down driver transistor.

[0056] In one type of embodiment, both the SSP SDA pull-down drive transistor and the MSP SDA pull-down drive transistor are NMOS transistors, namely N-channel metal oxide semiconductors (NMOS).

[0057] During normal communication, i.e., when no slave device initiates an interrupt arbitration, the data transmission direction is from the master-side port to the slave-side port (MSP to SSP). At this time, all downstream slave devices' SDA I / O ports are in a high-impedance input state and do not actively drive the bus. The voltage levels on the SSP SDA pins are entirely controlled by the master through the HUB: when the master transmits a logic "1" to the slave, the pin voltage is VDD, i.e., the device operating voltage (Voltage Drain-to-Drain, VDD); when the master transmits a logic "0" to the slave, the low-level clamping circuit operates, adjusting the SSP SDA pull-down drive transistor through an amplifier, and precisely stabilizing the SSP SDA pin voltage at the preset voltage V-pre through a negative feedback mechanism. Therefore, during normal communication, only two voltage levels exist on the SSP SDA pin: VDD or V-Pre. Since both VDD and V-pre are higher than the reference voltage VREF, the comparator in the voltage detection circuit will remain in a high-level logic state, i.e., node 1 is at a logic high level "1", indicating no arbitration event. The high-level signal at node 1 directly affects two control paths: The high level at node 1 is transmitted to node 2 (the gate of the MSP SDA pull-down driver transistor) via the first inverter (which enhances the driving capability and shapes the waveform), turning off the MSP SDA pull-down driver transistor and thus cutting off path 2 (SSP to MSP), prohibiting uplink transmission. Simultaneously, the high level at node 1 is inverted by the second inverter, generating a logic low level "0" at node 3. This signal enables path 1 (MSP to SSP) to conduct. With path 1 on and path 2 off, the data signal on the master MSP SDA is losslessly copied to the SSP SDA bus via path 1 for downstream slave devices to receive.

[0058] When a slave device connected downstream of the SSP needs to initiate interrupt arbitration to the master, the slave device's internal pull-down transistor will be strongly turned on, actively pulling the SSP SDA line low to a "true low level" (close to 0V). This action forcibly pulls the voltage on the SSP SDA pin down from the previously possible high-level device operating voltage (VDD) or preset voltage V-pre to a voltage value lower than VREF. The comparator in the voltage detection circuit will immediately detect this voltage change. Since the SSP SDA voltage is lower than VREF at this time, the comparator output (node ​​1) will quickly flip to a low-level logic state, i.e., node 1 is a logic low level "0". This low-level signal is the valid interrupt arbitration detection flag. This flag signal (logic low level "0") triggers the direction switching control logic: First, the low level of node 1 causes the second inverter to output a high level. This high level will close the downlink transmission path (path 1), thereby isolating the MSP and preventing conflicts between the master driver and the slave driver. Secondly, the low level of node 1, through the first inverter (which enhances the driving capability and shapes the waveform of the high-level signal), turns on the pull-down drive transistor on the MSP SDA path, i.e., path 2 is turned on. At this time, the low-level signal applied by the slave to the SSP SDA is effectively transmitted to the MSP SDA through the turned-on path 2, and thus detected by the upstream host. Thus, the data transmission direction is intelligently and quickly switched from the slave-side port to the host-side port, successfully completing the interrupt arbitration response, and the slave can begin transmitting interrupt data to the host.

[0059] This invention, by introducing a mechanism combining voltage clamping and real-time voltage comparison, shifts the arbitration decision from the complex timing domain to the simple voltage domain. It is independent of any specific sampling time and can respond to interrupt requests occurring at any point within the clock cycle, fundamentally eliminating timing design challenges. Furthermore, since the decision criterion is based on an absolute comparison of voltage amplitudes, rather than simple level states, it can clearly distinguish between "clamped low level driven by the HUB" and "true low level driven by the slave," thus perfectly resolving the arbitration conflict problem when the master and slave simultaneously drive low levels, greatly improving the robustness and reliability of the I3C HUB system.

[0060] Furthermore, the voltage-sensing-based arbitration circuit described in this invention possesses excellent functional scalability, simultaneously implementing clock stretching and slave acknowledgment (SSP ACK) detection functions without requiring additional circuitry. Regarding the clock stretching function: when the slave needs more time to process data, it can pause the clock by pulling the SCL line low. This circuit can be reused on the SSP SCL pin, using a voltage detection circuit similar to that on the SDA pin to monitor the SSP SCL pin voltage in real time. When it detects that the slave has pulled SCL low below VREF, a control signal is immediately generated to notify the HUB's internal state machine. The HUB then actively pulls the SCL line on the MSP side low, transmitting the clock pause state to the master, thus achieving complete clock stretching protocol support. Regarding the slave acknowledgment (SSP ACK) detection function: during data transmission, the slave needs to pull SDA low as an acknowledgment signal within a specific clock cycle. Utilizing the existing voltage detection mechanism of this circuit, the HUB can monitor the SSP SDA voltage in real time within the clock cycle corresponding to the ACK bit. Once a voltage below VREF is detected, it is considered a valid ACK signal. This status can be recorded or reported via logic circuitry, thus reliably completing ACK bit detection and ensuring the integrity of data transmission. This multi-functional integrated design significantly improves the overall efficiency and cost-effectiveness of the circuit.

[0061] To better illustrate the present invention, numerous specific details have been provided in the detailed embodiments described above. Those skilled in the art should understand that the present invention can be practiced even without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of the present invention.

[0062] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A circuit for implementing interrupt arbitration function in an I3C HUB chip, characterized in that, The circuitry for implementing interrupt arbitration in the I3C HUB chip is integrated into each SSP of the HUB chip, including: A low-level clamping circuit is used to clamp the voltage of the SSP SDA pin to a preset voltage V-pre when the HUB chip outputs a low level as a host driver SSP SDA pin. A voltage detection circuit, connected to the SSP SDA pin, is used to detect the voltage on the SSP SDA pin in real time, compare it with the reference voltage VREF, and output an arbitration decision signal. The direction control logic circuit controls the switching of the data path direction in response to the arbitration decision signal; Specifically, when the voltage detection circuit detects that the voltage on the SSP SDA pin is lower than the reference voltage VREF, the arbitration decision signal indicates that the slave interrupt arbitration occurs, and the direction control logic circuit switches the data transmission direction from MSP to SSP to SSP to MSP; the preset voltage V-pre=VREF+ΔV, where ΔV is a positive value, to ensure that the preset voltage V-pre is greater than the reference voltage VREF.

2. The circuit for implementing interrupt arbitration function in an I3C HUB chip according to claim 1, characterized in that, The low-level clamping circuit includes: An amplifier, wherein the inverting input terminal of the amplifier is connected to the preset voltage V-pre, and the non-inverting input terminal of the amplifier is connected to the SSP SDA pin; The SSP SDA pull-down driver transistor is connected between the SSP SDA pin and ground, and the gate of the SSP SDA pull-down driver transistor is controlled by the output of the amplifier. The amplifier controls the SSP SDA pull-down drive transistor through negative feedback, so that the SSP SDA pin is stabilized at the preset voltage V-pre when the HUB drive is low.

3. The circuit for implementing interrupt arbitration function in an I3C HUB chip according to claim 1, characterized in that: The voltage detection circuit includes a comparator, the non-inverting input of which is connected to the SSP SDA pin, the inverting input of which is connected to the reference voltage VREF, and the output of which outputs the arbitration decision signal.

4. A circuit for implementing interrupt arbitration function in an I3C HUB chip according to claim 2, characterized in that, The direction control logic circuit includes: The first inverter receives the arbitration decision signal at its input terminal and its output terminal is used to control the MSP SDA pull-down drive transistor of the SSP to MSP data path. The second inverter has an enable terminal that receives the arbitration decision signal and an output terminal that controls the switching of the MSP to SSP data path. Specifically, when the arbitration decision signal is low, the MSP to SSP data path is closed, and the SSP to MSP data path is open.

5. A circuit for implementing interrupt arbitration function in an I3C HUB chip according to claim 4, characterized in that: The SSP SDA pull-down driver transistor and the MSP SDA pull-down driver transistor are NMOS transistors.

6. A circuit for implementing interrupt arbitration function in an I3C HUB chip according to claim 1, characterized in that: It includes a reference voltage generation circuit for generating the reference voltage VREF.

7. A circuit for implementing interrupt arbitration function in an I3C HUB chip according to claim 6, characterized in that: The reference voltage generating circuit also generates the preset voltage V-pre.

8. A circuit for implementing interrupt arbitration function in an I3C HUB chip according to claim 1, characterized in that, The circuit that implements the interrupt arbitration function in the I3C HUB chip is also reused to implement at least one of the following functions: Clock extension function: The same voltage detection circuit is set on the SSP and SCL pins. When the SCL voltage is detected to be lower than the reference voltage VREF, a clock pause control signal is generated. Slave acknowledgment detection function: During the clock cycle corresponding to the ACK bit, it detects whether the SSP SDA voltage is lower than the reference voltage VREF to determine the validity of the ACK signal.

9. An I3C HUB chip, characterized in that: The circuit includes the interrupt arbitration function implemented in the I3C HUB chip as described in any one of claims 1 to 8.

10. An electronic device, characterized in that: It includes the I3C HUB chip as described in claim 9.

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