Integrated circuit

Abstract

According to one embodiment, an integrated circuit is described having a plurality of system components, the plurality of system components having a plurality of master units and a plurality of slave units, each slave unit being designed to communicate to the slave unit from a predefined set of identifications depending on the master unit, to enable each of the plurality of master units to access one or more functions of the slave unit; a writable configuration memory, the configuration memory storing, for each master unit and each identifier in an identifier set: when the master unit wishes to access the slave unit, whether the master unit allows communication of an identifier to the slave unit; and an identification control device which is designed to limit, for each master unit for each access of the master unit to any slave unit, an identification which is communicated by the master unit for the access to the respective slave unit to the following identification, a memory is configured to store the identification: the master unit allows communication of the identification to a slave unit.

Description

TECHNICAL FIELD

[0001] Embodiments relate generally to integrated circuits. BACKGROUND

[0002] The increasing complexity and integration of data processing devices leads to the need for logical partitioning of the respective implementation system and the separation or isolation of resources from each other. An example for this is the integration of various applications with different integrity levels in one system (e.g. a SoC (System on Chip)) which leads to the necessity to regulate access to different resources, e.g. memory areas, in order to, for example, prevent less trustworthy programs, i.e. for example unsecure processors, from accessing security critical data such as encryption keys. Therefore, an efficient and effective mechanism is desired to regulate access of a processor (typically a master unit) to other system components (typically slave units) of an integrated circuit. SUMMARY

[0003] According to one embodiment, an integrated circuit is provided having a plurality of system components, wherein the plurality of system components has a plurality of master units and a plurality of slave units, wherein each slave unit is designed to enable access of each master unit of the plurality of master units to one or more functions of the slave unit depending on which identity from a predetermined set of identities is communicated by the master unit to the slave unit, a writable configuration memory storing for each master unit and each identity of the set of identities whether the master unit is allowed to communicate the identity to the slave unit when the master unit wants to access the slave unit, and an identity control means designed to limit, for each access of a master unit to any slave unit, the identity communicated by the master unit to the respective slave unit for the access to the identities for which the configuration memory stores that the master unit is allowed to communicate the identity to the slave unit. BRIEF DESCRIPTION OF DRAWINGS

[0004] The drawings are not to scale and are merely intended for illustrative purposes. The individual embodiments are described below with reference to the following drawings.

[0005] Figure 1 An integrated circuit according to one embodiment is shown.

[0006] Figure 2 Access of a processor to a system component is illustrated.

[0007] Figure 3 A configuration memory according to one embodiment is illustrated.

[0008] Figure 4 Definition of allowed identities of a processor for different operating modes is illustrated. DETAILED DESCRIPTION

[0009] The following detailed description refers to the accompanying drawings that show details and embodiments. The embodiments are described in detail so that one skilled in the art can carry out the application. Other embodiments are feasible and can vary in structure, logic and electricity without departing from the subject matter of the application. The various embodiments are not necessarily mutually exclusive, but different embodiments can be combined with each other, so that new embodiments are created. In the scope of this description, the terms "connected", "coupled" and "linked" are used to describe direct and indirect connections, direct or indirect couplings and direct or indirect links.

[0010] Figure 1 An integrated circuit 100 according to one embodiment is shown.

[0011] The integrated circuit 100, e.g. a microcontroller, forms e.g. a system on a chip (SoC) in a vehicle, for example.

[0012] The integrated circuit has a plurality of processors (CPUs, central processing units) 101, e.g. RISC-V-CPUs, and a plurality of other system components 102, 103, such as memories 102 and peripheral components 103, which the processors can access. Correspondingly, the processors 101 can be regarded as master components and the other system components 102, 103 can be regarded as examples of slave units. Likewise, the processors can be regarded as examples of master units. The master units can also be DMA controllers, HARTs (hardware threads), virtual processors (virtual machines) or other components accessing other components, for example.

[0013] The processors 101 can execute various programs. The programs can have different integrity levels (i.e. they can be trusted to different degrees) and the programs can have different security requirements, i.e. different criticalities, which stem from e.g. the respective industrial environment in which the security requirements are used, such as ASIL (Automotive Safety Integrity Level), CAL (Common Criteria Assurance Level), EAL (Evaluation Assurance Level), SIL (Safety Integrity Level) or the like. The processors themselves can also have different trust levels (or integrity levels). For example, one processor is a processor of an HSM (hardware security module), which is very trustworthy (e.g. a hardware root of trust), and another processor is a co-processor (e.g. a GPU (graphics processing unit)), which is less trustworthy. The trust levels can also be different for the same mode of operation. For example, two processors 101 can have different trust levels, even if they are both in M-mode (machine mode).

[0014] Thus, the processor 101 itself or also due to the software it implements has different trust levels and thus also different permissions. For example, a processor 101 that should only have a high trust level can access a first memory area 104 of the memory 102 that stores safety-critical data, while a processor with a low trust level is also allowed to access a second memory area 105 that does not store safety-critical data. The same applies to peripheral components, such as a memory interface to off-chip memory, a network interface, an interface to actuators (for example in a vehicle), etc.

[0015] To achieve this, a mechanism is required to filter the access of master components (processors 101) to slave components (memory 102 and peripherals 103), i.e. for example, to prevent master components with a low integrity level from accessing safety-critical resources (for example memory areas). Here, in the case of a large number of master components (for example a chip with 32 processors), it should also be possible to group processors with the same integrity level in order to keep the number of different access permissions as low as possible and thus keep the number of bits required to specify them (and thus ultimately the chip area required to implement such a mechanism) as low as possible.

[0016] To provide such a mechanism, according to various embodiments, a configuration memory 106 is provided. The configuration memory determines which identification is allowed to be used by a processor (typically a master) 101 in an access message (i.e. a message for accessing other system components (typically slaves) 102, 103). This is explained below with reference to Figure 2 .

[0017] Figure 2 An access of a processor 201 (which for example corresponds to one of the processors 101) to a system component 202 (which for example corresponds to one of the other system components 102, 103) is illustrated.

[0018] To access the system component 202, the processor 201 sends an access message 203 to the system component 202 via a connection 205 (for example a bus).

[0019] The access message 203 contains a specification 206 of the access (for example a read access to a specific memory address) and contains an identification 207 from a set of pre-defined (total) identifications, i.e. the processor 201 inserts one of the identifications from this set of identifications into the access message 203.

[0020] The system component 202 comprises an access rights memory 208 from the content of which (e.g. an access rights table) it is known for each of the identities from the set of identities which access rights are associated with the identity. For example, the system component 202 is a memory having a first memory area 209 and a second memory area 210 and identifies itself by means of the identity WID0 (WID stands for "world identity", i.e. an identity of a "world" or access area to which the respective processor belongs or in which the processor runs) and WID1 (i.e. it is sent as an identity 207 in the respective access message 203) as having access rights to the first memory area 209 and the second memory area 210, whereas by means of the identities WID2, WID3 and WID4 it identifies itself as having access rights only to the second memory area 210 (i.e. in this case the system component 202 only allows access to the second memory area 210, i.e. access to the first memory area 209 which is specified in the respective access message 203 but contains WID2, WID3 or WID4 as an identity is not performed). In general, the memory areas 209, 210 correspond to specific functions, e.g. communication with a specific component in the case of the system component 202 being an interface, etc.

[0021] Each function (e.g. each memory area, i.e. access to the respective memory area) belongs to a specific "world", i.e. in other words, an access area, and each of the access areas corresponds to a respective identity of the set of predetermined identities (one-to-one correspondence, i.e. exactly one identity of the set of predetermined identities is associated with each access area and different identities are associated with different access areas, wherein the access areas can of course overlap or even one access area can contain other access areas). In particular, an access area defines a set of functions which belong to the same access rights class. For example, the first memory area 209 and the second memory area 210 belong to the access area of WID0, whereas the access area of WID2 contains only the second memory area 210. As mentioned above, the content of the access rights memory 208 defines to which access area a specific function of the system component 202 belongs.

[0022] In order to prevent the processor 201 from easily using an identity 207 which is associated with an access right which the processor 201 is not allowed to have by means of the content of the access rights memory 208 (e.g. an access rights table), there is an identity control device 211 (e.g. a corresponding hardware circuit) which restricts which identities the processor 201 is allowed to insert as an identity 207 into an access message 203, i.e. which set of identities the processor 201 is allowed to select from. The set of identities which the processor 201 is allowed to is a (possibly real) subset of the set of predetermined identities.

[0023] The set of identities allowed for the processor 201 is defined in the configuration memory 204 in the configuration memory 106 (204), which is designed, for example, as follows. Figure 2

[0024] Figure 3 The configuration memory 300 according to one embodiment is illustrated.

[0025] In the example, the configuration memory 300 has a matrix form: in the first configuration memory area 301, the configuration memory has one row for each security area (here W0 to W31) and one column for each processor. Each entry (for example, stored by a storage cell, such as a corresponding flip-flop) determines whether the corresponding processor is allowed to use the identities associated with the corresponding security area (i.e. the corresponding "world") (for example, by an entry equal to 1), i.e. to use as identities 207 in the access message 203, or not (for example, by an entry equal to 0). If the processor is not allowed to use the identity 207, the identity control device 211 prevents the processor from using the identity. This matrix (or each row thereof) can be considered as a mask of identities, in which the identities from the total set of identities are masked for each processor (for example, by zeros in the matrix) and the processor is only allowed to use the remaining identities.

[0026] Thus, the configuration memory 300 contains, for each access area, a register (as a row) defining which processor has access rights to this access area (as the processor is allowed to use the corresponding identities if necessary). In other words, the configuration memory 300 contains, for each processor, a register (as a column) defining which access areas this processor has access rights to.

[0027] In the example, the configuration memory 300 contains, in the second configuration memory area 302, for each row, the identity of the "owner" (here the OID of the "owner ID") of the corresponding security area. It can also be proposed that the owner of a row configures the row first and then the owner switches. Thus, the current owner always allows the configuration of the row (including the OID).

[0028] ​For example, the configuration memory 300 also contains a third storage area 303 which, for each processor, states the identity of the processor which is to use the identity in accessing messages in its highest privilege level (e.g. M-mode). The ID of the M-mode of the respective processor is for example assigned by a root software (which can run on the same processor or on another processor in the system). The reason for providing the third storage area 303 is that the ID of the M-mode of the processor should be preset "from the outside" by the root software. In the usual case, the root software is the software of another processor which determines the ID of the M-mode before the corresponding processor is started. In the special case of a boot processor (i.e. a root of trust), the ID can be determined by a reset value. It is thus excluded that the processor itself finds out its ID of the M-mode. Furthermore, the ID of the M-mode is limited to the IDs marked in the column of the storage area 301 as the IDs allowed for use by the master.

[0029] Which identity is allowed to configure the ID of the M-mode of the processor, i.e. the owner identity (OID) of the third storage area 303, is for example stored in a fourth configuration storage area 304 in the form of an association of each column OID with the identity of the respective processor (here hart0 to hart7 or H0 to H7). This is related to the write access to the configuration storage areas 303 and 304 (which identities have the right to write access to the configuration storage areas 301 and 302 is regulated by the second configuration storage area 302). In other words: The fourth configuration storage area 304 regulates who is allowed to write into the third configuration storage area 303 (i.e. which identity has to be used to write into the third configuration storage area 303), and the content of the first configuration storage area 301 (according to the column) regulates what is allowed to write into the third configuration storage area 303.

[0030] For example, the content of the configuration memory 300 is written (e.g. by one or more of the processors 101) each time the integrated circuit 100 is started (booted), and then remains static (i.e. "locked") during the run of the integrated circuit 100 (until the next boot). However, it is also possible to provide the possibility of dynamic reconfiguration. Thus, for example, a "1" can be added in the matrix at any time (i.e. the "world" can be extended to involve other processors as needed), and a "1" can also be removed, for example by the owner of the respective row. A row can be "locked" by setting the owner of the corresponding WID to an owner which does not exist in the system.

[0031] For example, the writing proceeds in a specific order (according to priority) of the processors 101, e.g. the HSM starts the writing, then by a relatively trustworthy processor, then by a less trustworthy processor, etc. Here, the processors are not allowed to change the configuration performed by the preceding processor in this order (i.e. to write in the configuration memory 300). It can also be feasible that the "root authority", e.g. the HSM, writes completely in the configuration memory 300.

[0032] The processor 101 can also implement one or more virtual processors. It can then be proposed that the allowed identities are not defined for each virtual processor, but that the allowed identities of a processor (e.g. by a virtual machine manager) are distributed among the virtual processors implemented by this processor.

[0033] The identities allowed for use by the processor 101 can also be defined for each operating mode, as Figure 4 is explained in the.

[0034] Figure 4 The definition of the allowed identities of the processor for different operating modes is explained.

[0035] For example, the processor 101 uses the identity "rlwid" in M mode, "mlwid" in S mode, and "slwid" in U mode, where the name is derived from the operating mode in which the identity is determined (by the processor having the respective mode): "rlwid" in root mode, "mlwid" in M mode, and "slwid" in S mode.

[0036] For example, a virtualizable processor (which can implement multiple virtual processors (or virtual machines)) has H mode, VS mode and VU mode instead of S mode and U mode, and correspondingly identities for this: "mlwid" for H (virtual machine manager) mode (determined by the processor in M mode), "hlwid" for VS mode (determined by the processor in H mode), and "vslwid" for VU mode (determined by the processor in VS mode).

[0037] According to various embodiments, thus, in each mode (integrity level) one or more available identities are assigned for the next lower level. The identities of M mode and the mask (rwiddeleg) for the lower trust levels are determined in the configuration memory 300. It is also possible to define additional masks (mwiddeleg in ) for the following lower trust levels, which further restrict the identities available for use by these levels. Figure 4

[0038] ​For example, the processor stores the identities it uses (i.e. selects) in the various runlevels in local (i.e. internal to the processor) registers 401, i.e. one register stores "mlwid", another register stores "slwid", etc., wherein "rlwid" is only stored in the configuration memory, as referred to above. Figure 3 The identities are described (in Figure 4 external to the processor 402, i.e. descriptively on system (e.g. SoC) level, not on master unit level).

[0039] The control means 211 control that the identities determined for the various runlevels are located within the (sub-)set of identities the processor is allowed to use, i.e. the possible or allowed identities, e.g. as defined in the configuration memory 106, 204, or at least control that the processor does not use any identity that is not allowed to be used as identity 207 in the access message 203.

[0040] According to one embodiment, the respective (sub-)set of identities the processor is allowed to use is forwarded from a mode of higher integrity level to a mode of lower integrity level, i.e. downward delegation, according to the different runlevels, wherein e.g. the identities are more and more restricted (as Figure 4 as illustrated in Fig. 3 by means of the mask mwiddeleg, which further restricts the externally preset mask rwiddeleg).

[0041] If no delegation mechanism is provided, the configuration memory 300 can in one embodiment also separately specify for the various runlevels and / or virtual processor (virtual machine) the respective (sub-)set of identities the processor is allowed to use. In Figure 3 the example of Fig. 3, a first configuration memory area 301 of the configuration memory 300 specifies e.g. the following identities: the respective processor is allowed to select from said identities for the S mode and the U mode (or in case of a virtualizable processor for the H, VS, VU mode). For the other runlevels, the configuration memory 300 then has e.g. other versions of the first configuration memory area 301: • another version, which specifies the following identities: the processor is allowed to select from said identities for the U mode (or in case of a virtualizable processor for the VS, VU mode), • another version, which specifies the following identities: the virtualizable processor is allowed to select from said identities for the U mode.

[0042] As already mentioned above, the trust level of the individual processors 101 is derived, for example, from which software the processor executes (as the software has different trust levels). Thus, the separation of the processors 101 with respect to their access rights also corresponds to a logical separation of different software components. According to various embodiments it is proposed that here the trustworthy processors (or trustworthy software components) can limit the access rights of less trustworthy processors (or less trustworthy software components), for example, by first starting a trustworthy program by the processor, which program is written at least partially into the configuration memory 106 and determines, for example, that only the program (or in one or more equally trustworthy processors) has a certain access right (for example, to a protected memory area). Subsequently started software components can then also write into the configuration memory 106 if necessary, but cannot circumvent the limitation. This enables, for example, a flexible and still secure start-up procedure, in which software components are loaded one after the other (for example, when needed) and their access rights can be configured, and here, in particular, the access rights of later started software components can be limited.

[0043] According to various embodiments, the access rights are defined globally in the sense that the configuration memory (which is external with respect to the processors) provides an identification (and thus the access rights thereof) which can be used by the processors.

[0044] In summary, according to various embodiments, an integrated circuit (see Figure 1 and Figure 2 ) is provided, which has • a plurality of system components, wherein the plurality of system components has a plurality of master units (DMA controllers, processors, virtual machines, HARTs, etc.) and a plurality of slave units (peripheral components or memories), wherein each slave unit is designed to implement an access of each of the plurality of master units to one or more functions of the slave unit depending on which identification from a preset (global, i.e., known to all system components) identification set is communicated to the slave unit by the (correspondingly accessing) master unit, • a writable configuration memory, which stores for each master unit and each identification of the identification set whether the master unit is allowed to communicate the identification to the slave unit when the master unit wishes to access the slave unit, and • an identification control device, which is designed to limit, for each access of a master unit to any slave unit by the master unit, the identification communicated to the respective slave unit by the master unit for the access to the identification for which the configuration memory stores that the master unit is allowed to communicate the identification to the slave unit (i.e., the identification control device masks, for example, the not allowed identifications).

[0045] According to various embodiments, a circuit block is provided in an integrated circuit, which stores for all identities of a global identity set which of a plurality of master units (e.g. the processors in the above described embodiments) are allowed to use the identity, wherein one access region is associated with each identity, i.e. one or more access rights are associated with each other access component.

[0046] The configuration memory is for example a central memory of the integrated circuit. In particular, the configuration memory is for example not a distributed memory, which for example expresses that the configuration memory is formed by storage cells of a contiguous memory address set. The configuration memory stores access rights collectively for the plurality of master units as described above, i.e. if a master unit wants to access a slave unit, whether the master unit is allowed to communicate the respective identity to the slave unit. The configuration memory stores the access rights system-wide, i.e. for all of the plurality of master units. According to various embodiments, the configuration memory is located outside and on a higher level than the master units, i.e. defines the "greatest" access rights for the master units (i.e. the identities the master units can choose from). The configuration memory stores the allowed identities per world ID (i.e. separated according to world ID), for example as described above.

[0047] The integrated circuit can have more master units than "plurality of master units" (for which the configuration memory stores access rights in the above described manner).

[0048] As described above, the configuration memory can have the form of a matrix, wherein from a software perspective the registers are the rows and each row has a separate owner, but the rwiddeleg registers related to the master units (e.g. CPUs) are the columns, i.e. one rwiddeleg consists of n (here for example 32) bits from different registers with (possibly) different owners. This enables the incremental roll-out, which would not be feasible if each rwiddeleg register had one owner. From a software perspective (as well as from an owner assignment perspective), the memory elements in the matrix are arranged in rows (one row per identity), but the hardware (i.e. the interface of the identity control means) extracts the information about the allowed identities applicable to a master unit column-wise. Here, it is a conversion from a logical perspective to a physical perspective, and finally the conversion enables the incremental roll-out, i.e. the owner of the first identity WID1 can at a first point in time unalterably determine which master unit is allowed to use the first identity WID1, and the owner of the second identity WID2 can at a second point in time unalterably determine which master unit is allowed to use the second identity WID2.

[0049] When writing into the configuration memory according to a predetermined order of the master units, it can be possible that 1. For each identification, the configuration memory is permanently determined for all processors, i.e. the writing can be permanent for each start of the integrated circuit (static case) or 2. For a single or all identifications, the configuration memory is initially filled and changed in runtime in coordination (dynamic case).

[0050] Various embodiments are explained below.

[0051] Embodiment 1 is an integrated circuit having: a plurality of system components, wherein the plurality of system components has a plurality of master units and a plurality of slave units, wherein each slave unit is designed to enable access of one or more functions of the slave unit by each master unit of the plurality of master units depending on which identification from a set of preset identifications is communicated by the master unit to the slave unit; a writable configuration memory storing for each master unit and each identification of the set of identifications whether the master unit is allowed to communicate the identification to the slave unit when the master unit wants to access the slave unit; and identification control means designed to limit, for each master unit for each access of the master unit to any slave unit, the identification communicated by the master unit for the access to the respective slave unit to the identifications for which the configuration memory stores that the master unit is allowed to communicate the identification to the slave unit.

[0052] Embodiment 2 is the integrated circuit according to embodiment 1, wherein the plurality of slave units has at least one memory and / or at least one peripheral component.

[0053] Embodiment 3 is the integrated circuit according to embodiment 1 or 2, wherein at least one of the plurality of slave units is a memory having a plurality of memory areas and one or more functions of the memory have a memory access, the memory enabling the access to the one or more functions depending on which identification from the set of identifications is communicated to the memory by the respective master unit making the access, wherein each memory access is an access to a respective memory area of the plurality of memory areas.

[0054] Embodiment 4 is the integrated circuit according to any of embodiments 1 to 3, wherein the master unit communicates the identification from the set of identifications to the slave unit in an access message.

[0055] Embodiment 5 is the integrated circuit according to any of embodiments 1 to 4, wherein for each slave unit, the slave unit enables the identification according to which the master unit accesses one of the functions of the slave unit is the identification inserted by the master unit into an access message sent by the master unit to the slave unit.

[0056] Embodiment 6 is the integrated circuit according to embodiment 5, wherein the master unit specifies the access in the access message.

[0057] Example 7 is the integrated circuit of any of examples 1 to 6, wherein each slave cell has an access rights memory in which for each of one or more functions of the slave cell it stores which of the one or more identities that any master cell communicates to the slave cell enables the slave cell to access the function.

[0058] Example 8 is the integrated circuit of any of examples 1 to 7, wherein the configuration memory has a matrix of memory elements, wherein each memory element is associated with a respective pair of one of the master cells and one of the identities of the set of identities, and stores whether the master cell of the pair is allowed to communicate the identity of the pair to one of the slave cells when the master cell of the pair wishes to access the slave cell.

[0059] Example 9 is the integrated circuit of any of examples 1 to 8, wherein the configuration memory is external to the plurality of master cells.

[0060] Example 10 is the integrated circuit of any of examples 1 to 9, wherein at least one of the master cells is designed to write in the configuration memory for at least a portion of the master cells and at least a portion of the set of identities in the configuration memory whether the master cell is allowed to communicate the identity to the slave cell if the master cell wishes to access the slave cell.

[0061] Example 11 is the integrated circuit of example 10, wherein the at least one master cell is a hardware security module and / or a hardware root of trust.

[0062] Example 12 is the integrated circuit of any of examples 1 to 9, wherein a plurality of the master cells are designed to write in the configuration memory in turn for at least a respective portion of the master cells and at least a respective portion of the set of identities in the configuration memory respectively according to a predetermined order whether the master cell is allowed to communicate the identity to the slave cell if the master cell wishes to access the slave cell.

[0063] Example 13 is the integrated circuit of example 12, wherein the order is an order in which the master cells take their run when the integrated circuit is started.

[0064] Example 14 is the integrated circuit of any of examples 1 to 13, wherein for each identity of the set of identities at least one of the identities is determined to be an owner of the identity, and only one of the master cells that is allowed to use the at least one identity is allowed to write in the configuration memory an entry that specifies which of the master cells are allowed to communicate the identities of the set of identities to the slave cell.

[0065] Embodiment 15 is the integrated circuit according to any one of Embodiments 1 to 14, wherein the configuration memory stores for each master unit and for each identification in the identification set: whether the master unit allows the identification to be communicated to a slave unit when the master unit wishes to access the slave unit, for each operating mode of a plurality of operating modes of the master unit, and the identification control means are designed to limit, for each master unit and for each operating mode of the master unit, for each access of any slave unit in the operating mode by the master unit, the identification communicated by the master unit for the access to the respective slave unit to the identification for which the configuration memory stores that the master unit allows the identification to be communicated to the slave unit in the operating mode.

[0066] While the application has been illustrated and described in detail in the drawings and foregoing description, the same is to be considered as illustrative and not restrictive in character, since the application includes all modifications in the spirit and scope of the application as defined by the following claims.

[0067] List of reference signs 100 integrated circuit 101 processor 102 memory 103 peripheral components 104, 105 storage areas 106 configuration memory 201 processor 202 system components 203 access message 204 configuration memory 205 connection 206 access specification 207 identification 208 access rights memory 209, 210 storage areas 211 identification control means 300 configuration memory 301-304 configuration storage areas 401 internal processor register 402 processor external register

Claims

1. An integrated circuit having: Multiple system components, wherein the multiple system components have multiple master units and multiple slave units, wherein each slave unit is designed to: communicate with the slave unit from a preset set of identifiers according to which identifier is communicated from the master unit to the slave unit, so as to enable each of the multiple master units to access one or more functions of the slave unit; A writable configuration memory stores for each of the master units and each of the identifiers in the identifier set whether the master unit allows the identifier to be communicated to the slave unit when it wishes to access the slave unit; and An identifier control device is designed to: for each master unit to access any of the slave units for each access by the master unit, restrict the identifier communicated by the master unit to the corresponding slave unit for the access to an identifier as follows, wherein the configuration memory stores the identifier for which the master unit allows the master unit to communicate the identifier to the slave unit.

2. The integrated circuit of claim 1, wherein the plurality of slave units have at least one memory and / or at least one peripheral component.

3. The integrated circuit according to claim 1 or 2, wherein at least one of the plurality of slave units is a memory having a plurality of storage regions and one or more functions of the memory having memory access, wherein the memory communicates to the memory, according to the master unit performing the access, which identifier from the identifier set to enable access to the one or more functions, wherein each memory access is an access to a corresponding storage region of the plurality of storage regions.

4. The integrated circuit according to any one of claims 1 to 3, wherein the master unit communicates the identifier from the identifier set to the slave unit in an access message.

5. The integrated circuit according to any one of claims 1 to 4, wherein for each slave unit, one of the identifiers on which the slave unit implements the function of the master unit accessing the slave unit is an identifier inserted by the master unit into an access message sent to the slave unit.

6. The integrated circuit of claim 5, wherein the main unit details the access in the access message.

7. The integrated circuit according to any one of claims 1 to 6, wherein each slave unit has an access permission memory, wherein the access permission memory stores for each of the one or more functions of the slave unit: for any one or more identifiers communicated by the master unit to the slave unit, the slave unit implements access to the function for the master unit.

8. The integrated circuit according to any one of claims 1 to 7, wherein the configuration memory has a matrix of memory elements, wherein each memory element is associated with a corresponding pair consisting of one of the master cells and one of the identifiers in the identifier set, and stores whether the master cell of the pair allows the identifier of the pair to be communicated to the slave cell when the master cell of the pair wishes to access one of the slave cells.

9. The integrated circuit according to any one of claims 1 to 8, wherein the configuration memory is located outside the plurality of main units.

10. The integrated circuit according to any one of claims 1 to 9, wherein at least one of the master cells is designed to: write in the configuration memory, for at least a portion of the master cell and at least a portion of the identifier set in the configuration memory, whether the master cell allows the identifier to be communicated to the slave cell if the master cell wishes to access the slave cell.

11. The integrated circuit of claim 10, wherein the at least one main unit is a hardware security module and / or a hardware root of trust.

12. The integrated circuit according to any one of claims 1 to 9, wherein a plurality of the master units are designed to: sequentially write, in a preset order, at least one corresponding portion of the master unit and at least one corresponding portion of the identifier set in the configuration memory respectively: whether the master unit allows the identifier to be communicated to the slave unit if the master unit wishes to access the slave unit.

13. The integrated circuit of claim 12, wherein the order is the sequence in which the main unit operates when the integrated circuit is started.

14. The integrated circuit according to any one of claims 1 to 13, wherein for each identifier in the identifier set, at least one of the identifiers is identified as the owner of the identifier, and only one of the master units that is allowed to use at least one identifier is allowed to write an entry in the configuration memory, the entry indicating which of the master units is allowed to communicate the identifier of the identifier set to the slave unit.

15. The integrated circuit according to any one of claims 1 to 14, wherein the configuration memory stores for each of the master units and for each of the identifiers in the identifier set: whether the master unit allows the identifier to be communicated to the slave unit when the master unit wishes to access the slave unit, stores for each of a plurality of operating modes of the master unit, and the identifier control unit is designed to: for each master unit and for each operating mode of the master unit, for each access of the master unit to any of the slave units in the operating mode, restrict the identifier communicated by the master unit to the corresponding slave unit for access to an identifier such that the configuration memory stores for the identifier that the master unit allows the identifier to be communicated to the slave unit in the operating mode.

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