Common voltage output circuit and display device

Abstract

The application provides a common voltage output circuit and a display device. The common voltage output circuit comprises a driving chip, a load adjusting circuit, a comparison circuit and a load control circuit. When the driving chip obtains initial data of a common electrode through communication, the driving chip generates an initial common electrode voltage. The comparison circuit compares the initial common electrode voltage with a threshold voltage and generates a comparison signal when the initial common electrode voltage exceeds the threshold voltage. The load control circuit generates a load adjusting signal according to the comparison signal. The load adjusting circuit reduces the voltage at the common electrode end from a first current to a second current according to the load adjusting signal, thereby reducing the output current of the driving chip and reducing the load output of a power management integrated circuit. The power management integrated circuit does not appear to be powered off at low voltage, thereby avoiding the black screen phenomenon of the display panel and improving the display reliability during the burning test or the driving power-on.

Description

Technical Field

[0001] This invention belongs to the field of display panel technology, and particularly relates to a common voltage output circuit and display device. Background Technology

[0002] The display panel may include an array substrate, an opposing substrate, and a liquid crystal layer disposed between the array substrate and the opposing substrate. The array substrate and the opposing substrate may each be provided with a corresponding common electrode layer. The common electrode layer receives a common electrode voltage, and the pixel electrodes on the array substrate receive data signals. The data signals and the common electrode voltage form a driving voltage, which drives the liquid crystal to deflect, thereby displaying the corresponding image information.

[0003] When the display panel is installed into the corresponding electronic product, the factory will use a fixture or programming module to program the common electrode voltage, so as to output the corresponding common electrode voltage to the common electrode, and test the display effect of the display panel to ensure that the display panel achieves the best picture quality.

[0004] However, during the programming or driver power-on process, the display panel exhibits a black screen. The specific reason is that the driver chip's default value is too low, for example, 0.08V. When debugging and lighting up the display panel, if... Figure 1 and Figure 2 As shown, the driver chip is supplied with the operating voltage AVEE by the power management integrated circuit. The driver chip outputs an initial common electrode voltage, such as 1.6V, based on the received data. If the voltage difference between the initial common electrode voltage and the default value is too large, the driver chip will detect the switching between the two voltages and need to perform a short-term rapid charge on the voltage regulator capacitor at the common electrode terminal of the display panel to quickly bring its terminal voltage to the initial common electrode voltage. At this time, the output current IAVEE of the driver chip generates a large current, the load output of the power management integrated circuit increases, and the supply voltage VIN of the power management integrated circuit drops briefly, causing the power management integrated circuit to stop working at low voltage, which in turn causes the power supply to the display panel to be cut off, resulting in a black screen on the display panel. Summary of the Invention

[0005] The purpose of this invention is to provide a common voltage output circuit, which aims to solve the problem of excessive voltage across the screen causing a black screen when a traditional display panel is initially powered on.

[0006] A first aspect of this invention provides a common voltage output circuit connected to a display panel, wherein the display panel has a common terminal and a voltage-regulating capacitor is connected to the common terminal, and the common voltage output circuit includes:

[0007] A driver chip is connected to a power management integrated circuit. The driver chip is used to communicate with a programming module or a control module to obtain initial data of the common electrode, and to generate an initial common electrode voltage and output a first current to the common electrode terminal based on the initial data of the common electrode.

[0008] A load adjustment circuit is connected to the display panel. The load adjustment circuit is used to reduce the input current of the common terminal from the first current to the second current according to the load adjustment signal.

[0009] A comparison circuit, connected to the driver chip, is used to compare the initial common electrode voltage with a threshold voltage, and output a comparison signal when the initial common electrode voltage exceeds the threshold voltage.

[0010] A load control circuit is connected to both the comparison circuit and the load adjustment circuit. The load control circuit is used to output the load adjustment signal based on the comparison signal.

[0011] Optionally, the load regulation circuit includes:

[0012] A current adjustment circuit is connected in series between the driver chip and the common terminal. The current adjustment circuit is used to adjust its own impedance from a first impedance to a second impedance according to the load adjustment signal, wherein the second impedance is greater than the first impedance.

[0013] Optionally, the current adjustment circuit includes a variable resistor, a first capacitor, a second capacitor, and an operational amplifier;

[0014] The first end of the variable resistor, the first end of the first capacitor, and the positive power supply terminal of the operational amplifier are connected. The second end of the variable resistor, the second end of the second capacitor, and the negative power supply terminal of the operational amplifier are connected. The control terminal of the variable resistor is connected to the signal terminal of the load adjustment circuit. The central axis of the variable resistor, the output terminal of the driver chip, and the non-inverting input terminal of the operational amplifier are connected. The inverting input terminal and the output terminal of the operational amplifier are connected to form the output terminal of the current adjustment circuit. The second ends of the first capacitor and the second ends of the second capacitor are grounded.

[0015] Optionally, the load regulation circuit further includes:

[0016] A delay circuit is connected between the current adjustment circuit and the common terminal. The delay circuit is used to receive the current signal output by the current adjustment circuit and output it to the common terminal after a delay.

[0017] Optionally, the delay circuit includes a first resistor and a third capacitor;

[0018] The first end of the first resistor constitutes the input terminal of the delay circuit, the second end of the first resistor and the first end of the third capacitor are connected to constitute the output terminal of the delay circuit, and the second end of the third capacitor is grounded.

[0019] Optionally, the comparator circuit includes a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, a first comparator, a second comparator, a first diode, and a second diode;

[0020] The first end of the second resistor is grounded. The second end of the second resistor, the first end of the third resistor, and the inverting input of the first comparator are connected. The second end of the third resistor is used to input the first reference voltage. The non-inverting input of the first comparator, the inverting input of the second comparator, and the output of the driver chip are connected. The first end of the fourth resistor is used to input the second reference voltage. The second end of the fourth resistor, the first end of the fifth resistor, and the non-inverting input of the second comparator are connected. The second end of the fifth resistor is grounded. The outputs of the first comparator, the second comparator, the first end of the sixth resistor, and the first end of the seventh resistor are connected. The second end of the sixth resistor, the cathode of the first diode, and the positive voltage terminal are connected. The second end of the seventh resistor, the cathode of the second diode, and the anode of the first diode constitute the output of the comparator circuit. The anode of the second diode is grounded. The first reference voltage is less than the second reference voltage.

[0021] Optionally, the load adjustment circuit is a sleep control circuit, which is connected to the display panel and the driving circuit that drives the display panel to display. The sleep control circuit is used to control the display panel and the driving circuit to enter a sleep state according to the sleep enable signal.

[0022] The load control circuit includes:

[0023] A sleep enable circuit is connected to the sleep control circuit. The sleep enable circuit is used to trigger the output of a sleep enable signal when a load adjustment signal is received.

[0024] Optionally, the sleep enable circuit includes a first electronic switch, a second electronic switch, a third electronic switch, a fourth electronic switch, a fifth electronic switch, and a sixth electronic switch.

[0025] The control terminals of the first and fourth electronic switches constitute the control terminals of the sleep enable circuit. The first terminals of the first, second, and third electronic switches are connected to a positive voltage terminal. The control terminals of the first, second, fourth, and third electronic switches are connected to the control terminal of the fifth electronic switch. The second terminal of the fourth electronic switch is connected to the first terminal of the sixth electronic switch. The control terminals of the sixth, second, and third electronic switches are connected to a positive voltage terminal. The second terminal of the third and fifth electronic switches are connected to form the output terminal of the sleep enable circuit. The second terminals of the fifth and sixth electronic switches are grounded.

[0026] Optionally, the comparison circuit includes an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a third comparator, a fourth comparator, a third diode, and a fourth diode;

[0027] The first terminal of the eighth resistor is grounded. The second terminal of the eighth resistor, the first terminal of the ninth resistor, and the non-inverting input terminal of the third comparator are connected. The second terminal of the ninth resistor is used to input the first reference voltage. The inverting input terminal of the third comparator, the non-inverting input terminal of the fourth comparator, and the output terminal of the driver chip are connected. The first terminal of the tenth resistor is used to input the second reference voltage. The second terminal of the tenth resistor, the first terminal of the eleventh resistor, and the inverting input terminal of the fourth comparator are connected. The second terminal of the eleventh resistor is grounded. The output terminal of the third comparator is connected to the anode of the third diode. The output terminal of the fourth comparator is connected to the anode of the fourth diode. The cathodes of the third diode and the fourth diode constitute the output terminal of the comparator circuit.

[0028] A second aspect of the present invention provides a display device, including a driving circuit for a display panel and a display panel connected to each other, wherein the driving circuit for the display panel includes at least the common voltage output circuit described above.

[0029] The beneficial effects of the embodiments of the present invention compared with the prior art are as follows: The above-mentioned common voltage output circuit includes a driver chip, a load adjustment circuit, a comparison circuit, and a load control circuit. When the driver chip obtains the initial data of the common electrode through communication, it generates an initial common electrode voltage. The comparison circuit compares the initial common electrode voltage with a threshold voltage and generates a comparison signal when the threshold voltage is exceeded. The load control circuit generates a load adjustment signal based on the comparison signal. The load adjustment circuit reduces the voltage at the common electrode terminal from a first current to a second current based on the load adjustment signal, thereby reducing the output current of the driver chip and reducing the load output of the power management integrated circuit. The power management integrated circuit will not experience low-voltage power failure, thereby avoiding the black screen phenomenon of the display panel and improving the display reliability during burning tests or driver power-on. Attached Figure Description

[0030] Figure 1 This is a circuit diagram of a traditional common voltage output circuit;

[0031] Figure 2 A schematic diagram of the power supply output waveform for a traditional common voltage output circuit;

[0032] Figure 3 This is a schematic diagram of a first type of common voltage output circuit provided in Embodiment 1 of the present invention;

[0033] Figure 4 This is a second circuit diagram of the common voltage output circuit provided in Embodiment 1 of the present invention;

[0034] Figure 5 This is a schematic diagram of the power supply output waveform of the common voltage output circuit provided in Embodiment 1 of the present invention;

[0035] Figure 6 This is a schematic diagram of a first type of common voltage output circuit provided in Embodiment 2 of the present invention;

[0036] Figure 7 This is a second circuit diagram of the common voltage output circuit provided in Embodiment 2 of the present invention;

[0037] Figure 8 This is a circuit diagram of the current adjustment circuit and the delay circuit provided in Embodiment 2 of the present invention;

[0038] Figure 9 This is a circuit diagram of the comparison circuit provided in Embodiment 2 of the present invention;

[0039] Figure 10 This is a circuit diagram of the driver chip provided in Embodiment 2 of the present invention;

[0040] Figure 11This is a circuit diagram of the common voltage output circuit provided in Embodiment 3 of the present invention;

[0041] Figure 12 This is a circuit diagram of the sleep enable circuit provided in Embodiment 3 of the present invention;

[0042] Figure 13 This is a circuit diagram of the comparison circuit provided in Embodiment 3 of the present invention;

[0043] Figure 14 This is a circuit diagram of a display device provided in Embodiment 4 of the present invention.

[0044] The figures in the diagram are labeled as follows:

[0045] 100. Display panel; 200. Display panel driving circuit; 30. Driving circuit; 10. Power management integrated circuit; 20. Common voltage output circuit; 210. Driver chip; 220. Load regulation circuit; 230. Comparison circuit; 240. Load control circuit; 221. Current adjustment circuit; 222. Delay circuit; 223. Sleep control circuit; 241. Sleep enable circuit;

[0046] R1, First resistor; R2, Second resistor; R3, Third resistor; R4, Fourth resistor; R5, Fifth resistor; R6, Sixth resistor; R7, Seventh resistor; R8, Eighth resistor; R9, Ninth resistor; R10, Tenth resistor; R11, Eleventh resistor; U1, Operational amplifier; U2, First comparator; U3, Second comparator; U4, Third comparator; U5, Fourth comparator; D1, First diode; D2, Second diode; D3, Third diode; D4, Fourth diode; Rx, Variable resistor; C0, Zener capacitor; C1, First capacitor; C2, Second capacitor; C3, Third capacitor; T1, First electronic switch; T2, Second electronic switch; T3, Third electronic switch; T4, Fourth electronic switch; T5, Fifth electronic switch; T6, Sixth electronic switch;

[0047] VCC, positive voltage terminal; Vcom, common electrode voltage; Vref, threshold voltage; Vref1, first reference voltage; Vref2, second reference voltage; IO, input / output port; VIN, supply voltage; AVEE, operating voltage; IAVEE, output current of the driver chip; BI, comparison signal; E, sleep enable signal. Detailed Implementation

[0048] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0049] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0050] Example 1

[0051] A first aspect of the present invention provides a common voltage output circuit 20.

[0052] like Figure 3 and Figure 4 As shown, in this embodiment, the common voltage output circuit 20 is connected to the display panel 100. The display panel 100 is provided with a common electrode terminal V0. The common electrode terminal V0 is connected to a voltage stabilizing capacitor C0. The common electrode terminal V0 is directly or indirectly connected to the common electrode layer and correspondingly transmits the common electrode voltage Vcom to the common electrode layer.

[0053] Common voltage output circuit 20 includes:

[0054] The driver chip 210 is connected to the power management integrated circuit 10. The driver chip 210 is used to connect and communicate with the programming module or the control module to obtain the initial data of the common electrode, and generate the initial common electrode voltage and output the first current to the common electrode terminal V0 according to the initial data of the common electrode.

[0055] The load adjustment circuit 220 is connected to the display panel 100. The load adjustment circuit 220 is used to reduce the input current of the common terminal V0 from a first current to a second current according to the load adjustment signal.

[0056] Comparison circuit 230 is connected to the output terminal of driver chip 210 and is used to compare the initial common electrode voltage with the threshold voltage Vref, and output comparison signal BI when the initial common electrode voltage exceeds the threshold voltage Vref.

[0057] The load control circuit 240 is connected to the comparator circuit 230 and the load adjustment circuit 220 respectively. The load control circuit 240 is used to output a load adjustment signal according to the comparison signal BI.

[0058] In this embodiment, the load adjustment circuit 220 can be connected in series between the common terminal V0 of the driver chip 210 and the display panel 100, or connected to the corresponding driver circuit 30 of the display panel 100.

[0059] The power management integrated circuit 10 provides the operating voltage AVEE to the driver chip 210. When the display panel 100 is powered on during programming and debugging, the driver chip 210 receives the initial data of the common electrode. The initial data of the common electrode can be a digital signal or an analog signal. When the driver chip 210 receives the initial data of the common electrode, it converts and outputs the initial common electrode voltage. The initial common electrode voltage is output to the common electrode terminal V0 through the load regulation circuit 220, or the initial common electrode voltage is directly transmitted to the common electrode terminal V0.

[0060] The comparator circuit 230 acquires the initial common electrode voltage output by the driver chip 210 and compares it with the threshold voltage Vref. When the initial common electrode voltage is less than the threshold voltage Vref, it indicates that the required common electrode voltage Vcom for the current common electrode V0 is less than the threshold voltage Vref. Correspondingly, the voltage difference between the initial common electrode voltage and the default value is small, the first current output by the driver chip 210 is small, the load on the power management integrated circuit 10 is small, the supply voltage VIN of the power management integrated circuit 10 reaches the preset value, and the power management integrated circuit 10 will not experience low-voltage power failure. At this time, the comparator circuit 230 may not output the comparison signal BI, or may output a level signal with the opposite level to the comparison signal BI. At this time, the load control circuit 240 will not output the load adjustment signal, and the load adjustment circuit 220 will not change the voltage of the common electrode V0. Correspondingly, the driver chip 210 can normally output the first current to the common electrode V0, thereby stabilizing the voltage at the end of the voltage regulator capacitor C0 and the voltage at the common electrode V0 to the initial common electrode voltage, and causing the common electrode layer to reach the initial common electrode voltage, thus displaying normal screen information.

[0061] When the initial common electrode voltage exceeds the threshold voltage Vref, such as Figure 5As shown, the required common electrode voltage Vcom at the current common electrode terminal V0 is greater than the threshold voltage Vref. Correspondingly, the voltage difference between the initial common electrode voltage and the default value is large. At this time, the first current output by the driver chip 210 is large, and correspondingly, the load on the power management integrated circuit 10 is large. The supply voltage VIN of the power management integrated circuit 10 may be less than the preset value, which may cause the power management integrated circuit 10 to shut down due to low voltage. In order to avoid the display panel 100 from going black due to low voltage shutdown of the power management integrated circuit 10, the comparator circuit 230 compares and outputs a comparison signal BI. The comparison signal BI triggers the load control circuit 240 to output a load adjustment signal. The load adjustment circuit 220 reduces the first current to a certain value according to the load adjustment signal. The second current is used to charge the voltage regulator capacitor C0 at a low current, thereby stabilizing the voltage at the terminal of the voltage regulator capacitor C0 and the voltage at the common electrode V0 to the initial common electrode voltage, and making the common electrode layer reach the initial common electrode voltage. At the same time, the output current IAVEE of the driver chip 210 switches to the second current, the output current IAVEE of the driver chip 210 decreases, the load output of the power management integrated circuit 10 decreases, the supply voltage VIN of the power management integrated circuit 10 reaches the preset value, the operating voltage AVEE of the driver chip 210 stabilizes at the preset value, the power management integrated circuit 10 will not experience low voltage power failure, the driver chip 210 can output normally, and can control the display panel 100 to display normal screen information.

[0062] The threshold voltage Vref can be set according to requirements. It can be a fixed value, such as 1V, or a range value, such as 0.5V~1.5V, depending on the magnitude of the operating voltage AVEE between the power management integrated circuit 10 and the driver chip 210.

[0063] The load regulation circuit 220 can be directly connected between the driver chip 210 and the common terminal V0, and can directly reduce or maintain the output current IAVEE of the driver chip 210. Alternatively, the load regulation circuit 220 can also be connected to the corresponding driver circuit 30 of the display panel 100. The driver circuit 30 is used to control the display panel 100 to perform display operations. The load regulation circuit 220 can control the display panel 100 to work in a sleep state or a normal working state through the driver circuit 30. When the display panel 100 is working in a sleep state, the power management integrated circuit 10 has no load output, and the output current IAVEE of the driver chip 210 can be approximately zero. However, the driver chip 210 can normally output the common electrode voltage Vcom. The power management integrated circuit 10 and the driver chip 210 can work normally without low-voltage power failure.

[0064] The comparator circuit 230 can be a corresponding comparator, and the load adjustment circuit 220 can be a corresponding impedance adjustment circuit or a sleep enable circuit 241; the specific structure is not limited.

[0065] Example 2

[0066] In an alternative embodiment, such as Figure 6 As shown, the load regulation circuit 220 includes:

[0067] The current adjustment circuit 221 is connected in series between the driver chip 210 and the common terminal V0. The current adjustment circuit 221 is used to adjust its own impedance from the first impedance to the second impedance according to the load adjustment signal. The second impedance is greater than the first impedance.

[0068] In this embodiment, when the initial common electrode voltage is less than the threshold voltage Vref, it indicates that the common electrode voltage Vcom required for the current common electrode V0 is less than the threshold voltage Vref. Correspondingly, the voltage difference between the initial common electrode voltage and the default value is small, the first current output by the driver chip 210 is small, and correspondingly, the load of the power management integrated circuit 10 is small. The supply voltage VIN of the power management integrated circuit 10 reaches the preset value, and the power management integrated circuit 10 will not experience low-voltage power failure. At this time, the comparator circuit 230 may not output the comparator signal BI, or may output a level signal with the opposite level to the comparator signal BI. At this time, the load control circuit 240 will not output the load adjustment signal. Correspondingly, the current adjustment circuit 221 maintains the first impedance, which is small. The first current output by the driver chip 210 can be normally output to the common electrode V0 through the current adjustment circuit 221, thereby stabilizing the voltage of the voltage regulator capacitor C0 and the voltage of the common electrode V0 to the initial common electrode voltage, and causing the common electrode layer to reach the initial common electrode voltage, thereby displaying normal screen information.

[0069] When the initial common electrode voltage exceeds the threshold voltage Vref, such as Figure 5As shown, the required common electrode voltage Vcom at the current common electrode terminal V0 is greater than the threshold voltage Vref. Correspondingly, the voltage difference between the initial common electrode voltage and the default value is large. At this time, the first current output by the driver chip 210 is large. Correspondingly, the load of the power management integrated circuit 10 is large, and the supply voltage VIN of the power management integrated circuit 10 may be less than the preset value, which will cause the power management integrated circuit 10 to shut down due to low voltage. In order to avoid the display panel 100 from going black due to low voltage shutdown of the power management integrated circuit 10, the comparator circuit 230 compares and outputs a comparison signal BI. The comparison signal BI triggers the load control circuit 240 to output a load adjustment signal. The current adjustment circuit 221 increases its own impedance from the first impedance to the second impedance. Correspondingly, the second impedance The first current limit is reduced to the second current, which charges the voltage regulator capacitor C0 at a low current. This allows the voltage at the terminal of the voltage regulator capacitor C0 and the voltage at the common electrode V0 to be stably charged to the initial common electrode voltage, and the common electrode layer reaches the initial common electrode voltage. At the same time, the output current IAVEE of the driver chip 210 is switched to the second current, the output current IAVEE of the driver chip 210 decreases, the load output of the power management integrated circuit 10 decreases, the supply voltage VIN of the power management integrated circuit 10 reaches the preset value, the operating voltage AVEE of the driver chip 210 stabilizes at the preset value, the power management integrated circuit 10 will not experience low voltage power failure, the driver chip 210 can output normally, and can control the display panel 100 to display normal screen information.

[0070] Furthermore, in order to further limit the large current at the common electrode V0, in an optional embodiment, such as Figure 7 As shown, the load regulation circuit 220 also includes:

[0071] The delay circuit 222 is connected between the current adjustment circuit 221 and the common terminal V0. The delay circuit 222 is used to receive the current signal output by the current adjustment circuit 221 and output it to the common terminal V0 after a delay.

[0072] In this embodiment, the delay circuit 222 can charge and delay the current signal output by the current adjustment circuit 221. By delaying the rise time of the common electrode voltage Vcom of the common terminal V0, the large current is further limited and the current limiting effect is strengthened.

[0073] The current adjustment circuit 221 can employ multiple resistors connected in series and parallel and switched by a switch to output different impedances, or it can employ a sliding rheostat or similar structure. The comparison circuit 230 can employ a corresponding comparator, and the delay circuit 222 can employ an RC circuit or similar structure. In an optional embodiment, such as... Figure 8 As shown, the current adjustment circuit 221 includes a variable resistor Rx, a first capacitor C1, a second capacitor C2, and an operational amplifier U1;

[0074] The first terminal of the variable resistor Rx, the first terminal of the first capacitor C1, and the positive power supply terminal of the operational amplifier U1 are connected. The second terminal of the variable resistor Rx, the second terminal of the second capacitor C2, and the negative power supply terminal of the operational amplifier U1 are connected. The control terminal of the variable resistor Rx is connected to the signal terminal of the load adjustment circuit 220. The central axis of the variable resistor Rx, the output terminal of the driver chip 210, and the non-inverting input terminal of the operational amplifier U1 are connected. The inverting input terminal of the operational amplifier U1 and the output terminal of the operational amplifier U1 are connected to form the output terminal of the current adjustment circuit 221. The second terminal of the first capacitor C1 and the second terminal of the second capacitor C2 are grounded.

[0075] The delay circuit 222 includes a first resistor R1 and a third capacitor C3;

[0076] The first end of the first resistor R1 forms the input terminal of the delay circuit 222. The second end of the first resistor R1 and the first end of the third capacitor C3 are connected to form the output terminal of the delay circuit 222. The second end of the third capacitor C3 is grounded.

[0077] like Figure 9 As shown, the comparator circuit 230 includes a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a first comparator U2, a second comparator U3, a first diode D1, and a second diode D2.

[0078] The first end of the second resistor R2 is grounded. The second end of the second resistor R2, the first end of the third resistor R3, and the inverting input of the first comparator U2 are connected. The second end of the third resistor R3 is used to input the first reference voltage Vref1. The non-inverting input of the first comparator U2, the inverting input of the second comparator U3, and the output of the driver chip 210 are connected. The first end of the fourth resistor R4 is used to input the second reference voltage Vref2. The second end of the fourth resistor R4, the first end of the fifth resistor R5, and the non-inverting input of the second comparator U3 are connected. The second end of the fifth resistor R5 is grounded. The outputs of the first comparator U2, the second comparator U3, the first end of the sixth resistor R6, and the first end of the seventh resistor R7 are connected. The second end of the sixth resistor R6, the cathode of the first diode D1, and the positive voltage terminal VCC are connected. The second end of the seventh resistor R7, the cathode of the second diode D2, and the anode of the first diode D1 constitute the output of the comparator circuit 230. The anode of the second diode D2 is grounded. The first reference voltage Vref1 is less than the second reference voltage Vref2.

[0079] In this embodiment, the threshold voltage Vref is a range value, consisting of a first threshold voltage and a second threshold voltage. The first reference voltage Vref1 is output as a first threshold voltage through a voltage divider between a second resistor R2 and a third resistor R3. The second reference voltage Vref2 is output as a second threshold voltage through a voltage divider between a fourth resistor R4 and a fifth resistor R5. The first threshold voltage is less than the second threshold voltage, for example, the first threshold voltage is 0.5V and the second threshold voltage is 1.5V.

[0080] When the driver chip 210 recognizes that the initial common electrode voltage is greater than the second threshold voltage, the first comparator U2 outputs a high level and the second comparator U3 outputs a low level. At this time, the comparator circuit 230 outputs a low level.

[0081] When the driver chip 210 recognizes that the initial common electrode voltage is less than the first threshold voltage, the first comparator U2 outputs a low level and the second comparator U3 outputs a high level. At this time, the comparator circuit 230 outputs a low level.

[0082] When the driver chip 210 recognizes that the initial common electrode voltage is greater than the first threshold voltage and the second threshold voltage, the first comparator U2 outputs a high level, the second comparator U3 outputs a high level, and at this time, the comparator circuit 230 outputs a high level.

[0083] Correspondingly, the comparison signal BI is a low-level signal. That is, when the initial common electrode voltage exceeds the threshold voltage Vref, the comparison circuit 230 outputs the comparison signal BI. The comparison signal BI triggers the load control circuit 240 to output a load adjustment signal. The variable resistor Rx in the current adjustment circuit 221 increases its impedance from the first impedance to the second impedance according to the load adjustment signal. Correspondingly, the second impedance reduces the first current limit to the second current, so that the voltage regulator capacitor C0 is charged with a low current. At the same time, the first resistor R1 and the third capacitor C3 form an RC buffer circuit, which can delay the charging of the current signal output by the current adjustment circuit 221. By delaying the common electrode voltage Vcom of the common electrode V0, the voltage of the common electrode V0 is increased. The rise time further limits the large current and strengthens the current limiting effect, thereby stabilizing the voltage at the terminal of the voltage regulator capacitor C0 and the voltage at the common electrode terminal V0 to the initial common electrode voltage, and making the common electrode layer reach the initial common electrode voltage. At the same time, the output current IAVEE of the driver chip 210 switches to the second current, the output current IAVEE of the driver chip 210 decreases, the load output of the power management integrated circuit 10 decreases, the supply voltage VIN of the power management integrated circuit 10 reaches the preset value, the operating voltage AVEE of the driver chip 210 stabilizes at the preset value, the power management integrated circuit 10 will not experience low voltage power failure, the driver chip 210 can output normally, and can control the display panel 100 to display normal screen information.

[0084] Operational amplifier U1 forms a voltage follower, which amplifies and stabilizes the output current IAVEE of driver chip 210 and outputs it to the delay circuit.

[0085] The first reference voltage Vref1 and the second reference voltage Vref2 can be provided by corresponding signal sources. The load control circuit 240 can be composed of corresponding controllers and processors. In an optional embodiment, in order to simplify the circuit structure, the first reference voltage Vref1 and the second reference voltage Vref2 are provided by the driver chip 210. At the same time, the output terminal of the comparator circuit 230 is connected to the signal terminal of the driver chip 210. The driver chip 210 synchronously completes the load control work of the load control circuit 240. That is, the control terminal of the driver chip 210 is also connected to the control terminal of the variable resistor Rx, and adjusts the resistance value of the variable resistor Rx when it receives the low-level signal output by the comparator circuit 230.

[0086] like Figure 10 As shown, the driver chip 210 may include input / output ports IO, which are connected to the programming module or control module to communicate and obtain the initial data of the common electrode. The driver chip 210 also includes four common ports, three of which output the first reference voltage Vref1, the second reference voltage Vref2, and the initial common electrode voltage, respectively, and the other common port receives the high and low level signals output by the comparator circuit 230.

[0087] When the driver chip 210 receives a high-level signal, it does not output a load adjustment signal to the variable resistor Rx. The variable resistor Rx maintains the first impedance, and the driver chip 210 maintains the current first current output and charges the voltage regulator capacitor C0.

[0088] Example 3

[0089] In another optional embodiment, the load adjustment circuit 220 is a sleep control circuit 223. The sleep control circuit 223 is connected to the display panel 100 and the driving circuit 30 that drives the display panel 100 to display. The sleep control circuit 223 is used to control the display panel 100 and the driving circuit 30 to enter a sleep state according to the sleep enable signal E.

[0090] The load control circuit 240 includes:

[0091] The sleep enable circuit 241 is connected to the sleep control circuit 223. The sleep enable circuit 241 is used to trigger the output sleep enable signal E when a load adjustment signal is received.

[0092] In this embodiment, the load adjustment circuit 220 is a sleep control circuit 223. The sleep control circuit 223 is connected to the corresponding drive circuit 30 of the display panel 100. The drive circuit 30 is used to control the display panel 100 to perform display work. The sleep control circuit 223 can control the display panel 100 to work in a sleep state or a normal working state through the drive circuit 30.

[0093] When the initial common electrode voltage is less than the threshold voltage Vref, it indicates that the common electrode voltage Vcom required for the current common electrode V0 is less than the threshold voltage Vref. Correspondingly, the voltage difference between the initial common electrode voltage and the default value is small, the first current output by the driver chip 210 is small, the load of the power management integrated circuit 10 is small, the supply voltage VIN of the power management integrated circuit 10 reaches the preset value, and the power management integrated circuit 10 will not experience low-voltage power failure. At this time, the comparator circuit 230 may not output the comparator signal BI, or may output a level signal with the opposite level to the comparator signal BI. At this time, the sleep enable circuit 241 may not output the sleep enable signal E. Correspondingly, the sleep control circuit 223 controls the display panel 100 and its driver circuit 30 to work normally. The common electrode V0 can normally receive the first current, and the driver chip 210 can normally output the first current to the common electrode V0, thereby stabilizing the voltage of the voltage regulator capacitor C0 and the voltage of the common electrode V0 to the initial common electrode voltage, and causing the common electrode layer to reach the initial common electrode voltage, thereby displaying normal screen information.

[0094] When the initial common electrode voltage exceeds the threshold voltage Vref, it indicates that the required common electrode voltage Vcom at the current common electrode V0 is greater than the threshold voltage Vref. Correspondingly, the voltage difference between the initial common electrode voltage and the default value is large. At this time, the first current output by the driver chip 210 is large, and correspondingly, the load on the power management integrated circuit 10 is large. The supply voltage VIN of the power management integrated circuit 10 may be less than the preset value, which may cause the power management integrated circuit 10 to shut down due to low voltage. In order to avoid the display panel 100 from going black due to low voltage shutdown of the power management integrated circuit 10, the comparator circuit 230 compares and outputs a comparison signal BI. The comparison signal BI triggers the sleep enable circuit 241 to output a sleep enable signal. Signal E is sent to the sleep control circuit 223, which controls the display panel 100 and its driving circuit 30 to enter sleep mode. At this time, each port of the display panel 100 cuts off the corresponding input voltage and current signals. The common terminal V0 cuts off the input common electrode voltage Vcom. The voltage regulator C0 does not charge. The second current is reduced to zero. At this time, the driving chip 210 and the power management integrated circuit 10 have no load output. The operating voltage AVEE of the driving chip 210 is stable at the preset value. The power management integrated circuit 10 will not experience low voltage power failure. The driving chip 210 can output the common electrode voltage Vcom normally, but there is no current signal output. At this time, the display panel 100 will not experience a black screen upon power-on.

[0095] The sleep control circuit 223 can be a conventional sleep control circuit 223, the sleep enable circuit 241 can be a corresponding signal source, switch switching circuit, etc., and the comparator circuit 230 can be specifically set according to the trigger signal required by the sleep enable circuit 241.

[0096] In an alternative embodiment, such as Figure 12 As shown, the sleep enable circuit 241 includes a first electronic switch T1, a second electronic switch T2, a third electronic switch T3, a fourth electronic switch T4, a fifth electronic switch T5, and a sixth electronic switch T6.

[0097] The control terminals of the first electronic switch T1 and the fourth electronic switch T4 constitute the control terminals of the sleep enable circuit 241. The first terminal of the first electronic switch T1, the first terminal of the second electronic switch T2, the first terminal of the third electronic switch T3, and the positive voltage terminal VCC are connected. The second terminal of the first electronic switch T1, the second terminal of the second electronic switch T2, the first terminal of the fourth electronic switch T4, the control terminal of the third electronic switch T3, and the control terminal of the fifth electronic switch T5 are connected. The second terminal of the fourth electronic switch T4 is connected to the first terminal of the sixth electronic switch T6. The control terminal of the sixth electronic switch T6, the control terminal of the second electronic switch T2, and the positive voltage terminal VCC are connected. The second terminal of the third electronic switch T3 and the first terminal of the fifth electronic switch T5 are connected to form the output terminal of the sleep enable circuit 241. The second terminals of the fifth electronic switch T5 and the second terminals of the sixth electronic switch T6 are grounded.

[0098] like Figure 13 As shown, the comparator circuit 230 includes an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a third comparator U4, a fourth comparator U5, a third diode D3, and a fourth diode D4.

[0099] The first end of the eighth resistor R8 is grounded. The second end of the eighth resistor R8, the first end of the ninth resistor R9, and the non-inverting input of the third comparator U4 are connected. The second end of the ninth resistor R9 is used to input the first reference voltage Vref1. The inverting input of the third comparator U4, the non-inverting input of the fourth comparator U5, and the output of the driver chip 210 are connected. The first end of the tenth resistor R10 is used to input the second reference voltage Vref2. The second end of the tenth resistor R10, the first end of the eleventh resistor R11, and the inverting input of the fourth comparator U5 are connected. The second end of the eleventh resistor R11 is grounded. The output of the third comparator U4 is connected to the anode of the third diode D3. The output of the fourth comparator U5 is connected to the anode of the fourth diode D4. The cathodes of the third diode D3 and the fourth diode D4 constitute the output of the comparator circuit 230.

[0100] In this embodiment, the threshold voltage Vref is a range value, consisting of a first threshold voltage and a second threshold voltage. The first reference voltage Vref1 is output as a first threshold voltage through a voltage divider between the eighth resistor R8 and the ninth resistor R9. The second reference voltage Vref2 is output as a second threshold voltage through a voltage divider between the tenth resistor R10 and the eleventh resistor R11. The first threshold voltage is less than the second threshold voltage, for example, the first threshold voltage is 0.5V and the second threshold voltage is 1.5V.

[0101] When the driver chip 210 recognizes that the initial common electrode voltage is greater than the second threshold voltage, the third comparator U4 outputs a low level and the fourth comparator U5 outputs a high level. At this time, the comparator circuit 230 outputs a high level.

[0102] When the driver chip 210 recognizes that the initial common electrode voltage is less than the first threshold voltage, the third comparator U4 outputs a high level and the fourth comparator U5 outputs a low level. At this time, the comparator circuit 230 outputs a high level.

[0103] When the driver chip 210 recognizes that the initial common electrode voltage is greater than the first threshold voltage and the second threshold voltage, the third comparator U4 outputs a low level, the fourth comparator U5 outputs a low level, and at this time, the comparator circuit 230 outputs a low level.

[0104] When the initial common electrode voltage exceeds the threshold voltage Vref, the comparator circuit 230 outputs a high level, the fourth electronic switch T4 is turned on, the sixth electronic switch T6 is turned on, and the third electronic switch T3 is turned on and outputs a high-level sleep enable signal E. The sleep control circuit 223 controls the display panel 100 and its driving circuit 30 to enter a sleep state. At this time, each port of the display panel 100 cuts off the corresponding input voltage and current signals. Correspondingly, the common electrode V0 cuts off the input common electrode voltage Vcom. Correspondingly, the voltage regulator capacitor C0 does not charge, and the second current drops to zero. At this time, the driving chip 210 and the power management integrated circuit 10 have no load output. The operating voltage AVEE of the driving chip 210 is stable at the preset value. The power management integrated circuit 10 will not experience low-voltage power failure. The driving chip 210 can output the common electrode voltage Vcom normally, but there is no current signal output. At this time, the display panel 100 will not experience a black screen upon power-on.

[0105] When the initial common electrode voltage does not exceed the threshold voltage Vref, the comparator circuit 230 outputs a low level, the first electronic switch T1 is turned on, the fifth electronic switch T5 is triggered to turn on and output a low level signal. At this time, the sleep control circuit 223 controls the display panel 100 and its driving circuit 30 to work normally. The common electrode V0 can receive the first current normally, and the driving chip 210 can output the first current to the common electrode V0 normally. This allows the voltage at the end of the voltage regulator C0 and the voltage at the common electrode V0 to be stably charged to the initial common electrode voltage, and the common electrode layer reaches the initial common electrode voltage, thereby displaying normal screen information.

[0106] Example 4

[0107] A second aspect of the present invention provides a display device, such as... Figure 14As shown, the display device includes a driving circuit 200 for the display panel and a display panel 100 connected to each other. The driving circuit 200 for the display panel includes at least a common voltage output circuit 20. The specific structure of the common voltage output circuit 20 is as described in the above embodiments. Since this display device adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here.

[0108] In this embodiment, the driving circuit 200 of the display panel may include one or more common electrode output circuits, and may also include a power management integrated circuit 10, a source driving circuit, a gate driving circuit and a timing controller. The source driving circuit is connected to the data line of the display panel 100 and provides data signals. The gate driving circuit is connected to the scan line of the display panel 100 and provides horizontal scanning signals. The common voltage output circuit 20 provides a common electrode voltage Vcom. The display panel 100 displays corresponding image information according to the data signal, the horizontal scanning signal and the common electrode voltage Vcom.

[0109] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A common voltage output circuit, connected to a display panel, wherein the display panel has a common terminal and a voltage-regulating capacitor is connected to the common terminal, characterized in that, The common voltage output circuit includes: A driver chip is connected to a power management integrated circuit. The driver chip is used to communicate with a programming module or a control module to obtain initial data of the common electrode, and to generate an initial common electrode voltage and output a first current to the common electrode terminal based on the initial data of the common electrode. A load adjustment circuit is connected to the display panel. The load adjustment circuit is used to reduce the input current of the common terminal from the first current to the second current according to the load adjustment signal. A comparison circuit, connected to the driver chip, is used to compare the initial common electrode voltage with a threshold voltage, and output a comparison signal when the initial common electrode voltage exceeds the threshold voltage. A load control circuit is connected to both the comparison circuit and the load adjustment circuit. The load control circuit is used to output the load adjustment signal based on the comparison signal.

2. The common voltage output circuit as described in claim 1, characterized in that, The load regulation circuit includes: A current adjustment circuit is connected in series between the driver chip and the common terminal. The current adjustment circuit is used to adjust its own impedance from a first impedance to a second impedance according to the load adjustment signal, wherein the second impedance is greater than the first impedance.

3. The common voltage output circuit as described in claim 2, characterized in that, The current adjustment circuit includes a variable resistor, a first capacitor, a second capacitor, and an operational amplifier; The first end of the variable resistor, the first end of the first capacitor, and the positive power supply terminal of the operational amplifier are connected. The second end of the variable resistor, the second end of the second capacitor, and the negative power supply terminal of the operational amplifier are connected. The control terminal of the variable resistor is connected to the signal terminal of the load adjustment circuit. The central axis of the variable resistor, the output terminal of the driver chip, and the non-inverting input terminal of the operational amplifier are connected. The inverting input terminal and the output terminal of the operational amplifier are connected to form the output terminal of the current adjustment circuit. The second ends of the first capacitor and the second ends of the second capacitor are grounded.

4. The common voltage output circuit as described in claim 2, characterized in that, The load regulation circuit further includes: A delay circuit is connected between the current adjustment circuit and the common terminal. The delay circuit is used to receive the current signal output by the current adjustment circuit and output it to the common terminal after a delay.

5. The common voltage output circuit as described in claim 4, characterized in that, The delay circuit includes a first resistor and a third capacitor; The first end of the first resistor constitutes the input terminal of the delay circuit, the second end of the first resistor and the first end of the third capacitor are connected to constitute the output terminal of the delay circuit, and the second end of the third capacitor is grounded.

6. The common voltage output circuit as described in claim 2, characterized in that, The comparator circuit includes a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, a first comparator, a second comparator, a first diode, and a second diode; The first end of the second resistor is grounded. The second end of the second resistor, the first end of the third resistor, and the inverting input of the first comparator are connected. The second end of the third resistor is used to input the first reference voltage. The non-inverting input of the first comparator, the inverting input of the second comparator, and the output of the driver chip are connected. The first end of the fourth resistor is used to input the second reference voltage. The second end of the fourth resistor, the first end of the fifth resistor, and the non-inverting input of the second comparator are connected. The second end of the fifth resistor is grounded. The outputs of the first comparator, the second comparator, the first end of the sixth resistor, and the first end of the seventh resistor are connected. The second end of the sixth resistor, the cathode of the first diode, and the positive voltage terminal are connected. The second end of the seventh resistor, the cathode of the second diode, and the anode of the first diode constitute the output of the comparator circuit. The anode of the second diode is grounded. The first reference voltage is less than the second reference voltage.

7. The common voltage output circuit as described in claim 1, characterized in that, The load adjustment circuit is a sleep control circuit. The sleep control circuit is connected to the display panel and the driving circuit that drives the display panel to display. The sleep control circuit is used to control the display panel and the driving circuit to enter a sleep state according to the sleep enable signal. The load control circuit includes: A sleep enable circuit is connected to the sleep control circuit. The sleep enable circuit is used to trigger the output of a sleep enable signal when a load adjustment signal is received.

8. The common voltage output circuit as described in claim 7, characterized in that, The sleep enable circuit includes a first electronic switch, a second electronic switch, a third electronic switch, a fourth electronic switch, a fifth electronic switch, and a sixth electronic switch. The control terminals of the first and fourth electronic switches constitute the control terminals of the sleep enable circuit. The first terminals of the first, second, and third electronic switches are connected to a positive voltage terminal. The control terminals of the first, second, fourth, and third electronic switches are connected to the control terminal of the fifth electronic switch. The second terminal of the fourth electronic switch is connected to the first terminal of the sixth electronic switch. The control terminals of the sixth, second, and third electronic switches are connected to a positive voltage terminal. The second terminal of the third and fifth electronic switches are connected to form the output terminal of the sleep enable circuit. The second terminals of the fifth and sixth electronic switches are grounded.

9. The common voltage output circuit as described in claim 8, characterized in that, The comparator circuit includes an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a third comparator, a fourth comparator, a third diode, and a fourth diode; The first terminal of the eighth resistor is grounded. The second terminal of the eighth resistor, the first terminal of the ninth resistor, and the non-inverting input terminal of the third comparator are connected. The second terminal of the ninth resistor is used to input the first reference voltage. The inverting input terminal of the third comparator, the non-inverting input terminal of the fourth comparator, and the output terminal of the driver chip are connected. The first terminal of the tenth resistor is used to input the second reference voltage. The second terminal of the tenth resistor, the first terminal of the eleventh resistor, and the inverting input terminal of the fourth comparator are connected. The second terminal of the eleventh resistor is grounded. The output terminal of the third comparator is connected to the anode of the third diode. The output terminal of the fourth comparator is connected to the anode of the fourth diode. The cathodes of the third diode and the fourth diode constitute the output terminal of the comparator circuit.

10. A display device, characterized in that, The device includes a driving circuit for a connected display panel and a display panel, wherein the driving circuit for the display panel includes at least a common voltage output circuit as described in any one of claims 1 to 9.

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