Memory device, operation method thereof and memory system

Abstract

The embodiment of the invention provides a memory device, an operation method thereof and a memory system. The memory device comprises a memory cell array; a plurality of word lines; a peripheral circuit coupled to the memory cell array through the plurality of word lines, the peripheral circuit configured to: at a first stage of a program operation, apply a first voltage to a first word line and a second word line of the plurality of word lines; in a second stage of the programming operation, applying a second voltage greater than the first voltage to the first word line and the second word line; wherein the first word line and the second word line are located on the same side of a selected word line in the multiple word lines.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a memory device and its operation method, and a memory system. Background Technology

[0002] Memory devices are storage devices used to store information in modern information technology. As a typical non-volatile semiconductor memory, NAND (Not-And) flash memory has become the mainstream product in the memory market due to its high storage density, controllable production cost, suitable erasure speed, and retention characteristics.

[0003] With the increasing demands on memory devices, improving programming efficiency has become one of the most pressing technical problems to be solved in this field. Summary of the Invention

[0004] This disclosure provides a memory device, its operation method, and a memory system.

[0005] In a first aspect, embodiments of this disclosure provide a memory device, the memory device comprising: a memory cell array; a plurality of word lines; and peripheral circuitry coupled to the memory cell array via the plurality of word lines. The peripheral circuitry is configured to: apply a first voltage to a first word line and a second word line among the plurality of word lines during a first stage of programming operations; and apply a second voltage greater than the first voltage to the first word line and the second word line during a second stage of programming operations; wherein the first word line and the second word line are located on the same side of a selected word line among the plurality of word lines.

[0006] In one alternative implementation, the peripheral circuitry is configured to: apply a first voltage to a third word line among a plurality of word lines in a first stage; and apply a second voltage to the third word line in a second stage; wherein the first, second, and third word lines are located on the same side of the selected word line.

[0007] In one alternative implementation, the peripheral circuitry is configured to: in a first stage, apply a third voltage to a third word line among a plurality of word lines; and in a second stage, apply a fourth voltage greater than the third voltage to the third word line; wherein the first word line, the second word line, and the third word line are located on the same side of the selected word line.

[0008] In one optional implementation, the peripheral circuitry includes: control logic and a first voltage generator and a second voltage generator coupled to the control logic; the control logic is configured to: control the first voltage generator to generate a first voltage, control the second voltage generator to generate the third voltage, apply the first voltage to the first word line and the second word line in a first stage, and apply the third voltage to the third word line; control the first voltage generator to generate the second voltage, control the second voltage generator to generate the fourth voltage, apply the second voltage to the first word line and the second word line in a second stage, and apply the fourth voltage to the third word line.

[0009] In one alternative implementation, the memory cells connected to the first word line, the second word line, and the third word line are in an unprogrammed state.

[0010] In one alternative implementation, the peripheral circuitry is configured to: in a first stage, apply a fifth voltage to a fourth word line among a plurality of word lines; and in a second stage, apply a sixth voltage greater than the fifth voltage to the fourth word line; wherein the fourth word line is located on a different side from the first and second word lines.

[0011] In one alternative implementation, the peripheral circuitry is configured to: apply a channel boost voltage to the selected word line in a first stage; and apply a target programming voltage to the selected word line in a second stage.

[0012] In one alternative implementation, the target programming voltage is applied earlier than the second voltage.

[0013] In one alternative implementation, the peripheral circuitry is configured to apply a fifth voltage to the fifth and sixth word lines among a plurality of word lines in a first stage; wherein the fifth word line is located on the side of the fourth word line away from the selected word line, and the sixth word line is located on the side of the third word line away from the selected word line.

[0014] In one alternative embodiment, the memory device further includes bit lines and source lines; the programming operation includes sequentially programming from word lines adjacent to source lines to word lines adjacent to bit lines, or sequentially programming from word lines adjacent to bit lines to word lines adjacent to source lines.

[0015] In a second aspect, embodiments of this disclosure provide a memory system, including: a memory device as described in any of the first aspects; and a memory controller; the memory controller is coupled to the memory device and is used to control the memory device.

[0016] Thirdly, embodiments of this disclosure provide an operation method for a memory device, the operation method comprising: in a first stage of programming operation, applying a first voltage to a first word line and a second word line among a plurality of word lines; in a second stage of programming operation, applying a second voltage greater than the first voltage to the first word line and the second word line; wherein the first word line and the second word line are located on the same side of a selected word line among the plurality of word lines.

[0017] In one alternative implementation, the method further includes: in a first stage, applying a first voltage to a third word line among a plurality of word lines; and in a second stage, applying a second voltage to the third word line; wherein the first word line, the second word line, and the third word line are located on the same side of the selected word line.

[0018] In an optional implementation, the method further includes: in a first stage, applying a third voltage to a third word line among a plurality of word lines; in a second stage, applying a fourth voltage greater than the third voltage to the third word line; wherein the first word line, the second word line, and the third word line are located on the same side of the selected word line.

[0019] In one alternative implementation, the memory cells connected to the first word line, the second word line, and the third word line are in an unprogrammed state.

[0020] In an optional implementation, the method further includes: in a first stage, applying a fifth voltage to a fourth word line among a plurality of word lines; in a second stage, applying a sixth voltage greater than the fifth voltage to the fourth word line; wherein the fourth word line is located on a different side from the first word line and the second word line.

[0021] In one alternative implementation, the method further includes: in a first stage, applying a channel boost voltage to a selected word line; and in a second stage, applying a target programming voltage to the selected word line.

[0022] In one alternative implementation, the target programming voltage is applied earlier than the second voltage.

[0023] In an alternative implementation, the method further includes: in a first stage, applying a fifth voltage to a fifth word line and a sixth word line among a plurality of word lines; wherein the fifth word line is located on the side of the fourth word line away from the selected word line, and the sixth word line is located on the side of the third word line away from the selected word line.

[0024] This disclosure provides a memory device and its operation method, as well as a memory system. The memory device includes: a memory cell array; multiple word lines; and peripheral circuitry coupled to the memory cell array via the multiple word lines. The peripheral circuitry is configured to: apply a first voltage to a first word line and a second word line among the multiple word lines during a first stage of programming operation; and apply a second voltage greater than the first voltage to the first word line and the second word line during a second stage of programming operation; wherein the first word line and the second word line are located on the same side of a selected word line among the multiple word lines. This disclosure improves the voltage rise rate of the selected word line by raising the voltage on the first word line and the second word line in two steps, thereby reducing the pulse width of the target programming voltage and thus reducing programming time. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure;

[0026] Figure 2A This is a schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present disclosure;

[0027] Figure 2B This is a schematic diagram of an exemplary solid-state drive with a memory system according to an embodiment of the present disclosure;

[0028] Figure 3A This is a schematic diagram showing the distribution of storage cells in a three-dimensional NAND type memory according to an embodiment of the present disclosure;

[0029] Figure 3B This is a schematic diagram of an exemplary memory device including peripheral circuitry according to an embodiment of the present disclosure;

[0030] Figure 4 This is a schematic cross-sectional view of a memory cell array including NAND memory strings according to an embodiment of the present disclosure;

[0031] Figure 5 This is a schematic diagram of an exemplary memory device including a memory cell array and peripheral circuitry according to an embodiment of the present disclosure;

[0032] Figure 6 This is a schematic diagram of the voltage timing corresponding to each element at different stages of the programming loop in one embodiment of the present disclosure. Figure 1 ;

[0033] Figure 7 This is a cross-sectional schematic diagram of a memory string provided in one embodiment of this application;

[0034] Figure 8 This is a schematic diagram of the voltage timing on each element at different stages of the programming loop in one embodiment of the present disclosure;

[0035] Figure 9 This is a flowchart illustrating an operation method of a memory system provided in an embodiment of the present disclosure. Detailed Implementation

[0036] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0037] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0038] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0039] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0040] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0041] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0042] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0043] Figure 1 This is a block diagram of an exemplary system 100 having memory according to an embodiment of this disclosure. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 1As shown, system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memories 104 and a memory controller 106. The host 108 may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 108 may be configured to send data to or receive data from the memory 104. The host 108 includes a host controller and a second interface for coupling with the memory controller 106; that is, the second interface may also be an interface for communication between the host and the memory controller.

[0044] In some embodiments, memory controller 106 is coupled to memory 104 and host 108 and is configured to control memory 104. Memory controller 106 can manage data stored in memory 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, memory controller 106 is designed to operate in high duty cycle environments, such as SSDs or embedded multimedia cards (eMMCs) used as data storage in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays.

[0045] The memory controller 106 can be configured to control the operation of the memory 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions relating to data stored or to be stored in the memory 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) relating to data read from or written to the memory 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory 104. The memory controller 106 can communicate with external devices (e.g., host 108) according to specific communication protocols. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), and Firewire. These interfaces can also be referred to as first interfaces (or front-end interfaces). Here, the first interface is the interface coupled to the aforementioned second interface of the host. In some embodiments, the memory controller 106 interacts with the memory 104 via multiple configured channels for command / data exchange. These channels are also referred to as back-end interfaces.

[0046] The memory controller 106 and one or more memories 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. Figure 2A In one example shown, the memory controller 106 and a single memory 104 can be integrated into the memory card 202. The memory card 202 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 can also include a connection between the memory card 202 and a host computer (e.g., Figure 1 The host 108) is coupled to the memory card connector 204. In such a... Figure 2B In another example shown, the memory controller 106 and multiple memories 104 can be integrated into the SSD 206. The SSD 206 may also include interfaces for connecting the SSD 206 to a host computer (e.g., Figure 1The SSD connector 208 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0047] Figure 3A This is a schematic diagram of the structure of a storage cell array of a three-dimensional NAND type memory according to an embodiment of the present disclosure, as shown below. Figure 3A As shown, the memory cell array of a three-dimensional NAND flash memory consists of several rows of parallel, staggered memory cell rows parallel to the gate isolation structure. Each pair of memory cell rows is separated by a gate isolation structure and an up-select gate isolation structure. Each memory cell row includes multiple memory strings. The gate isolation structure may include a first gate isolation structure and a second gate isolation structure. The first gate isolation structure divides the memory cell array into multiple memory blocks. Multiple second gate isolation structures can divide the memory blocks into multiple finger memory regions. An up-select gate isolation structure located in the middle of each finger memory region can divide the finger memory region into two parts, thereby dividing the finger memory region into two memory strings. Figure 3A The storage block shown contains 6 storage chips. In actual applications, the number of storage chips in a storage block is not limited to this.

[0048] It should be noted that, Figure 3A The number of cell rows between the gate isolation structure and the top-select gate isolation structure given is merely an exemplary example and is not intended to limit the number of cell rows contained in a single memory region of the three-dimensional NAND memory in this disclosure. In practical applications, the number of cell rows contained in a single memory region can be adjusted according to actual conditions, such as 2, 4, 8, 16, etc.

[0049] Figure 3B This is a schematic circuit diagram of an exemplary memory 300 including peripheral circuitry according to an embodiment of this disclosure. The memory 300 may be... Figure 1An example of memory 104 is provided. Memory 300 may include a memory cell array 301 and peripheral circuitry 302 coupled to the memory cell array 301. The memory cell array 301 is illustrated as a three-dimensional NAND-type memory cell array, wherein the memory cells 306 are provided in the form of an array of NAND memory strings 308, each NAND memory string 308 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0050] In some implementations, each memory cell 306 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 306 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC may store two bits per cell, three bits per cell (also known as a three-level cell (TLC)), or four bits per cell (also known as a four-level cell (QLC)). Each MLC can be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take one of three possible programming levels from the erase state by writing one of the three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for the erase state.

[0051] like Figure 3BAs shown, each NAND memory string 308 may include a lower select gate (BSG) 310 at its source end and an upper select gate (TSG) 312 at its drain end. BSG 310 and TSG 312 may be configured to activate a selected NAND memory string 308 during read and program operations. In some embodiments, the sources of NAND memory strings 308 within the same memory block 304 are coupled via a common source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 308 within the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each NAND memory string 308 is coupled to a corresponding bit line (BL) 316, from which data can be read or written via an output bus (not shown). In some implementations, each NAND memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having TSG 312) or a deselection voltage (e.g., 0V) to the corresponding TSG 312 via one or more TSG lines 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having BSG 310) or a deselection voltage (e.g., 0V) to the corresponding BSG 310 via one or more BSG lines 315.

[0052] like Figure 3B As shown, NAND memory strings 308 can be organized into multiple memory blocks 304, each of which may have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is the basic data unit for an erase operation, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase memory cells 306 in a selected memory block, an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)) can be used to bias and couple the source line 314 of the selected memory block and the unselected memory blocks on the same plane as the selected memory block. It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 306 of adjacent NAND memory strings 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations.

[0053] Figure 4 This is a schematic cross-sectional view of an exemplary memory cell array 301 including NAND memory strings 308 according to an embodiment of this disclosure. Figure 4As shown, the NAND memory string 308 may include a stacked structure 410, which includes multiple gate layers 411 and multiple insulating layers 412 stacked alternately in sequence, and a memory string 308 perpendicularly penetrating the gate layers 411 and insulating layers 412. The gate layers 411 and insulating layers 412 may be stacked alternately, with adjacent gate layers 411 separated by an insulating layer 412. The number of pairs of gate layers 411 and insulating layers 412 in the stacked structure 410 determines the number of memory cells included in the memory cell array 301.

[0054] The constituent materials of the gate layer 411 may include conductive materials. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, such as a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stack 410 may extend laterally as an upper select gate line, the gate layer 411 at the bottom of the stack 410 may extend laterally as a lower select gate line, and the gate layer 411 extending laterally between the upper and lower select gate lines may serve as a word line layer.

[0055] In some embodiments, the stacked structure 410 may be disposed on the semiconductor layer 401. The semiconductor layer 401 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0056] In some embodiments, the NAND memory string 308 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes channel vias filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0057] Return to reference Figure 3B The peripheral circuitry 302 can be coupled to the memory cell array 301 via bit line 316, word line 318, source line 314, BSG line 315, and TSG line 313. The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory cell array 301 by applying voltage and / or current signals to each selected memory cell 306 and sensing voltage and / or current signals from each target memory cell 306 via bit line 316, word line 318, source line 314, BSG line 315, and TSG line 313. The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. Figure 5 This is a schematic diagram of an exemplary memory device including a memory cell array and peripheral circuitry according to an embodiment of the present disclosure. The peripheral circuitry 302 includes a page buffer / sensor amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, it may also include... Figure 5 Additional peripheral circuitry not shown.

[0058] Control logic 512 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 514 can be coupled to control logic 512 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 516 can be coupled to control logic 512 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic 512, as well as to buffer status information received from control logic 512 and relay it to the host. Interface 516 can also be coupled to column decoder / bit line driver 506 via data bus 518 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory cell array 301. That is, interface 516 here is the interface coupled to the back-end interface of the aforementioned memory controller; that is, interface 516 can also be the interface for communication between the memory and the memory controller.

[0059] In some implementations, the page buffer / sensor amplifier 504 can be configured to read data from the memory cell array 301 and program (write) data to the memory cell array 301 according to control signals from the control logic 512. In one example, the page buffer / sensor amplifier 504 can store programming data (write data) to be programmed into memory cells 306 of the memory cell array 301. In another example, the page buffer / sensor amplifier 504 can perform a programming verification operation to ensure that data has been correctly programmed into memory cells 306 coupled to selected word lines 318. The column decoder / bit line driver 506 can be configured to be controlled by the control logic 512 and to select one or more NAND memory strings 308 by applying a bit line voltage generated from the voltage generator 510.

[0060] The row decoder / word line driver 508 can be configured to be controlled by control logic 512 and to select / deselect memory blocks 304 of the memory cell array 301 and to select / deselect word lines 318 of memory blocks 304. The row decoder / word line driver 508 can also be configured to drive word lines 318 using word line voltages generated from voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive BSG lines 315 and TSG lines 313. As described in detail below, the row decoder / word line driver 508 is configured to perform programming operations on memory cells 306 coupled to one or more selected word lines 318. The voltage generator 510 can be configured to be controlled by control logic 512 and to generate word line voltages (e.g., read voltage Vread, programming voltage Vpgm, pass voltage Vpass, channel boost voltage, verification voltage Vvrf, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0061] In some specific embodiments, the programming operation may include multiple stages. For example, the programming operation may include a first stage, a second stage, and a recovery stage. In the first stage, a channel boost voltage may be applied to the selected word line; in the second stage, a target programming voltage for each programming operation may be applied to the selected word line; in the recovery stage, the voltage may be reduced to the corresponding voltage, such as Vcc or Vdd, for both the non-selected and selected word lines. The recovery stage may achieve the purpose of step-down to the corresponding voltage through one or more steps, such as first reducing the voltage to an intermediate voltage, maintaining it at the intermediate voltage for a period of time, and then reducing the voltage to the corresponding voltage.

[0062] This disclosure provides a memory device, comprising: a memory cell array; multiple word lines; and peripheral circuitry coupled to the memory cell array via the multiple word lines. The peripheral circuitry is configured to: apply a first voltage to a first word line and a second word line among the multiple word lines during a first stage of programming operations; and apply a second voltage greater than the first voltage to the first word line and the second word line during a second stage of programming operations; wherein the first word line and the second word line are located on the same side of a selected word line among the multiple word lines.

[0063] In this embodiment, the voltage on the first word line and the second word line is raised in two steps to increase the voltage rise speed on the selected word line, thereby reducing the pulse width of the target programming voltage and thus reducing programming time.

[0064] In some embodiments, the selected word line can be any one of multiple word lines in the memory cell array. The first word line and the second word line are unselected word lines, and the first word line and the second word line are located on the same side of the selected word line. The second voltage can be a target pass voltage (Vpass_target), which can be applied to the unselected word line to connect the unselected memory cell connected to the unselected word line. The first voltage can be an intermediate voltage (Vpass_middle) that is less than the target pass voltage (Vpass_target).

[0065] Figure 6 This is a schematic diagram of the voltage timing corresponding to each element at different stages of the programming loop in one embodiment of the present disclosure. Figure 1 .like Figure 6 As shown, the selected word line is WLn, the first word line is WLn+1, and the second word line is WLn+2. In the first stage, WLn+1 and WLn+2 will rise from Vss to the first voltage. In the second stage, WLn+1 and WLn+2 will continue to rise from the first voltage to the second voltage.

[0066] Figure 7 This is a cross-sectional schematic diagram of a memory string according to an embodiment of this application. It should be noted that... Figure 7 Let's take reverse programming as an example. Figure 7 As shown, each memory string 308 includes a plurality of memory cells 306 that are series-coupled and vertically stacked. The memory string 308 also includes at least one field-effect transistor (e.g., MOSFET) at each end, controlled by a BSG and a TSG, respectively. The memory cells 306 can be controlled by a control gate, which can be connected to a word line. The TSG can be connected to a bit line, while the BSG can be connected to a source line. Here, Figure 7 Examples of word lines in which the plurality of memory cells 306 included in the memory string 308 are sequentially connected are WL0, WL2, ..., WLn, ..., WLm. In some embodiments, the programming operation includes sequentially programming from the word line adjacent to the bit line (such as WL0) to the word line adjacent to the source line (such as WLm) (also known as reverse programming).

[0067] In other embodiments, the programming operation includes sequentially programming from the word line adjacent to the source line to the word line adjacent to the bit line (also known as forward programming).

[0068] In some embodiments, the memory cells connected to the first word line and the second word line are in an unprogrammed state. Figure 6 and Figure 7 As shown, this programming operation is reverse programming, and the memory cells connected to WLn+1 and WLn+2 are in an unprogrammed state.

[0069] It should be noted that the embodiments disclosed herein are illustrated using reverse programming as an example of programming operations.

[0070] In some embodiments, the voltage Vpass can be generated by a first voltage generator. The first voltage generator is subordinate to the aforementioned voltage generator 510 and is used to generate a first voltage in a first stage and a second voltage in a second stage for application on the first word line and the second word line.

[0071] In this embodiment of the present disclosure, when applying the pass voltage Vpass, an intermediate voltage, namely the first voltage, is first applied to the unselected word line, and then the target pass voltage is applied to the unselected word line, so that the unselected word line is boosted from the intermediate voltage to the target pass voltage. In other words, in this embodiment of the present disclosure, the voltage on the first word line and the second word line is boosted to the target pass voltage in two steps.

[0072] Because there is coupling capacitance between the selected and unselected word lines, applying a pass voltage Vpass to the unselected word line can cause the voltage on the selected word line to rise. The timing of capacitive coupling between the selected and unselected word lines can be controlled by adjusting the timing of the second rise of the pass voltage Vpass (i.e., the timing of applying the target pass voltage). This capacitive coupling effect can be used to increase the rise rate of the voltage on the selected word line (e.g., the rise rate of the target programming voltage), thereby reducing the pulse width of the programming voltage Vpgm and consequently reducing the programming time tPROG.

[0073] In this embodiment of the disclosure, the peripheral circuit is configured to: apply a first voltage to a third word line among a plurality of word lines in a first stage; and apply a second voltage to the third word line in a second stage; wherein the first word line, the second word line, and the third word line are located on the same side of the selected word line.

[0074] Continue to refer to Figure 6 The third line is WLn+3. In the first stage, WLn+3 will rise from Vss to the first voltage. In the second stage, WLn+3 will continue to rise from the first voltage to the second voltage.

[0075] In some embodiments, a first voltage generator is used to generate a first voltage in a first stage and a second voltage in a second stage for application on a first word line, a second word line, and a third word line.

[0076] In some embodiments, the memory cell connected to the third word line is in an unprogrammed state.

[0077] In some embodiments, the first character line, the second character line, and the third character line are respectively adjacent character lines, and the first character line is the character line adjacent to the selected character line.

[0078] In this embodiment of the disclosure, the peripheral circuit is configured to: apply a third voltage to a third word line among a plurality of word lines in a first stage; and apply a fourth voltage greater than the third voltage to the third word line in a second stage; wherein the first word line, the second word line, and the third word line are located on the same side of the selected word line.

[0079] In some embodiments, the fourth voltage may be the target pass voltage, and the third voltage may be an intermediate voltage that is less than the target pass voltage.

[0080] Figure 8 This is a schematic diagram showing the voltage timing of each component at different stages of the programming loop in one embodiment of this disclosure. For example... Figure 8 As shown, the selected word line is WLn, the first word line is WLn+1, the second word line is WLn+2, and the third word line is WLn+3. In the first stage, WLn+1 and WLn+2 will rise from Vss to the first voltage, and WLn+3 will rise from Vss to the third voltage. In the second stage, WLn+1 and WLn+2 will continue to rise from the first voltage to the second voltage, and WLn+3 will continue to rise from the third voltage to the fourth voltage.

[0081] In some embodiments, the third voltage is equal to the first voltage, and the fourth voltage is different from the second voltage.

[0082] In some embodiments, the first voltage can be in the range of 3V to 5V, and the third voltage can be equal to the first voltage. In a specific example, the first and third voltages can be 4V. The second voltage can be in the range of 5V to 11V, and the fourth voltage can be in the range of 5V to 11V. In a specific example, the second voltage can be greater than the fourth voltage.

[0083] In some embodiments, where the fourth voltage differs from the second voltage, the third and fourth voltages can be generated by a second voltage generator. This second voltage generator is subordinate to the aforementioned voltage generator 510 and is used to generate the third voltage in a first stage and the fourth voltage in a second stage for application to the third word line. In other words, the voltages on the third word line are generated by different voltage generators than those on the first and second word lines.

[0084] In this embodiment of the disclosure, the peripheral circuit is configured to: apply a fifth voltage to the fourth word line among a plurality of word lines in a first stage; and apply a sixth voltage greater than the fifth voltage to the fourth word line in a second stage; wherein the fourth word line is located on a different side of the selected word line from the first word line and the second word line.

[0085] In some embodiments, the memory cell connected to the fourth word line is in a programmed state.

[0086] In some embodiments, the fourth character line is a character line adjacent to the selected character line, and the fourth character line and the first character line are located on different sides of the selected character line.

[0087] In some embodiments, the sixth voltage may be the target pass voltage, and the fifth voltage may be an intermediate voltage that is less than the target pass voltage.

[0088] Continue to refer to Figure 6 and Figure 8 The fourth line is WLn-1. In the first stage, WLn-1 will rise from Vss to the fifth voltage. In the second stage, WLn-1 will continue to rise from the fifth voltage to the sixth voltage.

[0089] In some embodiments, the first voltage and the fifth voltage are equal, and the second voltage is greater than the sixth voltage.

[0090] In some embodiments, the fifth voltage can be in the range of 3V to 5V, and the fifth voltage can be equal to the first voltage. In a specific example, the first voltage, the third voltage, and the fifth voltage can be equal.

[0091] The sixth voltage can be in the range of 5V to 11V.

[0092] In some embodiments, the difference between the first voltage and the fifth voltage is less than or equal to 1V.

[0093] Since the first word line and the fourth word line are both adjacent to the selected word line, and the fourth word line and the first word line are located on different sides of the selected word line, the difference between the voltage applied to the first word line and the fourth word line needs to be controlled within a certain range (such as within 1V) to avoid affecting the selected word line.

[0094] In some embodiments, the fifth voltage can be in the range of 3V to 5V. In a specific example, the first voltage can be greater than the fifth voltage.

[0095] In some embodiments, on the same memory string, the greater the distance from the selected word line, the smaller the target voltage applied to the word line.

[0096] In some embodiments, multiple target pass voltages, including a second voltage, a fourth voltage, and a sixth voltage, can be applied to corresponding word lines. During programming operations, all word lines in the memory string can be divided into multiple regions. Different target pass voltages can be applied to word lines in different regions to achieve individual control of the target pass voltage. This dynamic control of applying different target pass voltages based on the word line location can significantly reduce pass voltage Vpass interference.

[0097] In this embodiment of the disclosure, the peripheral circuitry is configured to: apply a channel boost voltage to a selected word line in a first stage; and apply a target programming voltage to the selected word line in a second stage.

[0098] In some embodiments, the channel boost voltage can be in the range of 6V to 11V, and the channel boost voltage can be greater than the first voltage.

[0099] Continue to refer to Figure 6 and Figure 8 In the first stage, WLn will rise from Vss to the channel boost voltage. In the second stage, WLn will continue to rise from the channel boost voltage to the target programming voltage.

[0100] In some embodiments, the programming voltage Vpgm can be generated by a third voltage generator. The third voltage generator is subordinate to the aforementioned voltage generator 510 and is used to generate a channel boost voltage in a first stage and a target programming voltage in a second stage for application to a selected word line.

[0101] In this embodiment, incremental step-pulse programming (ISPP) can be used to program the memory device. Specifically, during the target state programming operation, a first programming voltage is first applied to the selected word line, and then a verification operation is performed on the selected memory cells connected to the selected word line to check whether the threshold voltage of each selected memory cell connected to the selected word line reaches the target threshold voltage. If the number of selected memory cells that have not been programmed to the target threshold voltage is greater than an allowable range, a second programming voltage with a higher voltage is applied again, and the verification operation is performed again after applying the second programming voltage. The process of applying programming pulses and performing verification operations is repeated until the number of selected memory cells that have not been programmed to the target threshold voltage is within an allowable range, at which point programming ends.

[0102] In this embodiment of the disclosure, when applying the programming voltage, a channel boost voltage is first applied to the selected word line, and then the target programming voltage is applied to the selected word line, so that the selected word line is boosted from the channel boost voltage to the target programming voltage, which can effectively achieve voltage buffering and reduce damage to the device.

[0103] In some embodiments, the application time of the target programming voltage and the application time of the second voltage are the same. In other embodiments, the application time of the target programming voltage and the application time of the second voltage are different; for example, the application time of the target programming voltage is earlier than the application time of the second voltage.

[0104] Continue to refer to Figure 6 and Figure 8The second stage includes time T1 and time T2. At time T1, a programming voltage is applied to the selected word line WLn, and at time T2, a second voltage is applied to the first word line WLn+1 and the second word line WLn+2.

[0105] As programming voltage increases in the later stages, its rise rate gradually decreases; in other words, a higher programming voltage results in a slower rise rate. Specifically, in the second stage of programming, the voltage rise applied to the selected word line can have two slope stages. The slope of the slope stage starting with the channel boost voltage is greater than the slope of the slope stage ending with the target programming voltage. For example, in the second stage of programming, the selected word line will continue to rise from the channel boost voltage (e.g., 6V) to the target programming voltage (e.g., 20V). The rise from 6V to 20V includes two slope stages: a slope stage starting with the channel boost voltage (e.g., from 6V to 15V) and a slope stage ending with the target programming voltage (e.g., from 15V to 20V). The slope of the rise from 6V to 15V is greater than the slope of the rise from 15V to 20V. That is, the voltage rise rate from 15V to 20V should be less than the voltage rise rate from 6V to 15V. To improve the voltage rise rate of the selected word line from 15V to 20V, the target pass voltage is applied later than the target programming voltage, so that capacitive coupling between the selected and unselected word lines occurs during the selected word line's rise from 15V to 20V.

[0106] In this embodiment, the application timing of the target pass voltage and the target programming voltage can be controlled so that the capacitive coupling between the selected word line and the unselected word line occurs in the later stage of the selected word line's rise from the channel boost voltage to the target programming voltage, thereby increasing the voltage rise speed of the selected word line. This reduces the pulse width of the programming voltage Vpgm, thereby reducing the programming time tPROG.

[0107] In some embodiments, the interval between the application of the target programming voltage and the application of the second voltage is 7-10 microseconds. (Continue to refer to...) Figure 6 and Figure 8 The interval between time T1 and time T2 is 7-10 microseconds. The time interval between time T1 and time T2 is related to the voltage rise during the period when the selected word line rises from the channel boost voltage to the target programming voltage.

[0108] In this embodiment of the disclosure, the time interval between the application time of the target programming voltage and the application time of the second voltage can be determined based on the voltage rise during the period when the selected word line rises from the channel boost voltage to the target programming voltage.

[0109] In this embodiment of the disclosure, the peripheral circuit is configured to: apply a fifth voltage to the fifth word line and the sixth word line among a plurality of word lines in a first stage; wherein the fifth word line is located on the side of the fourth word line away from the selected word line, and the sixth word line is located on the side of the third word line away from the selected word line.

[0110] In some embodiments, the fifth voltage can be the target pass voltage, and the fifth voltage can be different from the second voltage. The fifth voltage can be in the range of 3V to 11V. In a specific example, the second voltage can be greater than the fifth voltage.

[0111] Continue to refer to Figure 6 and Figure 8 The fifth word line is WLn-2, ​​and the sixth word line is WLn+4. In the first stage, WLn-2 and WLn+4 will rise from Vss to the fifth voltage. In the second stage, WLn-2 and WLn+4 will maintain the fifth voltage.

[0112] Since the fifth and sixth word lines are farther away from the selected word line compared to the first to fourth word lines, their influence on the selected word line is weaker. Therefore, the voltage on the fifth, sixth, and other word lines located on the side of the fifth and sixth word lines that are farther away from the selected word line is increased to the target pass voltage in one step.

[0113] In this embodiment of the disclosure, the timing of capacitive coupling between the selected word line and the unselected word line is controlled by controlling the timing of the second-step rise of the through voltage Vpass (i.e., the timing of applying the target through voltage). In this way, the rise speed of the voltage on the selected word line (such as the rise speed of the target programming voltage) can be increased by utilizing the capacitive coupling effect, thereby reducing the pulse width of the programming voltage Vpgm, which in turn reduces the programming time tPROG.

[0114] In some embodiments, the memory device includes a three-dimensional NAND type memory.

[0115] However, the memory device in this disclosure is not limited to three-dimensional NAND type memory. In this disclosure, the memory device can be a semiconductor memory, including but not limited to three-dimensional NAND flash memory, vertical NAND flash memory, NOR flash memory, dynamic random access memory (DRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), phase change random access memory (PCRAM), resistive random access memory (RRAM), or nano random access memory (NRAM), etc.

[0116] This disclosure also provides a memory system, which includes: one or more memory devices as described in any of the above embodiments; and a memory controller; the memory controller is coupled to the memory device and is used to control the memory device.

[0117] Here, the specific structure and composition of the memory system can be referred to the foregoing. Figure 1 , Figure 2A , Figure 2B The relevant structure and composition of the memory system 102 are described below. For the sake of brevity, they will not be elaborated here.

[0118] In some embodiments, the memory system includes a memory card or a solid-state drive.

[0119] Based on the above-described memory device, this disclosure also provides a method for operating the memory device, such as... Figure 9 As shown, the method includes:

[0120] Step 901: In the first stage of the programming operation, a first voltage is applied to the first word line and the second word line among the multiple word lines;

[0121] Step 902: In the second stage of the programming operation, a second voltage greater than the first voltage is applied to the first word line and the second word line; wherein the first word line and the second word line are located on the same side of a selected word line among a plurality of word lines.

[0122] In some embodiments, the method further includes: in a first stage, applying a first voltage to a third word line among a plurality of word lines; in a second stage, applying a second voltage to the third word line; wherein the first word line, the second word line, and the third word line are located on the same side of the selected word line.

[0123] In some embodiments, the method further includes: in a first stage, applying a third voltage to a third word line among a plurality of word lines; in a second stage, applying a fourth voltage greater than the third voltage to the third word line; wherein the first word line, the second word line, and the third word line are located on the same side of the selected word line.

[0124] In some embodiments, the third voltage is equal to the first voltage, and the fourth voltage is different from the second voltage.

[0125] In some embodiments, the memory cells connected to the first word line, the second word line, and the third word line are in an unprogrammed state.

[0126] In some embodiments, the method further includes: in a first stage, applying a fifth voltage to a fourth word line among a plurality of word lines; in a second stage, applying a sixth voltage greater than the fifth voltage to the fourth word line; wherein the fourth word line is located on a different side of the selected word lines from the first word line and the second word line.

[0127] In some embodiments, the first voltage and the fifth voltage are equal, and the second voltage is greater than the sixth voltage.

[0128] In some embodiments, the difference between the first voltage and the fifth voltage is less than or equal to 1V.

[0129] In some embodiments, the method further includes: in a first stage, applying a channel boost voltage to selected word lines; and in a second stage, applying a target programming voltage to selected word lines.

[0130] In some embodiments, the target programming voltage is applied earlier than the second voltage.

[0131] In some embodiments, the method further includes: in a first stage, applying a fifth voltage to a fifth word line and a sixth word line among a plurality of word lines; wherein the fifth word line is located on the side of the fourth word line away from the selected word line, and the sixth word line is located on the side of the third word line away from the selected word line.

[0132] Since the contents and structures involved in the description of the memory device in any embodiment above are fully or partially applicable to the operation methods of the memory device described herein, related or similar contents will not be repeated here.

[0133] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0134] The above description is merely a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. Any equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A memory device, characterized in that, The memory device includes: Storage cell array; Multiple letter lines; The peripheral circuitry is coupled to the memory cell array via the multiple word lines, and the peripheral circuitry is configured as follows: In the first stage of the programming operation, a first voltage is applied to the first word line and the second word line among the plurality of word lines; In the second stage of the programming operation, a second voltage greater than the first voltage is applied to the first word line and the second word line; wherein the first word line and the second word line are located on the same side of a selected word line among the plurality of word lines.

2. The memory device according to claim 1, characterized in that, The peripheral circuit is configured as follows: In the first stage, the first voltage is applied to the third word line among the plurality of word lines; In the second stage, the second voltage is applied to the third word line; wherein the first word line, the second word line, and the third word line are located on the same side of the selected word line.

3. The memory device according to claim 1, characterized in that, The peripheral circuit is configured as follows: In the first stage, the third voltage is applied to the third word line among the plurality of word lines; In the second stage, a fourth voltage greater than the third voltage is applied to the third word line; wherein the first word line, the second word line, and the third word line are located on the same side of the selected word line.

4. The memory device according to claim 2 or 3, characterized in that, The peripheral circuitry includes: control logic and a first voltage generator and a second voltage generator coupled to the control logic. The control logic is configured to: control the first voltage generator to generate the first voltage, control the second voltage generator to generate the third voltage, apply the first voltage to the first word line and the second word line in the first stage, and apply the third voltage to the third word line; control the first voltage generator to generate the second voltage, control the second voltage generator to generate the fourth voltage, apply the second voltage to the first word line and the second word line in the second stage, and apply the fourth voltage to the third word line.

5. The memory device according to claim 2 or 3, characterized in that, The memory cells connected to the first word line, the second word line, and the third word line are in an unprogrammed state.

6. The memory device according to claim 2 or 3, characterized in that, The peripheral circuit is configured as follows: In the first stage, a fifth voltage is applied to the fourth word line among the plurality of word lines; In the second stage, a sixth voltage greater than the fifth voltage is applied to the fourth word line; wherein the fourth word line is located on a different side from the first word line and the second word line.

7. The memory device according to claim 1, characterized in that, The peripheral circuit is configured as follows: In the first stage, a channel boost voltage is applied to the selected word line; In the second stage, a target programming voltage is applied to the selected word line.

8. The memory device according to claim 7, characterized in that, The target programming voltage is applied earlier than the second voltage.

9. The memory device according to claim 6, characterized in that, The peripheral circuit is configured as follows: In the first stage, a fifth voltage is applied to the fifth and sixth word lines among the plurality of word lines; wherein the fifth word line is located on the side of the fourth word line away from the selected word line, and the sixth word line is located on the side of the third word line away from the selected word line.

10. The memory device according to claim 6, characterized in that, The memory device further includes: bit lines and source lines; The programming operation includes programming sequentially from the word line adjacent to the source line to the word line adjacent to the bit line, or programming sequentially from the word line adjacent to the bit line to the word line adjacent to the source line.

11. A memory system, characterized in that, include: The memory device as claimed in any one of claims 1 to 10; as well as Memory controller; The memory controller is coupled to the memory device and is used to control the memory device.

12. A method of operating a memory device, characterized in that, The operation method includes: In the first stage of the programming operation, a first voltage is applied to the first word line and the second word line among the plurality of word lines; In the second stage of the programming operation, a second voltage greater than the first voltage is applied to the first word line and the second word line; wherein the first word line and the second word line are located on the same side of a selected word line among the plurality of word lines.

13. The method of operating the memory device according to claim 12, characterized in that, The method further includes: In the first stage, the first voltage is applied to the third word line among the plurality of word lines; In the second stage, the second voltage is applied to the third word line; wherein the first word line, the second word line, and the third word line are located on the same side of the selected word line.

14. The method of operating the memory device according to claim 12, characterized in that, The method further includes: In the first stage, the third voltage is applied to the third word line among the plurality of word lines; In the second stage, a fourth voltage greater than the third voltage is applied to the third word line; wherein the first word line, the second word line, and the third word line are located on the same side of the selected word line.

15. The method of operating the memory device according to claim 13 or 14, characterized in that, The memory cells connected to the first word line, the second word line, and the third word line are in an unprogrammed state.

16. The method of operating the memory device according to claim 13 or 14, characterized in that, The method further includes: In the first stage, a fifth voltage is applied to the fourth word line among the plurality of word lines; In the second stage, a sixth voltage greater than the fifth voltage is applied to the fourth word line; wherein the fourth word line is located on a different side from the first word line and the second word line.

17. The method of operating the memory device according to claim 12, characterized in that, The method further includes: In the first stage, a channel boost voltage is applied to the selected word line; In the second stage, a target programming voltage is applied to the selected word line.

18. The method of operating the memory device according to claim 17, characterized in that, The target programming voltage is applied earlier than the second voltage.

19. The method of operating a memory device according to claim 16, characterized in that, The method further includes: In the first stage, a fifth voltage is applied to the fifth and sixth word lines among the plurality of word lines; wherein the fifth word line is located on the side of the fourth word line away from the selected word line, and the sixth word line is located on the side of the third word line away from the selected word line.

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