Large-scale screening and testing system for stored particles
By performing bidirectional electrical excitation and acquisition on the pins of the memory chip, the problem of traditional unidirectional criteria being unable to identify complex defects is solved, achieving efficient and sensitive screening results, which is suitable for the whole life cycle quality control of memory chips.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-09
- Publication Date
- 2026-03-20
AI Technical Summary
Traditional one-way or threshold-based criteria are insufficient to effectively identify complex and hidden defects in memory chips during the R&D stage, leading to frequent missed detections.
A bidirectional electrical excitation and acquisition mechanism is adopted. The main control unit generates synchronous control signals and uses an adjustable constant voltage source and a high-precision analog-to-digital converter (ADC) to perform forward and reverse tests on each pin of the storage chip, acquire electrical response values, and compare them with pre-stored good product benchmark data.
It significantly improves the ability to detect covert and directional failure modes, provides high-sensitivity and high-data-fidelity quality control, and is suitable for screening throughout the entire lifecycle from R&D to mass production.
Smart Images
Figure CN121709005A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor testing technology, and more specifically to a large-scale screening and testing system for memory chips. Background Technology
[0002] In the semiconductor manufacturing process, packaging and testing (referred to as "packaging and testing") are critical steps to ensure chip reliability. To prevent chip particles with physical or electrical defects (such as open circuits, short circuits, or internal structural damage) from damaging the automated test equipment (ATE) during subsequent power-on functional testing, the industry typically sets up a non-power-on screening process before functional testing to quickly identify and reject obviously abnormal devices.
[0003] A widely used low-cost initial screening method employs a microcontroller unit (MCU) in conjunction with a high-precision analog-to-digital converter (ADC). It assesses the electrical integrity of the pins by measuring their current or voltage responses under a fixed bias voltage. This method is based on the well-established fact that most memory chips (such as LPDDR, eMMC, and NAND Flash) integrate electrostatic discharge (ESD) protection circuitry within their input / output (I / O) pins. A typical structure includes a pair of anti-parallel PN junction diodes (i.e., diodes with their anode and cathode connected), causing the pins to exhibit distinguishable and repeatable nonlinear current-voltage (IV) characteristics under forward and reverse bias. By collecting the forward and reverse response data of each pin from known functional "good" chips in the same batch as a benchmark template, the chips under test can be compared and identified.
[0004] This solution offers significant advantages in the mass production stage: stable product design, mature process, high yield, and easy acquisition of reliable benchmark data; simultaneously, the multi-channel synchronous testing architecture can greatly improve screening throughput. However, in the chip development stage, traditional unidirectional or threshold-based criteria are insufficient to effectively identify complex defects. Failure modes in mature products typically concentrate on a few known types, such as loose connections at specific solder joints or short circuits between pins. Chips in the development stage, however, may exhibit atypical electrical behaviors such as asymmetric leakage, abnormal parasitic parameters, and unidirectional conduction failures due to circuit design flaws, material inhomogeneities, or process fluctuations. These defects often only manifest under specific bias directions, making them highly susceptible to being missed if relying solely on a single measurement or simple amplitude comparison.
[0005] Therefore, there is an urgent need for a testing mechanism that can comprehensively characterize the bidirectional electrical characteristics of pins in order to improve the ability to detect complex and hidden defects. Summary of the Invention
[0006] To address the shortcomings of existing technologies, the present invention aims to provide a large-scale screening and testing system for storage particles, thereby solving the problem that traditional unidirectional or threshold-based criteria are insufficient to effectively identify complex defects.
[0007] To solve the above-mentioned technical problems, the present invention is implemented through the following solution:
[0008] The present invention provides a large-scale screening and testing system for storage particles, comprising:
[0009] The main control unit uses a microcontroller (MCU) to generate synchronous control signals;
[0010] An adjustable constant voltage source is configured to output a fixed amplitude DC voltage throughout a single complete test cycle.
[0011] K test channels are configured in parallel, where K is an integer greater than or equal to 1, and each test channel includes a pin switching circuit and a high-precision analog-to-digital converter (ADC).
[0012] The pin switching circuit consists of a first analog switch array and a second analog switch array, and is used to selectively connect any pin of the storage particle to the test circuit.
[0013] The high-precision analog-to-digital converter (ADC) is used to acquire the electrical response of the pins of the storage particle under different bias directions;
[0014] A communication interface, supporting at least one of serial port, network port or USB, is used to transmit the raw test data of each of the test channels to an external data processing device;
[0015] Specifically, for each pin of the storage chip, the main control unit controls the pin switching circuit in the corresponding test channel to sequentially perform forward and reverse tests;
[0016] Forward test: The positive terminal of the adjustable constant voltage source is connected to the pin of the test channel, and the negative terminal of the adjustable constant voltage source is grounded. The first response value is acquired through the high-precision analog-to-digital converter (ADC).
[0017] Reverse test: The positive terminal of the adjustable constant voltage source is grounded, and the negative terminal of the adjustable constant voltage source is connected to the pin of the test channel. The second response value is acquired through the high-precision analog-to-digital converter (ADC).
[0018] The first response value and the second response value are used to compare with the pre-stored good product benchmark data.
[0019] Preferably, the first analog switch array is a 1*M selection structure, and the second analog switch array is a 1*N selection structure. The combination of the two enables the selection and access of M*N pins on the memory chips, where M and N are positive integers.
[0020] Preferably, all the test channels synchronously perform forward and reverse tests on the same pin number on the memory chip in each test cycle, with the main control unit issuing the control timing uniformly.
[0021] Preferably, the memory chip is a packaged chip with an internal ESD protection structure, including LPDDR, DDR, eMMC or NAND Flash chips, and the I / O pins of the memory chip contain a pair of anti-parallel PN junction diodes.
[0022] Preferably, the data storage module retains the first response value and the second response value from the most recent complete test when the large-scale screening test system for the storage particles experiences a power outage or communication failure.
[0023] Preferably, the large-scale screening test system further includes a data storage module, which is used to locally cache the original test data of each of the test channels;
[0024] The first response value and the second response value are compared with the pre-stored good product benchmark data to obtain the comparison result;
[0025] The external data processing device includes a host computer and a robotic arm controlled by the host computer. The host computer generates sorting instructions based on the comparison results and controls the robotic arm to physically sort the stored particles into qualified and defective products.
[0026] Preferably, the adjustable constant voltage source is connected in series with a current-limiting resistor R.
[0027] Compared with the prior art, the beneficial effects of the present invention are:
[0028] This invention fundamentally overcomes the limitations of traditional unidirectional or threshold criteria in identifying asymmetric defects by forcibly implementing bidirectional electrical excitation and acquisition at the hardware level. It is not only suitable for efficient screening in the mass production stage, but also particularly suited to the chip R&D stage's requirements for high sensitivity, high data fidelity, and flexible adaptability, providing reliable technical support for quality control throughout the entire lifecycle from engineering verification to mass production implementation.
[0029] The first and second response values of each pin in the storage chip together constitute its bidirectional electrical characteristics. These characteristics are transmitted to an external data processing device, such as a host computer, via a communication interface and compared with pre-stored benchmark data of a good chip of the same model. If the deviation exceeds the tolerance range, the chip is determined to have an electrical defect and is discarded. Through two independent measurements—forward and reverse—the electrical response of each pin under bidirectional bias is fully acquired; this effectively identifies asymmetric defects such as weak leakage only under reverse bias, or abnormal forward conduction but normal reverse conduction; compared to traditional single measurements, it significantly improves the detection capability for concealed and directional failure modes. The adjustable constant voltage source maintains a fixed test voltage throughout, eliminating noise introduced by voltage fluctuations; the high-precision analog-to-digital converter (ADC) can distinguish microampere-level current differences, is sensitive to early weak defects, and provides reliable quantitative evidence for device characteristic drift during the R&D stage. K parallel channels support a smooth transition from small-batch verification to mass production screening. The pin switching circuit uses an M*N switch array to adapt to memory chips with different pin counts, such as LPDDR, eMMC, or NAND, without the need to redesign the hardware. Attached Figure Description
[0030] Figure 1 This is a schematic diagram illustrating the principle of a large-scale screening and testing system for storage particles according to the present invention.
[0031] Figure 2 This is a schematic diagram showing the connection between a high-precision analog-to-digital converter (ADC) and a storage particle in a large-scale screening and testing system for storage particles according to the present invention.
[0032] Figure 3 This is a schematic diagram of the principle of a single test channel in a large-scale screening test system for storage particles according to the present invention. Detailed Implementation
[0033] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings, so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making a clearer and more definite definition of the scope of protection of the present invention. Obviously, the embodiments described in this invention are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0034] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.
[0035] Example 1: The specific content of the present invention is as follows:
[0036] like Figure 1 , Figure 2 and Figure 3 As shown, a large-scale screening and testing system for memory chips includes: a main control unit, employing a microcontroller (MCU), for generating synchronous control signals; an adjustable constant voltage source, configured to output a DC voltage of fixed amplitude during a single complete test cycle; K parallel test channels, where K is an integer greater than or equal to 1, each test channel including a pin switching circuit and a high-precision analog-to-digital converter (ADC); the pin switching circuit, composed of a first analog switch array and a second analog switch array, is used to selectively connect any pin of the memory chip to the test circuit; the high-precision ADC is used to acquire the electrical response of the memory chip's pins under different bias directions; and a communication interface, supporting at least one of serial port, Ethernet port, or USB, for transmitting the raw test data of each test channel to an external data processing device.
[0037] Specifically, for each pin of the storage particle, the main control unit controls the pin switching circuit in the corresponding test channel to sequentially perform forward and reverse tests; Forward test: the positive terminal of the adjustable constant voltage source is connected to the pin of the test channel, and the negative terminal of the adjustable constant voltage source is grounded, and a first response value is acquired through the high-precision analog-to-digital converter (ADC); Reverse test: the positive terminal of the adjustable constant voltage source is grounded, and the negative terminal of the adjustable constant voltage source is connected to the pin of the test channel, and a second response value is acquired through the high-precision analog-to-digital converter (ADC); The first response value and the second response value are used to compare with pre-stored good product benchmark data.
[0038] In this embodiment, the first and second response values of each pin of the storage chip together constitute its bidirectional electrical characteristics. These characteristics are transmitted to an external data processing device, such as a host computer, via a communication interface and compared with pre-stored benchmark data of a good chip of the same model. If the deviation exceeds the tolerance range, the chip is determined to have an electrical defect and is discarded. Through two independent measurements—forward and reverse—the electrical response of each pin under bidirectional bias is fully acquired; this effectively identifies asymmetric defects such as weak leakage only under reverse bias, or abnormal forward conduction but normal reverse conduction; compared to traditional single measurements, this significantly improves the detection capability for concealed and directional failure modes. The adjustable constant voltage source maintains a fixed test voltage throughout, eliminating noise introduced by voltage fluctuations; the high-precision analog-to-digital converter (ADC) can distinguish microampere-level current differences, is sensitive to early weak defects, and provides reliable quantitative evidence for device characteristic drift during the R&D stage. K parallel channels support a smooth transition from small-batch verification to mass production screening. The pin switching circuit uses an M*N switch array to adapt to memory chips with different pin counts, such as LPDDR, eMMC, or NAND, without the need to redesign the hardware.
[0039] This invention fundamentally overcomes the limitations of traditional unidirectional or threshold criteria in identifying asymmetric defects by forcibly implementing bidirectional electrical excitation and acquisition at the hardware level. It is not only suitable for efficient screening in the mass production stage, but also particularly suited to the chip R&D stage's requirements for high sensitivity, high data fidelity, and flexible adaptability, providing reliable technical support for quality control throughout the entire lifecycle from engineering verification to mass production implementation.
[0040] Furthermore, the first analog switch array is a 1*M selection structure, and the second analog switch array is a 1*N selection structure. The combination of the two enables the selection and access of M*N pins on the memory chip, where M and N are positive integers.
[0041] In this embodiment, the first and second analog switch arrays are cross-connected, typically using AND gates or direct interconnection, to form an M*N switch network, thereby creating M*N independent signal path nodes. In actual testing: the main control unit (MCU) sends a row selection signal to the first analog switch array (e.g., selecting row i) and a column selection signal to the second analog switch array (e.g., selecting column j). Only when row i and column j are selected simultaneously is the corresponding cross-connection activated, connecting the (i,j)th pin of the storage chip or its numbered physical pin to the test circuit. The high-precision analog-to-digital converter (ADC) can then perform the aforementioned forward or reverse test on this pin. By traversing all M*N combinations, the system can automatically scan and cover up to M*N pins without requiring manual wiring changes.
[0042] Furthermore, all the test channels synchronously perform forward and reverse tests on the same pin number on the memory chip during each test cycle, with the main control unit issuing control timing uniformly.
[0043] In this embodiment, the system includes K parallel test channels, each independently connected to a memory chip under test. The main control unit (MCU) acts as the sole timing source, generating and broadcasting the same control signal to all test channels at the start of each test cycle. All test channels simultaneously perform tests on the same numbered pins of their respective connected memory chips. For example, all channels simultaneously test the 5th I / O pin: a forward test is performed by applying a forward bias and acquiring the first response value; then a reverse test is performed by applying a reverse bias and acquiring the second response value. After completing one round of bidirectional measurement, the main control unit switches to the next pin number and repeats the above process until all pins are traversed.
[0044] Furthermore, the memory chip is a packaged chip with an internal ESD protection structure, including LPDDR, DDR, eMMC or NAND Flash chips, and the I / O pins of the memory chip contain a pair of anti-parallel PN junction diodes.
[0045] In this embodiment, each I / O signal pin of mainstream memory chips such as LPDDR, DDR, eMMC, and NAND Flash integrates a pair of anti-parallel PN junction diodes. The anode and cathode are connected to the power rail and ground, respectively, or directly across the I / O pin and VSS / VDD. This structure is in the off state during normal operation but provides bidirectional clamping protection in the event of electrostatic discharge (ESD). A key characteristic is that this structure exhibits non-linear but repeatable conduction characteristics under both forward and reverse bias, forming a unique bidirectional I / O response curve. LPDDR, DDR, eMMC, and NAND Flash chips all employ similar ESD architectures, eliminating the need for remodeling for each chip type. Only the pin definitions and package sockets need to be adapted to reuse the same test logic, thus solving the industry pain point of "customized test solutions for different chips."
[0046] Furthermore, the data storage module retains the first response value and the second response value from the most recent complete test when the large-scale screening test system for the storage particles experiences a power outage or communication failure.
[0047] In this embodiment, after each forward and reverse test of a pin, the main control unit (MCU) immediately writes the complete set of bidirectional raw data into the data storage module, rather than simply storing it temporarily in volatile memory. If the system encounters a sudden power outage during testing, such as a mains power interruption or power supply failure; or if a communication anomaly occurs, such as a USB disconnection, network port timeout, or host computer crash, the main control unit can trigger an emergency save process using its internal watchdog or power monitoring circuit to ensure that the complete bidirectional test data from the last round is permanently stored. After the system restarts, historical data can be read from the storage module through the communication interface to restore the test state before the breakpoint, support the continuation of unfinished test tasks, perform failure reproduction analysis on abnormal batches, audit the original electrical response, and avoid misjudgments or omissions due to data loss.
[0048] Furthermore, the large-scale screening and testing system also includes a data storage module, which is used to locally cache the original test data of each test channel; the first response value and the second response value are compared with the pre-stored good product benchmark data to obtain the comparison result; the external data processing device includes a host computer and a robotic arm controlled by the host computer, the host computer generates sorting instructions according to the comparison result, and controls the robotic arm to physically sort the stored particles into qualified and defective products.
[0049] In this embodiment, the data storage module locally caches the original data to prevent data loss in case of power failure and supports post-event backtracking analysis. The original data is transmitted to an external data processing device via a communication interface such as USB or Ethernet. The host computer in this device performs multi-dimensional comparisons between the received bidirectional response values and pre-stored good product benchmark data, such as threshold windows, correlation analysis, and statistical distribution deviation, to generate structured comparison results, such as "Pass / Fail" or defect level.
[0050] The host computer automatically generates sorting instructions based on the comparison results, and drives the robotic arm or the actuator integrated into the sorting machine through control signals to transfer the stored particles that are judged as qualified products to the good product tray, and transfer the particles that are judged as defective products to the waste / analysis area, thus realizing fully automatic sorting without human intervention.
[0051] Furthermore, the adjustable constant voltage source is connected in series with a current-limiting resistor R.
[0052] In this embodiment, the adjustable constant voltage source is not directly connected to the pin of the memory chip under test. Instead, a fixed or configurable current-limiting resistor R is connected in series in its output circuit. When a forward or reverse bias voltage is applied to the pin under test, if the pin has a hard defect such as a short circuit, breakdown, or severe leakage, the current will rise sharply. At this time, the current-limiting resistor R naturally limits the maximum current in the circuit through Ohm's law, preventing excessive current from flowing through the internal structure of the chip. This prevents the chip from overheating, melting, or secondary damage due to defective pins, which is especially important for unpackaged or engineering samples. At the same time, it protects the pin switching circuit and high-precision analog-to-digital converter (ADC) and other precision front-end circuits from surge current impact, improving the long-term operational reliability of the system.
[0053] The above description is only a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.
Claims
1. A large-scale screening and testing system for storage particles, characterized in that, include: The main control unit uses a microcontroller (MCU) to generate synchronization control signals; An adjustable constant voltage source is configured to output a fixed amplitude DC voltage throughout a single complete test cycle. K test channels are configured in parallel, where K is an integer greater than or equal to 1, and each test channel includes a pin switching circuit and a high-precision analog-to-digital converter (ADC). The pin switching circuit consists of a first analog switch array and a second analog switch array, and is used to selectively connect any pin of the storage particle to the test circuit. The high-precision analog-to-digital converter (ADC) is used to acquire the electrical response of the pins of the storage chip under different bias directions; A communication interface, supporting at least one of serial port, network port or USB, is used to transmit the raw test data of each of the test channels to an external data processing device; Specifically, for each pin of the storage chip, the main control unit controls the pin switching circuit in the corresponding test channel to sequentially perform forward and reverse tests; Forward test: The positive terminal of the adjustable constant voltage source is connected to the pin of the test channel, and the negative terminal of the adjustable constant voltage source is grounded. The first response value is acquired through the high-precision analog-to-digital converter (ADC). Reverse test: The positive terminal of the adjustable constant voltage source is grounded, and the negative terminal of the adjustable constant voltage source is connected to the pin of the test channel. The second response value is acquired through the high-precision analog-to-digital converter (ADC). The first response value and the second response value are used to compare with the pre-stored good product benchmark data.
2. The large-scale screening and testing system for storage particles according to claim 1, characterized in that, The first analog switch array is a 1*M selection structure, and the second analog switch array is a 1*N selection structure. The combination of the two realizes the selection and access of M*N pins on the memory chip, where M and N are positive integers.
3. The large-scale screening and testing system for storage particles according to claim 1, characterized in that, All the test channels synchronously perform forward and reverse tests on the same pin number on the memory chip during each test cycle, with the main control unit issuing the control timing uniformly.
4. The large-scale screening and testing system for storage particles according to claim 1, characterized in that, The memory chip is a packaged chip with an internal ESD protection structure, including LPDDR, DDR, eMMC or NAND Flash chips. The I / O pins of the memory chip contain a pair of anti-parallel PN junction diodes.
5. The large-scale screening and testing system for storage particles according to claim 1, characterized in that, The data storage module retains the first response value and the second response value from the most recent complete test when the large-scale screening test system for the storage particles experiences a power outage or communication failure.
6. The large-scale screening and testing system for storage particles according to claim 1, characterized in that, The large-scale screening test system also includes a data storage module, which is used to locally cache the original test data of each test channel; The first response value and the second response value are compared with the pre-stored good product benchmark data to obtain the comparison result; The external data processing device includes a host computer and a robotic arm controlled by the host computer. The host computer generates sorting instructions based on the comparison results and controls the robotic arm to physically sort the stored particles into qualified and defective products.
7. The large-scale screening and testing system for storage particles according to claim 1, characterized in that, The adjustable constant voltage source is connected in series with a current-limiting resistor (R).