Semiconductor device and semiconductor memory device
By designing gate-all-around transistors (SGTs) and optimizing the manufacturing process, the channel leakage current problem of oxide semiconductor transistors was solved, realizing a semiconductor device with low leakage current and high reliability, suitable for memory cells of dynamic random access memory.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-11
- Publication Date
- 2026-03-20
AI Technical Summary
In the prior art, oxide semiconductor transistors have the problem of large channel leakage current when they are disconnected, which affects their performance in dynamic random access memory.
A gate-all-around transistor (SGT) was designed with a gate electrode comprising two parts: one part facing the oxide semiconductor layer and in contact with the gate insulating layer, and the other part being half a distance away from the oxide semiconductor layer. The gate length is relatively long, and the gate insulating layer is formed by wet etching to reduce processing damage, combined with specific manufacturing processes to improve reliability.
It achieves lower disconnect leakage current and stable transistor characteristics, reduces inter-wire capacitance, lowers power consumption of semiconductor circuits, improves the reliability of the gate insulating layer, and suppresses short-channel effects and high threshold voltage.
Smart Images
Figure CN121711998A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] Embodiments of the present application relate to a semiconductor device and a semiconductor memory device. BACKGROUND
[0002] An oxide semiconductor transistor in which a channel is formed in an oxide semiconductor layer has an excellent characteristic that a channel leakage current is extremely small at the time of off operation. Thus, for example, the oxide semiconductor transistor can be applied to a switching transistor of a memory cell of a dynamic random access memory (DRAM). SUMMARY
[0003] A problem to be solved by the present application is to provide a semiconductor device with excellent transistor characteristics.
[0004] The semiconductor device according to an embodiment includes: a first electrode; a second electrode; a first oxide semiconductor layer provided between the first electrode and the second electrode; a third electrode; a fourth electrode; a second oxide semiconductor layer provided between the third electrode and the fourth electrode, which is provided apart from the first oxide semiconductor layer in a second direction perpendicular to a first direction connecting the first electrode and the second electrode; a gate electrode surrounding the first oxide semiconductor layer and the second oxide semiconductor layer, which extends in the second direction; and a gate insulating layer provided between the gate electrode and the first oxide semiconductor layer, wherein the gate electrode includes a first portion facing the first oxide semiconductor layer in the second direction, which is in contact with the gate insulating layer and has a first length in the first direction, and a second portion apart from the first oxide semiconductor layer by a distance of 1 / 2 of a distance between the first oxide semiconductor layer and the second oxide semiconductor layer in the second direction, which has a second length in the first direction, the first length being longer than the second length. BRIEF DESCRIPTION OF DRAWINGS
[0005] Figure 1 FIG. 1 is a schematic cross-sectional view of a semiconductor device of a first embodiment.
[0006] Figure 2 FIG. 2 is a schematic cross-sectional view of a semiconductor device of the first embodiment.
[0007] Figure 3 FIG. 3 is a schematic cross-sectional view of a semiconductor device of the first embodiment.
[0008] Figure 4 FIG. 4 is a schematic cross-sectional view illustrating an example of a manufacturing method of a semiconductor device of the first embodiment.
[0009] Figure 5is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device of Embodiment 1.
[0010] Figure 6 is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device of Embodiment 1.
[0011] Figure 7 is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device of Embodiment 1.
[0012] Figure 8 is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device of Embodiment 1.
[0013] Figure 9 is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device of Embodiment 1.
[0014] Figure 10 is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device of Embodiment 1.
[0015] Figure 11 is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device of Embodiment 1.
[0016] Figure 12 is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device of Embodiment 1.
[0017] Figure 13 is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device of Embodiment 1.
[0018] Figure 14 is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device of Embodiment 1.
[0019] Figure 15 is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device of Embodiment 1.
[0020] Figure 16 is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device of Embodiment 1.
[0021] Figure 17 is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device of Embodiment 1.
[0022] Figure 18 is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device of Embodiment 1.
[0023] Figure 19 is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device of Embodiment 1.
[0024] Figure 20 is a schematic cross-sectional view showing an example of a manufacturing method of the semiconductor device of the first embodiment.
[0025] Figure 21 is a schematic cross-sectional view showing an example of a manufacturing method of the semiconductor device of the first embodiment.
[0026] Figure 22 is a diagram for explaining an operation and effects of the semiconductor device of the first embodiment.
[0027] Figure 23 is a diagram for explaining an operation and effects of the semiconductor device of the first embodiment.
[0028] Figure 24 is a diagram for explaining an operation and effects of the semiconductor device of the first embodiment.
[0029] Figure 25 is a diagram for explaining an operation and effects of the semiconductor device of the first embodiment.
[0030] Figure 26 is a schematic cross-sectional view of the semiconductor device of the first embodiment of the first modification.
[0031] Figure 27 is a schematic cross-sectional view of the semiconductor device of the first embodiment of the second modification.
[0032] Figure 28 is a schematic cross-sectional view of the semiconductor device of the second embodiment.
[0033] Figure 29 is a schematic cross-sectional view showing an example of a manufacturing method of the semiconductor device of the second embodiment.
[0034] Figure 30 is a schematic cross-sectional view of the semiconductor device of the second embodiment of the first modification.
[0035] Figure 31 is a schematic cross-sectional view of the semiconductor device of the second embodiment of the second modification.
[0036] Figure 32 is a schematic cross-sectional view showing an example of a manufacturing method of the semiconductor device of the second embodiment of the second modification.
[0037] Figure 33 is a schematic cross-sectional view of the semiconductor device of the third embodiment.
[0038] Figure 34 is a schematic cross-sectional view of the semiconductor device of the fourth embodiment.
[0039] Figure 35 is a schematic cross-sectional view of a semiconductor device of the fourth embodiment.
[0040] Figure 36 is a schematic cross-sectional view of a semiconductor device of the fifth embodiment.
[0041] Figure 37 is a schematic cross-sectional view of a semiconductor device of the fifth embodiment.
[0042] Figure 38 is a schematic cross-sectional view of an example of a manufacturing method of a semiconductor device of the fifth embodiment.
[0043] Figure 39 is a schematic cross-sectional view of an example of a manufacturing method of a semiconductor device of the fifth embodiment.
[0044] Figure 40 is a schematic cross-sectional view of an example of a manufacturing method of a semiconductor device of the fifth embodiment.
[0045] Figure 41 is a schematic cross-sectional view of an example of a manufacturing method of a semiconductor device of the fifth embodiment.
[0046] Figure 42 is a schematic cross-sectional view of an example of a manufacturing method of a semiconductor device of the fifth embodiment.
[0047] Figure 43 is a schematic cross-sectional view of an example of a manufacturing method of a semiconductor device of the fifth embodiment.
[0048] Figure 44 is a schematic cross-sectional view of an example of a manufacturing method of a semiconductor device of the fifth embodiment.
[0049] Figure 45 is a schematic cross-sectional view of a semiconductor storage device of the sixth embodiment.
[0050] Figure 46 is a schematic cross-sectional view of a semiconductor storage device of the sixth embodiment.
[0051] Figure 47 is a schematic cross-sectional view of a semiconductor device of the seventh embodiment.
[0052] Figure 48 is a schematic cross-sectional view of a semiconductor device of a modification of the seventh embodiment. DETAILED DESCRIPTION
[0053] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. In addition, in the following description, identical or similar components are designated by the same reference numerals, and a description thereof will not be repeated.
[0054] Further, in this specification, in some cases, the term "above" or "below" is used. In addition, the term "above" or "below" is used for convenience only and does not limit the position relative to the direction of gravity.
[0055] Qualitative analysis and quantitative analysis of the chemical composition of components constituting the semiconductor device and the semiconductor memory device in this specification can be performed by, for example, Secondary Ion Mass Spectrometry (SIMS), Energy Dispersive X-ray Spectroscopy (EDX), or Rutherford Back-Scattering Spectroscopy (RBS). Further, for measurement of the thickness of components constituting the semiconductor device and the semiconductor memory device, the distance between components, the crystal grain diameter, or the like, a Transmission Electron Microscope (TEM) can be used, for example. Further, for determination of the constituent substance of components constituting the semiconductor device and the semiconductor memory device, measurement of the existence ratio of the constituent substance, an X-ray Photoelectron Spectroscopy (XPS), a Hard X-ray Photoelectron Spectroscopy (HAXPES), or Electron Energy Loss Spectroscopy (EELS) can be used, for example.
[0056] "Metal" in this specification is a general term for a substance having metallic properties, and for example, a metal compound such as a metal nitride or a metal carbide having metallic properties is also included in the range of "metal".
[0057] (First Embodiment)
[0058] The semiconductor device of the first embodiment includes: a first electrode; a second electrode; a first oxide semiconductor layer disposed between the first electrode and the second electrode; a third electrode; a fourth electrode; a second oxide semiconductor layer disposed between the third electrode and the fourth electrode, and spaced apart from the first oxide semiconductor layer in a second direction perpendicular to a first direction connecting the first electrode and the second electrode; a gate electrode surrounding the first oxide semiconductor layer and the second oxide semiconductor layer, extending in the second direction; and a gate insulating layer disposed between the gate electrode and the first oxide semiconductor layer. The gate electrode includes a first portion and a second portion. The first portion faces the first oxide semiconductor layer in the second direction, is in contact with the gate insulating layer, and has a first length in the first direction. The second portion extends from the first oxide semiconductor layer in the second direction by a distance equal to half the distance between the first oxide semiconductor layer and the second oxide semiconductor layer, and has a second length in the first direction. The first length is longer than the second length.
[0059] Figure 1 , Figure 2 and Figure 3 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment. Figure 1 yes Figure 2 AA' sectional view. Figure 2 yes Figure 1 BB' section. Figure 3 yes Figure 2 CC' section.
[0060] Figure 1 In this context, the up-down direction is referred to as the first direction. Figure 1 In this context, the left and right directions are referred to as the third direction. The third direction is perpendicular to the first direction. Figure 3 In this context, the left-right direction is referred to as the second direction. The second direction is perpendicular to the first and third directions. The first direction is the direction connecting the lower electrode 12 and the upper electrode 14.
[0061] The semiconductor device of the first embodiment includes a transistor 100. The transistor 100 is an oxide semiconductor transistor with a channel formed in an oxide semiconductor. In the transistor 100, a gate electrode is disposed surrounding the oxide semiconductor layer forming the channel. The transistor 100 is a so-called gate-around transistor (SGT). The transistor 100 is a so-called vertical transistor.
[0062] The transistor 100 includes a lower electrode 12, an upper electrode 14, an oxide semiconductor layer 16, a gate electrode 18, a gate insulating layer 20, and an interlayer insulating layer 22.
[0063] The lower electrode 12 is an example of a first electrode. The upper electrode 14 is an example of a second electrode. The oxide semiconductor layer 16 is an example of a first oxide semiconductor layer.
[0064] The semiconductor device of the first embodiment includes the transistor 100x, the first wiring layer 24, and the second wiring layer 26 in addition to the transistor 100.
[0065] The transistor 100x includes the lower electrode 13, the upper electrode 15, the oxide semiconductor layer 17, the gate electrode 18, the gate insulating layer 20, and the interlayer insulating layer 22.
[0066] The lower electrode 13 is an example of a third electrode. The upper electrode 15 is an example of a fourth electrode. The oxide semiconductor layer 17 is an example of a second oxide semiconductor layer.
[0067] The transistor 100x is provided in the second direction of the transistor 100. The oxide semiconductor layer 17 is provided apart from the oxide semiconductor layer 16 in the second direction.
[0068] The transistor 100x has the same structure as the transistor 100. Hereinafter, detailed description of the transistor 100x is omitted.
[0069] The lower electrode 12 is provided below the oxide semiconductor layer 16. The lower electrode 12 is electrically connected to the oxide semiconductor layer 16. The lower electrode 12 is in contact with the oxide semiconductor layer 16, for example. The lower electrode 12 functions as a source electrode or a drain electrode of the transistor 100.
[0070] The lower electrode 12 is a conductor. The lower electrode 12 includes an oxide conductor, for example. The lower electrode 12 is an oxide conductor layer, for example.
[0071] The lower electrode 12 includes indium (In), tin (Sn), and oxygen (O), for example. The lower electrode 12 includes indium tin oxide, for example. The lower electrode 12 is an indium tin oxide layer, for example.
[0072] The lower electrode 12 includes tin (Sn) and oxygen (O), for example. The lower electrode 12 includes tin oxide, for example. The lower electrode 12 is a tin oxide layer, for example.
[0073] The lower electrode 12 includes a metal, for example. The lower electrode 12 is a metal layer, for example.
[0074] The lower electrode 12 includes tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), titanium (Ti), or tantalum (Ta), for example. The lower electrode 12 is a tungsten layer, a molybdenum layer, a copper layer, an aluminum layer, a titanium layer, or a tantalum layer, for example.
[0075] The lower electrode 12 can have a stacked-layer structure of a plurality of conductive materials, for example. The lower electrode 12 is a stacked-layer structure of an oxide conductor layer and a metal layer, for example. For example, the surface of the lower electrode 12 on the oxide semiconductor layer 16 side is an oxide conductor layer.
[0076] The upper electrode 14 is provided over the oxide semiconductor layer 16. The upper electrode 14 is electrically connected to the oxide semiconductor layer 16. The upper electrode 14 is in contact with the oxide semiconductor layer 16, for example. The upper electrode 14 functions as a source electrode or a drain electrode of the transistor 100.
[0077] The upper electrode 14 is a conductive material. The upper electrode 14 includes an oxide conductor, for example. The upper electrode 14 is an oxide conductor layer, for example.
[0078] The upper electrode 14 includes indium (In), tin (Sn), and oxygen (O), for example. The upper electrode 14 includes indium tin oxide, for example. The upper electrode 14 is an indium tin oxide layer, for example.
[0079] The upper electrode 14 includes tin (Sn) and oxygen (O), for example. The upper electrode 14 includes tin oxide, for example. The upper electrode 14 is a tin oxide layer, for example.
[0080] The upper electrode 14 includes a metal, for example. The upper electrode 14 is a metal layer, for example.
[0081] The upper electrode 14 includes tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), titanium (Ti), or tantalum (Ta), for example. The upper electrode 14 is a tungsten layer, a molybdenum layer, a copper layer, an aluminum layer, a titanium layer, or a tantalum layer, for example.
[0082] The upper electrode 14 can have a stacked-layer structure of a plurality of conductive materials, for example. The upper electrode 14 is a stacked-layer structure of an oxide conductor layer and a metal layer, for example. For example, the surface of the upper electrode 14 on the oxide semiconductor layer 16 side is an oxide conductor layer.
[0083] The lower electrode 12 and the upper electrode 14 are formed of the same material, for example. The lower electrode 12 and the upper electrode 14 are an oxide conductor including indium (In), tin (Sn), and oxygen (O), for example. The lower electrode 12 and the upper electrode 14 include indium tin oxide, for example. The lower electrode 12 and the upper electrode 14 are an indium tin oxide layer, for example.
[0084] The oxide semiconductor layer 16 is provided between the lower electrode 12 and the upper electrode 14. The oxide semiconductor layer 16 is in contact with the lower electrode 12, for example. The oxide semiconductor layer 16 is in contact with the upper electrode 14, for example.
[0085] The oxide semiconductor layer 16 is columnar. The oxide semiconductor layer 16 is cylindrical, for example. The oxide semiconductor layer 16 can also be quadrangular prism-shaped, for example.
[0086] A channel which becomes a current path at the time of the on operation of the transistor 100 is formed in the oxide semiconductor layer 16.
[0087] The oxide semiconductor layer 16 is an oxide semiconductor. The oxide semiconductor layer 16 is, for example, molybdenum.
[0088] The oxide semiconductor layer 16 contains, for example, at least one element selected from the group consisting of indium (In), gallium (Ga), silicon (Si), aluminum (Al), and tin (Sn), zinc (Zn), and oxygen (O). The oxide semiconductor layer 16 contains, for example, indium (In), gallium (Ga), zinc (Zn), and oxygen (O). The oxide semiconductor layer 16 contains, for example, indium gallium zinc oxide. The oxide semiconductor layer 16 is, for example, an indium gallium zinc oxide layer.
[0089] The oxide semiconductor layer 16 contains, for example, at least one element selected from the group consisting of titanium (Ti), zinc (Zn), and tungsten (W), and oxygen (O). The oxide semiconductor layer 16 contains, for example, titanium oxide, zinc oxide, or tungsten oxide. The oxide semiconductor layer 16 is, for example, a titanium oxide layer, a zinc oxide layer, or a tungsten oxide layer.
[0090] The oxide semiconductor layer 16 has, for example, a chemical composition different from that of the lower electrode 12 and that of the upper electrode 14.
[0091] The oxide semiconductor layer 16 contains oxygen vacancies. The oxygen vacancies in the oxide semiconductor layer 16 function as donors.
[0092] The length of the oxide semiconductor layer 16 in the first direction is, for example, 80 nm or more and 200 nm or less. The length of the oxide semiconductor layer 16 in the second direction is, for example, 20 nm or more and 100 nm or less.
[0093] The gate electrode 18 surrounds the oxide semiconductor layer 16 and the oxide semiconductor layer 17. The gate electrode 18 is provided so that the position coordinate in the first direction thereof becomes a value between the position coordinates in the first direction of the lower electrode 12 and the upper electrode 14, respectively.
[0094] As shown in FIG. 1, the gate electrode 18 extends in the second direction perpendicular to the first direction. Figure 2
[0095] The length of the gate electrode 18 in the first direction of the portion of the oxide semiconductor layer 16 surrounding the portion of the gate insulating layer 20 is longer than the length of the gate electrode 18 in the first direction of the other portion of the oxide semiconductor layer 16 apart from the gate insulating layer 20 in the second direction.
[0096] As shown in FIG. 1, the gate electrode 18 extends in the second direction perpendicular to the first direction. Figure 3 As shown in FIG. 1, the gate electrode 18 includes a first portion 18a and a second portion 18b. The first portion 18a is a portion which is opposed to the oxide semiconductor layer 16 in the second direction and which is in contact with the gate insulating layer 20. The first portion 18a has a first length L1 in the first direction. The second portion 18b is a portion which is apart from the oxide semiconductor layer 16 by a distance d / 2 in the second direction. The second portion 18b has a second length L2 in the first direction. The first length L1 is longer than the second length L2. Figure 3 Figure 3 Figure 3 Figure 3
[0097] Further, as shown in FIG. 1, the gate electrode 18 includes a third portion 18c. The third portion 18c is a portion which is opposed to the oxide semiconductor layer 16 in the third direction and which is in contact with the gate insulating layer 20. The third portion 18c has a third length L3 in the first direction. The third length L3 is longer than the second length L2. Figure 1 Figure 1
[0098] The first length L1 is, for example, 1.2 times or more and 2 times or less of the second length L2. The third length L3 is, for example, 1.2 times or more and 2 times or less of the second length L2.
[0099] The gate electrode 18 is a conductor. The gate electrode 18 is, for example, a metal, a metal compound, or a semiconductor. The gate electrode 18 includes, for example, tungsten (W).
[0100] The length of the gate electrode 18 in the first direction is, for example, 20 nm or more and 100 nm or less.
[0101] The gate insulating layer 20 is provided between the oxide semiconductor layer 16 and the gate electrode 18. The gate insulating layer 20 is provided so as to surround the oxide semiconductor layer 16. The gate insulating layer 20 is provided between the lower electrode 12 and the upper electrode 14.
[0102] The gate insulating layer 20 is not in contact with the lower electrode 12, for example. The gate insulating layer 20 is in contact with the upper electrode 14, for example.
[0103] The gate insulating layer 20 is provided between the gate electrode 18 and the lower electrode 12 in the first direction, for example. The gate insulating layer 20 is provided between the gate electrode 18 and the interlayer insulating layer 22 in the first direction, for example. The gate insulating layer 20 is in contact with the gate electrode 18 and the interlayer insulating layer 22 in the first direction, for example.
[0104] The gate insulating layer 20 is, for example, an oxide, a nitride, or an oxide oxynitride. The gate insulating layer 20 may comprise, for example, silicon oxide, aluminum oxide, silicon nitride, aluminum nitride, or silicon oxynitride. The gate insulating layer 20 may be, for example, a silicon oxide layer, an aluminum oxide layer, a silicon nitride layer, an aluminum nitride layer, or a silicon oxynitride layer.
[0105] The gate insulating layer 20 may also have a multilayer structure. For example, the gate insulating layer 20 may be a multilayer structure of a nitride film and an oxide film. Alternatively, the gate insulating layer 20 may have a multilayer structure of a silicon nitride film and a silicon oxide film. For example, a silicon oxide film may be disposed between the oxide semiconductor layer 16 and the silicon nitride film. The thickness of the gate insulating layer 20 may be, for example, 0.5 nm or more and 5 nm or less.
[0106] The lower electrode 12 is spaced apart from the gate insulating layer 20, for example, in the first direction. In the first direction, for example, an interlayer insulating layer 22 is provided between the lower electrode 12 and the gate insulating layer 20.
[0107] The first wiring layer 24 extends in the second direction. The first wiring layers 24 are disposed adjacent to the gate electrode 18 in the third direction. For example, the gate electrode 18 is sandwiched between two first wiring layers 24 in the third direction.
[0108] The first wiring layer 24 contains the same material as the gate electrode 18. The first wiring layer 24 is formed of the same material as the gate electrode 18. The first wiring layer 24 is formed, for example, simultaneously with the gate electrode 18.
[0109] and Figure 1 The first and third directions shown are parallel, and the fourth length of the first wiring layer 24 in the first direction of the cross-section including the oxide semiconductor layer 16 is ( ). Figure 1 L4 in the middle is shorter than the first length of the gate electrode 18. Figure 3 In addition, the fourth length L4 of the first wiring layer 24 is shorter than the third length of the gate electrode 18 (L1). Figure 1 In addition, the fourth length L4 of the first wiring layer 24 is the same as the second length of the gate electrode 18. Figure 3 The L2 in the text is roughly the same.
[0110] A gate insulating layer 20 is disposed, for example, on the lower surface of the first wiring layer 24. The gate insulating layer 20 is disposed between the first wiring layer 24 and the interlayer insulating layer 22. The gate insulating layer 20 is in contact with the first wiring layer 24 and the interlayer insulating layer 22.
[0111] The second wiring layer 26 extends, for example, in a third direction. The second wiring layer 26 is repeated, for example, above the gate electrode 18 and the first wiring layer 24, in a second direction. An interlayer insulating layer 22 is provided between the second wiring layer 26 and the gate electrode 18 and the first wiring layer 24. The second wiring layer 26 intersects, for example, the gate electrode 18 and the first wiring layer 24. A portion of the second wiring layer 26 is electrically connected, for example, to the upper electrode 14.
[0112] Interlayer insulating layer 22, for example, surrounds the lower electrode 12, the upper electrode 14, the oxide semiconductor layer 16, and the gate insulating layer 20. Interlayer insulating layer 22, for example, is disposed between the lower electrode 12 and the gate electrode 18. Interlayer insulating layer 22, for example, is disposed between the upper electrode 14 and the gate electrode 18. Interlayer insulating layer 22, for example, is disposed between the gate electrode 18 and the first wiring layer 24.
[0113] Interlayer insulating layer 22 is an insulator. Interlayer insulating layer 22 may be, for example, an oxide, a nitride, or an oxide oxynitride. Interlayer insulating layer 22 may contain, for example, silicon (Si) and oxygen (O). Interlayer insulating layer 22 may contain, for example, silicon oxide. Interlayer insulating layer 22 may be, for example, silicon oxide. Interlayer insulating layer 22 may contain, for example, silicon (Si) and nitrogen (N). Interlayer insulating layer 22 may contain, for example, silicon nitride. Interlayer insulating layer 22 may be, for example, silicon nitride.
[0114] Next, an example of the manufacturing method of the semiconductor device according to the first embodiment will be described.
[0115] Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19 , Figure 20 and Figure 21 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment. Figures 4-21 They respectively represent the corresponding Figure 1 The cross-section. Figures 4-21 This is a diagram illustrating an example of a manufacturing method for transistor 100.
[0116] The following explanation will be based on the case where the lower electrode 12 of the transistor 100 is an indium tin oxide layer, the upper electrode 14 is an indium tin oxide layer, the oxide semiconductor layer 16 is an indium gallium zinc oxide layer, the gate electrode 18 is a tungsten layer, the gate insulating layer 20 is a silicon oxide layer, and the interlayer insulating layer 22 is a silicon oxide layer.
[0117] First, a first silicon oxide film 32 and a first silicon nitride film 34 are formed on the indium tin oxide layer 31 formed in the silicon oxide layer 30. Figure 4 The first silicon oxide film 32 and the first silicon nitride film 34 are formed, for example, by chemical vapor deposition (CVD).
[0118] The silicon oxide layer 30 ultimately becomes the interlayer insulating layer 22. The indium tin oxide layer 31 ultimately becomes the lower electrode 12. A portion of the first silicon oxide film 32 ultimately becomes the interlayer insulating layer 22.
[0119] Next, the first silicon nitride film 34 and the first silicon oxide film 32 are etched to form the first opening 35. Figure 5 The first opening 35 is formed using, for example, photolithography and reactive ion etching (RIE).
[0120] Next, the first opening 35 is embedded with an amorphous silicon film 36. Figure 6 The amorphous silicon film 36 is formed by, for example, deposition by CVD and planarization using chemical mechanical polishing (CMP).
[0121] Next, the first silicon nitride film 34 is etched to expose the amorphous silicon film 36. Figure 7 The exposed amorphous silicon film 36 forms columnar bodies 37.
[0122] Next, the columnar body 37 is covered with the second silicon oxide film 38. Figure 8 The second silicon oxide film 38 is formed, for example, using a CVD method. A portion of the second silicon oxide film 38 eventually becomes the gate insulating layer 20.
[0123] Next, the columnar body 37 is embedded with a tungsten film 39. Figure 9 The tungsten film 39 is formed, for example, using a CVD method. A portion of the tungsten film 39 eventually becomes the gate electrode 18 and the first wiring layer 24.
[0124] Next, the upper surface of the tungsten film 39 is planarized. Figure 10 The tungsten film 39 was planarized using CMP. The upper surface of the columnar body 37 was exposed.
[0125] Next, a portion of the tungsten film 39 is etched, exposing a portion of the second silicon oxide film 38 on the side of the columnar body 37.Figure 11 At this point, the tungsten film 39 is etched in such a way that the tungsten film 39 remaining around the columnar body 37 is thicker than that of other parts.
[0126] For example, by performing isotropic dry etching, the tungsten film 39 remaining around the columnar body 37 can be thicker than that of other parts.
[0127] Next, the columnar body 37 is covered with the second silicon nitride film 40. Figure 12 The second silicon nitride film 40 is formed, for example, using CVD.
[0128] Next, the second silicon nitride film 40 is etched to form a sidewall 41 on the side of the pillar 37. Figure 13 The sidewall 41 is formed, for example, using the RIE method.
[0129] Next, the columnar body 37 and the sidewall 41 are embedded with the third silicon oxide film 42. Figure 14 The third silicon oxide film 42 is formed, for example, using CVD.
[0130] Next, the third silicon oxide film 42 is etched to form the second opening 43, which exposes the sidewall 41 and the tungsten film 39. Figure 15 The second opening 43 is formed using photolithography and RIE.
[0131] Next, using the third silicon oxide film 42 and sidewall 41 as a mask, the tungsten film 39 is etched. Figure 16 Tungsten film 39 is etched, for example, using the RIE method.
[0132] Next, remove sidewall 41. Figure 17 The sidewall 41 is removed, for example, using a wet etching method.
[0133] Next, the second opening 43 is embedded with the fourth silicon oxide film 44. Figure 18 The fourth silicon oxide film 44 is formed, for example, by CVD.
[0134] Next, the fourth silicon oxide film 44 and the third silicon oxide film 42 on the columnar body 37 are removed, exposing the upper surface of the columnar body 37. Figure 19 The fourth silica film 44 and the third silica film 42 are removed, for example, by CMP.
[0135] Next, the columnar body 37 is etched and removed, forming a second silicon oxide film 38 exposed at the third opening 45 on the side. Figure 20 The etching of the amorphous silicon film 36 forming the columnar bodies 37 is performed, for example, using a wet etching method.
[0136] Next, the third opening 45 is embedded with an indium gallium zinc oxide film 46. Figure 21The indium gallium zinc oxide film 46 is formed, for example, using CVD, and then planarized using CMP. The indium gallium zinc oxide film 46 ultimately becomes the oxide semiconductor layer 16.
[0137] Then, using well-known process technology, the upper electrode 14 of the indium tin oxide layer and the second wiring layer 26 are formed.
[0138] Using the above manufacturing methods, manufacture products containing... Figure 1 , Figure 2 and Figure 3 The transistor 100 shown is a semiconductor device.
[0139] Next, the function and effects of the semiconductor device of the first embodiment will be explained.
[0140] Figure 22 , Figure 23 , Figure 24 and Figure 25 This is an explanatory diagram illustrating the operation and effects of the semiconductor device according to the first embodiment. Figure 22 , Figure 23 , Figure 24 and Figure 25 This is a schematic cross-sectional view illustrating an example of a manufacturing method for a comparative semiconductor device.
[0141] The difference between the manufacturing method of the comparative example semiconductor device and the manufacturing method of the semiconductor device of the first embodiment is that, after forming the opening 45x of the third opening 45 corresponding to the manufacturing method of the semiconductor device of the first embodiment, a second silicon oxide film 38 is formed as a gate insulating layer.
[0142] For example, such as Figure 22 As shown, a tungsten film 39 is exposed on the side, and an indium tin oxide layer 31 is exposed at the opening 45x on the bottom surface. Next, as... Figure 23 As shown, a second silicon oxide film 38, serving as a gate insulating layer, is formed in the opening 45x. Next, as... Figure 24 As shown, the second silicon oxide film 38 at the bottom of the opening 45x is removed using the RIE method. Then, as... Figure 25 As shown, the opening 45x is embedded with an indium gallium zinc oxide film 46.
[0143] The RIE method utilizes anisotropic etching caused by ion bombardment. In the manufacturing method of the comparative example, such as... Figure 24 As shown, when the second silicon oxide film 38 at the bottom of the opening 45x is removed using the RIE method, the surface of the second silicon oxide film 38 formed on the side of the opening 45x is directly exposed to ion bombardment. Therefore, processing damage remains on the second silicon oxide film 38.
[0144] The second silicon oxide film 38 ultimately becomes the gate insulating layer. Due to residual processing damage on the gate insulating layer, its reliability is reduced. Specifically, for example, the time-degradation insulation breakdown (TDDB) characteristic of the gate insulating layer deteriorates.
[0145] In the semiconductor device manufacturing method of the first embodiment, a columnar body 37 is formed, and a second silicon oxide film 38, which becomes the gate insulating layer 20, is finally formed on the surface of the columnar body 37. Figure 19 , Figure 20 As shown, when the indium tin oxide layer 31 is formed and exposed at the third opening 45 on the bottom surface, a wet etching method is used instead of a refining etching (RIE) method. Therefore, the second silicon oxide film 38, which forms the gate insulating layer 20, is not exposed to the ion bombardment of the RIE.
[0146] Therefore, compared to the manufacturing method of the semiconductor device in the comparative example, the reliability of the gate insulating layer 20 is improved. Thus, a transistor 100 with improved reliability can be achieved.
[0147] Furthermore, in the transistor 100 of the first embodiment, the length of the gate electrode 18 in the first direction surrounding the oxide semiconductor layer 16 and in contact with the gate insulating layer 20 is relatively long. In other words, the gate length of the transistor 100 is relatively long. The relatively long gate length of the transistor 100 can, for example, suppress the short-channel effect of the transistor 100, thus achieving a transistor 100 with stable characteristics. Furthermore, the relatively long gate length of the transistor 100 can, for example, achieve a high threshold voltage, thus enabling, for example, a transistor 100 with less leakage current when turned off.
[0148] On the other hand, in the transistor 100 of the first embodiment, the length of the portion of the transistor used as a wiring layer that extends away from the gate insulating layer 20 in the second direction perpendicular to the first direction is suppressed to be shorter. Therefore, for example, compared to the case where the length of the portion used as a wiring layer in the first direction is the same as the gate length of the transistor 100, the inter-wiring capacitance can be reduced, and the power consumption of the semiconductor circuit using the transistor 100 can be reduced.
[0149] Specifically, for example, the distance between the second wiring layer 26, which intersects with the gate electrode 18, and the gate electrode 18 is increased. Therefore, the inter-wiring capacitance between the gate electrode 18 and the second wiring layer 26 can be reduced. Furthermore, the area of the surface extending in the same direction as the gate electrode 18 and facing the adjacent first wiring layer 24 is reduced. Therefore, the inter-wiring capacitance between the gate electrode 18 and the first wiring layer 24 can be reduced.
[0150] Furthermore, it can reduce the inter-wire capacitance between the gate electrode 18 and the first wiring layer 24, thereby suppressing the erroneous operation of the transistor 100 by the potential change of the gate electrode 18 through potential coupling with the adjacent first wiring layer 24.
[0151] In addition, such as by Figure 2 It is known that the effective width of the gate electrode 18 in the third direction narrows near the transistor 100. In other words, the effective width of the gate electrode 18 in the third direction narrows around the oxide semiconductor layer 16. Therefore, the wiring resistance in the second direction of the gate electrode 18 increases due to the narrowing of the effective width of the gate electrode 18 around the oxide semiconductor layer 16. In the transistor 100 of the first embodiment, the length of the gate electrode 18 in the first direction at the portion surrounding the oxide semiconductor layer 16 that is in contact with the gate insulating layer 20 is relatively long. Therefore, even if the effective width of the gate electrode 18 around the oxide semiconductor layer 16 narrows, the increase in resistance of the gate electrode 18 around the oxide semiconductor layer 16 can be suppressed. Therefore, the increase in wiring resistance in the second direction of the gate electrode 18 can be suppressed.
[0152] The semiconductor device according to the first embodiment can realize a semiconductor device with excellent transistor characteristics.
[0153] (Example 1 of the variations)
[0154] Figure 26 This is a schematic cross-sectional view of a semiconductor device according to a first variation of the first embodiment. Figure 26 It corresponds to the first embodiment. Figure 1 The image.
[0155] The difference between the transistor 110 of the first variation of the first embodiment and the transistor 100 of the first embodiment is that the width of the oxide semiconductor layer 16 in the third direction decreases from the upper electrode 14 toward the lower electrode 12. The difference between the transistor 110 of the first variation of the first embodiment and the transistor 100 of the first embodiment is that the oxide semiconductor layer 16 has a so-called positive cone shape.
[0156] (Second variation example)
[0157] Figure 27 This is a schematic cross-sectional view of a semiconductor device in the second variation of the first embodiment. Figure 27 It corresponds to the first embodiment. Figure 1 The image.
[0158] The difference between the transistor 120 of the second variation of the first embodiment and the transistor 100 of the first embodiment is that the width of the oxide semiconductor layer 16 in the third direction increases from the upper electrode 14 toward the lower electrode 12. The difference between the transistor 120 of the second variation of the first embodiment and the transistor 100 of the first embodiment is that the oxide semiconductor layer 16 has a so-called inverted cone shape.
[0159] The semiconductor device according to the first embodiment and its variations can realize a semiconductor device with excellent transistor characteristics.
[0160] (Second Implementation)
[0161] The semiconductor device of the second embodiment differs from that of the semiconductor device of the first embodiment in that the oxide semiconductor layer includes a first region and a second region disposed between the first region and the second electrode. The first region is in contact with the gate insulating layer in a first direction, and the second region is surrounded by the gate insulating layer. In a cross-section parallel to the first direction, the first width of the first region in a third direction perpendicular to the second direction is wider than the second width of the second region in a third direction. Hereinafter, some descriptions that are repeated in the first embodiment will be omitted.
[0162] Figure 28 This is a schematic cross-sectional view of the semiconductor device according to the second embodiment. Figure 28 It corresponds to the first embodiment. Figure 1 The image.
[0163] The oxide semiconductor layer 16 of the transistor 200 in the second embodiment includes a first region 16a and a second region 16b. The second region 16b is disposed between the first region 16a and the upper electrode 14.
[0164] The first region 16a is connected to the gate insulating layer 20 in the first direction. The second region 16b is surrounded by the gate insulating layer 20. The first region 16a and the second region 16b are, for example, physically continuous.
[0165] In a cross-section parallel to the first direction, the first width of the first region 16a in the third direction perpendicular to the second direction ( Figure 28 w1 in the second region 16b is wider than the second width in the third direction. Figure 28 (w2 in the first region 16a). The difference between the first width w1 of the first region 16a and the second width w2 of the second region 16b is, for example, more than 1 nm and less than 20 nm.
[0166] Compared to the transistor 100 of the first embodiment, the oxide semiconductor layer 16 of the transistor 200 of the second embodiment has a smaller cross-sectional area perpendicular to the first direction, which is surrounded by the gate electrode 18. Furthermore, the oxide semiconductor layer 16 of the transistor 200 of the second embodiment includes a first region 16a and a second region 16b, whereby the end of the lower electrode 12 side of the gate insulating layer 20 is recessed into the inner side of the oxide semiconductor layer 16.
[0167] Figure 29 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment.
[0168] For example, in the semiconductor device manufacturing method of the first embodiment, after forming the columnar body 37 of the amorphous silicon film 36, as... Figure 29 As shown, the additional etching columnar body 37 is used to refine it, thereby enabling the manufacture of the transistor 200 of the second embodiment.
[0169] According to the transistor 200 of the second embodiment, by reducing the cross-sectional area perpendicular to the first direction of the oxide semiconductor layer 16 surrounded by the gate electrode 18, the intensity of the electric field applied to the oxide semiconductor layer 16 by the gate electrode 18 increases. Therefore, for example, the threshold voltage of the transistor 200 can be improved.
[0170] Furthermore, in the oxide semiconductor layer 16 of the transistor 200 of the second embodiment, the end of the lower electrode 12 side of the gate insulating layer 20 is embedded in the oxide semiconductor layer 16. Therefore, the controllability of the gate electrode 18 of the electric field in the oxide semiconductor layer 16 near the end of the lower electrode 12 side of the gate insulating layer 20 is improved. Therefore, for example, an increase in turn-on current or a decrease in leakage current can be achieved.
[0171] The semiconductor device according to the second embodiment can realize a semiconductor device with excellent transistor characteristics.
[0172] (Example 1 of the variations)
[0173] The semiconductor device of the first variation of the second embodiment differs from the semiconductor device of the second embodiment in that, in the first direction, a gate insulating layer is provided between the first region and the gate electrode.
[0174] Figure 30 This is a schematic cross-sectional view of a semiconductor device according to the first variation of the second embodiment. Figure 30 It corresponds to the second embodiment. Figure 28 The image.
[0175] In the first variation of the second embodiment, the transistor 210 has a gate insulating layer 20 disposed in the first direction between the first region 16a and the gate electrode 18.
[0176] The width w2 of the second region 16b in the third direction is shorter than that of the transistor 200 in the second embodiment. Therefore, the cross-sectional area of the oxide semiconductor layer 16 surrounded by the gate electrode 18 in the second variation of the transistor 210, for example, is further reduced in the first direction compared to the transistor 200 in the second embodiment.
[0177] According to the first variation of the second embodiment, the threshold voltage of the transistor 210 can be further increased by further reducing the cross-sectional area of the oxide semiconductor layer 16 surrounded by the gate electrode 18 perpendicular to the first direction.
[0178] Furthermore, in the first variation of the second embodiment, the end of the lower electrode 12 side of the gate insulating layer 20 in the oxide semiconductor layer 16 of the transistor 210 is further recessed into the oxide semiconductor layer 16. Therefore, for example, it is possible to further increase the turn-on current or reduce the leakage current.
[0179] (Second variation example)
[0180] The difference between the semiconductor device of the second variation of the second embodiment and the semiconductor device of the second embodiment is that, in the first direction, no gate insulating layer is provided between the first electrode and the gate electrode.
[0181] Figure 31 This is a schematic cross-sectional view of a semiconductor device in the second variation of the second embodiment. Figure 31 It corresponds to the second embodiment. Figure 28 The image.
[0182] In the second variation of the second embodiment, the transistor 220 in the first direction does not have a gate insulating layer 20 provided between the lower electrode 12 and the gate electrode 18.
[0183] Figure 32 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to a second variation of the second embodiment.
[0184] For example, in the semiconductor device manufacturing method of the first embodiment, after forming the columnar body 37 of the amorphous silicon film 36, an oxide film 38x is finally formed by oxidizing the amorphous silicon film 36 to replace the second silicon oxide film 38 formed by CVD to become the gate insulating layer 20. The oxide film 38x is formed, for example, by thermal oxidation or plasma oxidation of the amorphous silicon film 36. The oxide film 38x formed by oxidizing the amorphous silicon film 36 ultimately becomes the gate insulating layer 20.
[0185] The semiconductor device according to the second embodiment and its variations can realize a semiconductor device with excellent transistor characteristics.
[0186] (Third Implementation)
[0187] The semiconductor device of the third embodiment differs from that of the semiconductor device of the first embodiment in that the gate insulating layer includes a first film and a second film with a different chemical composition than the first film, and the second film is sandwiched between the second and the oxide semiconductor layer. Hereinafter, some descriptions that are repeated in the first embodiment will be omitted.
[0188] Figure 33 This is a schematic cross-sectional view of the semiconductor device according to the third embodiment. Figure 33 It corresponds to the first embodiment. Figure 1 The image.
[0189] The gate insulating layer 20 of the transistor 300 in the third embodiment includes a first film 20a and a second film 20b. The first film 20a is sandwiched between the second film 20b and the oxide semiconductor layer 16. The first film 20a is disposed between the oxide semiconductor layer 16 and the second film 20b. The gate insulating layer 20 has a stacked structure of the first film 20a and the second film 20b.
[0190] The chemical composition of the second membrane 20b differs from that of the first membrane 20a. The first membrane 20a, for example, contains silicon oxide. The second membrane 20b, for example, contains a material with a dielectric constant higher than that of silicon oxide.
[0191] Substances with a dielectric constant higher than that of silicon oxide contained in the second film 20b include, for example, silicon nitride, aluminum nitride, aluminum oxide, hafnium oxide, zirconium oxide, lanthanum oxide, yttrium oxide, or tantalum oxide.
[0192] According to the transistor 300 of the third embodiment, the stacked structure of the gate insulating layer 20 having a first film 20a and a second film 20b can, for example, improve the threshold voltage of the transistor 300. Furthermore, the stacked structure of the gate insulating layer 20 having a first film 20a and a second film 20b can, for example, improve the reliability of the gate insulating layer 20.
[0193] The semiconductor device according to the third embodiment can realize a semiconductor device with excellent transistor characteristics.
[0194] (Fourth implementation)
[0195] The semiconductor device of the fourth embodiment differs from the semiconductor device of the first embodiment in that the gate electrode includes a first layer and a second layer with a different chemical composition than the first layer, and the first layer is sandwiched between the second and the gate insulating layer. Hereinafter, some descriptions that are repeated in the first embodiment will be omitted.
[0196] Figure 34 ,Figure 35 This is a schematic cross-sectional view of the semiconductor device according to the fourth embodiment. Figure 34 It corresponds to the first embodiment. Figure 1 The image. Figure 35 It corresponds to the first embodiment. Figure 3 The image.
[0197] The gate electrode 18 of the transistor 400 in the fourth embodiment includes a first layer 18x and a second layer 18y. The first layer 18x is sandwiched between the second layer 18y and the gate insulating layer 20. The first layer 18x is disposed between the gate insulating layer 20 and the second layer 18y. The gate electrode 18 has a stacked structure of the first layer 18x and the second layer 18y.
[0198] The chemical composition of the second 18y layer differs from that of the first 18x layer. The second 18y layer contains substances different from those in the first 18x layer. The resistivity of the substances contained in the second 18y layer is, for example, lower than that of the substances contained in the first 18x layer.
[0199] The first layer, 18x, contains materials such as titanium nitride, tungsten nitride, or tantalum nitride. The second layer, 18y, contains materials such as tungsten or molybdenum.
[0200] According to the transistor 400 of the fourth embodiment, by having a multilayer structure of a first layer 18x and a second layer 18y on the gate electrode 18, it is possible to balance the control of the threshold voltage of the transistor 400 with the reduction of the resistance of the gate electrode 18. Specifically, for example, a material with a work function optimized for the threshold voltage of the transistor 400 is applied to the first layer 18x. And, for example, a material with low resistivity is applied to the second layer 18y.
[0201] The semiconductor device according to the fourth embodiment can realize a semiconductor device with excellent transistor characteristics.
[0202] (Fifth Embodiment)
[0203] The semiconductor device of the fifth embodiment differs from that of the semiconductor device of the fourth embodiment in that the gate electrode further includes a third portion. This third portion faces the oxide semiconductor layer and is connected to the gate insulating layer in a third direction perpendicular to both the first and second directions, and has a third length in the first direction, which is shorter than the first length. Hereinafter, some descriptions that are repeated in the fourth embodiment will be omitted.
[0204] Figure 36 , Figure 37 This is a schematic cross-sectional view of the semiconductor device according to the fifth embodiment. Figure 36 It corresponds to the first embodiment. Figure 1 The image. Figure 37 It corresponds to the first embodiment.Figure 3 The image.
[0205] The gate electrode 18 of the transistor 500 in the fifth embodiment is similar to that of the transistor 400 in the fourth embodiment, comprising a first layer 18x and a second layer 18y. The first layer 18x is sandwiched between the second layer 18y and the gate insulating layer 20. The first layer 18x is disposed between the gate insulating layer 20 and the second layer 18y. The gate electrode 18 has a multilayer structure of the first layer 18x and the second layer 18y.
[0206] like Figure 36 As shown, the gate electrode 18 includes a third portion 18c. The third portion 18c is the portion facing the oxide semiconductor layer 16 and connected to the gate insulating layer 20 in a third direction. The third portion 18c has a third length in a first direction (…). Figure 36 L3 in the middle.
[0207] In addition, such as Figure 37 As shown, the gate electrode 18 includes a first portion 18a. The first portion 18a is the portion that faces the oxide semiconductor layer 16 in the second direction and is in contact with the gate insulating layer 20. The first portion 18a has a first length in the first direction ( Figure 37 (L1 in the original text). The third length L3 is shorter than the first length L1.
[0208] The third length L3 is, for example, more than 0.5 times and less than 0.8 times the first length L1.
[0209] The gate electrode 18 disposed in the third direction of the oxide semiconductor layer 16 does not include a second layer 18y. The gate electrode 18 disposed in the third direction of the oxide semiconductor layer 16 is formed only by the first layer 18x.
[0210] Figure 38 , Figure 39 , Figure 40 , Figure 41 , Figure 42 , Figure 43 and Figure 44 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the fifth embodiment. Figures 38-43 It corresponds to Figure 36 The image. Figure 44 It corresponds to Figure 37 The image.
[0211] For example, in the semiconductor device manufacturing method of the first embodiment, a titanium nitride film 50 is formed before the columnar body 37 is embedded with a tungsten film 39. A tungsten film 39 is formed on the titanium nitride film 50. Figure 38 ).
[0212] The titanium nitride film 50 is formed, for example, using a CVD method. The tungsten film 39 is formed, for example, using a CVD method. A portion of the titanium nitride film 50 and a portion of the tungsten film 39 ultimately become the gate electrode 18 and the first wiring layer 24. A portion of the titanium nitride film 50 becomes the first layer 18x. A portion of the tungsten film 39 becomes the second layer 18y.
[0213] Next, a portion of the tungsten film 39 is etched to expose the titanium nitride film 50 on the upper surface and sides of the columnar body 37. Figure 39 Tungsten film 39 is etched, for example, by RIE.
[0214] Next, the titanium nitride film 50 on the upper surface of the columnar body 37 is etched, exposing a portion of the second silicon oxide film 38 on the side of the columnar body 37. Figure 40 At this point, the titanium nitride film 50 is etched in such a way that the titanium nitride film 50 remaining along the side of the column 37 is thicker than that of other parts.
[0215] For example, by using a wet etching method, a thicker titanium nitride film 50 can be left along the columnar body 37.
[0216] Next, the columnar body 37 and the sidewall 41 are embedded with the third silicon oxide film 42. Figure 41 The third silicon oxide film 42 is formed, for example, using CVD.
[0217] Next, the third silicon oxide film 42 is etched to form the second opening 43 exposed by the titanium nitride film 50 and the tungsten film 39. Figure 42 The second opening 43 is formed using photolithography and RIE.
[0218] Next, using the third silicon oxide film 42 as a mask, the tungsten film 39 and the titanium nitride film 50 are etched. Figure 43 The tungsten film 39 and the titanium nitride film 50 are etched, for example, using the RIE method.
[0219] The etching process involves two steps: etching the tungsten film 39 and etching the titanium nitride film 50. During the etching of the tungsten film 39, conditions are selected that achieve a selectivity ratio with the titanium nitride film 50. This ensures that the titanium nitride film 50 remains reliably along the side of the columnar body 37.
[0220] in addition, Figure 44 It is relative to Figure 43 A cross-sectional view in the vertical direction. In this direction, the tungsten film 39 and the titanium nitride film 50 are completely shielded by the third silicon oxide film 42, and therefore the tungsten film 39 and the titanium nitride film 50 are not etched and are retained.
[0221] Then, the transistor 500 of the fifth embodiment can be manufactured by the same method as that of the first embodiment.
[0222] According to the transistor 500 of the fifth embodiment, similarly to the fourth embodiment, the gate electrode 18 has a multilayer structure with a first layer 18x and a second layer 18y, which, for example, can balance the control of the threshold voltage of the transistor 500 with the reduction of the resistance of the gate electrode 18. Specifically, for example, a material with a work function optimized for the threshold voltage of the transistor 500 is applied to the first layer 18x. And a material with low resistivity is applied to the second layer 18y.
[0223] In transistor 500, where the gate electrode 18 in the third direction of the oxide semiconductor layer 16 is formed only with the first layer 18x, the resistance increase of the gate electrode 18 around the oxide semiconductor layer 16 can be suppressed compared to the case where the transistor 400 of the fourth embodiment has a stacked structure of the first layer 18x and the second layer 18y. As described in the first embodiment, the effective width of the gate electrode 18 in the third direction narrows around the oxide semiconductor layer 16. An oxide film is formed, for example, at the interface between the first layer 18x and the second layer 18y. When the effective width is narrow and the first layer 18x and the second layer 18y are relatively thin, the resistance of the gate electrode 18 in the third direction of the oxide semiconductor layer 16 increases due to the fine-line effect of electron scattering from the oxide film at the interface. In transistor 500 of the fifth embodiment, since the gate electrode 18 in the third direction of the oxide semiconductor layer 16 is formed only with the first layer 18x, there is no interface. Therefore, the fine-line effect caused by electron scattering from the oxide film at the interface is not generated, and the increase in resistance of the gate electrode 18 in the third direction of the oxide semiconductor layer 16 is suppressed. Therefore, for example, the increase in wiring resistance in the second direction of the gate electrode 18 can be suppressed.
[0224] Furthermore, in the transistor 500 of the fifth embodiment, the gate electrode 18 in the third direction of the oxide semiconductor layer 16 is shortened along the length of the oxide semiconductor layer 16. This portion functions as an oxygen supply path after the transistor 500 is formed. Therefore, the oxygen vacancy concentration in the oxide semiconductor layer 16 can be easily adjusted, and the characteristics of the transistor 500 are stable.
[0225] Furthermore, in forming the pattern of the gate electrode 18, the transistor 500 of the fifth embodiment can be manufactured without forming the sidewall 41 used in the manufacturing method of the first embodiment. Therefore, the transistor 500 of the fifth embodiment can be manufactured using a simpler manufacturing method.
[0226] The semiconductor device according to the fifth embodiment can realize a semiconductor device with excellent transistor characteristics.
[0227] (Sixth Embodiment)
[0228] The semiconductor memory device of the sixth embodiment includes the semiconductor device of the first embodiment and a capacitor electrically connected to the first electrode or the second electrode.
[0229] The semiconductor memory device of the sixth embodiment is a semiconductor memory 600. The semiconductor memory device of the sixth embodiment is a DRAM. The semiconductor memory 600 uses the transistor 100 of the first embodiment as the switching transistor of the memory cell of the DRAM.
[0230] Hereinafter, some descriptions that are repeated in the first embodiment will be omitted.
[0231] Figure 45 This is an equivalent circuit diagram of the semiconductor memory device according to the sixth embodiment. Figure 45 The example shows a case where there is one storage unit MC, but storage units MC can also be arranged in an array.
[0232] The semiconductor memory 600 includes a memory cell MC, a word line WL, a bit line BL, and a board line PL. The memory cell MC includes a switching transistor TR and a capacitor CA. Figure 45 In the diagram, the area enclosed by the dashed line is the storage unit MC.
[0233] Word line WL is electrically connected to the gate electrode of switching transistor TR. Bit line BL is electrically connected to one of the source / drain electrodes of switching transistor TR. One electrode of capacitor CA is electrically connected to the other of the source / drain electrodes of switching transistor TR. The other electrode of capacitor CA is connected to plate line PL.
[0234] The storage cell MC stores data by accumulating charge in the capacitor CA. Data writing and reading are performed by turning on the switching transistor TR.
[0235] For example, when the desired voltage is applied to the bit line BL, the switching transistor TR is turned on to write data to the memory cell MC.
[0236] In addition, for example, by turning on the switching transistor TR, the voltage change of the bit line BL corresponding to the amount of charge accumulated in the capacitor is detected, and data is read out of the memory cell MC.
[0237] Figure 46 This is a schematic cross-sectional view of the semiconductor memory device according to the sixth embodiment. Figure 46 This shows a cross-section of the memory cell MC of the semiconductor memory 600.
[0238] The semiconductor memory 600 includes a silicon substrate 10, a switching transistor TR, a capacitor CA, and an interlayer insulating layer 22.
[0239] The switching transistor TR has a lower electrode 12, an upper electrode 14, an oxide semiconductor layer 16, a gate electrode 18, and a gate insulating layer 20.
[0240] The switching transistor TR has the same construction as the transistor 100 in the first embodiment.
[0241] Capacitor CA is disposed between silicon substrate 10 and switching transistor TR. Capacitor CA is disposed between silicon substrate 10 and lower electrode 12. Capacitor CA is electrically connected to lower electrode 12.
[0242] The capacitor CA includes a unit electrode 71, a plate electrode 72, and a capacitor insulating film 73. The unit electrode 71 is electrically connected to the lower electrode 12. For example, the unit electrode 71 is connected to the lower electrode 12.
[0243] Unit electrode 71 and plate electrode 72 are, for example, titanium nitride. The capacitor insulating film 73 has, for example, a multilayer structure of zirconium oxide, aluminum oxide, and zirconium oxide.
[0244] Gate electrode 18 is electrically connected, for example, to word line WL (not shown). Upper electrode 14 is electrically connected, for example, to bit line BL (not shown). Plate electrode 72 is connected, for example, to plate line PL (not shown).
[0245] The semiconductor memory 600 utilizes an oxide semiconductor transistor with extremely low channel leakage current during disconnection in the switching transistor TR. This results in DRAM with excellent charge retention characteristics.
[0246] Furthermore, the gate insulating layer 20 of the switching transistor TR in the semiconductor memory 600 has high reliability. Therefore, the reliability of the semiconductor memory 600 is improved.
[0247] In the sixth embodiment, a semiconductor memory using the transistor of the first embodiment has been described as an example, but the semiconductor memory of the embodiments of the present invention may also be a semiconductor memory using the transistor of the second to fourth embodiments.
[0248] In the sixth embodiment, the case where capacitor CA is electrically connected to the lower electrode 12 has been described as an example, but capacitor CA may also be electrically connected to the upper electrode 14.
[0249] The semiconductor memory device according to the sixth embodiment can realize a semiconductor memory device with excellent transistor characteristics.
[0250] (Seventh Embodiment)
[0251] The semiconductor device of the seventh embodiment differs from that of the semiconductor device of the first embodiment in that the first wiring layer functions as a gate electrode. Hereinafter, some details that are repeated in the first embodiment will be omitted.
[0252] Figure 47 This is a schematic cross-sectional view of the semiconductor device according to the seventh embodiment. Figure 47 It corresponds to the first embodiment. Figure 2 The image.
[0253] The semiconductor device of the seventh embodiment includes a transistor in which the first wiring layer 24 is configured as a gate electrode. The first wiring layer 24 has the same function as the gate electrode 18.
[0254] The first wiring layer 24 surrounds the oxide semiconductor layer 19 and the gate insulating layer 20. A channel for a transistor, with the first wiring layer 24 serving as the gate electrode, is formed in the oxide semiconductor layer 19. Figure 47 As shown, the transistor with the first wiring layer 24 as the gate electrode is configured such that the position of the transistor with the first wiring layer 24 as the gate electrode in the second direction is between the positions of the transistor with the gate electrode 18 as the gate electrode in the second direction.
[0255] (Example of variation)
[0256] The semiconductor device of the variation example of the seventh embodiment differs from the semiconductor device of the seventh embodiment in that the configuration of the transistor in which the first wiring layer is set as the gate electrode is different.
[0257] Figure 48 This is a schematic cross-sectional view of a semiconductor device according to a variation of the seventh embodiment. Figure 48 This corresponds to the 7th embodiment. Figure 47 The image.
[0258] like Figure 48 As shown, the transistor with the first wiring layer 24 as the gate electrode is configured such that the position of the transistor with the first wiring layer 24 as the gate electrode in the second direction is the same as the position of the transistor with the gate electrode 18 as the gate electrode in the second direction.
[0259] The semiconductor device according to the seventh embodiment and its variations can realize a semiconductor device with excellent transistor characteristics.
[0260] The foregoing has described several embodiments of the present invention, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, the constituent elements of one embodiment can be substituted or modified with the constituent elements of other embodiments. The embodiments or variations thereof are included within the scope or spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.
[0261] [Symbol Explanation]
[0262] 12 Lower electrode (Electrode 1)
[0263] 13 Lower electrode (3rd electrode)
[0264] 14 Upper electrode (second electrode)
[0265] 15. Upper electrode (4th electrode)
[0266] 16 Oxide semiconductor layer (first oxide semiconductor layer)
[0267] 16a, Region 1
[0268] 16b Region 2
[0269] 17. Oxide semiconductor layer (2nd oxide semiconductor layer)
[0270] 18 gate electrodes
[0271] 18a Part 1
[0272] Part 2 of 18b
[0273] Part 3 of 18c
[0274] 18x Level 1
[0275] 18y second floor
[0276] 20 gate insulating layers
[0277] 20a 1st film
[0278] 20b second membrane
[0279] 100 transistors (semiconductor devices)
[0280] 200 transistors (semiconductor devices)
[0281] 300 transistors (semiconductor devices)
[0282] 400 transistors (semiconductor devices)
[0283] 500 transistors (semiconductor devices)
[0284] 600 Semiconductor Memory (Semiconductor Storage Device)
[0285] w1 first width
[0286] w2 second width
[0287] CA capacitors
[0288] L1 first length
[0289] L2 second length
[0290] L3 third length
[0291] L4 is the fourth length.
Claims
1. A semiconductor device comprising: Electrode 1; Second electrode; A first oxide semiconductor layer is disposed between the first electrode and the second electrode; Third electrode; 4th electrode; The second oxide semiconductor layer is disposed between the third electrode and the fourth electrode, and is spaced apart from the first oxide semiconductor layer in a second direction perpendicular to the first direction connecting the first electrode and the second electrode; A gate electrode surrounds the first oxide semiconductor layer and the second oxide semiconductor layer, and extends in the second direction; and A gate insulating layer is disposed between the gate electrode and the first oxide semiconductor layer; and The gate electrode comprises a first part and a second part. The first portion faces the first oxide semiconductor layer in the second direction, is connected to the gate insulating layer, and has a first length in the first direction. The second portion is a distance equal to half the distance between the first oxide semiconductor layer and the second oxide semiconductor layer in the second direction, and has a second length in the first direction. The first length is longer than the second length.
2. The semiconductor device according to claim 1, wherein the gate insulating layer is disposed between the gate electrode and the first electrode in the first direction.
3. The semiconductor device of claim 1, wherein the gate electrode further comprises a third portion. The third portion faces the first oxide semiconductor layer and is connected to the gate insulating layer in a third direction perpendicular to the first and second directions, and has a third length in the first direction, the third length being longer than the second length.
4. The semiconductor device of claim 1, wherein the first oxide semiconductor layer includes a first region and a second region disposed between the first region and the second electrode, the first region being connected to the gate insulating layer in a first direction, and the second region being surrounded by the gate insulating layer. In a cross-section parallel to the first direction, the first width of the first region in the third direction, which is perpendicular to the second direction, is wider than the second width of the second region in the third direction.
5. The semiconductor device according to claim 4, wherein the gate insulating layer is disposed in the first direction, between the first region and the gate electrode.
6. The semiconductor device of claim 4, wherein the difference between the first width and the second width is more than 1 nm and less than 20 nm.
7. The semiconductor device of claim 1, wherein the gate insulating layer comprises a first film and a second film having a different chemical composition from the first film and sandwiching the first film between the second film and the first oxide semiconductor layer.
8. The semiconductor device of claim 7, wherein the first film comprises silicon oxide and the second film comprises a material having a dielectric constant higher than that of silicon oxide.
9. The semiconductor device of claim 1, wherein the gate electrode comprises a first layer and a second layer having a different chemical composition from the first layer and sandwiched between the second and the gate insulating layer, wherein the first layer is present.
10. The semiconductor device of claim 9, wherein the resistivity of the material contained in the second layer is lower than the resistivity of the material contained in the first layer.
11. The semiconductor device of claim 9, wherein the gate electrode further comprises a third portion. The third portion faces the first oxide semiconductor layer and is connected to the gate insulating layer in a third direction perpendicular to the first and second directions, and has a third length in the first direction, the third length being shorter than the first length.
12. The semiconductor device of claim 1, further comprising a first wiring layer, the first wiring layer being disposed in a third direction perpendicular to the first direction and the second direction of the gate electrode, extending in the first direction, and comprising the same material as the gate electrode; The fourth length of the first wiring layer in the first direction, which is parallel to the first direction and the third direction and includes the first oxide semiconductor layer, is shorter than the first length.
13. The semiconductor device of claim 12, wherein the gate insulating layer is connected to the first wiring layer.
14. The semiconductor device of claim 1, wherein the first electrode is spaced apart from the gate insulating layer in the first direction.
15. A semiconductor memory device comprising: The semiconductor device according to claim 1; and A capacitor electrically connected to the first electrode or the second electrode.