Method of forming self-aligned blocking structures and semiconductor structures

Abstract

The application relates to a self-aligned barrier structure forming method and a semiconductor structure, and relates to the technical field of integrated circuits. The self-aligned barrier structure forming method of the application forms a protective sidewall for protecting the line width of a barrier pattern on the sidewall of the barrier pattern before wet etching. In the wet etching process, the protective sidewall delays or avoids the contact between a wet etchant and the barrier pattern, thereby improving the problem of the lateral etching of the wet etchant on the barrier pattern, improving the line width precision of the formed self-aligned barrier structure, improving or eliminating the leakage problem caused by the reduction of the line width of the self-aligned barrier structure, and improving the stability of a device. The etching process or the wet etchant does not need to be changed, the current manufacturing process of the self-aligned barrier structure has good compatibility, the process is simple, and the cost is low.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a method for forming a self-aligned blocking structure and a semiconductor structure. Background Technology

[0002] As semiconductor manufacturing processes continue to advance to more advanced technology nodes, the feature size of semiconductor devices is constantly shrinking, and the requirements for process precision are becoming increasingly stringent. Any tiny dimensional deviation or structural defect may lead to severe degradation or even failure of semiconductor device performance.

[0003] At advanced nodes, in order to improve device contact performance and reduce series resistance, a self-aligned silicide block (SAB) is used to define the formation region of the self-aligned silicide, thereby forming a self-aligned silicide with low contact resistance. The self-aligned silicide process has very high requirements for the dimensional accuracy of the self-aligned block. If the dimensional accuracy of the self-aligned block deviates, the self-aligned silicide may form in an unexpected location, leading to the risk of short circuit leakage. Summary of the Invention

[0004] Therefore, it is necessary to provide a method for forming a self-aligned blocking structure and a semiconductor structure to address the problems in the prior art.

[0005] To achieve the above objectives, in a first aspect, this application provides a method for forming a self-aligned blocking structure, comprising:

[0006] A substrate is provided, on which a first barrier layer and a second barrier layer are sequentially formed;

[0007] Using the first barrier layer as an etch stop layer, the second barrier layer is patterned and etched to form a barrier pattern;

[0008] A protective sidewall is formed on the sidewall of the blocking pattern;

[0009] Perform wet etching to remove the protective sidewalls and the first barrier layer not covered by the barrier pattern. The first barrier layer and the second barrier layer remaining after etching together form a self-aligned barrier structure.

[0010] In one embodiment, during the wet etching process, the etching rate of the wet etchant on the first barrier layer is greater than the etching rate on the second barrier layer.

[0011] The wet etchant has a higher etching rate on the protective sidewall than on the second barrier layer.

[0012] In one embodiment, forming a protective sidewall on the sidewall of the blocking pattern includes:

[0013] A protective material layer is formed, which covers the blocking pattern and the top surface of the first blocking layer exposed by the blocking pattern;

[0014] Using the top surface of the second barrier layer as the etching stop layer, the protective material layer is etched back, retaining the protective material layer on the sidewall of the barrier pattern to form the protective sidewall.

[0015] In one embodiment, the material of the protective material layer is the same as the material of the first barrier layer.

[0016] In one embodiment, the thickness ratio of the protective sidewall to the first barrier layer is (0.9-1.1):1.

[0017] In one embodiment, the thickness of the first barrier layer is between 70 angstroms and 110 angstroms; the thickness of the second barrier layer is between 200 angstroms and 300 angstroms; wherein the protective sidewall has the same thickness as the first barrier layer.

[0018] In one embodiment, the first barrier layer and the protective sidewall are silicon oxide layers; the second barrier layer is a silicon nitride layer; and the wet etchant includes hydrofluoric acid.

[0019] In one embodiment, during wet etching, the protective sidewall protects the barrier pattern so that the critical dimensions of the barrier pattern remain unchanged before and after wet etching.

[0020] In one embodiment, after forming the self-aligned blocking structure, the following is included:

[0021] A metal silicide layer is formed on the substrate surface exposed by the self-aligned barrier structure.

[0022] In a second aspect, this application provides a semiconductor structure including a substrate and a self-aligned barrier structure disposed on the substrate, wherein the sidewall profile of the self-aligned barrier structure is defined by the method for forming the self-aligned barrier structure described in the first aspect.

[0023] The unexpected technical effect of this application is that, before wet etching, a protective sidewall is formed on the sidewall of the barrier pattern to protect the linewidth of the barrier pattern. During the wet etching process, the protective sidewall delays or prevents the wet etchant from contacting the barrier pattern, thereby improving the problem of the wet etchant laterally etching the barrier pattern, improving the linewidth accuracy of the formed self-aligned barrier structure, and improving or eliminating the leakage problem caused by the reduction in the linewidth of the self-aligned barrier structure, thus improving the stability of the device. The self-aligned barrier structure formation method of this embodiment does not require changes to the etching process or wet etchant, and has good compatibility with the current fabrication process of self-aligned barrier structures. The process is simple and low in cost. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a process flow diagram of a method for forming a self-aligned blocking structure provided in an exemplary embodiment of this application;

[0026] Figure 2 This is a schematic diagram of the structure after forming a first barrier layer and a second barrier layer on a substrate, as provided in an exemplary embodiment of this application.

[0027] Figure 3 This is a schematic diagram of the structure after the patterned second barrier layer forms a barrier pattern, as provided in an exemplary embodiment of this application.

[0028] Figure 4 This is a schematic diagram of the structure after the formation of the protective material layer, provided in an exemplary embodiment of this application;

[0029] Figure 5 This is a schematic diagram of the structure after a protective sidewall is formed on the sidewall of the blocking pattern, as provided in an exemplary embodiment of this application.

[0030] Figure 6 This is a schematic diagram of the structure after forming a self-aligning barrier, provided in an exemplary embodiment of this application.

[0031] Figure 7 This is a schematic diagram of the structure after the formation of a metal silicide layer, provided in an exemplary embodiment of this application.

[0032] Explanation of reference numerals in the attached figures:

[0033] 10. Substrate; 21. First barrier layer; 22. Second barrier layer; 22a. Barrier pattern; 20. Self-aligned barrier structure; 31. Protective material layer; 30. Protective sidewall; 41. Metal silicide layer. Detailed Implementation

[0034] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0036] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0037] As described in the background section, as the size nodes of semiconductor fabrication continue to shrink, the tolerance for process precision decreases dramatically. Any minute dimensional deviation or structural defect can be amplified, leading to severe degradation or even failure of device performance. Therefore, self-aligned silicide processes place even higher demands on the dimensional accuracy of self-aligned barrier structures.

[0038] In self-aligned silicide processes, a silicon oxide layer and a silicon nitride layer are typically deposited sequentially on a semiconductor substrate. The silicon nitride layer is first patterned to form the desired barrier pattern. Then, wet etching is used to remove the exposed silicon oxide layer, allowing subsequent silicide reactions to occur only in areas not covered by the self-aligned barrier structure, thus forming the self-aligned silicide process. However, wet etching is isotropic. During the etching of the silicon oxide layer, the etchant not only etches the silicon oxide layer but also erodes the silicon nitride layer laterally. This results in the actual linewidth of the silicon nitride portion of the formed self-aligned barrier structure being smaller than the designed linewidth, leading to a reduction in the effective barrier area of ​​the self-aligned barrier structure.

[0039] During the subsequent self-aligned silicide formation process, metal diffuses beneath the over-etched silicon nitride layer of the self-aligned barrier structure, reacting with the substrate below the silicon nitride layer to form metal silicides. These excess silicides may bridge the source / drain regions with the gate, or form conductive paths between different active regions, leading to severe junction leakage or even short circuits, reducing device yield and reliability.

[0040] To address the issue of lateral erosion in silicon nitride layers, related technologies employ increasing the thickness of the silicon nitride layer. However, this approach introduces greater stress, impacting device performance and increasing the difficulty and cost of patterning etching. Other technologies utilize wet etchants with higher etching ratios for silicon nitride layers, but this approach suffers from poor compatibility between the new etchant and the original fabrication process, as well as high costs. Furthermore, replacing wet etching with dry etching of the silicon oxide layer presents challenges, including significant substrate damage and low etching selectivity.

[0041] Therefore, how to effectively suppress or even eliminate the lateral etching problem of self-aligned barrier structures while maintaining process simplicity, low cost, and high compatibility with existing production lines has become an urgent problem to be solved in advanced processes.

[0042] According to an exemplary embodiment, this embodiment provides a method for forming a self-aligned blocking structure, such as... Figure 1 As shown, the method for forming the self-aligned blocking structure in this embodiment includes the following steps:

[0043] Step S101: Provide a substrate 10, and sequentially form a first barrier layer 21 and a second barrier layer 22 on the substrate 10.

[0044] In this embodiment, as Figure 2As shown, substrate 10 can be a semiconductor substrate; the material of the semiconductor substrate can include silicon (Si), germanium (Ge), or silicon-germanium (GeSi), silicon carbide (SiC); it can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it can include other materials, such as gallium arsenide and other group III-V compounds. The substrate can be a single-layer structure or a multi-layer structure.

[0045] In this embodiment, as Figure 2 As shown, a first barrier layer 21 and a second barrier layer 22 are sequentially stacked on the substrate 10. The material of the first barrier layer 21 is selected to be a dielectric material with a relatively high etching rate to the wet etchant used subsequently, such as silicon oxide (SiO2). The second barrier layer 22 is used to form the main part of the self-aligned barrier structure 20, and the material of the second barrier layer 22 is selected to be a dielectric material with a relatively low etching rate to the wet etchant, such as silicon nitride (SiN).

[0046] For example, the first barrier layer 21 can be formed using thermal oxidation, atomic layer deposition (ALD), or chemical vapor deposition (CVD).

[0047] For example, an atomic layer deposition process or a chemical vapor deposition process is used to deposit a second barrier layer 22.

[0048] Step S102: Using the first barrier layer 21 as the etch stop layer, pattern the second barrier layer 22 to form a barrier pattern 22a.

[0049] In this embodiment, a photoresist layer is formed on the second barrier layer 22, and an exposure-development process is performed on the photoresist layer to form a photoresist pattern. The second barrier layer 22 is etched according to the photoresist pattern. The etching process is dry etching, and the first barrier layer 21 is used as the etching stop layer to form a barrier pattern 22a.

[0050] In this embodiment, the second barrier layer 22 can be etched using a reactive ion etching (RIE) process containing fluorocarbon gas. The fluorocarbon gas has extremely high selectivity for the underlying first barrier layer 21 (selectivity ratio typically >20:1), ensuring that the etching rate slows down or stops when it reaches the surface of the first barrier layer 21, thereby etching the second barrier layer 22 into a barrier pattern 22a with vertical or nearly vertical sidewalls.

[0051] For example, the material of the first barrier layer 21 can be selected as doped silicon oxide, such as at least one of phosphorus silicate glass (PSG) and borosilicate glass (BSG); or, the material of the first barrier layer 21 can also be selected as other low-k dielectric materials or amorphous silicon.

[0052] For example, the material of the second dielectric layer may include at least one of silicon nitride (SIN), silicon oxynitride (SiON), silicon carbide (SiC), or other high-k dielectric materials.

[0053] Step S103: Form a protective sidewall 30 on the sidewall of the blocking pattern 22a.

[0054] In this embodiment, a protective material layer 31 can be deposited to cover the blocking pattern 22a and the first blocking layer 21 exposed by the blocked pattern 22a. Then, the protective material layer 31 on the first blocking layer 21 can be etched away to form a protective sidewall 30 covering the sidewall of the blocking pattern 22a. The protective sidewall 30 is used to protect the blocking pattern 22a and prevent the blocking pattern 22a from being laterally etched in the subsequent etching step of the first blocking layer 21.

[0055] For example, the material of the protective sidewall 30 can be selected as doped silicon oxide, such as at least one of phosphorus silicate glass (PSG) and borosilicate glass (BSG); or, the material of the protective sidewall 30 can also be selected as other low-k dielectric materials or amorphous silicon.

[0056] The material of the protective sidewall 30 can be the same as that of the first barrier layer 21, or the material of the protective sidewall 30 can be a different material from that of the first barrier layer 21.

[0057] Step S104: Perform wet etching to remove the protective sidewall 30 and the first barrier layer 21 not covered by the barrier pattern 22a. The first barrier layer 21 and the second barrier layer 22 remaining after etching together form a self-aligned barrier structure 20.

[0058] In this embodiment, the structure after the protective sidewall 30 is formed is treated with a wet etchant. The wet etchant etches the protective sidewall 30 and the first barrier layer 21 not covered by the barrier pattern 22a. During the wet etching process, the sidewall of the barrier pattern 22a is protected by the protective sidewall 30. The protective sidewall 30 prevents the wet etchant from contacting the barrier pattern 22a, thereby delaying or even avoiding the lateral etching of the barrier pattern 22a by the wet etchant, which would reduce its lateral size. Finally, the protective sidewall 30 and the first barrier layer 21 not covered by the barrier pattern 22a are etched away, exposing part of the surface of the substrate 10. The first barrier layer 21 located below the barrier pattern 22a is retained. The retained first barrier layer 21 and the second barrier layer 22 of the barrier pattern 22a together form a self-aligned barrier structure 20.

[0059] In this embodiment, the method for forming a self-aligned barrier structure involves forming a protective sidewall 30 on the sidewall of the barrier pattern 22a before wet etching to protect the linewidth of the barrier pattern 22a. During wet etching, the protective sidewall 30 delays or prevents the wet etchant from contacting the barrier pattern 22a, thereby improving the problem of the wet etchant laterally etching the barrier pattern 22a and improving the linewidth accuracy of the formed self-aligned barrier structure 20. This method can improve or eliminate leakage problems caused by the reduction in linewidth of the self-aligned barrier structure 20 and improve the stability of the device. The method for forming a self-aligned barrier structure in this embodiment does not require changes to the etching process or wet etchant, and has good compatibility with the current manufacturing process of the self-aligned barrier structure 20. The process is simple and low-cost.

[0060] In some embodiments, during the wet etching process, the etching rate of the wet etchant on the first barrier layer 21 is greater than the etching rate on the second barrier layer 22; this ensures that the wet etching can cleanly remove all of the first barrier layer 21 not covered by the barrier pattern 22a, while also helping to reduce the lateral etching damage of the wet etchant to the barrier pattern 22a.

[0061] The wet etchant has a higher etching rate for the protective sidewall 30 than for the second barrier layer 22. This allows for the complete removal of the protective sidewall 30 during wet etching, preventing its residue on the sidewalls of the barrier pattern 22a and thus avoiding an increase in linewidth. During wet etching, the protective sidewall 30 consumes the etchant's horizontal etching action (parallel to the substrate 10), delaying and shortening the contact time between the wet etchant and the sidewalls of the second barrier layer 22. This improves the lateral etching of the second barrier layer 22 of the barrier pattern 22a by isotropic wet etching, thereby increasing the linewidth accuracy of the final self-aligned barrier structure 20.

[0062] In some embodiments, step S103, forming a protective sidewall 30 on the sidewall of the blocking pattern 22a, includes the following steps:

[0063] Step S1031: Form a protective material layer 31, which covers the blocking pattern 22a and the top surface of the first blocking layer 21 exposed by the blocking pattern 22a.

[0064] In this embodiment, an atomic layer deposition (ALD) or high-density plasma chemical vapor deposition (HDP-CVD) process can be used to deposit a full-layer protective material layer 31. The protective material layer 31 conformally covers the blocking pattern 22a and the top surface of the first blocking layer 21 exposed by the blocking pattern 22a, so as to ensure that the thickness of the protective material layer 31 located on the sidewall of the blocking pattern 22a is uniform.

[0065] In this embodiment, an atomic layer deposition process is used to form the protective material layer 31. Atomic layer deposition can achieve atomic-level thickness control and near 100% step coverage, ensuring that the protective material layer 31 forms a uniform thickness and height coverage on the top of the barrier pattern 22a, the steep sidewalls, and the exposed horizontal surface of the first barrier layer 21.

[0066] Step S1032: Using the top surface of the second barrier layer 22 as the etching stop layer, etch back the protective material layer 31, retaining the protective material layer 31 on the sidewall of the barrier pattern 22a, to form a protective sidewall 30.

[0067] In this embodiment, an anisotropic dry etching process is used to etch back the protective material layer 31. The etching rate along the direction perpendicular to the substrate 10 is much higher than that along the direction parallel to the substrate 10. By controlling the composition of the etching gas, the etching power, and the etching time, the horizontal protective material layer 31 is selectively and substantially vertically removed during the back etching process. The protective material layer 31 on top of the barrier pattern 22a and the protective material layer 31 on the surface of the first barrier layer 21 are etched away. In this embodiment, during the back etching of the protective material layer 31, the top surface of the second barrier layer 22 is used as the etching stop layer. Etching stops when the top surface of the second barrier layer 22 is exposed, thus leaving only the protective material layer 31 attached to the sidewall of the barrier pattern 22a, forming the protective sidewall 30.

[0068] For example, fluorocarbon gas and / or oxygen can be used as etching gas to etch the protective material layer 31.

[0069] In some embodiments, the material of the protective material layer 31 is the same as the material of the first barrier layer 21. This ensures that the protective sidewall 30 and the first barrier layer 21 have completely identical or highly similar etching rates to the wet etchant, guaranteeing that during wet etching, the protective sidewall 30 and the first barrier layer 21 can be removed at a synchronous and predictable rate. This makes the entire wet etching process more uniform and controllable, avoiding uneven etching or residues that may result from different materials.

[0070] In one example, the material of the protective material layer 31 and the material of the first barrier layer 21 may both include silicon oxide.

[0071] In another example, the material of the protective material layer 31 and the material of the first barrier layer 21 may both include amorphous silicon.

[0072] In some embodiments, the thickness ratio of the protective sidewall 30 to the first barrier layer 21 is (0.9-1.1):1. When the thickness ratio of the protective sidewall 30 to the first barrier layer 21 is less than 0.9:1 (i.e., the protective sidewall 30 is relatively too thin), the protective sidewall 30 may be completely etched away before the first barrier layer 21 is completely etched through and the substrate 10 is exposed. This results in the sidewall of the barrier pattern 22a losing its protection, and the second barrier layer 22 coming into direct contact with the wet etchant. The second barrier layer 22 is subjected to lateral erosion, affecting the linewidth accuracy of the self-aligned barrier structure 20. On the other hand, when the thickness ratio of the protective sidewall 30 to the first barrier layer 21 is greater than 1.1:1 (i.e., the protective sidewall 30 is relatively too thick), the excessively thick protective sidewall 30 may cause a micro-load effect on the top of the barrier pattern 22a, increasing the process difficulty and non-uniformity of the dry etch-back protective material layer 31.

[0073] For example, the thickness ratio of the protective sidewall 30 to the first barrier layer 21 can be 0.9:1, 0.91:1, 0.92:1, 0.93:1, 0.94:1, 0.95:1, 0.96:1, 0.97:1, 0.98:1, 0.99:1, 1.0:1, 1.02:1, 1.04:1, 1.05:1, 1.07:1, 1.09:1, or 1.1:1.

[0074] In some embodiments, the thickness ratio of the protective sidewall 30 to the first barrier layer 21 is 1:1. Thus, the protective sidewall 30 and the first barrier layer 21 are removed substantially simultaneously during wet etching. As the first barrier layer 21 is etched, the protective sidewall 30 is also completely etched away, exposing the sidewalls of the second barrier layer 22. Immediately afterward, the wet etching process ends and a cleaning step begins, minimizing the contact time between the wet etchant and the second barrier layer 22, or even achieving near-non-contact. This prevents the wet etchant from laterally eroding the second barrier layer 22, ensuring that the critical dimensions of the second barrier layer 22 remain unchanged, and that the actual linewidth of the self-aligned barrier structure 20 matches the designed linewidth.

[0075] In some embodiments, the thickness of the first barrier layer 21 is between 70 angstroms and 110 angstroms; this ensures that the thickness of the first barrier layer 21 is sufficient to effectively protect the substrate 10 during the patterning etching of the second barrier layer 22, while avoiding excessively thick first barrier layer 21 which would lead to excessively long wet etching time. The protective sidewall 30 has the same thickness as the first barrier layer 21.

[0076] For example, the thickness of the first barrier layer 21 can be 70 angstroms, 75 angstroms, 80 angstroms, 85 angstroms, 90 angstroms, 95 angstroms, 100 angstroms, 105 angstroms or 110 angstroms; the thickness of the protective sidewall 30 can be 70 angstroms, 75 angstroms, 80 angstroms, 85 angstroms, 90 angstroms, 95 angstroms, 100 angstroms, 105 angstroms or 110 angstroms.

[0077] The thickness of the second barrier layer 22 is between 200 angstroms and 300 angstroms; this thickness of the second barrier layer 22 can provide the necessary mechanical strength and barrier capability for the finally formed self-aligned barrier structure 20 to effectively resist the diffusion of metal atoms during the subsequent formation of metal silicides.

[0078] For example, the thickness of the second barrier layer 22 can be 200 angstroms, 210 angstroms, 220 angstroms, 230 angstroms, 240 angstroms, 250 angstroms, 260 angstroms, 270 angstroms, 280 angstroms, 290 angstroms or 300 angstroms.

[0079] In one example, the thickness of the first barrier layer 21 is 95 angstroms, the thickness of the second barrier layer 22 can be 210 angstroms, and the thickness of the protective sidewall 30 is 70 angstroms.

[0080] It is understandable that, for the fabrication of devices corresponding to more advanced nodes, under the premise that the thickness ratio of the protective sidewall 30 to the first barrier layer 21 is kept within the range of (0.9-1.1:1), the thickness of the first barrier layer 21, the second barrier layer 22 and the protective sidewall 30 can be reduced proportionally.

[0081] In some embodiments, the first barrier layer 21 and the protective sidewall 30 are silicon oxide layers; the second barrier layer 22 is a silicon nitride layer; and the wet etchant includes hydrofluoric acid.

[0082] The wet etching agent can be a diluted hydrofluoric acid solution (DHF); for example, the wet etching agent can be a diluted hydrofluoric acid solution (DHF) with a concentration of 0.1% to 5%, and the temperature of the wet etching agent can be 20℃-30℃.

[0083] In some embodiments, during wet etching, the protective sidewall 30 protects the blocking pattern 22a so that the critical dimensions of the blocking pattern 22a remain unchanged before and after wet etching.

[0084] It should be noted that "critical dimensions remain unchanged" in this application refers to the critical dimensions remaining substantially unchanged. Specifically, during the wet etching process in step S104, the protective sidewall 30 replaces the second barrier layer 22, consuming the lateral activity of the wet etchant and delaying the time for the wet etchant to directly etch the sidewalls of the second barrier layer 22. Therefore, compared with the process without the protective sidewall 30, the lateral erosion of the second barrier layer 22 caused by the wet etching step is suppressed to a negligible level. Measurement results show that after adopting the formation method of this application, the critical dimension change of the barrier pattern 22a before and after wet etching is less than 3 nanometers, and can even reach the sub-nanometer level, achieving the goal of keeping the critical dimensions of the barrier pattern 22a unchanged before and after wet etching.

[0085] The self-aligned barrier structure 20 formed in this embodiment includes a first barrier layer 21 at the bottom and a second barrier layer 22 at the top. The line width of the first barrier layer 21 at the bottom is the same as that of the second barrier layer 22 at the top. The sidewall profile of the self-aligned barrier structure 20 is a vertical plane that is substantially perpendicular to the substrate 10.

[0086] In some embodiments, after step S104 forms the self-aligned blocking structure 20, the following steps are also performed:

[0087] Step S105: Form a metal silicide layer 41 on the surface of the substrate 10 exposed by the self-aligned blocking structure 20.

[0088] In this embodiment, a metal layer (not shown) is first deposited, which continuously covers the surface of the substrate 10 exposed by the self-alignment barrier structure 20 and the outer surface of the self-alignment barrier structure 20. For example, the material of the metal layer may include nickel (Ni).

[0089] Subsequently, the structure after the metal layer is formed undergoes a thermal annealing process, which can be performed in a furnace tube. Specifically, in the region where the substrate 10 contacts the metal layer, the metal material of the metal layer reacts with the silicon in the substrate 10 to form a metal silicide layer 41. For example, the material of the metal silicide layer 41 may include nickel silicide, such as NiSi.

[0090] Then, selective wet etching can be used to remove the unreacted metal layer. Finally, thermal annealing can be performed again to stabilize the phase state of the metal silicide layer 41 and further reduce its resistance.

[0091] For example, a mixed solution of sulfuric acid and hydrogen peroxide, i.e., SC-1 solution, can be used to etch away the unreacted metal layer.

[0092] In this embodiment, due to the high verticality of the sidewall morphology of the self-aligned barrier structure 20 and the fact that the horizontal linewidth of the self-aligned barrier structure 20 is consistent with the designed linewidth height, the self-aligned barrier structure 20 can effectively prevent metal atoms from diffusing to the region below its sidewall during the thermal annealing process of forming the metal silicide layer 41, thus avoiding the formation of metal silicide below the self-aligned barrier structure 20. This improves or even avoids the leakage and short circuit risks caused by the formation of metal silicide below the self-aligned barrier structure 20, thereby improving the electrical performance of the semiconductor device and the product yield.

[0093] In some embodiments, the method for forming the self-aligned barrier structure of this embodiment can be used to form the source / drain contacts of a transistor. The self-aligned barrier structure 20 is formed at the edge of the active region. For example, the self-aligned barrier structure 20 can be located near the shallow trench isolation structure or the gate sidewall of the active region. The self-aligned barrier structure 20 exposes the source or drain region of the transistor and is used to prevent metal from diffusing below the shallow trench isolation structure or the gate. This ensures that the formed metal silicide layer 41 is located on top of the source or drain region or on top of the raised source or drain region, optimizing the contact resistance of the source or drain region, while eliminating leakage paths between the source or drain region and adjacent active regions or gates caused by bridging with the metal silicide layer 41.

[0094] In some embodiments, the method for forming the self-aligned barrier structure of this embodiment can also be used to form a gate contact.

[0095] In some embodiments, the method for forming the self-aligned barrier structure of this embodiment is applied to advanced logic technology nodes. For example, it can be applied to the fabrication of transistors at 7 nanometers and below.

[0096] According to an exemplary embodiment, this embodiment provides a semiconductor structure including a substrate 10 and a self-aligned barrier structure 20 disposed on the substrate 10, wherein the sidewall profile of the self-aligned barrier structure 20 is defined by the method for forming the self-aligned barrier structure described in the above embodiment.

[0097] The semiconductor structure of this embodiment includes a self-aligned barrier structure 20 comprising a bottom first barrier layer 21 and a top second barrier layer 22. The linewidth of the bottom first barrier layer 21 is the same as that of the top second barrier layer 22. The sidewall profile of the self-aligned barrier structure 20 is a vertical plane substantially perpendicular to the substrate 10.

[0098] The semiconductor structure in this embodiment can be Dynamic Random Access Memory (DRAM), Static Random-Access Memory (SRAM), Flash EPROM, Ferroelectric Random Access Memory (FeRAM), Magnetic Random-Access Memory (MRAM), or other types of memory.

[0099] The unexpected technical effect of this application is that: before wet etching, a protective sidewall is formed on the sidewall of the barrier pattern 22a to protect the linewidth of the barrier pattern 22a. During the wet etching process, the protective sidewall 30 delays or prevents the wet etchant from contacting the barrier pattern 22a, thereby improving the problem of the wet etchant laterally etching the barrier pattern 22a, improving the linewidth accuracy of the formed self-aligned barrier structure 20, improving or eliminating the leakage problem caused by the reduction in linewidth of the self-aligned barrier structure 20, and improving the stability of the device; it does not require changing the etching process or wet etchant, has good compatibility with the current manufacturing process of the self-aligned barrier structure 20, and the process is simple and low in cost.

[0100] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0101] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for forming a self-aligned blocking structure, characterized in that, include: A substrate is provided, on which a first barrier layer and a second barrier layer are sequentially formed; Using the first barrier layer as an etch stop layer, the second barrier layer is patterned and etched to form a barrier pattern; A protective sidewall is formed on the sidewall of the blocking pattern; Wet etching is performed to remove the protective sidewall and the first barrier layer not covered by the barrier pattern. The first barrier layer and the second barrier layer remaining after etching together form a self-aligned barrier structure. The etching rate of the wet etchant on the first barrier layer is greater than the etching rate on the second barrier layer, and the etching rate of the wet etchant on the protective sidewall is greater than the etching rate on the second barrier layer.

2. The method for forming a self-aligned blocking structure according to claim 1, characterized in that, The formation of a protective sidewall on the sidewall of the blocking pattern includes: A protective material layer is formed, which covers the blocking pattern and the top surface of the first blocking layer exposed by the blocking pattern; Using the top surface of the second barrier layer as the etching stop layer, the protective material layer is etched back, retaining the protective material layer on the sidewall of the barrier pattern to form the protective sidewall.

3. The method for forming a self-aligned blocking structure according to claim 2, characterized in that, The material of the protective material layer is the same as that of the first barrier layer.

4. The method for forming a self-aligned blocking structure according to claim 1 or 3, characterized in that, The thickness ratio of the protective sidewall to the first barrier layer is (0.9-1.1):

1.

5. The method for forming a self-aligned blocking structure according to claim 4, characterized in that, The thickness of the first barrier layer is between 70 angstroms and 110 angstroms; the thickness of the second barrier layer is between 200 angstroms and 300 angstroms; wherein the protective sidewall has the same thickness as the first barrier layer.

6. The method for forming a self-aligned blocking structure according to claim 1 or 3, characterized in that, The first barrier layer and the protective sidewall are silicon oxide layers; the second barrier layer is a silicon nitride layer; the wet etchant includes hydrofluoric acid.

7. The method for forming a self-aligned blocking structure according to claim 1 or 3, characterized in that, During wet etching, the protective sidewalls protect the barrier pattern so that the critical dimensions of the barrier pattern remain unchanged before and after wet etching.

8. The method for forming a self-aligned blocking structure according to claim 1, characterized in that, After forming the self-aligned blocking structure, the following is included: A metal silicide layer is formed on the substrate surface exposed by the self-aligned barrier structure.

9. A semiconductor structure, characterized in that, It includes a substrate and a self-aligned barrier structure disposed on the substrate, the sidewall profile of the self-aligned barrier structure being defined by the method of forming the self-aligned barrier structure according to any one of claims 1-8.

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