Semiconductor device

Abstract

Embodiments provide a semiconductor device having a highly reliable terminal structure. According to one embodiment, a semiconductor device includes: a circuit board; the circuit substrate is arranged above the circuit substrate; a semiconductor chip provided between the circuit substrates; a first pillar provided between the circuit substrates; and a main terminal provided at one end of the circuit board in the Y direction and having a cutout. A cutout of the main terminal has a first portion, a second portion, and a third portion. The first portion extends in the Y direction from one end of the main terminal, the second portion is continuous with the first portion and extends in the X direction, and the third portion is continuous with the second portion and extends in the Y direction.

Description

[0001] Reference to Related Applications

[0002] This application claims priority to Japanese Patent Application No. 2024-160087 (Filing Date: September 17, 2024). This application incorporates by reference the entire contents of the base application. TECHNICAL FIELD

[0003] Embodiments of the present application relate to a semiconductor device. BACKGROUND

[0004] A semiconductor device including an insulating circuit board on which a semiconductor chip is mounted is known. SUMMARY

[0005] An object of the present application is to provide a semiconductor device having a terminal structure with high reliability.

[0006] The semiconductor device of an embodiment includes a first circuit board, a second circuit board disposed above the first circuit board, a first semiconductor chip disposed between the first circuit board and the second circuit board, a first pillar disposed between the first circuit board and the second circuit board, and a first terminal disposed at one end of the first circuit board in a first direction and having a first cutout. The first cutout of the first terminal has a first portion, a second portion, and a third portion. The first portion extends from one end of the first terminal in the first direction, the second portion is continuous with the first portion and extends in a second direction intersecting the first direction, and the third portion is continuous with the second portion and extends in the first direction. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is a perspective view showing an external configuration of a semiconductor device of an embodiment.

[0008] Figure 2 is a perspective view of a main terminal of a semiconductor device of an embodiment.

[0009] Figure 3 is a circuit diagram showing a circuit structure of a semiconductor device of an embodiment.

[0010] Figure 4 is a top view showing an internal configuration of a semiconductor device of an embodiment.

[0011] Figure 5 and Figure 6 is a sectional view showing an internal configuration of a semiconductor device of an embodiment.

[0012] Figure 7is a plan view of a main terminal of the semiconductor device of the embodiment.

[0013] Figure 8 is a sectional view of a main terminal of the semiconductor device of the embodiment.

[0014] Figure 9 is a plan view of another main terminal of the semiconductor device of the embodiment. DETAILED DESCRIPTION

[0015] Embodiments will be described below with reference to the accompanying drawings. In the following description, components having the same function and structure are designated by the same reference numerals. In addition, the embodiments shown below exemplify devices, methods, and the like for embodying the technical ideas of the embodiments, and the materials, shapes, configurations, arrangements, and the like of the constituent components are not limited to those described below.

[0016] (Embodiment)

[0017] A semiconductor device of an embodiment will be described. The semiconductor device includes a semiconductor chip and two insulating circuit substrates sandwiching the semiconductor chip from above and below, and has a package configuration in which they are held with a molding material. The semiconductor device is a power module, for example, for motor drive for an electric automobile.

[0018] 1. Outline configuration of semiconductor device

[0019] First, the outline configuration of the semiconductor device 1 of the embodiment will be described with reference to Figure 1 and Figure 2 Figure 1 is a perspective view showing the outline configuration of the semiconductor device 1 of the embodiment. In the following description, an XYZ orthogonal coordinate system is used. The X direction corresponds to the length direction of the outline of the semiconductor device 1 other than terminals. The Y direction corresponds to the width direction of the outline of the semiconductor device 1 other than terminals. The Z direction corresponds to the thickness direction of the outline of the semiconductor device 1 other than terminals, and is also referred to as the upward direction and the downward direction.

[0020] The semiconductor device 1 is provided with a main body portion 2, main terminals TP, TN, and TAC, and a plurality of lead terminals TG1, TG2, TD1, TD2, TS1, and TS2. The main body portion 2 includes a molding material 3, a lower insulating circuit substrate 10, an upper insulating circuit substrate 20, semiconductor chips (or semiconductor elements) 30 and 40, chip spacers (or pillars) 50 and 60, and substrate-to-substrate spacers (or pillars) 70 and 80.

[0021] Figure 2 is a perspective view showing the main terminals TP, TN, and TAC of the semiconductor device 1 of the embodiment. In the following description, the main terminals TP, TN, and TAC are collectively referred to as main terminals. Figure 2 ​In the middle, the main terminals TP, TN, and TAC as viewed through the molding material 3 are shown.

[0022] The main terminals TP and TN are provided at one end of the main body 2 in the Y direction. The main terminal TAC, the lead terminals TG1, TG2, TD1, TD2, TS1, and TS2 are provided at the other end of the main body 2 in the Y direction. The lead terminals TG1, TD1, TS1 and the lead terminals TG2, TD2, TS2 are arranged in a manner sandwiching the main terminal TAC. The main terminals TP, TN, and TAC have notches 90a and 90b, respectively.

[0023] 2. Circuit structure of semiconductor device

[0024] Next, the circuit structure of the semiconductor device 1 of the embodiment will be described with reference to Figure 3 to FIG. 1. Figure 3 is a circuit diagram showing the circuit structure of the semiconductor device of the embodiment.

[0025] The semiconductor device 1 includes, for example, a half-bridge circuit. The semiconductor device 1 is provided with transistors NM1 and NM2, the main terminals TP, TN, TAC, and the lead terminals TG1, TG2, TD1, TD2, TS1, and TS2 as described above.

[0026] The transistors NM1 and NM2 are, for example, n-type MOS field effect transistors, respectively.

[0027] The main terminals TP and TN are power supply terminals in the semiconductor device 1, respectively. The main terminal TP is supplied with a positive power supply voltage. The main terminal TP is also referred to as a P terminal. The main terminal TN is supplied with a negative power supply voltage. The main terminal TN is also referred to as an N terminal. The main terminal TAC is an output terminal in the semiconductor device 1. An alternating voltage is output from the main terminal TAC. The main terminal TAC is also referred to as an AC terminal.

[0028] The lead terminals TG1 and TG2 are control terminals in the semiconductor device 1, respectively. The lead terminals TD1, TD2, TS1, and TS2 are terminals for monitoring the operation of the semiconductor device 1, respectively. The lead terminal TD1 senses the voltage of the drain of the transistor NM1. The lead terminal TS1 senses the voltage of the source of the transistor NM1. The lead terminal TD2 senses the voltage of the drain of the transistor NM2. The lead terminal TS2 senses the voltage of the source of the transistor NM2.

[0029] The drain of the transistor NM1 is connected to the main terminal TP. The source of the transistor NM1 is connected to the main terminal TAC. The gate of the transistor NM1 is connected to the lead terminal TG1. The drain of the transistor NM2 is connected to the main terminal TAC. The source of the transistor NM2 is connected to the main terminal TN. The gate of the transistor NM2 is connected to the lead terminal TG2.

[0030] The drain of the transistor NM1 is connected to the lead terminal TD1. The source of the transistor NM1 is connected to the lead terminal TS1. The drain of the transistor NM2 is connected to the lead terminal TD2. The source of the transistor NM2 is connected to the lead terminal TS2.

[0031] 3. Internal configuration of semiconductor device

[0032] Next, the internal configuration of the semiconductor device 1 of the embodiment will be described with reference to Figure 4 , Figure 5 , and Figure 6 . Figure 4 is a plan view showing the internal configuration of the semiconductor device 1 of the embodiment.

[0033] Figure 5 is a sectional view along the V-V line in Figure 4 . Figure 6 is a sectional view along the VI-VI line in Figure 4 . Also, Figure 4 the plan view shown in indicates the configuration on the insulating circuit substrate 10 when viewed through the insulating circuit substrate 20 and the molding material 3. Also, in the following drawings, the arrow directions in the X direction, the Y direction, and the Z direction will be referred to as the +X direction, the +Y direction, and the +Z direction, respectively, and the directions opposite to the arrow directions will be referred to as the -X direction, the -Y direction, and the -Z direction, respectively.

[0034] As shown in Figure 4 , a semiconductor chip 30 is provided on one end side of the insulating circuit substrate 10 in the X direction, and a semiconductor chip 40 is provided on the other end side of the insulating circuit substrate 10. Between the semiconductor chip 30 and the semiconductor chip 40, inter-substrate spacers 70 and 80 are provided in the Y direction. As shown in Figure 5 and Figure 6 , the inter-substrate spacers 70 and 80 are provided between the insulating circuit substrate 10 and the insulating circuit substrate 20.

[0035] The insulating circuit substrate 10 includes a conductive plate (or conductive layer) 11, a conductive plate (or conductive layer) 12, and a ceramic substrate 13. The ceramic substrate 13 is provided between the conductive plate 11 and the conductive plate 12. That is, the conductive plate 11 is arranged on the upper surface of the ceramic substrate 13, and the conductive plate 12 is arranged on the lower surface of the ceramic substrate 13. The thickness of each of the conductive plates 11 and 12 is, for example, about 0.4 mm. The conductive plates 11 and 12 include, for example, copper. The ceramic substrate 13 is formed of an insulating material and has electrical insulation.

[0036] A slit 14 is provided in the conductive plate 11 by removing a portion of the conductive plate 11 in a certain pattern. That is, the slit 14 is a groove provided in the conductive plate 11 and in which a portion of the conductive plate 11 is removed.

[0037] The conductive plate 11 is separated into three conductive patterns (or circuit patterns, conductive layers) 11a, 11b, and 11c by the slits 14. The conductive patterns 11a, 11b, and 11c are electrically insulated from each other.

[0038] Likewise, the insulating circuit substrate 20 includes a conductive plate (or conductive layer) 21, a conductive plate (or conductive layer) 22, and a ceramic substrate 23. The ceramic substrate 23 is provided between the conductive plate 21 and the conductive plate 22. That is, the conductive plate 21 is arranged on the upper surface of the ceramic substrate 23, and the conductive plate 22 is arranged on the lower surface of the ceramic substrate 23. The thickness of each of the conductive plates 21 and 22 is, for example, about 0.4 mm. The conductive plates 21 and 22 include, for example, copper. The ceramic substrate 23 is formed of an insulating material and has electrical insulation.

[0039] Although not shown, the conductive plate 22 is separated into a plurality of conductive patterns (or circuit patterns, conductive layers) that are electrically insulated from each other by slits.

[0040] On the conductive pattern 11a, a semiconductor chip 30 is provided via a conductive member, such as a solder material 31. On the semiconductor chip 30, a chip spacer 50 is provided via a conductive member, such as a solder material 51. Further, on the chip spacer 50, a conductive pattern of the conductive plate 22 is provided via a conductive member, such as a solder material 52.

[0041] The semiconductor chip 30 includes a transistor NM1. The semiconductor chip 30 has a gate, a source, and a drain of the transistor NM1 as electrodes.

[0042] For example, the drain of the semiconductor chip 30 is electrically connected to the conductive pattern 11a via the solder material 31. The source of the semiconductor chip 30 is electrically connected to the chip spacer 50 via the solder material 51.

[0043] The semiconductor chip 30 and the chip spacer 50 are provided between the insulating circuit substrate 10 and the insulating circuit substrate 20. The chip spacer 50 is provided between the insulating circuit substrate 20 and the semiconductor chip 30. The chip spacer 50 has, for example, a shape of a column having a quadrangular shape when viewed in the Z direction and having a thickness in the Z direction. The chip spacer 50 includes a conductive material and has conductivity. Thus, the source of the semiconductor chip 30 is electrically connected to the conductive pattern of the conductive plate 22 via the solder material 51, the chip spacer 50, and the solder material 52. The chip spacer 50 also functions as a heat dissipation path that releases heat generated in the semiconductor chip 30 to the insulating circuit substrate 20.

[0044] On the conductive pattern 11b, an inter-substrate spacer 70 is provided via a conductive member such as a solder material 71. On the inter-substrate spacer 70, a conductive pattern of the conductive board 22 is provided via a conductive member such as a solder material 72.

[0045] The inter-substrate spacer 70 has, for example, a shape of a column having a circular shape in a Z direction and having a thickness in the Z direction. In one example, the inter-substrate spacer 70 has a shape of a circular column or a prismatic column. The inter-substrate spacer 70 contains a conductive material and has conductivity. Thus, the conductive pattern 11b is electrically connected with the conductive pattern of the conductive board 22 via the solder material 71, the inter-substrate spacer 70, and the solder material 72.

[0046] On the conductive pattern 11c, a semiconductor chip 40 is provided via a conductive member such as a solder material 41. On the semiconductor chip 40, a chip spacer 60 is provided via a conductive member such as a solder material 61. Further, on the chip spacer 60, a conductive pattern of the conductive board 22 is provided via a conductive member such as a solder material 62.

[0047] The semiconductor chip 40 contains a transistor NM2. The semiconductor chip 40 has, as electrodes, a gate, a source, and a drain of the transistor NM2.

[0048] For example, the drain of the semiconductor chip 40 is electrically connected with the conductive pattern 11c via the solder material 41. The source of the semiconductor chip 40 is electrically connected with the chip spacer 60 via the solder material 61.

[0049] The semiconductor chip 40 and the chip spacer 60 are provided between the insulating circuit substrate 10 and the insulating circuit substrate 20. The chip spacer 60 is provided between the insulating circuit substrate 20 and the semiconductor chip 40. The chip spacer 60 has, for example, a shape of a column having a quadrangular shape in a Z direction and having a thickness in the Z direction. The chip spacer 60 contains a conductive material and has conductivity. Thus, the source of the semiconductor chip 40 is electrically connected with the conductive pattern of the conductive board 22 via the solder material 61, the chip spacer 60, and the solder material 62. The chip spacer 60 also functions as a heat dissipation path that releases heat generated in the semiconductor chip 40 to the insulating circuit substrate 20.

[0050] On the conductive pattern 11c, an inter-substrate spacer 80 is provided via a conductive member such as a solder material 81. On the inter-substrate spacer 80, a conductive pattern of the conductive board 22 is provided via a conductive member such as a solder material 82.

[0051] The inter-substrate spacer 80 has, for example, the shape of a pillar that is circular when viewed from the Z direction and has a thickness in the Z direction. In one example, the inter-substrate spacer 80 has a cylindrical or prismatic shape. The inter-substrate spacer 80 contains a conductive material and is conductive. Therefore, the conductive pattern 11c is electrically connected to the conductive pattern of the conductive plate 22 via solder material 81, the inter-substrate spacer 80, and solder material 82.

[0052] In addition, such as Figure 4 As shown, main terminals TP and TN are provided at one end of the insulating circuit board 10 in the Y direction. A main terminal TAC is provided at the other end of the insulating circuit board 10 in the Y direction. The main terminals TP, TN, and TAC each have conductive components, such as metal components containing copper. The thickness of each of the main terminals TP, TN, and TAC is, for example, 0.8 mm.

[0053] A main terminal TP is disposed at one end of the conductive pattern 11a in the Y direction. The main terminal TP is bonded to the conductive pattern 11a via a conductive component, such as solder. That is, the main terminal TP is electrically connected to the conductive pattern 11a via solder. A main terminal TN is disposed at one end of the conductive pattern 11b in the Y direction. The main terminal TN is bonded to the conductive pattern 11b via a conductive component, such as solder. That is, the main terminal TN is electrically connected to the conductive pattern 11b via solder. Furthermore, a main terminal TAC is disposed at the other end of the conductive pattern 11c in the Y direction. The main terminal TAC is bonded to the conductive pattern 11c via a conductive component, such as solder. That is, the main terminal TAC is electrically connected to the conductive pattern 11c via solder.

[0054] In addition, a plurality of lead terminals TG1, TG2, TD1, TD2, TS1 and TS2 are provided at the other end of the insulating circuit board 10 in the Y direction.

[0055] Conductive patterns 11a, 11d, and 11e are disposed on the other end of the insulating circuit substrate 10 in the Y direction relative to the semiconductor chip 30. Conductive patterns 11d and 11e are island-shaped patterns.

[0056] The lead terminal TG1 is bonded to the conductive pattern 11d via a conductive component, such as solder. The conductive pattern 11d is connected to the pad 33g of the semiconductor chip 30 via a bonding wire 32g. The pad 33g is connected to the gate of the semiconductor chip 30. Thus, the lead terminal TG1 is electrically connected to the gate of the semiconductor chip 30 via the conductive pattern 11d, the bonding wire 32g, and the pad 33g.

[0057] The lead terminal TD1 is joined with the conductive pattern 11a via a conductive member such as a solder material. The conductive pattern 11a is connected with the drain of the semiconductor chip 30. Thus, the lead terminal TD1 is electrically connected with the drain of the semiconductor chip 30 via the conductive pattern 11a.

[0058] The lead terminal TS1 is joined with the conductive pattern 11e via a conductive member such as a solder material. The conductive pattern 11e is connected with the pad 33s of the semiconductor chip 30 through the bonding wire 32s. The pad 33s is connected with the source of the semiconductor chip 30. Thus, the lead terminal TS1 is electrically connected with the source of the semiconductor chip 30 via the conductive pattern 11e, the bonding wire 32s, and the pad 33s.

[0059] Further, on the other end side of the insulating circuit substrate 10 in the Y direction with respect to the semiconductor chip 40, the conductive pattern 11c, and the conductive patterns 11f and 11h are arranged. The conductive patterns 11f and 11h are island-shaped patterns, respectively.

[0060] The lead terminal TG2 is joined with the conductive pattern 11f via a conductive member such as a solder material. The conductive pattern 11f is connected with the pad 43g of the semiconductor chip 40 through the bonding wire 42g. The pad 43g is connected with the gate of the semiconductor chip 40. Thus, the lead terminal TG2 is electrically connected with the gate of the semiconductor chip 40 via the conductive pattern 11f, the bonding wire 42g, and the pad 43g.

[0061] The lead terminal TD2 is joined with the conductive pattern 11c via a conductive member such as a solder material. The conductive pattern 11c is connected with the drain of the semiconductor chip 40. Thus, the lead terminal TD2 is electrically connected with the drain of the semiconductor chip 40 via the conductive pattern 11c.

[0062] The lead terminal TS2 is joined with the conductive pattern 11h via a conductive member such as a solder material. The conductive pattern 11h is connected with the pad 43s of the semiconductor chip 40 through the bonding wire 42s. The pad 43s is connected with the source of the semiconductor chip 40. Thus, the lead terminal TS2 is electrically connected with the source of the semiconductor chip 40 via the conductive pattern 11h, the bonding wire 42s, and the pad 43s.

[0063] As shown in FIG. 9, the through holes 90a, 90b, and 90c are provided in the main terminals TP, TN, and TAC, respectively. Figure 4 Figure 4 ​In the embodiment, as viewed from the Z direction, that is, as viewed from above (or as viewed from an orthogonal direction) with respect to the face of the conductive plate 11 of the insulating circuit substrate 10, the cutout 90a of the main terminal TP extends from one end in the Y direction of the main terminal TP toward the -Y direction, then extends toward the +X direction, and further extends toward the -Y direction. The cutout 90b of the main terminal TP extends from one end in the Y direction of the main terminal TP toward the -Y direction, then extends toward the +X direction, and further extends toward the -Y direction. The cutouts 90a and 90b of the main terminal TN have substantially the same shapes as the cutouts 90a and 90b of the main terminal TP, respectively.

[0064] In the embodiment, as viewed from the Z direction, that is, as viewed from above (or as viewed from an orthogonal direction) with respect to the face of the conductive plate 11 of the insulating circuit substrate 10, the cutout 90a of the main terminal TP extends from one end in the Y direction of the main terminal TP toward the -Y direction, then extends toward the +X direction, and further extends toward the -Y direction. The cutout 90b of the main terminal TP extends from one end in the Y direction of the main terminal TP toward the -Y direction, then extends toward the +X direction, and further extends toward the -Y direction. The cutouts 90a and 90b of the main terminal TN have substantially the same shapes as the cutouts 90a and 90b of the main terminal TP, respectively. Figure 4

[0065] In the embodiment, as viewed from the Z direction, that is, as viewed from above (or as viewed from an orthogonal direction) with respect to the face of the conductive plate 11 of the insulating circuit substrate 10, the cutout 90a of the main terminal TP extends from one end in the Y direction of the main terminal TP toward the -Y direction, then extends toward the +X direction, and further extends toward the -Y direction. The cutout 90b of the main terminal TP extends from one end in the Y direction of the main terminal TP toward the -Y direction, then extends toward the +X direction, and further extends toward the -Y direction. The cutouts 90a and 90b of the main terminal TN have substantially the same shapes as the cutouts 90a and 90b of the main terminal TP, respectively. Figure 4 In the embodiment, as viewed from the Z direction, that is, as viewed from above (or as viewed from an orthogonal direction) with respect to the face of the conductive plate 11 of the insulating circuit substrate 10, the cutout 90a of the main terminal TP extends from one end in the Y direction of the main terminal TP toward the -Y direction, then extends toward the +X direction, and further extends toward the -Y direction. The cutout 90b of the main terminal TP extends from one end in the Y direction of the main terminal TP toward the -Y direction, then extends toward the +X direction, and further extends toward the -Y direction. The cutouts 90a and 90b of the main terminal TN have substantially the same shapes as the cutouts 90a and 90b of the main terminal TP, respectively.

[0066] The cutouts 90a and 90b of the main terminals TP, TN, and TAC will be described below.

[0067] 4. Configuration of main terminal

[0068] Figure 7 Next, the configuration of the main terminals TP, TN, and TAC in the semiconductor device 1 of the embodiment will be described with reference to Figure 8 Figure 9 Figure 7 is a plan view of the main terminal TP (or TN) in the semiconductor device 1 of the embodiment. Figure 8 is a sectional view along the line VIII-VIII in Figure 7 , showing the cross-sectional configuration of the insulating circuit substrate 10 including the main terminal TP and the conductive pattern 11a.

[0069] The main terminal TP has a shape in which a flat plate-like metal member extending in the -Y direction is slightly bent in the +Z direction, then extends in the -Y direction, and further bent in the +Z direction.

[0070] As viewed from the Z direction, the main terminal TP has a rectangular shape (or a polygonal shape). As described above, the main terminal TP has the cutouts 90a and 90b and the hole 90c.

[0071] As Figure 7 ​​​​As shown, the cutout 90a has a first portion 90aa extending from one end of the main terminal TP in the Y direction in the -Y direction, a second portion 90ab extending in the -X direction, and a third portion 90ac extending in the -Y direction. The second portion 90ab is continuously disposed at the end of the first portion 90aa. The third portion 90ac is continuously disposed at the end of the second portion 90ab.

[0072] The first part 90aa has a first width in the X direction and a first length in the Y direction. The second part 90ab has a second width in the Y direction and a second length in the X direction. The third part 90ac has a third width in the X direction and a third length in the Y direction. The first, second, and third widths can be the same or different. The first, second, and third lengths can be different or the same. For example, the first length is longer than both the second and third lengths, and the third length is longer than the second length.

[0073] Cut 90b is positioned close to cut 90a in the X direction. Cut 90b has a structure that is symmetrical about a line along the Y direction with respect to the line of cut 90a.

[0074] The cutout 90b has a first portion 90ba extending from one end of the main terminal TP in the Y direction in the -Y direction, a second portion 90bb extending in the +X direction, and a third portion 90bc extending in the -Y direction. The second portion 90bb is continuously disposed at the end of the first portion 90ba. The third portion 90bc is continuously disposed at the end of the second portion 90bb.

[0075] Similar to cut 90a, the first portion 90ba has a first width in the X direction and a first length in the Y direction. The second portion 90bb has a second width in the Y direction and a second length in the X direction. The third portion 90bc has a third width in the X direction and a third length in the Y direction. The first width, second width, and third width can each be the same or different. The first length, second length, and third length can each be different or the same. For example, the first length is longer than both the second and third lengths, and the third length is longer than the second length.

[0076] In addition, such as Figure 7 and Figure 8 As shown, a conductive component, such as solder material 91, is disposed between the main terminal TP and the conductive pattern 11a. Figure 7 In region A shown, the main terminal TP is connected to the conductive pattern 11a via solder material 91. Solder feet 91a of solder material 91 are formed on the side of the main terminal TP.

[0077] The first portions 90aa and 90ba of the notches 90a and 90b of the main terminal TP are provided in a region A where the main terminal TP is connected to the conductive pattern 11a by the solder material 91. Therefore, the solder fillets 91a are formed not only on the side surface of the outer periphery of the main terminal TP, but also on the side surface of the first portion 90aa of the notch 90a and on the side surface of the first portion 90ba of the notch 90b.

[0078] The first length of the first portion 90aa in the Y direction is equal to or greater than the length of the region A in the Y direction. In other words, the first length of the first portion 90aa in the Y direction is equal to or greater than the length of the solder material 91 in the Y direction between the conductive pattern 11a and the main terminal TP. Similarly, the first length of the first portion 90ba in the Y direction is equal to or greater than the length of the region A in the Y direction. In other words, the first length of the first portion 90ba in the Y direction is equal to or greater than the length of the solder material 91 in the Y direction between the conductive pattern 11a and the main terminal TP.

[0079] The main terminal TN has substantially the same configuration as the main terminal TP. The main terminal TN has a rectangular shape (or a polygonal shape) when viewed in the Z direction. The notches 90a, 90b, and the hole 90c are provided in the main terminal TN. The configuration of the notches 90a, 90b, and the hole 90c of the main terminal TN is substantially the same as the configuration of the notches 90a, 90b, and the hole 90c of the main terminal TP.

[0080] Figure 9 is a plan view of the main terminal TAC in the semiconductor device 1 according to the embodiment. The main terminal TAC also has substantially the same configuration as the main terminal TP. The main terminal TAC has a configuration that is linearly symmetrical with respect to the main terminal TP with a line along the X direction as an axis of symmetry, and is further disposed near the center of the insulating circuit board 10 in the X direction.

[0081] The main terminal TAC has a shape in which a flat metal member along the XY plane extends in the +Y direction, slightly bends in the +Z direction, then extends in the +Y direction, and further bends in the +Z direction.

[0082] The main terminal TAC has a rectangular shape (or a polygonal shape) when viewed in the Z direction. The notches 90a, 90b, and the hole 90c are provided in the main terminal TAC. The configuration of the notches 90a, 90b, and the hole 90c of the main terminal TAC is substantially the same as the configuration of the notches 90a, 90b, and the hole 90c of the main terminal TP.

[0083] According to the above-described embodiment, it is possible to provide a semiconductor device having a terminal configuration with high reliability.

[0084] In the configuration of the embodiment, the first portions 90aa and 90ba of the cutouts 90a and 90b that the main terminal TP has are provided in the region A where the main terminal TP (or TN, TAC) is connected to the conductive pattern 11a (or 11b, 11c). Thus, the fillets 91a of the solder material 91 are formed on the side surface of the outer periphery of the main terminal TP and the side surface of the main terminal TP where the first portions 90aa and 90ba are provided. Thereby, the area where the fillets 91a of the solder material 91 are formed on the side surface of the main terminal TP can be increased, and the main terminal TP can be firmly connected to the conductive pattern 11a of the insulating circuit board 10.

[0085] In addition, in the configuration of the embodiment, the cutouts 90a and 90b are provided in the main terminal TP (or TN, TAC). When a current flows through the semiconductor device 1, there is a case where the semiconductor device 1 becomes high temperature due to heat generation. Thus, there are cases where deformation due to stress occurs in the insulating circuit boards 10 and 20 and the main terminal TP, and the solder material that joins the main terminal TP to the conductive pattern 11a is peeled off. As described above, the main terminal TP has the cutouts 90a and 90b, and thus stress that occurs in the main terminal TP can be mitigated. Thereby, peeling of the solder material that joins the main terminal TP to the conductive pattern 11a can be prevented.

[0086] In addition, in the configuration of the embodiment, the cutouts 90a and 90b provided in the main terminal TP (or TN, TAC) are covered with the molding material 3. Thus, the molding material 3 enters the cutouts 90a and 90b, and the adhesion or joining of the molding material 3 to the main terminal TP is strengthened. Thereby, a strong configuration can be formed in which damage and the like of the main terminal TP and the molding material 3 can be reduced even when a force is applied to the main terminal TP due to external or internal stress. For example, even when a force such as a stretching force to the outside is applied to the main terminal TP from the outside, or a force such as a stretching force is applied to the main terminal TP due to internal stress, a strong configuration in which deformation of the main terminal TP and the molding material 3 can be reduced, that is, durability against the stretching force can be improved.

[0087] As described above, according to the semiconductor device 1 of the embodiment, a terminal configuration with high reliability can be formed.

[0088] In addition, in the foregoing embodiment, an example in which the semiconductor device configures a MOS type field effect transistor (that is, a MOSFET) is described, but the semiconductor device can configure other switching elements, for example, an IGBT (insulated gate bipolar transistor). In a case where the semiconductor device configures an IGBT, the source corresponds to the emitter, and the drain corresponds to the collector.

[0089] Several embodiments of the present application are described, but these embodiments are presented by way of example only, and are not intended to limit the scope of the application. These embodiments can be implemented in other various ways, and various omissions, substitutions, and changes can be made without departing from the spirit of the application. These embodiments and their modifications are included within the scope and spirit of the application, and are also included within the scope of the application and its equivalents as set forth in the claims.

[0090] Explanation of Reference Signs

[0091] 1…semiconductor device, 2…main body, 3…molding material, 10…insulating circuit substrate, 11…conductive plate (conductive layer), 11a…conductive pattern, 11b…conductive pattern, 11c…conductive pattern, 11d…conductive pattern, 11e…conductive pattern, 11f…conductive pattern, 11h…conductive pattern, 12…conductive plate (conductive layer), 13…ceramic substrate, 14…slit, 20…insulating circuit substrate, 21…conductive plate (conductive layer), 22…conductive plate (conductive layer), 23…ceramic substrate, 30…semiconductor chip, 31…solder material, 32g…bonding wire, 32s…bonding wire, 33g…pad, 33s…pad, 40…semiconductor chip, 41…solder material, 42g…bonding wire, 42s…bonding wire, 43g…pad, 43s…pad, 50…chip spacer, 51…solder material, 52…solder material, 60…chip spacer, 61…solder material, 62…solder material, 70…substrate-to-substrate spacer, 71…solder material, 72…solder material, 80…substrate-to-substrate spacer, 90a…cutout, 90b…cutout, 90c…hole, 91…solder material, 91a…solder leg, NM1…transistor, NM2…transistor, TP…main terminal, TN…main terminal, TAC…main terminal.

Claims

1. A semiconductor device, characterized in that, have: First circuit board; The second circuit board is disposed above the first circuit board; A first semiconductor chip is disposed between the first circuit substrate and the second circuit substrate; The first pillar is disposed between the first circuit board and the second circuit board; as well as A first terminal is disposed at one end of the first circuit board in a first direction and has a first notch. The first cut in the first terminal has a first portion, a second portion, and a third portion. The first portion extends from one end of the first terminal along the first direction. The second portion is continuous with the first portion and extends along a second direction that intersects the first direction. The third part is continuous with the second part and extends along the first direction.

2. The semiconductor device according to claim 1, characterized in that, It also includes a conductive component disposed between the first circuit board and the first terminal, connecting the first circuit board and the first terminal. The first portion of the first cut of the first terminal is disposed in the area where the conductive component is provided.

3. The semiconductor device according to claim 2, characterized in that, In the first direction, the length of the first portion of the first cut is greater than or equal to the length of the conductive component.

4. The semiconductor device according to claim 2, characterized in that, The conductive component has a solder foot on the side of the first terminal in the first portion having the first cut.

5. The semiconductor device according to claim 1, characterized in that, It also includes a molding material covering the first circuit board and the second circuit board. The first cut in the first terminal is covered by the molding material.

6. The semiconductor device according to claim 1, characterized in that, The first circuit board has a first conductive layer, a second conductive layer, and a first insulating substrate disposed between the first conductive layer and the second conductive layer. The second circuit board has a third conductive layer, a fourth conductive layer, and a second insulating substrate disposed between the third conductive layer and the fourth conductive layer.

7. The semiconductor device according to claim 1, characterized in that, The first terminal has a second cut that is disposed in the second direction relative to the first cut. The second incision has a fourth part, a fifth part, and a sixth part. The fourth portion extends from one end of the first terminal along the first direction. The fifth part is continuous with the fourth part and extends along the second direction. The sixth part is continuous with the fifth part and extends along the first direction.

8. The semiconductor device according to claim 1, characterized in that, It also has: The second semiconductor chip is disposed between the first circuit substrate and the second circuit substrate; The second pillar is disposed between the first circuit board and the second circuit board; The third pillar is disposed between the first semiconductor chip and the second circuit substrate; as well as The fourth pillar is disposed between the second semiconductor chip and the second circuit board.

9. The semiconductor device according to claim 1, characterized in that, The first column has a circular shape when viewed from a third direction orthogonal to the first and second directions, and has a thickness in the third direction.

10. The semiconductor device according to claim 1, characterized in that, The first post electrically connects the first circuit board to the second circuit board.

11. The semiconductor device according to claim 8, characterized in that, The first column and the second column have a circular shape when viewed from a third direction orthogonal to the first direction and the second direction, respectively, and have a thickness in the third direction. The third column and the fourth column each have a quadrilateral shape when viewed from the third direction, and have a thickness in the third direction.

12. The semiconductor device according to claim 8, characterized in that, The first post and the second post electrically connect the first circuit board and the second circuit board, respectively. The third pillar electrically connects the first semiconductor chip to the second circuit board. The fourth pillar electrically connects the second semiconductor chip to the second circuit board.

13. The semiconductor device according to claim 1, characterized in that, One end of the first circuit board in the first direction also has a second terminal, which is disposed in the second direction relative to the first terminal and has a cutout. The cutout of the second terminal has a seventh portion, an eighth portion, and a ninth portion. The seventh portion extends from one end of the second terminal along the first direction. The eighth part is continuous with the seventh part and extends along the second direction. The ninth part is continuous with the eighth part and extends along the first direction.

14. The semiconductor device according to claim 13, characterized in that, It also includes a third terminal, which is disposed at the other end of the first circuit board in the first direction and has a cutout. The cut in the third terminal has a tenth portion, an eleventh portion, and a twelfth portion. The tenth portion extends from one end of the third terminal along the first direction. The eleventh part is continuous with the tenth part and extends along the second direction. The twelfth part is continuous with the eleventh part and extends along the first direction.

15. The semiconductor device according to claim 14, characterized in that, It also includes a second semiconductor chip disposed between the first circuit board and the second circuit board. The first semiconductor chip includes a first MOS-type field-effect transistor. The second semiconductor chip includes a second MOS-type field-effect transistor. The first terminal is electrically connected to the drain of the first MOS field-effect transistor. The second terminal is electrically connected to the source of the second MOS field-effect transistor. The third terminal is electrically connected to the source of the first MOS field-effect transistor and the drain of the second MOS field-effect transistor.

16. The semiconductor device according to claim 1, characterized in that, The first semiconductor chip includes a MOS field-effect transistor.

17. The semiconductor device according to claim 1, characterized in that, The first semiconductor chip includes an insulated gate bipolar transistor, i.e., an IGBT.

18. The semiconductor device according to claim 6, characterized in that, The first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer contain copper.

19. The semiconductor device according to claim 6, characterized in that, The first insulating substrate and the second insulating substrate comprise a ceramic substrate.

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