Ground screen and backflow state monitoring device

Abstract

The invention discloses an earth screen and backflow state monitoring device, and the device comprises a current conversion module which is used for converting an induction current into a low-voltage differential voltage signal; the voltage conversion module is used for processing the multiple paths of voltage signals and outputting stable analog voltage signals; the AD conversion module is used for respectively converting the low-voltage differential voltage signal output by the current conversion module and the analog voltage signal output by the voltage conversion module into a first digital signal and a second digital signal; and the main control module is used for analyzing and processing the first digital signal and the second digital signal output by the AD conversion module so as to judge the grounding state of the grounding grid.

Description

Technical Field

[0001] This application belongs to the field of power system monitoring technology, and specifically relates to a grounding grid and return current status monitoring device. Background Technology

[0002] With the rapid development of electrified railways in my country, traction loads are continuously increasing, and the power supply system is frequently subjected to impacts, resulting in high levels of high-order harmonics and large return currents in the grounding grid. This places more stringent demands on the performance of the grounding system. As a key component of the traction power supply system, the performance of the grounding system directly affects the safety of personnel and equipment, as well as the reliable operation of the railway network. In particular, the widespread application of microelectronics and digital devices in the system, which use low-operating-voltage integrated circuits, places extremely stringent requirements on the grounding system, which serves as the potential reference point. Once the performance of the grounding grid deteriorates, the connection is unreliable, or the return current ratio of the return line is insufficient, electromagnetic interference and overvoltage backflash can easily occur, seriously threatening safety.

[0003] Currently, grounding system testing mainly relies on periodically dispatching personnel for on-site testing. This method is inefficient, lacks real-time performance, is particularly difficult in remote substation locations, and consumes significant manpower and resources. Even with some online testing equipment, their functional modules mostly operate independently, making synchronous sampling and comprehensive analysis impossible, and failing to reveal the intrinsic correlations between different measurement parameters. Therefore, there is an urgent need for an intelligent device capable of comprehensive, online, and synchronous monitoring of the grounding and return current status of railway power supply systems. This would help operating units promptly identify and eliminate potential faults and hazards, ensuring the long-term stable and safe operation of the system. Summary of the Invention

[0004] In order to overcome the shortcomings of the prior art, the purpose of this application is to provide a grounding grid and return current status monitoring device. This application can effectively overcome the limitations of traditional grounding grid detection methods and realize real-time, reliable, and comprehensive safety monitoring and intelligent diagnosis of the railway grounding system status.

[0005] To achieve the above objectives, this application provides the following technical solution: A grounding grid and return current status monitoring device, the device comprising: a current conversion module for converting induced current into a low-voltage differential voltage signal; a voltage conversion module for processing multiple voltage signals and outputting a stable analog voltage signal; an AD conversion module for converting the low-voltage differential voltage signal output by the current conversion module and the analog voltage signal output by the voltage conversion module into a first digital signal and a second digital signal, respectively; and a main control module for analyzing and processing the first digital signal and the second digital signal output by the AD conversion module to determine the grounding status of the grounding grid.

[0006] Optionally, the current conversion module includes: a current transformer, a first bidirectional TVS diode, a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, and a second capacitor. The current transformer and the first bidirectional TVS diode are connected in parallel. The first end of the first resistor is connected to the first end of the first bidirectional TVS diode to form a first node. The second end of the first resistor is connected to the second end of the first bidirectional TVS diode via the second resistor to form a second node. The connection point between the first resistor and the second resistor is connected to a first ground terminal. The first end of the fourth resistor is connected to the first node. The first end of the third resistor is connected to the second node. The first end of the first capacitor and the second end of the fourth resistor are simultaneously connected to the positive terminal of the differential analog voltage signal of the AD conversion module. The second end of the first capacitor is connected to the negative terminal of the differential analog voltage signal of the AD conversion module via the second capacitor and the second end of the third resistor.

[0007] Optionally, the voltage conversion module includes: an input signal conditioning unit for conditioning multiple voltage signals; a channel switching network for selecting the conditioned multiple voltage signals as needed; and an output signal conditioning and ADC driving unit for conditioning any voltage signal selected by the channel switching network and sending it to the AD conversion module.

[0008] Optionally, the input signal conditioning unit includes: a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, and a second bidirectional TVS diode. The first terminal of the fifth resistor is connected to a positive differential voltage signal, and its second terminal is connected in series with the ninth and twelfth resistors and then to the first terminal of the thirteenth resistor. The first terminal of the sixth resistor is connected in series with the tenth resistor and then to the second terminal of the thirteenth resistor. The first terminal of the seventh resistor is connected to the second terminal of the sixth resistor, and its second terminal is connected in series with the eleventh resistor and then to the first terminal of the fourteenth resistor. The first terminal of the eighth resistor is connected to the second terminal of the fourteenth resistor, and its second terminal is connected to the first terminal of the second bidirectional TVS diode to form a third node. This third node serves as the output terminal of the input signal conditioning unit and is connected to the input terminal of the output signal conditioning and ADC driving unit via a channel switching network. The second terminal of the second bidirectional TVS diode is connected to a second ground terminal. The first terminal of the fifteenth resistor is connected to a negative differential voltage signal, and its second terminal is connected to a second ground terminal.

[0009] Optionally, the channel switching network includes: a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, a twentieth resistor, a twenty-first resistor, a twenty-second resistor, a twenty-third resistor, a first solid-state relay, a second solid-state relay, a third solid-state relay, and a fourth solid-state relay. The anodes of the first, second, third, and fourth solid-state relays are simultaneously connected to a third node. The cathode of the first solid-state relay is connected to a third ground terminal via the sixteenth resistor, the collector is connected to a 3.3V power supply via the twentieth resistor, and the emitter is connected to a seventh ground terminal. The cathode of the second solid-state relay is connected to a fourth ground terminal via the seventeenth resistor, the collector is connected to a 3.3V power supply via the twenty-first resistor, and the emitter is connected to an eighth ground terminal. The cathode of the third solid-state relay is connected to a fifth ground terminal via the eighteenth resistor, the collector is connected to a 3.3V power supply via the twenty-second resistor, and the emitter is connected to a ninth ground terminal. The cathode of the fourth solid-state relay is connected to a sixth ground terminal via the nineteenth resistor, the collector is connected to a 3.3V power supply via the twenty-third resistor, and the emitter is connected to a tenth ground terminal.

[0010] Optionally, the output signal conditioning and ADC driving unit includes: a 24th resistor, a 25th resistor, a third bidirectional TVS diode, a third capacitor, a fourth capacitor, and an operational amplifier. The first end of the 24th resistor serves as the input terminal of the output signal conditioning and ADC driving unit, and the second end is connected to the non-inverting input terminal of the operational amplifier to form a fourth node. The first end of the third capacitor C3 is connected to the fourth node, and the second end is connected to the eleventh ground terminal. The inverting input terminal of the operational amplifier is shorted to its output terminal. The first end of the 25th resistor is connected to the output terminal of the operational amplifier, and the second end, after being connected to the third bidirectional TVS diode and the fourth capacitor in parallel, is connected to the twelfth ground terminal.

[0011] Optionally, the AD conversion module includes: an AD conversion chip, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, an eleventh capacitor, a twelfth capacitor, a first crystal oscillator, a twenty-sixth resistor, a twenty-seventh resistor, and a second inductor. The first terminal of the fifth capacitor is connected to the digital power supply pin of the AD conversion chip, and the second terminal is connected to the fourteenth ground terminal. The sixth and seventh capacitors are connected in parallel between the core power supply pin of the AD conversion chip and the fourteenth ground terminal. The first terminal of the twenty-sixth resistor is connected to the test pin of the AD conversion chip, and the second terminal is connected to a +5V power supply. The first terminal of the eighth capacitor is connected to the analog power supply pin of the AD conversion chip to form a fifth node, and the second terminal is connected to the signal input pin of the AD conversion chip. A sixth node is formed and connected to the thirteenth ground terminal; the first end of the second inductor is connected to the fifth node, and the second end is connected to the +5V power supply; the ninth and tenth capacitors are connected in parallel between the reference pin of the AD conversion chip and the thirteenth ground terminal; the first end of the twenty-seventh resistor is connected to the first communication pin of the AD conversion chip, and the second end is connected to the +5V power supply; the first crystal oscillator is connected in parallel between the output pin and the input pin of the AD conversion chip, forming the seventh and eighth nodes; the first ends of the eleventh and twelfth capacitors are connected to the seventh and eighth nodes respectively, and the second ends of the eleventh and twelfth capacitors are simultaneously connected to the sixteenth ground terminal; the ground pin of the AD conversion chip is connected to the fifteenth ground terminal, and the second communication pin is connected to the input terminal of the main control module.

[0012] Optionally, the main control module includes: a main control chip, the communication pins of which serve as the input terminals of the main control module, and the main control chip is electrically connected to a core power supply and clock generation unit, a reference voltage decoupling unit, and a filtering and multi-power domain decoupling unit. The core power supply and clock generation unit is used to provide a stable power supply and timing reference for the main control chip; the reference voltage decoupling unit is used to provide a clean analog power supply and voltage reference for the main control chip; and the filtering and multi-power domain decoupling unit is used to achieve noise isolation and fine decoupling between different power domains within the main control chip.

[0013] Optionally, the core power supply and clock generation unit includes: a thirteenth capacitor, a fourteenth capacitor, a fifteenth capacitor, and an active crystal oscillator. The thirteenth and fourteenth capacitors are connected in parallel to the power ground pin and the first power input pin of the main control chip, and the connection point of the thirteenth and fourteenth capacitors is connected to the seventeenth ground terminal. The first end of the fifteenth capacitor is connected to the power supply pin of the active crystal oscillator and is also connected to a 3.3V voltage, and the second end is connected to the eighteenth ground terminal. The ground terminal of the active crystal oscillator is connected to the nineteenth ground terminal.

[0014] Optionally, the reference voltage decoupling unit includes: a sixteenth capacitor, a seventeenth capacitor, an eighteenth capacitor, a nineteenth capacitor, and a twentieth capacitor, wherein the first end of the sixteenth capacitor is connected to the second power input pin of the main control chip, and the second end is connected to the twentieth ground terminal; the seventeenth and eighteenth capacitors are connected in parallel between the twentieth ground terminal and the third power input pin of the main control chip; and the nineteenth and twentieth capacitors are connected in parallel between the twentieth ground terminal and the reference voltage input pin of the main control chip.

[0015] The beneficial effects of this application are as follows: This application constructs a centralized, online synchronous monitoring system by integrating current conversion, voltage conversion, AD conversion and main control analysis modules, realizing high-precision, real-time acquisition and comprehensive analysis of ground grid return current and multiple voltage signals; this application improves the anti-interference capability and measurement accuracy in complex electromagnetic environments by adopting differential signal processing, channel isolation switching and multi-level decoupling design. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the overall circuit structure of a grounding grid and return current status monitoring device according to an embodiment of this application; Figure 2 This is a schematic diagram of the circuit structure of a current conversion module provided in another embodiment of this application; Figure 3 This is a schematic diagram of the circuit structure of a voltage conversion module provided in another embodiment of this application; Figure 4 This is a schematic diagram of the circuit structure of an AD conversion module provided in another embodiment of this application; Figure 5 This is a schematic diagram of the circuit structure of the main control module provided in another embodiment of this application. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0018] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indication will also change accordingly.

[0019] In this invention, unless otherwise explicitly specified and limited, the terms "connection," "fixed," etc., should be interpreted broadly. For example, "fixed" can mean a fixed connection, a detachable connection, or an integral part; it can mean a mechanical connection or an electrical connection; it can mean a direct connection or an indirect connection through an intermediate medium; it can mean the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0020] Furthermore, if the embodiments of this invention involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the meaning of "and / or" throughout the text includes three parallel solutions; for example, "A and / or B" includes solution A, solution B, or a solution where both A and B are satisfied simultaneously. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0021] Figure 1 This is a schematic diagram of the overall structure of a grounding grid and return current status monitoring device provided in an embodiment of this application, as shown below. Figure 1 As shown, the device includes: a current conversion module, a voltage conversion module, an AD conversion module, and a main control module. The current conversion module converts the induced current into a low-voltage differential voltage signal; the voltage conversion module processes multiple voltage signals and outputs a stable analog voltage signal; the AD conversion module converts the low-voltage differential voltage signal output by the current conversion module and the analog voltage signal output by the voltage conversion module into a first digital signal and a second digital signal, respectively; the main control module analyzes and processes the first and second digital signals output by the AD conversion module to determine the grounding status of the grounding grid.

[0022] In another exemplary embodiment, such as Figure 2As shown, the current conversion module includes a current transformer (e.g., HCT226A-3) L1, a first bidirectional TVS diode D1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first capacitor C1, and a second capacitor C2. The current transformer L1 is connected in parallel with the first bidirectional TVS diode D1. The first terminal of the first resistor R1 is connected to the first terminal of the first bidirectional TVS diode D1 to form a first node N1. The second terminal of the first resistor R1 is connected to the second terminal of the first bidirectional TVS diode D1 via the second resistor R2. The connection forms the second node N2, and the connection point of the first resistor R1 and the second resistor R2 is connected to the first ground terminal GND1; the first end of the fourth resistor R4 is connected to the first node N1, the first end of the third resistor R3 is connected to the second node N2, the first end of the first capacitor C1 and the second end of the fourth resistor R4 are simultaneously connected to the positive terminal (UA-V3P) of the differential analog voltage signal of the AD conversion module, and the second end of the first capacitor C1 is simultaneously connected to the negative terminal (UA-V3N) of the differential analog voltage signal of the AD conversion module through the second capacitor C2 and the second end of the third resistor R3.

[0023] In this embodiment, the current conversion module accurately and safely converts the large primary current induced by the current transformer L1 into a low-voltage differential voltage signal suitable for direct sampling by the AD conversion module. Its workflow is as follows: When the AC current monitored in the local grid passes through the primary side of the current transformer L1, it induces a proportional but significantly reduced current on its secondary side. This induced current first flows through a parallel-series combination network composed of a first resistor R1 and a second resistor R2. The core function of this network is to convert the induced current into a preliminary voltage signal and provide a stable reference ground (GND1) at the connection point of the first resistor R1 and the second resistor R2, thereby forming a voltage difference between the first node N1 and the second node N2 with reference ground GND1. Simultaneously, the first bidirectional TVS diode D1, connected in parallel with the current transformer L1, acts as a transient overvoltage protection device, quickly clamping any abnormally high voltage that may be generated across the current transformer L1 due to unexpected situations such as lightning strikes or operational overvoltages, thus protecting subsequent circuits from damage. Subsequently, the voltage signals from the first node N1 and the second node N2 are transmitted to the RC filter network composed of the first capacitor C1 and the second capacitor C2 through the fourth resistor R4 and the third resistor R3, respectively. This network can act as a differential low-pass filter, effectively suppressing high-frequency noise and spurious interference in the initial voltage signal. Finally, the filtered and conditioned pure differential voltage signals—namely UA-V3P (positive terminal) and UA-V3N (negative terminal)—are output to the AD conversion module, thus completing the conversion process from current to voltage.

[0024] This current conversion module first safely isolates the primary circuit, which is at a high potential or high current, from the subsequent low-voltage measurement circuit through a current transformer L1, while simultaneously completing the signal scale conversion from high current to low voltage. Secondly, a filter network consisting of a third resistor R3, a fourth resistor R4, a first capacitor C1, and a second capacitor C2 improves the signal-to-noise ratio of the initial voltage signal, filtering out high-frequency harmonics and noise that may interfere with the measurement, thus ensuring the accuracy of the measurement results. Finally, the module employs a differential signal output method, which can greatly suppress common-mode noise superimposed on the two signal lines during transmission and is independent of absolute ground potential, making it suitable for accurate measurements in grounding grid environments with ground potential fluctuations and complex electromagnetic interference.

[0025] In another exemplary embodiment, such as Figure 3 As shown, the voltage conversion module includes an input signal conditioning unit, a channel switching network, and an output signal conditioning and ADC driving unit. The input signal conditioning unit is used to condition multiple voltage signals; the channel switching network is used to select the conditioned multiple voltage signals as needed; and the output signal conditioning and ADC driving unit is used to condition any selected voltage signal and send it to the AD conversion module.

[0026] In another exemplary embodiment, the input signal conditioning unit includes a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, and a second bidirectional TVS diode D2. The first terminal of the fifth resistor R5 is connected to the positive differential voltage signal MEASURE-U+, and its second terminal is connected in series with the ninth resistor R9 and the twelfth resistor R12 before being connected to the first terminal of the thirteenth resistor R13. The first terminal of the sixth resistor R6 is connected in series with the tenth resistor R10 before being connected to the second terminal of the thirteenth resistor R13. The first terminal of the seventh resistor R7... The first terminal of the 14th resistor R14 is connected to the second terminal of the sixth resistor R6. The second terminal of the seventh resistor R7 is connected in series with the eleventh resistor R11 and then connected to the first terminal of the fourteenth resistor R14. The first terminal of the eighth resistor R8 is connected to the second terminal of the fourteenth resistor R14. The second terminal of the eighth resistor R8 is connected to the first terminal of the second bidirectional TVS diode D2 to form the third node N3. The third node N3 serves as the output terminal of the input signal conditioning unit and is connected to the input terminal of the output signal conditioning and ADC driving unit via the channel switching network. The second terminal of the second bidirectional TVS diode D2 is connected to the second ground terminal GND2. The first terminal of the fifteenth resistor R15 is connected to the negative differential voltage signal MEASURE-U-, and the second terminal is connected to the second ground terminal GND2.

[0027] In this embodiment, the input signal conditioning unit receives differential voltage signals MEASURE-U+ and MEASURE-U-, and then conditions and converts them through a precision resistor network. Specifically, the MEASURE-U+ signal first flows through the fifth resistor R5, then sequentially through the ninth resistor R9 and the twelfth resistor R12, and enters the first terminal of the thirteenth resistor R13; simultaneously, the MEASURE-U- signal is connected to the second ground terminal GND2 through the fifteenth resistor R15 to provide a stable common-mode reference point for this unit. The sixth resistor R6 and the tenth resistor R10 are connected in series to the second terminal of the thirteenth resistor R13, while the seventh resistor R7 and the eleventh resistor R11 are connected in series to the first terminal of the fourteenth resistor R14. The eighth resistor R8 is connected between the second terminal of the fourteenth resistor R14 and the third node N3. The entire resistor network constitutes a differential attenuation and filtering circuit, which converts the input differential voltage into a ground-referenced single-ended voltage signal through voltage division and impedance matching, and outputs it at the third node N3. In addition, the second bidirectional TVS diode D2 is connected between the third node N3 and the second ground terminal GND2 as a key overvoltage protection component. When the unit generates an abnormally high voltage transient at the third node N3 due to external interference (such as lightning strikes or operational overvoltages), the second bidirectional TVS diode D2 will quickly conduct and clamp the voltage to a safe level to prevent damage to subsequent precision circuits.

[0028] This input signal conditioning unit, through an optimized resistor network, achieves high-precision attenuation, impedance matching, and common-mode noise suppression of the input differential voltage signal pair. This ensures the output signal remains stable within the voltage range of the third node N3 and meets the input requirements of the subsequent ADC driver unit, preventing signal saturation or distortion. The introduction of the second bidirectional TVS diode D2 provides reliable transient overvoltage protection, significantly improving the unit's anti-interference capability and robustness in complex electromagnetic environments. Overall, this unit not only enhances the accuracy and reliability of signal measurements but also reduces the risk of system failure and extends the device's lifespan through effective isolation and protection mechanisms.

[0029] In another exemplary embodiment, the channel switching network includes a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, a nineteenth resistor R19, a twentieth resistor R20, a twenty-first resistor R21, a twenty-second resistor R22, a twenty-third resistor R23, a first solid-state relay G1, a second solid-state relay G2, a third solid-state relay G3, and a fourth solid-state relay G4. The anodes of the first solid-state relay G1, the second solid-state relay G2, the third solid-state relay G3, and the fourth solid-state relay G4 are simultaneously connected to a third node N3. The cathode of the first solid-state relay G1 is connected to the third ground terminal GND3 through the sixteenth resistor R16, and its collector is connected to the third ground terminal GND3 through the twentieth resistor R20. The first solid-state relay G2 has a 3.3V power supply, with its emitter connected to the seventh ground terminal GND7. The cathode of the second solid-state relay G2 is connected to the fourth ground terminal GND4 through the seventeenth resistor R17, and its collector is connected to the 3.3V power supply through the twenty-first resistor R21. Its emitter is connected to the eighth ground terminal GND8. The cathode of the third solid-state relay G3 is connected to the fifth ground terminal GND5 through the eighteenth resistor R18, and its collector is connected to the 3.3V power supply through the twenty-second resistor R22. Its emitter is connected to the ninth ground terminal GND9. The cathode of the fourth solid-state relay G4 is connected to the sixth ground terminal GND6 through the nineteenth resistor R19, and its collector is connected to the 3.3V power supply through the twenty-third resistor R23. Its emitter is connected to the tenth ground terminal GND10.

[0030] In this embodiment, the channel switching network achieves high-reliability switching and electrical isolation of multiple ground network monitoring signals through the gating control of the first to fourth solid-state relays (G1-G4) by the main controller. Its working principle includes: the anodes of all solid-state relays are connected to the output terminal (third node N3) of the front-end input signal conditioning unit. When the main controller drives the control electrode (collector) of the corresponding solid-state relay, the relay conducts, thereby routing the input signal to a specific measurement circuit composed of its cathode resistor (one of R16-R19) and an independent grounding terminal (one of GND3-GND6). The cathode resistor is used to limit current and match impedance, while the independent grounding path of each relay achieves electrical isolation between different ground network measurement points. Simultaneously, the twentieth to twenty-third resistors (R20-R23) act as pull-up resistors for the control signal, ensuring the stability of the switching logic.

[0031] This network enables intelligent selection and high-isolation switching of four ground grid monitoring signals. It not only completely blocks potential difference interference and ground loop current that may exist between different ground grid measurement loops through the optocoupler isolation characteristics of solid-state relays, ensuring the safety of the weak current measurement system, but also enables the back-end ADC to sequentially acquire multiple signals through the time-division multiplexing mechanism, which significantly improves the system integration and measurement efficiency, and provides key hardware support for comprehensive and synchronous analysis of the ground grid status.

[0032] In another exemplary embodiment, the output signal conditioning and ADC driving unit includes a twenty-fourth resistor R24, a twenty-fifth resistor R25, a third bidirectional TVS diode D3, a third capacitor C3, a fourth capacitor C4, and an operational amplifier U1. The first end of the twenty-fourth resistor R24 ​​serves as the input terminal of the output signal conditioning and ADC driving unit, and the second end is connected to the non-inverting input terminal of the operational amplifier U1 to form a fourth node N4. The first end of the third capacitor C3 is connected to the fourth node N4, and the second end is connected to the eleventh ground terminal GND11. The inverting input terminal of the operational amplifier U1 is shorted to its output terminal. The first end of the twenty-fifth resistor R25 is connected to the output terminal of the operational amplifier U1, and the second end is connected to the twelfth ground terminal GND12 after being connected to the third bidirectional TVS diode D3 and the fourth capacitor C4 which are arranged in parallel.

[0033] In this embodiment, the function of this unit is to perform final conditioning on the single-channel voltage signal selected from the channel switching network and drive the downstream AD conversion module for high-precision sampling. Specifically, the single-channel voltage signal is input to a first-order RC low-pass filter (at node N4) composed of the 24th resistor R24 ​​and the 3rd capacitor C3. This filter can effectively attenuate the high-frequency noise and sampling clock feedback interference remaining in the power supply signal. The filtered voltage signal is directly fed into the non-inverting input of operational amplifier U1. It should be noted that operational amplifier U1 is configured as a voltage follower here (because its inverting input is shorted to its output). This structure has extremely high input impedance and extremely low output impedance. The extremely high input impedance ensures that the load effect on the front-end circuit (channel switching network) is minimized, thereby avoiding voltage signal attenuation during transmission; while the extremely low output impedance gives the unit a strong load-driving capability, providing fast and stable drive for the transient large current required by the sample-and-hold circuit of the subsequent AD conversion module. In addition, the 25th resistor R25 connected in series at the output of operational amplifier U1, together with the third bidirectional TVS diode D3 and the fourth capacitor C4 connected in parallel, constitute an output protection and decoupling network. Among them, the 25th resistor R25 acts as a current limiting resistor, and works together with the fourth capacitor C4 to further smooth the output signal and suppress transient oscillations. The third bidirectional TVS diode D3 acts as the last line of defense, which can clamp the high voltage spikes superimposed on the output signal due to unexpected situations (such as electrostatic discharge, line coupling) to a safe voltage, thereby ensuring the safety of the subsequent AD conversion module.

[0034] In conclusion, Figure 3In the voltage conversion module shown, the voltage between MEASURE-U+ and MEASURE-U- is the external sampling voltage. This voltage is initially conditioned and attenuated by a voltage divider network consisting of multiple 200kΩ resistors (R5, R9, R12, R6, R10, R13, R7, R11, R14, R8). The channel switching network flexibly switches between different voltage divider resistors (R16, R17, R18, R19) by controlling the selection of four solid-state relays (G1-G4) to adapt to input voltages of different amplitudes. When the external input voltage is a 400V to 40V AC signal (peak voltage can reach 565V), G1 is turned on (corresponding to ground terminal GND7), and R16 (3.5kΩ) is used for voltage division, so that the peak voltage UA-V1P output to the AD converter is about 0.987V, which meets the AD input requirements (<1V).

[0035] When the input voltage drops to 40V~4V (peak 56.5V), G2 (GND8) is turned on, switching to the voltage divider R17 (35kΩ). The peak value of UA-V1P is about 0.9717V, which avoids the waste of AD accuracy due to excessively low voltage and ensures that the signal is within the ideal range.

[0036] For a lower input range (4V to 2V or no more than 2V), turn on G3 (using R18=350kΩ) or G4 (using R19=1MΩ) respectively, and further adjust the voltage divider ratio so that the UA-V1P always stays within the high-precision sampling range of the AD converter.

[0037] The above design, through intelligent gating and resistor matching, achieves adaptive voltage division over a wide input voltage range, ensuring the safe operation of the AD converter while maximizing its resolution and accuracy. Combined with subsequent output signal conditioning and the ADC drive unit (including filtering, buffering, and protection circuits), a stable and clean analog voltage signal is finally output to the AD conversion module, providing a reliable data foundation for accurate grounding status determination.

[0038] In another exemplary embodiment, such as Figure 4As shown, the AD conversion module includes an AD conversion chip U2, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9, a tenth capacitor C10, an eleventh capacitor C11, a twelfth capacitor C12, a first crystal oscillator X1, a twenty-sixth resistor R26, a twenty-seventh resistor R27, and a second inductor L2. The first terminal of the fifth capacitor C5 is connected to the digital power supply pin DVDD of the AD conversion chip U2, and the second terminal is connected to the fourteenth ground terminal GND14. The sixth capacitor C6 and the seventh capacitor C7 are connected in parallel between the core power supply pin VDD1P8 of the AD conversion chip U2 and the fourteenth ground terminal GND14. The first terminal of the twenty-sixth resistor R26 is connected to the test pin TEST of the AD conversion chip U2, and the second terminal is connected to the +5V power supply. The first terminal of the eighth capacitor C8 is connected to the analog power supply pin AVCC of the AD conversion chip U2 to form the fifth node N5, and the second terminal is connected to the signal input pin V1N of the AD conversion chip U2 to form... The sixth node N6 is connected to the thirteenth ground terminal GND13; the first end of the second inductor L2 is connected to the fifth node N5, and the second end is connected to the +5V power supply; the ninth capacitor C9 and the tenth capacitor C10 are connected in parallel between the reference pin VREF of the AD converter chip U2 and the thirteenth ground terminal GND13; the first end of the twenty-seventh resistor R27 is connected to the first communication pin SPI / UART of the AD converter chip U2, and the second end is connected to the +5V power supply; the first crystal oscillator X1 is connected in parallel between the output pin OSCO and the input pin OSCI of the AD converter chip U2, forming the seventh node N7 and the eighth node N8; the first ends of the eleventh capacitor C11 and the twelfth capacitor C12 are connected to the seventh node N7 and the eighth node N8 respectively, and the second ends are connected to the sixteenth ground terminal GND16; the ground pin DGND of the AD converter chip U2 is connected to the fifteenth ground terminal GND15, and the second communication pin SPIDO / RX of the AD converter chip U2 is connected to the input terminal of the main control module.

[0039] In this embodiment, the AD conversion module achieves high-precision analog-to-digital conversion through precise power management, clock generation, and signal processing mechanisms. The AD conversion chip U2 is powered by independent analog power supplies (AVCC) and digital power supplies (DVDD), with power isolation achieved through the second inductor L2. A multi-layered decoupling capacitor network, consisting of the fifth capacitor C5, sixth capacitor C6, seventh capacitor C7, and eighth capacitor C8, filters out high and low frequency noise from both the digital and analog power supplies, ensuring the conversion process is unaffected by power supply interference. The first crystal oscillator X1, along with the eleventh capacitor C11 and twelfth capacitor C12, constitutes a precise clock source, providing a stable timing reference for sampling and conversion. The ninth capacitor C9 and the tenth capacitor C10 form a low-impedance path at the VREF pin, greatly stabilizing the reference voltage required for conversion and fundamentally guaranteeing quantization accuracy. Simultaneously, the twenty-sixth resistor R26 and the twenty-seventh resistor R27 provide correct bias and signal integrity guarantees for the test pin and communication pin, respectively.

[0040] Ultimately, this module can construct a highly clean, low-noise, and highly interference-resistant data acquisition environment, enabling it to achieve high-resolution, high-signal-to-noise ratio conversion of multiple analog signals in complex electromagnetic environments such as traction substations. It also transmits precise digital signals to the main controller via reliable SPI / UART communication, providing a solid data foundation for the analysis and decision-making of the entire monitoring system.

[0041] In another exemplary embodiment, such as Figure 5 As shown, the main control module includes a main control chip U3. The communication pins PB14 / MOSI2 of the main control chip U3 serve as the input terminals of the main control module. The main control chip U3 is electrically connected to a core power supply and clock generation unit, a reference voltage decoupling unit, and a filtering and multi-power domain decoupling unit. The core power supply and clock generation unit is used to provide a stable power supply and timing reference for the main control chip U3. The reference voltage decoupling unit is used to provide a clean analog power supply and voltage reference for the main control chip U3. The filtering and multi-power domain decoupling unit is used to achieve noise isolation and fine decoupling between different power domains within the main control chip U3.

[0042] In this embodiment, the main control module receives a first digital signal (originating from the induced current signal of the current conversion module) and a second digital signal (originating from the multi-channel voltage signal of the voltage conversion module) from the AD conversion module through the input pins (such as PB14 / MOSI2) of its main control chip U3. First, it uses a built-in digital signal processing algorithm (e.g., using a Fast Fourier Transform (FFT) algorithm to convert the time-domain signal to a frequency-domain signal to accurately analyze the harmonic components in the return current, and using a moving average filtering algorithm to smooth the sampled data to suppress random noise and extract stable signal trends) to perform synchronous calibration, digital filtering, and noise suppression on these two signals to extract effective current and voltage characteristic values ​​(such as amplitude, phase, harmonic content, and time-domain waveform). Subsequently, the main control chip uses a preset grounding state model (e.g., using an existing model based on grounding resistance and leakage current amplitude) to perform synchronous calibration, digital filtering, and noise suppression on these two signals. The fault diagnosis model based on phase characteristics monitors the voltage to ground (or grounding resistance) and the amplitude and phase of leakage current at key nodes of the grounding grid over a long period of time, and sets safety thresholds according to standards such as the "Code for Grounding Design of AC Electrical Installations". When the monitored grounding resistance continues to increase beyond the threshold, or when the amplitude / phase of the leakage current undergoes an unexpected abrupt change, the model determines that the grounding grid may have fault states such as connection point corrosion, breakage, or deterioration of soil physical and chemical properties. The model also uses threshold rules (such as grounding resistance calculation, return current ratio analysis, common-mode noise assessment, etc.) to compare these characteristic values ​​with reference data under normal operating conditions in real time, thereby comprehensively judging the grounding status of the grounding grid, including whether the grounding is reliable, whether the return path is unobstructed, and whether there are abnormal conditions such as overvoltage or insulation deterioration. Finally, it generates status indications, fault alarms, or control commands to ensure the safe and stable operation of the grounding system.

[0043] In another exemplary embodiment, the core power supply and clock generation unit includes a thirteenth capacitor C13, a fourteenth capacitor C14, a fifteenth capacitor C15, and an active crystal oscillator X2. The thirteenth capacitor C13 and the fourteenth capacitor C14 are connected in parallel to the first power ground pin VSS and the first power input pin VDD of the main control chip U3, and the connection point of the thirteenth capacitor C13 and the fourteenth capacitor C14 is connected to the seventeenth ground terminal GND17. The first end of the fifteenth capacitor C15 is connected to the power supply pin Vcc of the active crystal oscillator X2 and is also connected to a 3.3V voltage, and the second end is connected to the eighteenth ground terminal GND18. The ground terminal GND of the active crystal oscillator X2 is connected to the nineteenth ground terminal GND19.

[0044] In this embodiment, the unit forms a highly efficient decoupling and filtering network through two capacitors, C13 and C14, connected in parallel between the first power input pin VDD and the power ground pin VSS of the main control chip U3. This unit utilizes the charging and discharging characteristics of capacitors to provide transient current to the core of the main control chip U3 and absorb noise on the power line. When the transistors inside the main control chip U3 switch at high speed under the action of the active crystal oscillator X2, a huge instantaneous current demand is generated, causing micro-fluctuations in the power supply voltage. At this time, the thirteenth capacitor C13 and the fourteenth capacitor C14, acting as local miniature energy pools, can quickly respond and replenish the charge of the main control chip U3, thereby maintaining the stability of its power supply voltage. Simultaneously, the thirteenth capacitor C13 and the fourteenth capacitor C14 can also short-circuit the high-frequency noise signal superimposed on the power supply to ground (GND17), purifying the power supply sent to the main control chip U3. On the other hand, the active crystal oscillator X2 is a complete oscillator; after being powered on (decoupled via C15), it can directly output a stable and accurate square wave clock signal. The fifteenth capacitor, C15, is connected to the power supply pin of the active crystal oscillator X2. It provides a clean local power supply for the active crystal oscillator X2 itself, filters out noise from the 3.3V main power supply, and prevents this noise from interfering with the internal oscillation circuit of the crystal oscillator, thereby ensuring the frequency stability and phase noise performance of its output clock.

[0045] In another exemplary embodiment, the reference voltage decoupling unit includes a sixteenth capacitor C16, a seventeenth capacitor C17, an eighteenth capacitor C18, a nineteenth capacitor C19, and a twentieth capacitor C20. The first end of the sixteenth capacitor C16 is connected to the second power input pin VDD1 of the main control chip U3, and the second end is connected to the twentieth ground terminal GND20. The seventeenth capacitor C17 and the eighteenth capacitor C18 are connected in parallel between the twentieth ground terminal GND20 and the third power input pin VDDA of the main control chip U3. The nineteenth capacitor C19 and the twentieth capacitor C20 are connected in parallel between the twentieth ground terminal GND20 and the reference voltage input pin VREF of the main control chip U3.

[0046] In this embodiment, the unit can ensure the stable and reliable operation of the main control chip U3 by providing localized energy storage and high-frequency noise filtering for different functional power domains. Specifically, the sixteenth capacitor C16 ensures the normal operation of the digital logic circuit by suppressing the power ripple on the VDD1 pin of the main control chip U3; the seventeenth capacitor C17 and the eighteenth capacitor C18 are connected in parallel between the analog power supply VDDA and ground, which are responsible for providing extremely clean power to sensitive modules such as the ADC and analog front-end inside the main control chip U4, effectively isolating digital switching noise, thereby ensuring the conversion accuracy of analog signals; the nineteenth capacitor C19 and the twentieth capacitor C20 are connected in parallel between the reference voltage VREF and ground, which directly stabilizes the voltage reference of the ADC conversion and prevents its fluctuation from introducing system errors.

[0047] This unit enables efficient decoupling and noise isolation between the digital, analog, and reference power supplies within the main control chip U3, thereby improving the system's signal-to-noise ratio, ADC sampling accuracy, and the device's anti-interference capability and long-term operational stability in complex electromagnetic environments.

[0048] In another exemplary embodiment, the filtering and multi-power-domain decoupling unit includes a twenty-first capacitor C21, a twenty-third capacitor C23, a twenty-fourth capacitor C24, a twenty-fifth capacitor C25, and a twenty-sixth capacitor C26. The first terminal of the twenty-first capacitor C21 is connected to the fourth power input pin VDD4 of the main control chip U3. The first terminal of the twenty-second capacitor C22 is connected to the first filter pin VCAP2 of the main control chip U3. The second terminals of both the twenty-first and twenty-second capacitors C21 and C22 are simultaneously connected to the second power ground pin VSS4 of the main control chip U3. The first terminal of the twenty-third capacitor C23 is connected to the first filter pin VCAP2 of the main control chip U3. The first power input pin VDD is connected to the second filter pin VCAP1 of the main control chip U3. The second ends of the twenty-third capacitor C23 and the second ends of the twenty-fourth capacitor C24 are simultaneously connected to the twenty-second ground terminal GND22. The first end of the twenty-fifth capacitor C25 is connected to the third power ground pin VSS2 of the main control chip U3, and the second end is connected to the VDD2 pin of the main control chip U3. The first end of the twenty-sixth capacitor C26 is connected to the first power input pin VDD of the main control chip U3, and the second end is connected to the first power ground pin VSS of the active chip U3, while also being connected to the twenty-first ground terminal GND21.

[0049] In this embodiment, this unit serves as the core power integrity circuit to ensure the stable operation of the main control chip U3. It achieves noise isolation and voltage stability by providing high-frequency paths and energy buffers for different power domains. Specifically, the twenty-fourth capacitor C24 and the twenty-second capacitor C22 connected to the VCAP1 and VCAP2 pins are essential external compensation and filtering capacitors for the core voltage regulator inside the main control chip U3. They directly determine the stability of the core voltage, prevent the regulator from self-oscillating, and provide transient current for the most sensitive circuits such as the CPU core and the phase-locked loop. The twenty-first capacitor C21, the twenty-third capacitor C23, and the twenty-sixth capacitor C26 perform high-frequency decoupling for I / O power domains such as VDD4 and VDD, effectively suppressing the current ripple generated by digital circuit switching. The twenty-fifth capacitor C25, connected between VDD2 and VSS2, forms a complete local decoupling loop.

[0050] This unit enables refined management and noise isolation of key power rails such as the internal digital core, I / O interface, and internal voltage regulator output of the main control chip U3, significantly improving power quality. This ensures the clock accuracy, logic reliability, and overall anti-interference capability of the system under complex loads, avoiding faults such as program crashes, data errors, or communication failures caused by power noise.

[0051] Finally, it should be noted that the above descriptions are merely optional examples of this application and are not intended to limit this application. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A grounding grid and return current status monitoring device, characterized in that, The device includes: The current conversion module is used to convert the induced current into a low-voltage differential voltage signal; The voltage conversion module is used to process multiple voltage signals and output a stable analog voltage signal; The AD conversion module is used to convert the low-voltage differential voltage signal output by the current conversion module and the analog voltage signal output by the voltage conversion module into a first digital signal and a second digital signal, respectively. The main control module is used to analyze and process the first and second digital signals output by the AD conversion module to determine the grounding status of the grounding grid.

2. The apparatus according to claim 1, characterized in that, The current conversion module includes: The components include a current transformer, a first bidirectional TVS diode, a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, and a second capacitor. The current transformer is connected in parallel with the first bidirectional TVS diode; The first end of the first resistor is connected to the first end of the first bidirectional TVS diode to form a first node, and the second end of the first resistor is connected to the second end of the first bidirectional TVS diode via the second resistor to form a second node. The connection point of the first resistor and the second resistor is connected to the first ground terminal. The first end of the fourth resistor is connected to the first node, the first end of the third resistor is connected to the second node, the first end of the first capacitor and the second end of the fourth resistor are simultaneously connected to the positive terminal of the differential analog voltage signal of the AD conversion module, and the second end of the first capacitor is simultaneously connected to the negative terminal of the differential analog voltage signal of the AD conversion module via the second capacitor and the second end of the third resistor.

3. The apparatus according to claim 1, characterized in that, The voltage conversion module includes: The input signal conditioning unit is used to condition multiple voltage signals. The channel switching network is used to select multiple conditioned voltage signals as needed; The output signal conditioning and ADC drive unit is used to condition any voltage signal selected by the channel switching network and send it to the AD conversion module.

4. The apparatus according to claim 3, characterized in that, The input signal conditioning unit includes: The fifth resistor, sixth resistor, seventh resistor, eighth resistor, ninth resistor, tenth resistor, eleventh resistor, twelfth resistor, thirteenth resistor, fourteenth resistor, fifteenth resistor, and second bidirectional TVS diode, among which, The first end of the fifth resistor is connected to a positive differential voltage signal, and the second end is connected in series with the ninth and twelfth resistors and then connected to the first end of the thirteenth resistor. The first end of the sixth resistor is connected in series with the tenth resistor, and then connected to the second end of the thirteenth resistor. The first end of the seventh resistor is connected to the second end of the sixth resistor, and the second end is connected in series with the eleventh resistor and then connected to the first end of the fourteenth resistor. The first end of the eighth resistor is connected to the second end of the fourteenth resistor. The second end is connected to the first end of the second bidirectional TVS diode to form a third node. The third node serves as the output end of the input signal conditioning unit and is connected to the input end of the output signal conditioning and ADC driving unit via a channel switching network. The second terminal of the second bidirectional TVS diode is connected to the second ground terminal; The first end of the fifteenth resistor is connected to the negative differential voltage signal, and the second end is connected to the second ground terminal.

5. The apparatus according to claim 3, characterized in that, The channel switching network includes: The sixteenth resistor, the seventeenth resistor, the eighteenth resistor, the nineteenth resistor, the twentieth resistor, the twenty-first resistor, the twenty-second resistor, the twenty-third resistor, the first solid-state relay, the second solid-state relay, the third solid-state relay, and the fourth solid-state relay, wherein, The anodes of the first solid-state relay, the second solid-state relay, the third solid-state relay, and the fourth solid-state relay are all connected to the third node; The cathode of the first solid-state relay is connected to the third ground terminal through the sixteenth resistor, the collector is connected to the 3.3V power supply through the twentieth resistor, and the emitter is connected to the seventh ground terminal. The cathode of the second solid-state relay is connected to the fourth ground terminal through the seventeenth resistor, the collector is connected to the 3.3V power supply through the twenty-first resistor, and the emitter is connected to the eighth ground terminal. The cathode of the third solid-state relay is connected to the fifth ground terminal through the eighteenth resistor, the collector is connected to the 3.3V power supply through the twenty-second resistor, and the emitter is connected to the ninth ground terminal. The cathode of the fourth solid-state relay is connected to the sixth ground terminal through the nineteenth resistor, the collector is connected to the 3.3V power supply through the twenty-third resistor, and the emitter is connected to the tenth ground terminal.

6. The apparatus according to claim 3, characterized in that, The output signal conditioning and ADC driving unit includes: The system includes the 24th resistor, the 25th resistor, the 3rd bidirectional TVS diode, the 3rd capacitor, the 4th capacitor, and the operational amplifier. The first end of the twenty-fourth resistor serves as the input terminal of the output signal conditioning and ADC driving unit, and the second end is connected to the non-inverting input terminal of the operational amplifier to form the fourth node. The first terminal of the third capacitor C3 is connected to the fourth node, and the second terminal is connected to the eleventh ground terminal. The inverting input terminal of the operational amplifier is shorted to its output terminal. The first end of the twenty-fifth resistor is connected to the output terminal of the operational amplifier, and the second end is connected to the twelfth ground terminal after being connected to the third bidirectional TVS diode and the fourth capacitor in parallel.

7. The apparatus according to claim 1, characterized in that, The AD conversion module includes: The components include an AD conversion chip, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, an eleventh capacitor, a twelfth capacitor, a first crystal oscillator, a twenty-sixth resistor, a twenty-seventh resistor, and a second inductor. The first end of the fifth capacitor is connected to the digital power pin of the AD converter chip, and the second end is connected to the fourteenth ground terminal. The sixth and seventh capacitors are connected in parallel between the core power supply pin and the fourteenth ground pin of the AD conversion chip. The first end of the twenty-sixth resistor is connected to the test pin of the AD conversion chip, and the second end is connected to the +5V power supply. The first end of the eighth capacitor is connected to the analog power supply pin of the AD converter chip to form the fifth node, and the second end is connected to the signal input pin of the AD converter chip to form the sixth node and is connected to the thirteenth ground terminal. The first end of the second inductor is connected to the fifth node, and the second end is connected to the +5V power supply. The ninth and tenth capacitors are connected in parallel between the reference pin and the thirteenth ground pin of the AD conversion chip; The first end of the twenty-seventh resistor is connected to the first communication pin of the AD conversion chip, and the second end is connected to the +5V power supply. The first crystal oscillator is connected in parallel between the output pin and the input pin of the AD conversion chip, forming the seventh node and the eighth node; The first terminals of the eleventh and twelfth capacitors are connected to the seventh and eighth nodes respectively, and the second terminals of the eleventh and twelfth capacitors are connected to the sixteenth ground terminal. The ground pin of the AD conversion chip is connected to the fifteenth ground terminal, and the second communication pin is connected to the input terminal of the main control module.

8. The apparatus according to claim 1, characterized in that, The main control module includes: The main control chip has communication pins that serve as input terminals for the main control module. The main control chip is electrically connected to a core power supply and clock generation unit, a reference voltage decoupling unit, and a filtering and multi-power domain decoupling unit. The core power supply and clock generation unit is used to provide stable power and timing reference for the main control chip; The reference voltage decoupling unit is used to provide a clean analog power supply and voltage reference for the main control chip; The filtering and multi-power domain decoupling unit is used to achieve noise isolation and fine decoupling between different power domains within the main control chip.

9. The apparatus according to claim 8, characterized in that, The kernel power supply and clock generation unit includes: The thirteenth capacitor, fourteenth capacitor, fifteenth capacitor, and active crystal oscillator, among which, The thirteenth and fourteenth capacitors are connected in parallel to the power ground pin and the first power input pin of the main control chip, and the connection point of the thirteenth and fourteenth capacitors is connected to the seventeenth ground terminal. The first terminal of the fifteenth capacitor is connected to the power supply pin of the active crystal oscillator and also to a 3.3V voltage, while the second terminal is connected to the eighteenth ground terminal. The grounding terminal of the active crystal oscillator is connected to the nineteenth grounding terminal.

10. The apparatus according to claim 8, characterized in that, The reference voltage decoupling unit includes: The sixteenth capacitor, the seventeenth capacitor, the eighteenth capacitor, the nineteenth capacitor, and the twentieth capacitor, among which... The first end of the sixteenth capacitor is connected to the second power input pin of the main control chip, and the second end is connected to the twentieth ground terminal. The seventeenth and eighteenth capacitors are connected in parallel between the twentieth ground terminal and the third power input pin of the main control chip; The nineteenth and twentieth capacitors are connected in parallel between the twentieth ground terminal and the reference voltage input pin of the main control chip.

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