Photoelectric co-packaging method for protecting optical fiber through hole and photosensitive area

Abstract

The invention discloses a photoelectric co-packaging method for protecting an optical fiber through hole and a photosensitive area. The photoelectric co-packaging method comprises the following steps: preprocessing a glass cover plate; coating the whole surface of the pretreated glass cover plate with positive photoresist, exposing, and developing the exposed glass cover plate to obtain a patterned glass cover plate; performing dry etching on the patterned glass cover plate by adopting etching gas, and removing the photoresist by a dry method after etching; and performing scribing and sorting on the glass cover plate subjected to dry etching to obtain a small glass cover plate matched with the area of a PIC chip photosensitive region, mounting the small glass cover plate on a corresponding region of a PIC silicon carrier plate, and performing plastic packaging treatment to obtain the photoelectric co-packaged packaging structure. According to the invention, pollution prevention, optical path alignment and mechanical support are considered at the same time, and the packaging reliability is remarkably improved.

Description

Technical Field

[0001] This invention belongs to the field of optoelectronic integrated packaging technology, and relates to an optoelectronic co-packaging method for protecting optical fiber vias and photosensitive areas. Background Technology

[0002] With the rapid development of artificial intelligence, big data, cloud computing, and high-performance computing (HPC), traditional electronic integrated circuits (EICs) are gradually facing bottlenecks in terms of bandwidth, latency, and energy consumption. Photonic integrated circuits (PICs), with their advantages in high-speed, low-power, and high-bandwidth transmission, are gradually becoming core devices for next-generation information processing and interconnection. To achieve efficient collaboration between PICs and EICs, the industry commonly adopts 2.5D / 3D opto-electronic co-packaging (OECP) technology, which enables high-density interconnection of optoelectronic chips through silicon interposers, glass substrates, or fan-out redistribution (RDL) methods.

[0003] In 2.5D / 3D advanced packaging, optoelectronic co-packaging technology has the following important significance: (1) Improve bandwidth and energy efficiency: By introducing optical interconnects into the packaging layer, the power consumption and delay of inter-chip electrical interconnects can be greatly reduced, achieving Tbps-level inter-chip bandwidth.

[0004] (2) Reduce package size: Through vertical interconnect (Through-Package Vias, TPV) or fiber optic direct connection channels, avoid signal loss caused by long-distance traces on traditional PCBs.

[0005] (3) Supports large-scale integration: suitable for applications with extremely high bandwidth requirements such as AI training chips, data center switching chips, and high-speed SerDes chips.

[0006] However, PIC chips typically have multiple photosensitive areas on their surface (such as grating couplers, photodetectors (PDs), and light wave input / output ports). These areas directly determine the input / output characteristics of the optical signal and the photoelectric conversion efficiency. In existing technologies, the following main problems exist: (1) Risk of contamination and damage: When UPAD (Under Pad) or RDL (Redistribution Layer) is directly fabricated on the PIC surface, the photosensitive area may be contaminated by processes such as metal deposition, photoresist residue, and plasma etching, which may lead to a decrease in coupling efficiency or even failure.

[0007] (2) Lack of reliable protective layer: Most existing packages only deposit a transparent passivation layer above the photosensitive area, but it is easy to be damaged or stress cracked when opening the through hole and aligning the package, and cannot simultaneously take into account the fiber optic channel reservation.

[0008] (3) Insufficient process compatibility: The protection of optical apertures and photosensitive areas is usually implemented separately, lacking wafer-level mass production and integrated solutions, making it difficult to meet the needs of high-precision alignment and large-scale manufacturing at the same time.

[0009] Therefore, the existing solution cannot simultaneously meet the following requirements: (1) Effective protection of the photosensitive area; (2) Direct access channel for optical fibers or optical components; (3) Achieve batch integration at the wafer level; (4) The PIC surface is processed with high precision UPAD / RDL. Summary of the Invention

[0010] The purpose of this invention is to provide a photoelectric co-packaging method that protects the optical fiber via and the photosensitive area, thereby solving the problem of contamination of the photosensitive area caused by plastic encapsulation in existing photoelectric co-packaging applications.

[0011] To achieve the above objectives, the present invention employs the following technical solution: A method for optoelectronic co-encapsulation to protect the optical fiber via and the photosensitive area includes: Pre-treat the glass cover plate; The pretreated glass cover plate is coated with positive photoresist and exposed. The exposed glass cover plate is then developed to obtain a patterned glass cover plate. The patterned glass cover was dry etched using an etching gas, and the photoresist was then removed by dry etching. After dry etching, the glass cover plate is divided and sorted to obtain small glass cover plates that match the photosensitive area of ​​the PIC chip. The small glass cover plates are then mounted on the corresponding area of ​​the PIC silicon substrate and vertically integrated with the EIC chip. The integrated module is encapsulated using optoelectronic co-encapsulation, and the front side is thinned to obtain the optoelectronic co-encapsulated packaging structure.

[0012] Furthermore, the pretreatment process for the glass cover includes: Clean the glass cover to remove surface impurities, oil, particles, and residual film. The cleaned glass cover plate is annealed at a temperature of 500~600℃ for 1~3 hours. The annealed glass cover plate is subjected to chemical mechanical thinning and polishing.

[0013] Furthermore, the etching gas includes a main etching gas and an auxiliary etching gas. The main etching gas is a fluorine-containing gas, and the auxiliary etching gas is argon.

[0014] Furthermore, dry etching achieves anisotropic etching through ion-assisted etching and sidewall passivation protection, resulting in vertical sidewalls.

[0015] Furthermore, the dry process for removing photoresist is as follows: Process gas is introduced into the vacuum reaction chamber, and an electromagnetic field is applied by a radio frequency power supply to ionize the gas and form plasma. The plasma is used to convert the photoresist on the surface of the glass cover into gaseous products, which are then removed by the vacuum system.

[0016] Furthermore, the main component of the process gas is oxygen, with hydrogen, nitrogen, or fluorine-containing gases added depending on the type of photoresist.

[0017] Furthermore, the parameters affecting dry photoresist removal include RF power, chamber pressure, and processing time.

[0018] Furthermore, the depth of the dry-etched fiber access via is the same as that of the protective groove.

[0019] Furthermore, the photoresist is a positive photoresist, which is an organic polymer composed of carbon, hydrogen, and oxygen elements.

[0020] Furthermore, the small glass cover is attached to the PIC silicon substrate using bonding adhesive.

[0021] Compared with the prior art, the present invention has the following beneficial effects: This invention provides a photoelectric co-packaging method for protecting fiber optic vias and photosensitive areas. Through dry etching, localized etching and opening design are performed on a glass cover plate to form a glass cover plate with a protective groove structure and fiber optic access vias. Precision alignment vias are reserved at the wafer level to improve optical coupling efficiency. Temporary bonding between the glass cover plate and the carrier wafer protects the photosensitive area, preventing contamination of the PD / grating area by photoresist, metal sputtering, or etching. While protecting the photosensitive areas such as the grating / PD from process contamination, fiber optic access vias are reserved. The packaging structure design of this invention is compatible with refined patterning processes, ensuring protection of the photosensitive area while supporting large-scale wafer-level batch processing. It possesses manufacturability for mass production and large-scale packaging, reducing per-wafer costs and improving process yield. Compared to traditional solutions that only apply a passivation layer, this invention simultaneously addresses contamination prevention, optical path alignment, and mechanical support, providing a stable fiber optic via path for direct coupling to external optical devices. It also meets the requirements for high-density electrical interconnects, significantly improving packaging reliability and enabling complete 2.5D / 3D optoelectronic co-packaging capabilities. Furthermore, this invention is the first to simultaneously protect both the photosensitive area and the fiber optic via at the packaging structure level, resolving the pain point of existing technologies that cannot simultaneously ensure the reliability of optical channels and photosensitive surfaces. By protecting the photosensitive area while maintaining isolation, it resolves the inherent contradiction in existing technologies of the incompatibility between "protecting the photosensitive area" and "achieving electrical interconnects." Therefore, this invention not only effectively improves the reliability and scalability of optoelectronic co-packaging but also lays the foundation for future large-scale HPC, AI, and optoelectronic integrated applications. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a planar structural diagram of the PIC chip silicon wafer of the present invention.

[0024] Figure 2 This is a cross-sectional view of the vertically integrated structure of the EIC and PIC chip of the present invention.

[0025] Figure 3 This is a planar structural diagram of the glass substrate of the present invention.

[0026] Figure 4 This is a cross-sectional view of the glass cover plate structure of the present invention.

[0027] Figure 5 This is a schematic diagram of the glass substrate dicing and sorting process according to the present invention.

[0028] Figure 6 This is a schematic diagram of the protective photosensitive area of ​​the glass cover plate before molding according to the present invention.

[0029] Figure 7 This is a schematic diagram of the photoelectric co-encapsulated module after molding according to the present invention.

[0030] Figure 8 This is a schematic diagram of the thinned photoelectric co-sealed module of the present invention.

[0031] Figure 9 This is a flowchart of the optoelectronic co-encapsulation method for protecting the optical fiber through-hole and the photosensitive area according to the present invention.

[0032] Figure 10 This is a schematic diagram of the glass substrate after cleaning and stress relief treatment according to the present invention.

[0033] Figure 11 This is a flowchart of the glass cover cleaning and stress relief process of the present invention.

[0034] Figure 12 This is a schematic diagram of the glass cover plate after the adhesive has been applied according to the present invention.

[0035] Figure 13 This is a schematic diagram of the glass cover plate after exposure according to the present invention.

[0036] Figure 14 This is a schematic diagram of the glass cover plate after development according to the present invention.

[0037] Figure 15 This is a flowchart illustrating the fabrication process of the optical fiber access via and protective groove of the present invention.

[0038] Figure 16 This is a schematic diagram of the glass cover plate after dry etching according to the present invention.

[0039] Figure 17 This is a schematic diagram of the glass cover plate after dry adhesive removal according to the present invention.

[0040] Figure 18 This is a schematic diagram of the glass cover plate after the bonding adhesive has been applied according to the present invention.

[0041] Figure 19 This is a schematic cross-sectional view of the small glass cover plate of the present invention.

[0042] Wherein: 1-PIC chip, 1a-PIC_upad, 1b-PIC_PD, 2-silicon substrate, 3-photosensitive area, 4-EIC chip, 4a-EIC_upad, 4b-EIC_ubump, 5-glass cover, 5a-fiber optic access via, 5b-protective groove, 8-bonding adhesive, 9-photoresist, 9a-photoresist decomposition, 9b-photoresist dissolution, 10-molding. Detailed Implementation

[0043] To enable those skilled in the art to understand the features and effects of the present invention, the terms and expressions used in the specification and claims are explained and defined in general below. Unless otherwise specified, all technical and scientific terms used herein have the ordinary meaning understood by those skilled in the art regarding the present invention, and in case of conflict, the definitions in this specification shall prevail.

[0044] The theories or mechanisms described and disclosed herein, whether right or wrong, should not in any way limit the scope of the invention, that is, the contents of the invention can be implemented without being limited by any particular theory or mechanism.

[0045] In this document, all features defined by numerical ranges or percentage ranges, such as numerical values, quantities, contents, and concentrations, are for the sake of brevity and convenience only. Accordingly, descriptions of numerical ranges or percentage ranges should be considered as covering and specifically disclosing all possible sub-ranges and individual numerical values ​​(including integers and fractions) within those ranges.

[0046] In this article, unless otherwise specified, “contains,” “includes,” “containing,” “has,” or similar terms cover the meanings of “composed of” and “mainly composed of,” for example, “A contains a” covers the meanings of “A contains a and others” and “A contains only a.”

[0047] For the sake of brevity, not all possible combinations of the technical features in each implementation scheme or embodiment are described herein. Therefore, as long as there is no contradiction in the combination of these technical features, the technical features in each implementation scheme or embodiment can be combined arbitrarily, and all possible combinations should be considered within the scope of this specification.

[0048] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. The present invention will be further illustrated with specific embodiments. It should be understood that these embodiments are only for illustrating the present invention and not for limiting the scope of the present invention. The described embodiments are some embodiments of the present invention, not all embodiments. The detailed description of the embodiments of the present invention is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the invention. Furthermore, it should be understood that after reading the teachings of this invention, those skilled in the art can make various modifications or alterations to the present invention, and these equivalent forms also fall within the scope defined by the appended claims. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of the present invention.

[0049] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the embodiments of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0050] To enable those skilled in the art to more clearly understand the technical solutions described in this invention, the following embodiments are provided for illustration. It should be noted that the following embodiments do not constitute a limitation on the scope of protection claimed by this invention. Unless otherwise specified, the raw materials, reagents, or apparatus used in the following embodiments can be obtained from conventional commercial sources or by existing known methods. Conventional instruments and equipment in the art are used in the following embodiments. Experimental methods in the following embodiments that do not specify specific conditions are generally performed under conventional conditions or according to the manufacturer's recommendations. Various raw materials used in the following embodiments are all conventional commercially available products with specifications that are conventional in the art, unless otherwise stated. In the specification of this invention and the following embodiments, unless otherwise specified, "%" represents weight percentage, "parts" represents parts by weight, and "ratio" represents weight ratio.

[0051] The present invention will now be described in further detail with reference to the accompanying drawings: This invention provides a photoelectric co-packaging method for protecting optical fiber vias and photosensitive areas. In this method, a bonding glass cover 5 protects the photosensitive area 3, while simultaneously supporting high-precision alignment of the photosensitive area on the PIC chip 1. By adding a glass cover to protect the photosensitive area after vertical integration of the PIC and EIC before re-molding, the problem of contamination of the photosensitive area caused by molding in photoelectric co-packaging applications is solved. This method is particularly suitable for advanced packaging fields such as fan-out packaging and 2.5D / 3D heterogeneous integration. The fabrication method of this glass cover involves processes such as coating, exposure, development, dry etching, dry resist removal, dicing and sorting, surface mounting, molding, and thinning, ensuring the alignment accuracy between the via and photosensitive area positions, the stability of the bonding interface, and the reliability of high-density interconnects.

[0052] like Figure 1As shown, the incoming material is a silicon wafer for mass integration of PIC chips. The surface of PIC chip 1 has both an electrical connection area vertically integrated with EIC chip 4 and multiple photosensitive areas to complete the input / output of optical signals and photoelectric conversion. First, the upad on the surface of PIC chip 1, as well as EIC_upad 4a and EIC_ubump 4b, are fabricated. Then, EIC chip 4 is vertically integrated with PIC chip 1, that is, electrical interconnection is achieved through EIC_ubump 4b and PIC_upad 1a, as shown. Figure 2 As shown. After the EIC chip 4 and PIC chip 1 are vertically integrated, the integrated OM module needs to be molded. However, this will contaminate the photosensitive area 3 on the surface of the PIC chip 1. Therefore, before molding, a glass cover plate 5 integrating photosensitive area protection and fiber optic through-hole is first prepared. The planar structure layout of the glass substrate 5 is as follows. Figure 3 As shown, the position of the incoming wafer corresponding to the PIC chip 1 is marked, and the positions of the protective groove 5b and the optical fiber access through hole 5a to be prepared are marked in the DIE area. Figure 4 The diagram shows a cross-sectional view of the glass cover plate structure. Patterned openings, including a fiber optic access via 5a and a protective groove 5b, are created on one side. These openings are used for fiber optic connection and optical sensing, respectively. The via structure also assists in positioning, achieving high-precision alignment with the photosensitive area on the PIC surface. Subsequently, bonding adhesive 8 is applied to the opening side of the glass cover plate. The glass substrate 5 is then diced according to the size of the photosensitive area 3 on the PIC chip 1 surface, as shown below. Figure 5 As shown, each small piece of glass cover is then glued to the photosensitive area 3 on the PIC surface to achieve the protective function before molding. Figure 6 As shown; then, the optoelectronic co-sealed module 10 is performed to achieve mechanical stability and electrical insulation of the structure, and to provide a good heat dissipation environment for the module, such as... Figure 7 As shown. Finally, front-side thinning is performed to expose the uncontaminated optical fiber access via 5a and photosensitive area 3, as shown. Figure 8 The preparation is completed as shown.

[0053] like Figure 9 As shown, the specific steps include: Step 1: Pre-treatment of the glass cover plate like Figure 11 As shown, the pre-selected glass cover plate 5 is cleaned to remove surface impurities, oil, particles, and residual film. Subsequently, the glass cover plate 5 undergoes necessary stress-relief treatment. It is first annealed in a vertical curing oven at 500-600℃ for 1-3 hours to release internal stress, improve mechanical stability, and reduce warping. Then, chemical mechanical polishing is performed to remove micro-stress layers and improve surface smoothness. This ensures that warping or stress cracks will not occur during subsequent dry etching, thinning, and bonding processes. The treated glass substrate is shown below. Figure 10 As shown.

[0054] Step 2: Patterning of fiber optic access via 5a and protective groove 5b (same depth) like Figure 15 As shown, positive photoresist 9 is first applied to the entire surface of the glass cover plate 5, and its cross-sectional structure is as follows. Figure 12 As shown, the thickness of photoresist 9 is related to the precision of the patterned CD, and the uniformity of the coating affects the overall warpage and CD uniformity. The viscosity of photoresist 9 affects the adhesion between the glass substrate 5 and photoresist 9. Therefore, the selection of photoresist 9 must achieve both small-size CD patterning and strong adhesion to the glass substrate, while also possessing strong corrosion resistance to prevent photoresist 9 from being corroded or detached during dry etching of vias or grooves due to photoresist decomposition 9a and photoresist dissolution 9b. Subsequently, as... Figure 13 The image shows a positive photoresist photomask being exposed in an exposure machine. As light passes through the photomask pattern, the solubility of the photoresist in the developer increases dramatically. Figure 14 The image shows the patterned glass cover plate after development.

[0055] Step 3: Dry etching openings (at the same depth) for fiber optic access via 5a and protective groove 5b. Dry etching typically uses fluorine-containing gases such as carbon tetrafluoride and sulfur hexafluoride because the main component of glass is SiO2, which can react with fluoride ions to generate volatile products. Argon is usually added as an auxiliary gas because it is an inert gas and does not participate in the chemical reaction, but its large mass enhances the intensity of ion sputtering. Anisotropic etching is key to achieving high perpendicularity, mainly achieved through two mechanisms: ion-assisted etching and sidewall passivation protection, which balance the physical bombardment and chemical reaction. The core mechanism of ion-assisted etching is to accelerate ion perpendicular bombardment of the sample surface by adjusting the electric field direction to be parallel to the sidewall, thereby enhancing the chemical reaction rate. Simultaneously, few ions directly bombard the sidewalls under the vertical electric field, thus suppressing lateral etching and forming vertical sidewalls. Sidewall passivation protection is a more sophisticated technique. By selecting appropriate gas formulations (such as adding carbon-rich gases like CHF3 and C4F8), these gases deposit a thin layer of fluorocarbon polymer on the sidewalls of the etched pattern during the etching process, effectively protecting the sidewalls from chemical free radical erosion. The bottom layer, subjected to continuous vertical bombardment by ions, gradually erodes the polymer film, allowing the etching process to continue. This achieves the effect of bottom etching and sidewall protection, resulting in relatively vertical sidewalls. Figure 16 The diagram shown is a schematic cross-sectional view of the pattern opening after dry etching following development.

[0056] Step 4: Dry removal of adhesive after etching Dry photoresist stripping essentially utilizes the high reactivity of plasma (the fourth state of matter) to convert solid photoresist 9 into gaseous products, which are then removed by a vacuum system. The core reaction is the "ashing" process. First, a small amount of process gas (most commonly O2) is introduced into the vacuum reaction chamber, and then a high-frequency electromagnetic field is applied via an RF power supply. Gas molecules are ionized under high-energy electron bombardment, forming a plasma containing various active particles such as ions, electrons, and active free radicals. Positive photoresist 9 is mainly composed of organic polymers of elements such as carbon, hydrogen, and oxygen. The highly reactive ions in the plasma (especially oxygen free radicals O) undergo a strong redox reaction with the photoresist 9 molecules, generating small-molecule gaseous products such as carbon dioxide, carbon monoxide, and water vapor. Furthermore, positively charged ions are accelerated under the electric field, vertically bombarding the photoresist 9 surface, which helps break the cross-linked polymer chains and expose new reaction interfaces, especially effective for photoresist layers with modified surfaces (such as those hardened after ion implantation). To achieve the best photoresist removal effect, the following key parameters need to be precisely controlled: (1) Gas selection: Oxygen is the most commonly used, providing oxygen free radicals for oxidation reaction. Adding hydrogen or nitrogen helps to remove specific residues or regulate reaction activity. For special photoresists (such as SU-8), a small amount of fluorine-containing gas (such as CF4) needs to be added to increase the removal rate. (2) Radio frequency power: The higher the power, the higher the plasma density and the faster the removal rate. However, excessive power may cause the substrate temperature to rise significantly or even cause damage. It needs to be optimized according to the chamber size and process requirements. For photoresists with a hard shell on the surface, a gradient power method can be used, first softening the hard shell with low power and then removing it completely with high power. (3) Chamber pressure: Pressure affects the uniformity of plasma and the mean free path of active particles. If the pressure is too low, there are fewer active particles; if the pressure is too high, the collision between particles intensifies and the energy decreases. Usually, a low vacuum level (e.g., on the order of 1.3~13 Pa) is maintained. (4) Processing time: determined by the thickness of the photoresist and the removal rate. Ideally, an endpoint detection system should be installed to determine whether the photoresist has been completely removed by detecting changes in the plasma emission spectrum, thus preventing over-etching or incomplete removal. Figure 17 This is a schematic diagram of the cross-sectional structure of the glass cover plate after dry adhesive removal.

[0057] Step 5: Apply bonding adhesive Bonding adhesive 8 is applied to specific areas of the glass substrate 5 using a roller coating method. This allows the diced small glass cover plates 5 to be mounted onto corresponding areas of the PIC silicon carrier 2, achieving high-precision alignment. Figure 18 The diagram shows a cross-sectional view of the glass cover plate after the adhesive has been rolled onto it.

[0058] Step Six: Segmentation & Sealing After applying bonding adhesive 8, the entire glass substrate 5 is diced and sorted to obtain small glass coverslet pieces corresponding to the area of ​​the photosensitive area 3 of the PIC chip, such as... Figure 5 As shown, the small glass cover plates protecting the photosensitive areas of each PIC chip 1 are separated out, and their cross-sectional structure is shown in the schematic diagram below. Figure 19 As shown, a small glass cover plate contains not only fiber optic through-holes but also a protective groove 5b structure for the photosensitive area 3, which provides excellent protection for the photosensitive area of ​​the PIC chip before molding the PIC and EIC chips. Vertical integration with the EIC chip is then performed, followed by molding the optoelectronic co-encapsulation module 10 to achieve mechanical stability and electrical insulation of the structure. Finally, front-side thinning is performed to expose the uncontaminated fiber optic access through-hole 5a and the photosensitive area 3, completing the encapsulation.

[0059] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for photoelectric co-encapsulation of protecting optical fiber vias and photosensitive areas, characterized in that, include: Pre-treat the glass cover plate; The pretreated glass cover plate is coated with positive photoresist and exposed. The exposed glass cover plate is then developed to obtain a patterned glass cover plate. The patterned glass cover was dry etched using an etching gas, and the photoresist was then removed by dry etching. After dry etching, the glass cover plate is diced and sorted to obtain small glass cover plates that match the photosensitive area of ​​the PIC chip. The small glass cover plates are then mounted on the corresponding area of ​​the PIC silicon substrate and vertically integrated with the EIC chip. The integrated module is encapsulated using optoelectronic co-encapsulation, and the front side is thinned to obtain the optoelectronic co-encapsulated packaging structure.

2. The optoelectronic co-encapsulation method for protecting the optical fiber via and the photosensitive area according to claim 1, characterized in that, The pretreatment process for the glass cover plate includes: Clean the glass cover to remove surface impurities, oil, particles, and residual film. The cleaned glass cover plate is annealed at a temperature of 500~600℃ for 1~3 hours. The annealed glass cover plate is subjected to chemical mechanical thinning and polishing.

3. The optoelectronic co-encapsulation method for protecting the optical fiber via and the photosensitive area according to claim 1, characterized in that, The etching gas includes a main etching gas and an auxiliary etching gas. The main etching gas is a fluorine-containing gas, and the auxiliary etching gas is argon.

4. The optoelectronic co-encapsulation method for protecting the optical fiber via and the photosensitive area according to claim 1, characterized in that, Dry etching achieves anisotropic etching through ion-assisted etching and sidewall passivation protection, resulting in vertical sidewalls.

5. The optoelectronic co-encapsulation method for protecting the optical fiber via and the photosensitive area according to claim 1, characterized in that, The dry process for removing photoresist is as follows: Process gas is introduced into the vacuum reaction chamber, and an electromagnetic field is applied by a radio frequency power supply to ionize the gas and form plasma. The plasma is used to convert the photoresist on the surface of the glass cover into gaseous products, which are then removed by the vacuum system.

6. The optoelectronic co-encapsulation method for protecting the optical fiber via and the photosensitive area according to claim 5, characterized in that, The main component of the process gas is oxygen, with hydrogen, nitrogen, or fluorine-containing gases added depending on the type of photoresist.

7. The optoelectronic co-encapsulation method for protecting the optical fiber via and the photosensitive area according to claim 1, characterized in that, The parameters affecting dry photoresist removal include RF power, chamber pressure, and processing time.

8. The optoelectronic co-encapsulation method for protecting optical fiber vias and photosensitive areas according to claim 1, characterized in that, The depth of the optical fiber access via and the protective groove are the same when dry-etched.

9. The optoelectronic co-encapsulation method for protecting the optical fiber via and the photosensitive area according to claim 1, characterized in that, Photoresist is a positive photoresist, an organic polymer composed of carbon, hydrogen, and oxygen elements.

10. The optoelectronic co-encapsulation method for protecting the optical fiber via and the photosensitive area according to claim 1, characterized in that, The small glass cover is attached to the PIC silicon substrate using bonding adhesive.

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