Memory software fault tolerance and quick starting method for single event upset

Abstract

The invention provides a single event upset-oriented memory software fault tolerance and quick start method, which relates to the field of memory software fault tolerance, and comprises the following steps of: uniformly mapping high-risk error bits distributed in a plurality of data blocks in start-up related data into a mapping table by observing and analyzing the high-risk error bits; according to the method, the corresponding high-risk error bit can be quickly and accurately positioned in the starting stage, and quick access and error repair of starting key data are realized. In the starting stage of the Flash memory, firstly, a cyclic redundancy check technology with low calculation cost is adopted to carry out rapid error detection and repair on a mapping table and starting related data, so that high-risk error bits in the starting related data are processed and repaired in a centralized manner, and in the correctness check of the subsequent starting related data, the high-risk error bits in the starting related data are not subjected to error detection. And only the cyclic redundancy check operation needs to be executed, so that the correctness check burden in the starting stage of the Flash memory is effectively reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of memory software fault tolerance, in particular to a memory software fault tolerance and fast start method for single event upsets. BACKGROUND

[0002] In the space radiation environment, high-energy particles hitting the Flash memory can easily cause single event upset effects, leading to the silent destruction of stored data, and seriously affecting the stability and reliability of the system.

[0003] Current solutions to the problem of single event upset of Flash memory mainly include hardware fault tolerance and software fault tolerance: (1) Hardware fault tolerance scheme: typical hardware fault tolerance techniques include triple modular redundancy and radiation-hardened design. Triple modular redundancy corrects errors by duplicating key modules three times and combining majority voting mechanism. Although this method is highly reliable, it requires additional hardware resources.

[0004] (2) Software fault tolerance scheme: the most representative software fault tolerance technique is the error correction code (ECC) based method. Although the traditional ECC technique can effectively correct multiple bit errors, it needs to consume fixed computing resources even in normal conditions without errors, which will bring significant performance overhead in the system startup phase.

[0005] The main limitations of the prior art are: 1) The hardware solution is too expensive and difficult to implement in a consumer SoC; 2) The traditional ECC technique requires full decoding, which has large computing overhead; Although the prior art has proposed various solutions to the problem of single event upset of Flash memory, there are still the following significant deficiencies: (1) Defects of hardware fault tolerance scheme (such as triple modular redundancy TMR): this scheme is highly reliable, but has a serious resource waste problem. Due to the need for three times replication of key modules and the addition of voting circuit, the chip area increases by about 200%, and the power consumption increases by about 180%.

[0006] (2) Defects of traditional ECC technique: although it can effectively correct multiple bit errors, it has a prominent fixed overhead problem.

[0007] (3) Defects of CRC-ECC combination scheme: although it reduces part of the decoding operation through CRC pre-screening, it has the problem of low error handling efficiency. SUMMARY

[0008] In view of the deficiencies of the prior art, the purpose of the present application is to propose a memory software fault tolerance and fast start method for single event upset, which includes: In a process of starting a flash memory multiple times based on a starting data block, a high-risk bit of the starting data block and a position of the high-risk bit in the starting data block are determined, the starting data block includes an original data area and ECC check bits, and the original data area includes multiple bits. According to the high-risk bit of the starting data block and the position of the high-risk bit in the starting data block, a mapping table is generated, and the mapping table is encoded to generate an encoded mapping table. The mapping table includes a mark of whether each bit is a high-risk bit. A plurality of starting data blocks of the flash memory are obtained, a target starting data block is determined based on the encoded mapping table, and then all target starting data blocks are obtained, and the flash memory is started based on the all target starting data blocks.

[0009] Optionally, in the process of starting the flash memory multiple times based on the starting data block, the high-risk bit of the starting data block and the position of the high-risk bit in the starting data block are determined, and the method includes the following steps. The multiple starting data blocks are sequentially read from the memory. In the process of starting the flash memory multiple times, the position of an error bit in the starting data block is determined based on the original data area and the ECC check bits, and the error times of the error bit are recorded. The error bit with the error times greater than a preset threshold is obtained as the high-risk bit of the starting data block, and then the position of the high-risk bit in the starting data block is determined.

[0010] Optionally, in the process of starting the flash memory multiple times, the error bit in the starting data block is determined based on the original data area and the ECC check bits, and the error times of the error bit are recorded, and the method includes the following steps. The flash memory is started based on the starting data block, a first starting data block is obtained, and for the first starting data block, a comprehensive vector is calculated according to the original data area and the ECC check bits. When the comprehensive vector is 0, it is indicated that the starting data block does not have an error bit, a next starting data block is obtained, and the step of calculating the comprehensive vector according to the original data area and the ECC check bits is performed again; when the comprehensive vector is not 0, it is indicated that the starting data block has an error bit, and the error bit in the original data area of the starting data block is obtained by solving the comprehensive vector using an ECC decoding algorithm. The bit of the error bit is inverted or corrected, the starting data block number to which the error bit belongs and the position of the error bit in the starting data block are recorded, the error times of the error bit are increased by one, a next starting data block is obtained, and the step of calculating the comprehensive vector according to the original data area and the ECC check bits is performed again until the last starting data block. Multiple times to start the flash memory, repeat the above operation, get each start data block in the position of the error bit and its corresponding error bit error times.

[0011] Optionally, according to the original data area and the ECC check bit, the comprehensive vector is calculated, including: Based on the pre-set encoding scheme, the check matrix H is determined, the original data area and the ECC check bit are spliced according to the pre-defined position, the received code word vector r is obtained, and the comprehensive vector s is generated based on the check matrix H and the received code word vector r. The comprehensive vector s is realized by the following formula: s=H•r T (mod2); Wherein, T represents transposition.

[0012] Optionally, according to the high-risk bit of the start data block and the position of the high-risk bit in the start data block, a mapping table is generated, and the mapping table is encoded to generate an encoding mapping table, including: According to the high-risk bit of the start data block and the position of the high-risk bit in the start data block, the start data block is marked to obtain the mapping table, and the mapping table contains the start data block and the mark of each bit in the start data block. The mark of each bit represents whether the bit is a high-risk bit; According to the mark of the bit, the mapping table is divided into high-risk data segment and non-high-risk data segment; According to the preset encoding scheme, the check redundancy information is generated for the high-risk data segment or the non-high-risk data segment; The high-risk data segment and its corresponding check redundancy information are encapsulated, and the non-high-risk data segment and its corresponding check redundancy information are encapsulated to obtain a plurality of encoding segment units; All encoding segment units are written into the target storage location according to the position order before division to obtain the encoding mapping table, and the version number and validity flag of the encoding mapping table are generated.

[0013] Optionally, based on the encoding mapping table, the target start data block is determined, including: The start data block is subjected to CRC check to obtain a check result, and in the case that the check result matches the check redundancy information in the encoding mapping table, the start data block is taken as the target start data block. In the case that the check result does not match the check redundancy information in the encoding mapping table, the start data block is subjected to ECC decoding, and the target start data block is determined based on the encoding mapping table.

[0014] Optionally, the start data block is subjected to ECC decoding, and the target start data block is determined based on the encoding mapping table, including: The start data block is parsed, high-risk bit positions in the start data block are determined according to the encoding mapping table, the high-risk bit positions are flipped or reconstructed, and the target start data block is obtained.

[0015] The technical scheme has the beneficial effects that: The application unifies the high-risk error bit positions distributed in multiple data blocks in the start-related data to a special data structure, called a mapping table, thereby realizing centralized and unified management of the high-risk error bit positions. Through the mapping table, the Flash memory can quickly and accurately locate the corresponding high-risk error bit positions in the start phase, realize fast access and error repair of the start key data, and introduce a correctness verification operation of the start-related file in the Flash memory start phase. The operation is based on the error aggregation mapping mechanism, adopts a verification-decoding hierarchical mechanism, and sequentially performs correctness verification on the mapping table and the start-related data. To reduce the start time overhead, the Flash memory first uses the cyclic redundancy check technology with low calculation cost to quickly detect errors of the mapping table and the start-related data. Only when the detection result shows that there is a potential high-risk error bit position, the decoding operation of the error correction code is triggered. Since the high-risk error bit positions in the start-related data have been concentrated and repaired in the correctness verification of the mapping table, the correctness verification of the subsequent start-related data usually only needs to perform the cyclic redundancy check operation, and does not need to trigger the decoding operation of the complete error correction code, thereby effectively reducing the correctness verification burden of the Flash memory in the start phase. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 A schematic diagram of the single-event upset oriented memory software fault tolerance and fast start method in the embodiment of the application; Figure 2 A flowchart of the single-event upset oriented memory software fault tolerance and fast start method in the embodiment of the application. DETAILED DESCRIPTION

[0017] The specific embodiments of the application will be further described in detail below with reference to the accompanying drawings and embodiments. The following embodiments are used to illustrate the application, but are not used to limit the scope of the application.

[0018] In view of the problems in the prior art, the application aims to solve the three core problems faced by consumer-grade SoC in the space radiation environment: Overcome the problem of low efficiency of traditional fault-tolerant solutions: the existing ECC technology adopts a full-amount decoding mechanism, which leads to the need to perform a complete error detection-location-correction process on all data blocks during the system (i.e. Flash memory) startup process. Experimental data shows that even in the normal case without errors, it still takes a fixed decoding time of 1.2 seconds to process 300MB of startup data. The present invention shortens the verification time of error-free data blocks to 1 / 20 of the traditional method through an innovative hierarchical processing mechanism, significantly improving the system startup efficiency.

[0019] Solve the problem of lack of targeting in error handling: the traditional solution fails to effectively utilize the spatial locality feature of single event upset errors, and uses the same processing strength for high-frequency error bits and ordinary error bits. Based on in-depth research on the radiation sensitivity characteristics of floating gate memory (see the literature "Heavy ion induced upset errors in 90-nm 64 Mb NOR-type floating-gate Flash memory"), the present invention proposes an error aggregation mapping mechanism to accurately identify and protect high-risk error bits, which improves the utilization rate of fault-tolerant resources by more than 3 times.

[0020] Break through the adaptability limitations of static fault-tolerant strategies: existing technologies use fixed parameter configurations and cannot adapt to dynamic changes in the radiation environment. As described in the literature "Neutron induced strike: On the likelihood of multiple bit-flips in logic circuits", the radiation sensitivity of devices changes with the increase of cumulative dose. The present invention introduces a dynamic updating algorithm that can automatically track the evolution of error distribution and maintain the best fault-tolerant effect through real-time error statistics and MAD analysis.

[0021] By solving the above problems, the present invention ultimately aims to achieve the following technical objectives: (1) Reduce the system startup time by 60-80% while ensuring error correction capability (8bit / 512B); (2) Compress the storage of the error bit mapping table to control the fault-tolerant management overhead within 0.1% of the storage space; (3) Implement dynamic adaptive adjustment to maintain stable fault-tolerant performance within 10^5 erase-write cycles.

[0022] The realization of these objectives will enable consumer-grade SoCs to achieve the reliability level of space-grade chips in a space radiation environment, while maintaining their cost and performance advantages, providing key technical support for low-cost spacecraft design.

[0023] In combination with Figure 1, in view of the discrete space distribution of high-risk error bits in the startup-related data, the application designs an error aggregation mapping mechanism, the core of the mechanism is to observe and analyze the high-risk error bits distributed in multiple data blocks in the startup-related data, and map them to a special data structure, called error bit mapping table, so that the centralized and unified management of these high-risk error bits is realized. Through the error bit mapping table, the system (i.e. the flash memory) can quickly and accurately locate the corresponding high-risk error bits in the startup phase, realize the fast access and error repair of the startup key data. In the system running stage, the system real-time statistics the new error bits observed in the startup process, and after each statistical window ends, the error bit mapping table is reconstructed based on the latest observation results, and the gradual optimization of the error space distribution model is realized. It is worth noting that the dynamic updating process of the error bit mapping table can be executed asynchronously using the background idle resources, so as not to introduce additional startup delay and interfere with the normal operation of the foreground task of the system.

[0024] In the system startup phase, the application introduces the correctness verification operation of the startup-related files in the conventional startup process, which is based on the error aggregation mapping mechanism and adopts the verification-decoding hierarchical mechanism to verify the correctness of the error bit mapping table and the startup-related data one by one. In order to reduce the startup time overhead, the system first uses the cyclic redundancy check technology with lower calculation cost to quickly detect errors in the error bit mapping table and the startup-related data, and only when the detection result shows that there is a potential high-risk error bit, the decoding operation of the error correction code is triggered. Since the high-risk error bits in the startup-related data have been concentrated and repaired in the correctness verification of the error bit mapping table, the correctness verification of the subsequent startup-related data usually only needs to perform the cyclic redundancy check operation, without triggering the decoding operation of the complete error correction code, effectively reducing the correctness verification burden of the system startup phase.

[0025] The error bit mapping table is the core component of the error aggregation mapping mechanism. Each data item in the error bit mapping table actually records a mapping relationship, which is used to point to the address of a specific high-risk error bit in the startup-related data (such as the value b stored in table item a, b is the address of the high-risk error bit in the memory). With the help of the error bit mapping table, the system can quickly and accurately locate the corresponding high-risk error bit, access and read the data at this position, and thus realize the pre-correction verification of the high-risk error bit group in the startup-related data. With the passage of system running time and the change of external radiation environment conditions, the spatial distribution of high-risk error bits may present a dynamic evolution trend. In order to maintain the accuracy of error aggregation mapping and continuously exert the effectiveness of hierarchical fault tolerance strategy, the application proposes an error bit mapping table dynamic updating algorithm (as shown in algorithm 1), which aims to adapt to the time-varying characteristics of error bit space distribution.

[0026] Algorithm 1 Error bit map dynamic updating algorithm Input: Set of startup related data blocks D, system startup times N Output: Error bit map ErrorMap 1. / / Stage one: error bit information collection 2. ErrorLog <- Observe_Error_Bits(D, N) 3. / / Stage two: high-risk error bit analysis 4. ErrorMap <- Analyze_Error_Log(ErrorLog) 5. / / Stage three: error bit map double encoding 6. ErrorMap <- Encode_And_Protect(ErrorMap, D) 7. return ErrorMap The dynamic updating process of the error bit map can be divided into three stages in chronological order: error bit information collection, high-risk error bit analysis, and error bit map double encoding. This process can be executed asynchronously with the help of system background idle resources, without introducing additional startup delay and without interfering with the normal operation of the foreground task.

[0027] Based on this, the application provides a single event upset oriented memory software fault tolerance and fast startup method, which combines Figure 2 may include the following steps: Step 1: In the process of multiple startups of the Flash memory based on startup data blocks, the high-risk bit positions of the startup data blocks and the high-risk bit positions in the startup data blocks are determined, the startup data blocks include an original data area and ECC check bits, and the original data area includes a plurality of bits. In order to construct an accurate and effective error bit map, the Flash memory needs to comprehensively perceive the error bit distribution characteristics in the startup related data in the early stage of operation. By collecting error bit information in the first N startup processes of the Flash memory, the actual error space distribution occurring in the startup stage of the Flash memory can be obtained, which provides key data support for the subsequent identification and mapping relationship establishment of high-risk error bits.

[0028] As shown in Algorithm 2, in the first N startup processes of the Flash memory, the Flash memory uses the traditional error correction code decoding process for correctness verification operation.

[0029] Algorithm 2 Error bit information collection algorithm Input: Set of startup related data blocks D, system startup times N Output: ErrorLog Function: Observe_Error_Bits(D, N) 1. ErrorLog ← ∅ 2. for (i from 1 to N) do 3. for (each blk in D) do 4. / / Check if the current data block is in error 5. if (Decode(blk) == error) then 6. / / Record the specific location information of the error bits 7. err_bits ← Locate(blk) 8. / / Count the error frequency of each error bit 9. for (each bit in err_bits) do 10. ErrorLog[bit.bid][bit.off]+= 1 11. return ErrorLog Algorithm 2 is implemented by the following steps: Step 1.1: Read multiple start data blocks from the memory in turn; Step 1.2: During the multiple start process of the Flash memory, based on the original data area and the ECC check bits, the position of the error bit in the start data block is determined, and the error frequency of the error bit is recorded; Step 1.21: Based on the start data block, the Flash memory is started, and the first start data block is obtained. For the first start data block, the comprehensive vector is calculated according to the original data area and the ECC check bits; Specifically, based on the pre-set encoding scheme, the check matrix H is determined, the original data area and the ECC check bits are spliced according to the pre-defined position to obtain the received code word vector r, and the comprehensive vector s is generated based on the check matrix H and the received code word vector r, which is realized by the following formula: s=H•r T (mod2); Where T represents the transpose; Step 1.2.2: When the comprehensive vector is 0, it indicates that the start-up data block does not have error bits, the next start-up data block is obtained, and the execution is returned: the comprehensive vector is calculated according to the original data area and the ECC check bits; when the comprehensive vector is not 0, it indicates that the start-up data block has error bits, and the error bits in the original data area of the start-up data block are obtained by solving the comprehensive vector using the ECC decoding algorithm; Step 1.2.3: The bits of the error bits are inverted or corrected, the start-up data block number to which the error bits belong and the position in the start-up data block are recorded, and the error number of the error bits is incremented by one, the next start-up data block is obtained, and the execution is returned: the comprehensive vector is calculated according to the original data area and the ECC check bits, and the execution is returned until the last start-up data block; Step 1.2.4: The Flash memory is started multiple times, and the above operations are repeated, that is, steps 1.2.1 to 1.2.3 are repeated multiple times to obtain the position of the error bits in each start-up data block and the error number of the corresponding error bits; Step 1.3: Obtain the error bits with an error number greater than a preset threshold, and take them as high-risk bits of the start-up data block, and then determine the position of the high-risk bits in the start-up data block; Through the above steps, the Flash memory can obtain the accurate position of the high-frequency error bits in each data block based on the actual running conditions of the previous N start-ups, and provide data basis for subsequent construction of the bit error mapping table. The error detection, error positioning and error correction operations are performed on the start-up related data block by block and sequentially. Unlike the conventional decoding process, the Flash memory automatically records the specific position information of each error bit, including the data block index and the bit offset in the block, after completing the error positioning once.

[0030] In the specific implementation process, all the error bit information observed in the previous N start-ups is uniformly collected to form an error bit observation record table, which provides basic data support for subsequent construction of the error bit mapping table, and generates an error log file, as shown in Algorithm 3. The Flash memory first counts the error occurrence frequency of each bit in the entire observation period based on the error log during the start-up, and constructs a bit error frequency distribution graph based thereon to provide data basis for subsequent high-risk error bit analysis.

[0031] Algorithm 3: High-risk error bit analysis algorithm Input: Error bit observation record table ErrorLog Output: Error bit mapping table ErrorMap Function: Analyze_Error_Log(ErrorLog) 1. ErrorMap ← ∅ 2. / / Aggregate statistics of error bit occurrence frequency 3. FreqMap ← Aggregate(ErrorLog) 4. / / Calculate anomaly detection threshold using median absolute deviation method 5. threshold ← MAD(FreqMap) 6. for (each bit in FreqMap) do 7. if (FreqMap[bit]>threshold) then 8. / / Mark high-risk error bit 9. ErrorMap.add(bit) 10. return ErrorMap In one embodiment, when the Flash memory completes the first N boot processes, the error bit information recorded in each boot is subjected to aggregate statistical analysis to identify the high-risk bit error area existing in the memory. The process includes the following steps: Step S201: Collect error logs.

[0032] The Flash memory reads the error log files generated in the first N boot processes, which contain the position data of the error bits detected and corrected in each boot, including the data block number and bit offset.

[0033] Step S202: Construct a bit error count table.

[0034] The Flash memory initializes a bit error count table (ErrorCountTable) in the storage space according to the error bit information obtained in step S201, where each table entry is used to record the number of errors of the corresponding bit in N boots, and the initial value is set to zero.

[0035] Step S203: Count error occurrence frequency.

[0036] The Flash memory traverses all boot log records. For each error bit information, the Flash memory increases the count value of the corresponding table entry in the bit error count table by 1, thereby obtaining the actual error occurrence frequency of the bit in multiple boots.

[0037] Step S204: Generate a frequency distribution graph.

[0038] The flash memory forms an error frequency distribution graph for each bit based on the statistical result obtained in step S203. The distribution graph can be in the form of a one-dimensional array, a two-dimensional matrix, or a graphical histogram, and is used to reflect the cumulative number of errors of different bits.

[0039] Step S205: Identify high-risk bits The flash memory uses a preset threshold to mark the bits with a high error frequency based on the error frequency distribution graph, and divides them into a high-risk bit set for subsequent optimization processes.

[0040] The error bit mapping table and the boot-related data block have essential differences in function and content: the boot-related data block is only responsible for storing actual data required for operating the flash memory, such as kernel images, device trees, and file systems, while the error bit mapping table is composed of several mapping items, each recording the logical redirection relationship of a high-risk error bit, used to assist in locating and correcting potential errors during the flash memory boot phase. If the mapping item in the error bit mapping table is damaged, the flash memory will not be able to accurately identify the position of the high-risk error bit corresponding to the item, directly affecting the subsequent fault tolerance repair process.

[0041] As shown in Algorithm 4, to ensure that the system can efficiently and reliably handle high-risk error bits during the boot process, the system uses a double encoding protection mechanism for the error bit mapping table. First, the system applies a first re-encoding protection to the error bit mapping table itself to ensure its structural integrity and content reliability. The purpose of this re-encoding protection is to prevent the error bit mapping table from losing valid information due to hardware failure or data damage during storage or transmission, thereby ensuring the normal reading and use of the error bit mapping table. The specific content is described in detail in step 2.

[0042] Algorithm 4 Double encoding algorithm for error bit mapping table Input: Error bit mapping table ErrorMap, boot data block set D Output: ErrorMap protected by double encoding Function: Encode_And_Protect(ErrorMap, D) 1. / / First re-encoding protection 2. ErrorMap ← Add_CRC(ErrorMap) 3. ErrorMap ← ECC_Encode(ErrorMap) 4. TempVector ← ∅ 5. for (each bit in ErrorMap) do 6. TempVector.add(D[bit.bid][bit.off]] 7. / / Second encoding protection 8. ProtectedVector ← Add_CRC(TempVector) 9. ProtectedVector ← ECC_Encode(ProtectedVector) 10. ErrorMap.attach(ProtectedVector) 11. return ErrorMap Step 2: According to the high-risk bit positions of the startup data block and the positions of the high-risk bit positions in the startup data block, a mapping table is generated, and the mapping table is encoded to generate an encoded mapping table. Wherein, the mapping table contains a mark of whether each bit is a high-risk bit. Step 2.1: According to the high-risk bit positions of the startup data block and the positions of the high-risk bit positions in the startup data block, mark the startup data block to obtain a mapping table, which contains the startup data block and the mark of each bit in the startup data block. The mark of each bit represents whether the bit is a high-risk bit. Wherein, the mapping table adopts an index table structure, and the initial content is the "original data block" before encoding.

[0043] To ensure that the system can efficiently and reliably handle high-risk error bits in subsequent startup processes, the system first applies first encoding protection to the mapping table to prevent data damage caused by single event upset, power-off risk or memory aging during storage, loading or transmission. Details are described in steps 2.2 to 2.5.

[0044] Step 2.2: According to the mark of the bit, the mapping table is divided into a high-risk data segment and a non-high-risk data segment. Wherein, this segmentation mechanism reduces the influence range of single segment error on the overall mapping table, and the segmentation length can be configured according to the SoC memory width or the ECC decoding unit size.

[0045] Step 2.3: According to a preset encoding scheme such as CRC check code, Hamming code, BCH code or RS code, generate check redundancy information for the high-risk data segment or the non-high-risk data segment. Step 2.4: encapsulating the high-risk data segments and their corresponding check redundancy information, and encapsulating the non-high-risk data segments and their corresponding check redundancy information, to obtain a plurality of encoding segment units, and forming the following structure: [DataSegment_i | CheckBits_i ].

[0046] wherein the Flash memory generates an independent data check boundary for each encoding segment to quickly locate the error segment Step 2.5: writing all the encoding segment units in the order of the positions before the division into the target storage position to obtain an encoding mapping table, generating a version number and a validity flag of the encoding mapping table; wherein a check confirmation mechanism (Write-Verify) is used to prevent errors in the writing process, and a redundant backup writing strategy (such as writing double A / B areas) is provided in this step. The version number is automatically incremented after each re-counting, and the validity flag is used to quickly determine whether the backup mapping table needs to be called in the startup process.

[0047] On this basis, to further cope with the high-risk error bits that may occur in the startup process, the Flash memory introduces a second re-encoding protection, which is specifically aimed at the high-risk error bits in the area pointed to by the mapping table. This re-encoding protection mainly focuses on the anti-interference ability of startup-related data, and uses cyclic redundancy check and error correction code technology to ensure that even if a part of the area is damaged, the Flash memory can still recover or redirect to the correct high-risk error bit position, thereby effectively avoiding the startup failure error caused by the unavailability of error bits.

[0048] Through the above three-stage process and the construction of a layered fault-tolerant encoding strategy, the Flash memory not only obtains the centralized management ability of high-risk error bits, but also provides a robust structural guarantee for startup fault tolerance.

[0049] To improve the correctness verification efficiency of the Flash memory for key data in the startup phase, the present application proposes a check-decoding hierarchical mechanism on the basis of error aggregation mapping. This mechanism introduces a lightweight cyclic redundancy check as a preliminary error screening method, which preferentially uses cyclic redundancy check to quickly detect whether there is potential error in the data block. Only in the case of cyclic redundancy check failure, the high-cost error correction code decoding process is triggered. By introducing the check-decoding hierarchical mechanism, the Flash memory can significantly reduce the redundant decoding operation of error-free data blocks, thereby effectively reducing the average cost of correctness verification of startup-related data.

[0050] The "check-decoding hierarchical mechanism" provided by the application is essentially a multi-level error screening architecture for key data verification in the starting stage. The core idea is to split the data integrity check into a 'quick check layer' and a 'high-cost decoding layer' two stages, and decide whether to enter the decoding stage according to the check result. This mechanism significantly reduces the number of unnecessary ECC decoding, and ultimately shortens the starting time of the Flash memory.

[0051] To ensure the availability of the error bit mapping table in the system startup stage, the system performs cyclic redundancy check on the above two areas respectively to quickly determine whether the structure and content are damaged. Only when both cyclic redundancy checks pass, the system determines that the error bit mapping table is in a reliable state as a whole, and in this case, the subsequent high-cost error correction process will be skipped, and the hierarchical check stage of the startup data block will be directly entered to complete the integrity confirmation of the subsequent key data. On the contrary, if any cyclic redundancy check fails, the system will immediately enable high-strength error correction code (such as BCH code or RS code) to accurately decode and repair the corresponding area to restore its original state and readability. This design not only ensures that the error bit mapping table as the data basis for fault tolerance has sufficient robustness, but also maximizes the reduction of unnecessary redundant decoding operations through pre-checking, thereby effectively improving the processing efficiency and fault tolerance capability of the system in the startup stage. Details are explained in step 3.

[0052] Step 3: Obtain a plurality of startup data blocks of the Flash memory, determine the target startup data block based on the encoding mapping table, and then obtain all target startup data blocks, and start the Flash memory based on all target startup data blocks; Among them, based on the encoding mapping table, the target startup data block is generated, including: The startup data block is subjected to CRC check to obtain a check result. In the case that the check result matches the check redundancy information in the encoding mapping table, the startup data block is taken as the target startup data block. In the case that the check result does not match the check redundancy information in the encoding mapping table, the startup data block is subjected to ECC decoding (BCH, Hamming code, Reed-Solomon, LDPC). Based on the encoding mapping table, the target startup data block is determined. Specifically, the startup data block is parsed, the high-risk bit in the startup data block is determined according to the encoding mapping table, and the high-risk bit is flipped or reconstructed to obtain the target startup data block. This phase continues the hierarchical verification strategy proposed previously, first using cyclic redundancy check for error detection of data blocks; only when the cyclic redundancy check fails, the Flash memory starts the error correction code decoding process of the corresponding data block. Since the high-risk error bits in the relevant data have been concentrated in the error bit mapping table through the error aggregation mapping mechanism, the probability of error in the relevant data block is significantly reduced, thereby improving the fault tolerance efficiency of the Flash memory startup process as a whole.

[0053] It is worth noting that when a certain data block fails the cyclic redundancy check and starts the error correction decoding process, the Flash memory records the data block index and bit offset of the error bit. At the end of each statistical period, the Flash memory analyzes the error bit information and dynamically updates the mapping content of the error bit mapping table, thereby gradually optimizing the error space distribution model.

[0054] The present application aims at the problem of single event upset fault tolerance and fast startup of Flash memory in space radiation environment, and proposes an innovative solution, the key technical points of which are reflected in the following aspects: 1. Dynamic mapping mechanism based on error space locality. In view of the low efficiency problem caused by the uniform processing of error bits by traditional fault tolerance technology, the present application first discovers and utilizes the distribution characteristics of single event upset error in Flash memory, i.e. "macroscopic dispersion, microscopic aggregation" (experiments show that 85% of errors are concentrated in 15% of storage areas), and designs a dynamic error bit mapping table. This mechanism accurately identifies high-frequency error bits through the median absolute deviation (MAD) algorithm, and compared with the traditional mean method, the accuracy of anomaly detection is improved by 32%, thus fundamentally solving the problem of unreasonable allocation of fault tolerance resources.

[0055] 2. Hierarchical verification-decoding architecture. In view of the performance bottleneck caused by the full-amount decoding of traditional ECC technology, the present application innovatively divides the processing flow into three levels: CRC32 fast verification layer, error bit mapping verification layer, and ECC accurate decoding layer.

[0056] The present application verifies through experiments that the fault tolerance and fast startup scheme proposed has significant advantages compared with traditional technology, and the specific effects are as follows: 1. Breakthrough improvement in system startup performance. On the space radiation environment simulation test platform, we conducted comparative tests on startup data of different scales. When processing 300MB of typical startup data, the traditional BCH decoding scheme takes a fixed time of 1.2 seconds due to the need to perform a full decoding process; while the scheme of this invention, through an innovative layered processing mechanism, takes an average time of only 200ms. It is particularly noteworthy that the performance improvement is more significant in small data scenarios: when processing 10MB of startup data, the time taken is reduced from 120ms in the traditional scheme to 20ms, an improvement of up to 83.3%. This performance improvement is mainly due to: (1) CRC32 fast check filtering of 95.7% of error-free data blocks; (2) the error bit mapping table realizes the accurate location of high-risk areas; (3) only 4.3% of data blocks that actually have errors are subjected to full ECC decoding.

[0057] 2. Comprehensive optimization of processing efficiency. The intelligent hierarchical architecture of this invention enables an overall processing throughput of 800MB / s, which is 5 times that of the traditional solution (160MB / s). Test data shows that the system can maintain stable processing efficiency under continuous radiation conditions: (1) The CRC check stage uses SIMD instructions for acceleration, and can process 32 bytes of data in a single cycle; (2) The ECC decoding engine supports 8-way parallel computing; (3) The 4KB dedicated error mapping cache enables the high-frequency access hit rate to reach more than 85%. These optimizations enable the system to achieve a qualitative leap in processing efficiency while ensuring error correction capability (8bit / 512B).

[0058] 3. Excellent environmental adaptability. By simulating test environments with different radiation intensities, the present invention demonstrates excellent adaptability: (1) In terms of data size, the performance fluctuation is less than 5% in the range of 10MB-500MB, and the processing time increases linearly with the amount of data; 4. Significant improvement in resource utilization efficiency. In terms of storage resource usage, the present invention shows significant advantages: (1) The error bit mapping table adopts a compressed storage structure, which occupies only 0.1% of the storage space. (2) It saves 15% of storage space compared with the traditional full ECC scheme.

[0059] These effects enable consumer-grade SoCs to achieve aerospace-grade chip reliability levels in space radiation environments while maintaining their cost and performance advantages, providing reliable technical support for low-cost spacecraft design. Experimental data fully validate the significant improvements in performance, reliability, and energy efficiency achieved by this invention.

[0060] The above description is merely that of the preferred embodiments of the present disclosure and a description of the technical principles of the present disclosure. It should be understood by those skilled in the art that the inventive scope of the embodiments of the present disclosure is not limited to the technical solutions formed by the specific combinations of the above technical features, and should also cover other technical solutions formed by the combinations of the above technical features or equivalent features without departing from the above inventive concept. For example, the technical solutions formed by the mutual replacement of the above features and the technical features with similar functions disclosed in the embodiments of the present disclosure (but not limited to) form the technical solutions.

Claims

1. A memory software fault tolerance and fast startup method for single-event flips, characterized in that, include: During the multiple boots of the Flash memory based on the boot data block, the high-risk bits of the boot data block and their positions within the boot data block are determined. The boot data block includes a raw data area and an ECC check bit. The raw data area includes multiple bits. Based on the high-risk bits of the startup data block and their positions within the startup data block, a mapping table is generated, and the mapping table is encoded to generate an encoded mapping table. The mapping table contains a marker indicating whether each bit is a high-risk bit; Multiple boot data blocks of the Flash memory are obtained. Based on the encoding mapping table, the target boot data block is determined, and then all target boot data blocks are obtained. The Flash memory is then started based on all target boot data blocks.

2. The memory software fault tolerance and fast startup method for single-event flips according to claim 1, characterized in that, During multiple boot processes based on the boot data block in the Flash memory, the high-risk bits of the boot data block and their positions within the boot data block are determined, including: Multiple startup data blocks are read sequentially from memory; During multiple boot processes of the Flash memory, the location of the error bit in the boot data block is determined based on the original data area and ECC check bits, and the number of errors of the error bit is recorded. The error bits with more than a preset threshold are identified and used as high-risk bits in the startup data block, thereby determining the position of the high-risk bits in the startup data block.

3. The memory software fault tolerance and fast startup method for single-event flips according to claim 2, characterized in that, During multiple boot processes of the Flash memory, based on the original data area and ECC check bits, the error bits in the boot data block are determined, and the number of errors in the error bits is recorded, including: The Flash memory is started based on the boot data block. The first boot data block is obtained. For the first boot data block, the synthesis vector is calculated based on the original data area and ECC check bits. When the composite vector is 0, it indicates that there are no error bits in the startup data block. Obtain the next startup data block and return to execution: calculate the composite vector based on the original data area and ECC check bits; when the composite vector is not 0, it indicates that there are error bits in the startup data block. Use the ECC decoding algorithm to solve the composite vector to obtain the error bits in the original data area of ​​the startup data block. Reverse or correct the bit of the erroneous bit, record the start data block number to which the erroneous bit belongs and its position in the start data block, increment the error count of the erroneous bit by one, obtain the next start data block, and return to execution: calculate the synthesis vector based on the original data area and ECC check bits, until the last start data block; By repeatedly starting the Flash memory and repeating the above operation, the position of the error bit in each startup data block and the number of errors corresponding to that error bit can be obtained.

4. The memory software fault tolerance and fast startup method for single-event flips according to claim 3, characterized in that, Based on the original data area and ECC check bits, calculate the composite vector, including: Based on the pre-set encoding scheme, the parity check matrix H is determined. The original data area and the ECC parity bits are concatenated according to predefined positions to obtain the received codeword vector r. Based on the parity check matrix H and the received codeword vector r, the comprehensive vector s is generated, which is specifically achieved through the following formula: s=H•r T (mod2); Where T represents transpose.

5. The memory software fault tolerance and fast startup method for single-event flips according to claim 1, characterized in that, Based on the high-risk bits of the startup data block and their positions within the startup data block, a mapping table is generated. This mapping table is then encoded to generate an encoded mapping table, including: Based on the high-risk bits of the startup data block and their positions within the startup data block, the startup data block is marked to obtain a mapping table. The mapping table contains the startup data block and the markings of each bit in the startup data block. The markings of each bit indicate whether the bit is a high-risk bit. Based on the bit markings, the mapping table is divided into high-risk data segments and non-high-risk data segments; For high-risk or non-high-risk data segments, verification redundancy information is generated according to the preset encoding scheme; High-risk data segments and their corresponding check redundancy information are encapsulated, while non-high-risk data segments and their corresponding check redundancy information are also encapsulated to obtain multiple coding segment units. Write all coded segment units into the target storage location in the order of their positions before partitioning to obtain the encoding mapping table, and generate the version number and validity flag of the encoding mapping table.

6. The memory software fault tolerance and fast startup method for single-event flips according to claim 1, characterized in that, Based on the encoding mapping table, the target startup data block is determined, including: Perform CRC check on the startup data block to obtain the check result. If the check result matches the check redundancy information in the encoding mapping table, the startup data block is taken as the target startup data block. If the check result does not match the check redundancy information in the encoding mapping table, perform ECC decoding on the startup data block and determine the target startup data block based on the encoding mapping table.

7. The memory software fault tolerance and fast startup method for single-event flips according to claim 6, characterized in that, The boot data block is ECC decoded, and the target boot data block is determined based on the encoding mapping table, including: The startup data block is parsed, and the high-risk bits in the startup data block are identified according to the encoding mapping table. The high-risk bits are then flipped or reconstructed to obtain the target startup data block.

Images