Verification test method for M-PHY layer of UFS

Abstract

The invention discloses a verification test method for an M-PHY layer of a UFS. The verification test method comprises the following steps: step 1) setting up a test environment; configuring a multi-rate adaptive test engine; configuring an inter-channel interference simulation system; configuring a protocol perception type state machine verifier; the verification test method for testing the M-PHY layer of the UFS comprises the steps of (1) carrying out an M-PHY layer, (2) carrying out a multi-rate adaptive test, (3) carrying out an inter-channel interference simulation test, and (4) carrying out protocol perception type state machine verifier.The verification test method for testing the M-PHY layer of the UFS can verify the data integrity and reliability of UFS equipment on the M-PHY layer.

Description

Technical Field

[0001] This invention relates to semiconductor memory technology, and more particularly to a verification and testing method for the M-PHY layer of a UFS (Unstable Memory System). Background Technology

[0002] With the increasing demands for storage performance from mobile terminals and IoT devices, UFS, as a mainstream high-speed storage protocol, relies heavily on its M-PHY layer, which serves as the physical layer interface for UFS (Universal Flash Storage) devices. Based on the MIPI Alliance's M-PHY specification, it is the underlying hardware interface in the UFS protocol stack that connects the host (SoC) to the UFS device, responsible for achieving high-speed, low-power serial data transmission. The transmission efficiency and power consumption control of the M-PHY layer have become key technical bottlenecks. As the core of the UFS protocol stack, the M-PHY is responsible for modulation and demodulation of electrical signals, clock synchronization, noise suppression, and physical link management, directly impacting the read / write speed, stability, and energy consumption of the entire storage system.

[0003] Existing M-PHY verification schemes have three major bottlenecks: 1. Rate switching blind spot Traditional BERT (Bit Error Rate Tester) only supports fixed-rate testing (such as HS-G3 23.2Gbps) and cannot dynamically simulate clock drift during the PWM→HS mode switching process (typical problem: CDR loss of lockout leads to 10...). -6 (Error rate surges) 2. Channel coupling interference missing Existing solutions independently test single channels (such as TX / RX differential pairs), ignoring crosstalk issues when dual or multiple channels are in parallel (e.g., when a 2-channel HS-G4 is working, crosstalk between adjacent channels can reach -18dB). 3. Insufficient state machine coverage Commercial protocol analyzers (such as the Keysight U4131A) only monitor protocols above the link layer and lack the ability to capture nanosecond-level timing of power state switching such as HIBERN8→STALL→HS-BURST in M-PHY. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a verification and testing method for the M-PHY layer of UFS, which addresses the deficiencies in the prior art.

[0005] The technical solution adopted by this invention to solve its technical problem is: a verification and testing method for the M-PHY layer of UFS, comprising the following steps: Step 1) Set up the test environment; Configure a multi-rate adaptive test engine, which is used to generate high-speed differential signals, low-speed signals and control signals required by the M-PHY layer; the piecewise linear clock generator provides the test engine with multi-rate, high-precision and dynamically adjustable clock signals through a piecewise linear frequency modulation and clock generation mechanism. Configure an inter-channel interference simulation system to simulate crosstalk interference between multiple channels of UFS device through a programmable impedance network, and realize crosstalk coupling between adjacent channels; Configure a protocol-aware state machine verifier. The protocol-aware state machine verifier is used to monitor the transition process of the M-PHY layer state machine in real time, verify whether the state transitions conform to the protocol specifications, and record abnormal state transitions and triggering conditions. Step 2) Perform multi-rate adaptive testing; 2.1) In the M-PHY layer test, the dynamic rate switching model is invoked to make the physical layer transmission rate of the UFS device switch sequentially from PWM low-speed mode to HS-G1, and then to HS-G4; 2.2) Inject CRC errors into the Lane Alignment field; set the clock jitter range to ±100ppm; 2.3) Configure the UFS device to output a normal high-level signal at the M-TX and M-RX transmitter ends of the physical layer module M-PHY, and use a piecewise linear clock generator to divide the signal into N segments of sequentially increasing level signals; at the M-TX receiver end and M-RX transmitter end of the M-PHY, the normal low-level signal is divided into N segments of sequentially decreasing level signals using a piecewise linear clock generator; 2.4) Monitor UFS device output: 2.5) Analyze BER and time series data: Step 3) Conduct inter-channel interference simulation tests; 3.1) Based on the interference strength, set the coupling coefficient K and the signal swing V. swing Injecting crosstalk interference into adjacent channels; 3.2) When the M-PHY rate f rate During switching, the impedance network automatically updates the K value and synchronously adjusts the interference intensity to obtain the configured values ​​of K value and interference intensity; the tested M-PHY speed covers the entire speed range from PWM low-speed mode to high-speed mode; 3.3) After completing the configuration, start the interference injection process to ensure that the interference signal is superimposed on the adjacent channel of the UUT and synchronized with the rate switching and bit error injection test actions; 3.4) After injecting interference, it is necessary to verify whether the interference intensity meets the target value. Calculate the interference intensity at different rates and different K values ​​according to the formula. If the collected interference intensity does not meet the target value, the impedance of the coupling network is reconfigured through the feedback adjustment mechanism until the preset K value and interference intensity are reached. 3.5) Observe the correlation between the degree of eye diagram closure and the data transmission error rate; Step 4) Verification of the protocol-aware state machine; 4.1) Cover 27 M-PHY state transition paths using a state transition sequence generator; 4.2) Dynamically generate TDM test sequences based on UniPro scheduling logic; 4.3) In the multi-dimensional damage joint injection mode, power supply noise, channel crosstalk and clock jitter are applied simultaneously; signal events are injected into the M-PHY layer to prepare for triggering the cross-layer mechanism; 4.4) Use the 1.25ps timing violation capture window comparator to monitor state switching timing. If it exceeds the compliance range, trigger power supply noise spectrum recording to locate the root cause of timing violation. 4.5) Comparison of pre- and post-silicon data; Run the test sequence to collect pre-Silicon simulated eye diagrams and post-Silicon measured data. Apply the channel impairment prediction model to compare the differences in eye diagram closure and bit error rate.

[0006] According to the above scheme, in step 2.4), monitoring the output of the UFS device is specifically as follows: Use a high-precision oscilloscope to capture the signal eye diagram and record the bit error rate (BER). Check whether the firmware triggers the error handling mechanism when a certain segment of the level increment sequence is missing; At the same time, measure whether the CDR recovery time exceeds the standard.

[0007] According to the above scheme, in step 2.5), the BER and time series data are analyzed as follows: If BER > 10 - ¹² or CDR recovery time > 1μs, performance verification is deemed a failure; Generate a report, including the degree of eye diagram degradation and firmware processing efficiency.

[0008] According to the above scheme, in step 3.1), the interference intensity P = K * (f rate / f max )² * V swing ; Among them, f rate For the current M-PHY rate being tested, f maxThe maximum rate supported by the M-PHY layer.

[0009] According to the above scheme, in step 3.5), the S-parameter deconvolution algorithm is used to accelerate the eye diagram degradation test.

[0010] According to the above scheme, in step 4.2), the TDM test sequence is dynamically generated as follows: 4.2.1) First, define 27 triggering conditions and execution actions for state transitions using a state transition sequence generator; 4.2.2) Dynamically generate TDM test sequences based on UniPro scheduling logic.

[0011] According to the above scheme, step 4.2.2) is specifically as follows: 4.2.2.1) Parse UniPro TDM time slot rules; Determine the basic parameters of the TDM frame: Configure frame duration and number of time slots per frame; classify the service type for each time slot; define the service priority of time slots: Command stream > Response stream > Data stream > Idle time slot; 4.2.2.2) Map Command / Data / Response flows to the corresponding service priority levels, and allocate each time slot to the service flow of the specified priority, ensuring that the time slot allocation conforms to the priority rules of UniPro scheduling; 4.2.2.3) Map 27 M-PHY state transition paths to TDM time slots; To cover 27 paths, state switching instructions will be dynamically inserted into the service gaps of the TDM time slots. 4.2.2.4) Generate the final dynamic TDM test sequence: The final test sequence is a combination of TDM time slot service data and M-PHY state switching instructions; the service data transmission and state switching instructions are combined in time slot order.

[0012] According to the above scheme, in step 4.2.2.3), the state switching command is dynamically inserted into the service gap of the TDM time slot; specifically as follows: Embed state paths by scenario category: Normal path: Trigger regular state switching in low-load time slots to verify the compatibility of state switching during service transmission; Abnormal Path: Triggering abnormal switching in high-load time slots to verify UniPro scheduling's fault tolerance to physical layer anomalies; Achieve full path coverage and deduplication: Traverse the 27 M-PHY state transition paths to ensure that at least one uncovered path is triggered in each round of TDM test frames, until all 27 paths are triggered without repetition.

[0013] According to the above scheme, step 4.2.2.4) also includes a dynamic adjustment strategy; based on UniPro scheduling logic, the test sequence is dynamically adjusted in real time, and its dynamic adaptation logic includes: 1) Service congestion adaptation: If UniPro detects that the service queue in a certain time slot is full, it delays the M-PHY state switching instruction for that time slot to avoid conflicts between service transmission and state switching; 2) Adaptation for state transition failure: If the M-PHY state transition check fails, UniPro retransmission or speed reduction logic is triggered, and the failure path and scenario are recorded.

[0014] 3) Priority adaptation: High-priority time slots are prohibited from triggering abnormal state transitions, and abnormal path tests are only performed in low-priority time slots.

[0015] The beneficial effects of this invention are: 1. This invention decomposes a single high-level or low-level signal into multiple (N) segments of sequentially increasing or decreasing level signal sequences. This segmentation method can more precisely simulate the gradual distortion (such as slow voltage drift) that the signal may encounter during transmission, thereby more thoroughly testing the UFS firmware algorithm's ability to identify, tolerate, and correct abnormal signals at the physical layer, and discover potential design boundary defects. 2. A formula for calculating crosstalk intensity based on coupling coefficient K and signal swing is proposed to achieve precise adjustment of interference intensity and solve the problem of ambiguous interference intensity in traditional crosstalk testing. 3. Based on UniPro scheduling logic, TDM test sequences are dynamically generated to solve the problem that traditional random test vectors cannot cover the boundary scenarios of Time Division Multiplexing (TDM) and improve test coverage. Attached Figure Description

[0016] The present invention will be further described below with reference to the accompanying drawings and embodiments. In the accompanying drawings: Figure 1 This is a flowchart of a method according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the level signal segmentation in an embodiment of the present invention. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0018] like Figure 1 As shown, a verification test method for the M-PHY layer of UFS includes the following steps: Step 1) Set up the test environment; Configure a multi-rate adaptive test engine and a piecewise linear clock generator; the multi-rate adaptive test engine is used to generate the high-speed differential signals (HS-Gear1 / 2 / 3 / 4), low-speed signals (LS), and control signals (such as Enable and Reset) required by the M-PHY layer. Configure an inter-channel interference simulation system to simulate crosstalk interference between multiple channels (such as Lane0 / Lane1 / Lane2 / Lane3) of a UFS device through a programmable impedance network, thereby achieving crosstalk coupling between adjacent channels; Configure a protocol-aware state machine verifier. The protocol-aware state machine verifier is used to monitor the transition process of the M-PHY layer state machine (such as Reset, Low Power, HS Active, Rate Switch) in real time, verify whether the state transition conforms to the protocol specification, and record abnormal state transitions and triggering conditions. After configuration, initialize and set key parameters: clock jitter range (±100ppm), crosstalk coupling coefficient K (0.1~0.6), signal swing V_swing (300±10% mV), state switching compliance timing (T (ACTIVATE)≤3UI, T(HIBERN8_EXIT)≤10UI), and multi-dimensional impairment parameters (power supply noise ±5% Vcc, channel crosstalk -20dB, clock jitter 0.3UI). Step 2) Perform multi-rate adaptive testing; 2.1) In the M-PHY layer test, the dynamic rate switching model is called and the rate_switch_test() function is executed to make the physical layer transmission rate of the UFS device switch sequentially from PWM low speed mode to HS-G1 (high speed level 1) and then to HS-G4 (high speed level 4). 2.2) Inject CRC errors into the Lane Alignment field; set the clock jitter range to ±100ppm; 2.3) Configure the UFS device to output a normal high-level signal (e.g., 3.3V) at the M-TX and M-RX transmitter ends of the physical layer module M-PHY. Use a piecewise linear clock generator to divide the signal into N sequentially increasing level signals (gradually increasing from 0.5V to 3.3V; multiple signals can be N level signals with equal or unequal intervals); at the M-TX receiver end and M-RX transmitter end of the M-PHY, use a piecewise linear clock generator to divide the normal low-level signal into N sequentially decreasing level signals; for example... Figure 2 ; 2.4) Monitor UFS device output: Use a high-precision oscilloscope to capture the signal eye diagram and record the bit error rate (BER); Check whether the firmware triggers an error handling mechanism (such as retransmission or state reset) when a certain segment of the level increment sequence is missing. At the same time, measure whether the CDR recovery time exceeds the standard (target ≤10ns). 2.5) Analyze BER and time series data: If BER > 10 - ¹² or CDR recovery time > 1μs, is considered a failure. A report is generated, including the degree of eye diagram degradation and firmware processing efficiency (e.g., error identification delay). Step 3) Conduct inter-channel interference simulation tests; 3.1) Based on interference intensity P = K * (f rate / f max )² * V swing ; Set the coupling coefficient K and the signal swing V swing Injecting crosstalk interference into adjacent channels; Among them, f rate For the current M-PHY rate being tested, f max The maximum rate supported by the M-PHY layer; 3.2) When the M-PHY rate f rate During switching, the impedance network automatically updates the K value and adjusts the interference intensity synchronously; the tested M-PHY rate covers the full rate range of PWM (3-9MHz) → HS-G1 → HS-G4; 3.3) After completing the parameter configuration, start the interference injection process to ensure that the interference signal is superimposed on the adjacent channel of the UUT and synchronized with the rate switching and bit error injection test actions; 3.4) After injecting interference, it is necessary to verify whether the interference intensity meets the target value. Calculate the interference intensity at different rates and different K values ​​according to the formula. If the collected interference intensity does not meet the target value, the impedance of the coupling network is reconfigured through the feedback adjustment mechanism until the preset K value and interference intensity are reached. 3.5) The S-parameter deconvolution algorithm was used to accelerate the eye diagram degradation test (100 hours of aging effect compressed to 5 minutes), and the correlation between the degree of eye diagram closure and the data transmission error rate was observed. Step 4) Verification of the protocol-aware state machine; 4.1) Cover 27 M-PHY state transition paths using a state transition sequence generator; 4.2) Dynamically generate TDM test sequences based on UniPro scheduling logic; 4.2.1) Generate the basic sequence of 27 state transition paths for M-PHY; First, define 27 state transition trigger conditions and execution actions using a state transition sequence generator; 4.2.2) Dynamically generate TDM test sequences based on UniPro scheduling logic; 4.2.2.1) Parse UniPro TDM time slot rules; Determine the basic parameters of the TDM frame: Configure frame duration (e.g., 1ms), number of time slots per frame (e.g., 8 time slots / frame); classify the service type of each time slot (e.g., Slot1=Command stream, Slot2-Slot6=Data stream, Slot7=Response stream, Slot8=Idle); define the service priority of time slots (Command stream > Response stream > Data stream > Idle time slot).

[0019] 4.2.2.2) Map Command / Data / Response flows to the corresponding service priority levels, and allocate each time slot to the service flow of the specified priority, ensuring that the time slot allocation conforms to the priority rules of UniPro scheduling; 4.2.2.3) Map 27 M-PHY state transition paths to TDM time slots; To cover 27 paths, state switching instructions will be dynamically inserted into the service gaps of the TDM time slots. Embed state paths by scenario category: Normal path: Trigger regular state switching (e.g., Idle→HS-G3, HS-G3→Idle) in low-load time slots (e.g., Slot8 idle time slot) to verify the compatibility of state switching during service transmission; Abnormal Path: Trigger abnormal switching (such as HS-G2→Reset, Sleep→Forced HS-G1) in high-load time slots (such as Slot2-Slot6 in Data Streaming) to verify UniPro scheduling's fault tolerance to physical layer anomalies.

[0020] Achieve full path coverage and deduplication: The algorithm iterates through 27 M-PHY state transition paths to ensure that at least one uncovered path is triggered in each round of TDM test frames, until all 27 paths are triggered; 4.2.2.4) Generate the final dynamic TDM test sequence: The final test sequence is a combination of TDM time slot service data and M-PHY state switching instructions; Combine service data transmission and status switching instructions in time slot order. Example format: TDM Frame 1: Slot 1: Send Command stream (QoS=high) → Trigger M-PHY path 1 (Idle→HS-G1) Slot 2-Slot 6: Send Data Stream (1GB Data) → M-PHY Holds HS-G1 Slot 7: Receive Response stream → Trigger M-PHY path 2 (HS-G1 → HS-G2) Slot 8: Idle → Trigger M-PHY path 3 (HS-G2 → Sleep) TDM Frame 2: Slot 1: Send Command stream → Trigger M-PHY path 4 (Sleep → Deep Sleep) ... (Loop until all 27 paths are triggered) Based on UniPro scheduling logic, the test sequence is dynamically adjusted in real time. The dynamic adaptation logic includes: 1) Service congestion adaptation: If UniPro detects that the service queue in a certain time slot is full (such as data stream congestion), it delays the M-PHY state switching instruction for that time slot to avoid conflicts between service transmission and state switching.

[0021] 2) Adaptation for state transition failure: If the M-PHY state transition check fails (e.g., HS-G2→Reset execution fails), UniPro retransmission / slowdown logic is triggered (e.g., Data stream is slowed down to HS-G1), and the failure path and scenario are recorded.

[0022] 3) Priority adaptation: High-priority time slots (such as Slot 1 where the Command stream is located) are prohibited from triggering abnormal state switching, and abnormal path tests are only performed in low-priority time slots.

[0023] 4.3) In the multi-dimensional damage co-injection mode, power supply noise (±5% Vcc), channel crosstalk (-20dB), and clock jitter (0.3UI) are applied simultaneously. Signal events (such as CDR lockout) are injected into the M-PHY layer to prepare for triggering the cross-layer mechanism; 4.4) Use the 1.25ps timing violation capture window comparator to monitor state switching timing. If it exceeds the compliance range, trigger power supply noise spectrum recording to locate the root cause of timing violation. 4.5) Comparison of pre- and post-silicon data; Run the test sequence to collect pre-Silicon simulated eye diagrams and post-Silicon measured data. Apply the channel impairment prediction model to compare the differences in eye diagram closure and bit error rate.

[0024] It should be understood that those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A verification and testing method for the M-PHY layer of UFS, characterized in that, Includes the following steps: Step 1) Set up the test environment; Configure a multi-rate adaptive test engine, which is used to generate the high-speed differential signal, low-speed signal and control signal required by the M-PHY layer; The piecewise linear clock generator provides the test engine with multi-rate, high-precision, and dynamically adjustable clock signals through a piecewise linear frequency modulation and clock generation mechanism. Configure an inter-channel interference simulation system to simulate crosstalk interference between multiple channels of UFS device through a programmable impedance network, and realize crosstalk coupling between adjacent channels; Configure a protocol-aware state machine verifier. The protocol-aware state machine verifier is used to monitor the transition process of the M-PHY layer state machine in real time, verify whether the state transitions conform to the protocol specifications, and record abnormal state transitions and triggering conditions. Step 2) Perform multi-rate adaptive testing; 2.1) In the M-PHY layer test, the dynamic rate switching model is invoked to make the physical layer transmission rate of the UFS device switch sequentially from PWM low-speed mode to HS-G1, and then to HS-G4; 2.2) Inject CRC errors into the Lane Alignment field; set the clock jitter range to ±100ppm; 2.3) Configure the UFS device to output a normal high-level signal at the M-TX and M-RX transmitter ends of the physical layer module M-PHY, and use a piecewise linear clock generator to divide the signal into N segments of sequentially increasing level signals; at the M-TX receiver end and M-RX transmitter end of the M-PHY, the normal low-level signal is divided into N segments of sequentially decreasing level signals using a piecewise linear clock generator; 2.4) Monitor UFS device output: 2.5) Analyze BER and time series data: Step 3) Conduct inter-channel interference simulation tests; 3.1) Based on the interference strength, set the coupling coefficient K and the signal swing V. swing Injecting crosstalk interference into adjacent channels; 3.2) When the M-PHY rate f rate During switching, the impedance network automatically updates the K value and synchronously adjusts the interference intensity to obtain the configured values ​​of K value and interference intensity; the tested M-PHY speed covers the entire speed range from PWM low-speed mode to high-speed mode; 3.3) After completing the configuration, start the interference injection process to ensure that the interference signal is superimposed on the adjacent channel of the UUT and synchronized with the rate switching and bit error injection test actions; 3.4) After injecting interference, it is necessary to verify whether the interference intensity meets the target value. Calculate the interference intensity at different rates and different K values ​​according to the formula. If the collected interference intensity does not meet the target value, the impedance of the coupling network is reconfigured through the feedback adjustment mechanism until the preset K value and interference intensity are reached. 3.5) Observe the correlation between the degree of eye diagram closure and the data transmission error rate; Step 4) Verification of the protocol-aware state machine; 4.1) Cover 27 M-PHY state transition paths using a state transition sequence generator; 4.2) Dynamically generate TDM test sequences based on UniPro scheduling logic; 4.3) In the multi-dimensional damage joint injection mode, power supply noise, channel crosstalk and clock jitter are applied simultaneously; signal events are injected into the M-PHY layer to prepare for triggering the cross-layer mechanism; 4.4) Use the 1.25ps timing violation capture window comparator to monitor state switching timing. If it exceeds the compliance range, trigger power supply noise spectrum recording to locate the root cause of timing violation. 4.5) Comparison of pre- and post-silicon data; Run the test sequence to collect pre-Silicon simulated eye diagrams and post-Silicon measured data. Apply the channel impairment prediction model to compare the differences in eye diagram closure and bit error rate.

2. The verification and testing method for the M-PHY layer of UFS according to claim 1, characterized in that, In step 2.4), the output of the UFS device is monitored, specifically as follows: Use a high-precision oscilloscope to capture the signal eye diagram and record the bit error rate (BER). Check whether the firmware triggers the error handling mechanism when a certain segment of the level increment sequence is missing; At the same time, measure whether the CDR recovery time exceeds the standard.

3. The verification and testing method for the M-PHY layer of UFS according to claim 1, characterized in that, In step 2.5), the BER and time series data are analyzed, as follows: If BER > 10 - ¹² or CDR recovery time > 1μs, performance verification is deemed a failure; Generate a report, including the degree of eye diagram degradation and firmware processing efficiency.

4. The verification and testing method for the M-PHY layer of UFS according to claim 1, characterized in that, In step 3.1), the interference intensity P = K * (f rate / f max )² * V swing ; Among them, f rate For the current M-PHY rate being tested, f max The maximum rate supported by the M-PHY layer.

5. The verification and testing method for the M-PHY layer of UFS according to claim 1, characterized in that, In step 4.2), the TDM test sequence is dynamically generated, as follows: 4.2.1) First, define 27 triggering conditions and execution actions for state transitions using a state transition sequence generator; 4.2.2) Dynamically generate TDM test sequences based on UniPro scheduling logic.

6. The verification and testing method for the M-PHY layer of UFS according to claim 5, characterized in that, In step 4.2.2), the specific details are as follows: 4.2.2.1) Parse UniPro TDM time slot rules; Determine the basic parameters of the TDM frame: Configure frame duration and number of time slots per frame; classify the service type for each time slot; define the service priority of time slots: Command stream > Response stream > Data stream > Idle time slot; 4.2.2.2) Map Command / Data / Response flows to the corresponding service priority levels, and allocate each time slot to the service flow of the specified priority, ensuring that the time slot allocation conforms to the priority rules of UniPro scheduling; 4.2.2.3) Map 27 M-PHY state transition paths to TDM time slots; To cover 27 paths, state switching instructions will be dynamically inserted into the service gaps of the TDM time slots. 4.2.2.4) Generate the final dynamic TDM test sequence: The final test sequence is a combination of TDM time slot service data and M-PHY state switching instructions; the service data transmission and state switching instructions are combined in time slot order.

7. The verification and testing method for the M-PHY layer of UFS according to claim 6, characterized in that, In step 4.2.2.3), the state switching command is dynamically inserted into the service gap of the TDM time slot; specifically as follows: Embed state paths by scenario category: Normal path: Trigger a regular state switch in a low-load time slot to verify the compatibility of state switching during service transmission; Abnormal Path: Triggering abnormal switching in high-load time slots to verify UniPro scheduling's fault tolerance to physical layer anomalies; Achieve full path coverage and deduplication: Traverse the 27 M-PHY state transition paths to ensure that at least one uncovered path is triggered in each round of TDM test frames, until all 27 paths are triggered without repetition.

8. The verification and testing method for the M-PHY layer of UFS according to claim 6, characterized in that, Step 4.2.2.4 also includes a dynamic adjustment strategy; based on UniPro scheduling logic, the test sequence is dynamically adjusted in real time, and its dynamic adaptation logic includes: 1) Service congestion adaptation: If UniPro detects that the service queue in a certain time slot is full, it delays the M-PHY state switching instruction for that time slot to avoid conflicts between service transmission and state switching; 2) Adaptation for state transition failure: If the M-PHY state transition check fails, UniPro retransmission or speed reduction logic is triggered, and the failure path and scenario are recorded. 3) Priority adaptation: High-priority time slots are prohibited from triggering abnormal state transitions, and abnormal path tests are only performed in low-priority time slots.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method described in any one of claims 1 to 8.

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