Particle protection inspection

Abstract

An apparatus includes a particle protection inspection circuit to: obtain particle protection information associated with a target particle of a physical address including the target physical address; and determining whether a selected physical address space associated with the target physical address is allowed to access a target particle of the physical address based on the particle protection information. The apparatus includes a prefetch circuit configured to initiate a prefetch operation for a target physical address such that target data identified by the target physical address can be prefetched into the cache before the particle protection check circuit determines whether the selected physical address space is allowed to access a target particle of the physical address.

Description

BACKGROUND TECHNICAL FIELD

[0001] The present technology relates to the field of data processing. TECHNICAL BACKGROUND

[0003] A data processing system can have circuitry for restricting access to particular locations in a memory system. In particular, it can be desirable to prevent at least some software processes executing on the data processing system from accessing memory locations associated with particular physical addresses. This can allow different software processes having different security requirements to operate on the same data processing system, while reducing the risk of data leakage between these software processes. SUMMARY

[0004] At least some examples of the present technology provide an apparatus comprising:

[0005] granule protection checking circuitry configured to:

[0006] perform a granule protection lookup based on the target physical address to obtain granule protection information associated with a target granule of physical addresses including the target physical address; and

[0007] determine, based on the granule protection information, whether a selected physical address space associated with the target physical address and selected from a plurality of physical address spaces is permitted to access the target granule of physical addresses; and

[0008] prefetch circuitry configured to initiate a prefetch operation for the target physical address prior to the granule protection checking circuitry determining whether the selected physical address space is permitted to access the target granule of physical addresses, such that target data identified by the target physical address can be prefetched into a cache.

[0009] At least some examples provide a method comprising:

[0010] performing a granule protection lookup based on the target physical address to identify granule protection information associated with a target granule of physical addresses including the target physical address;

[0011] determining, based on the granule protection information, whether a selected physical address space associated with the target physical address and selected from a plurality of physical address spaces is permitted to access the target granule of physical addresses; and

[0012] initiating a prefetch operation for the target physical address prior to the granule protection checking circuitry determining whether the selected physical address space is permitted to access the target granule of physical addresses, such that target data identified by the target physical address can be prefetched into a cache.

[0013] At least some examples provide computer-readable code for manufacturing an apparatus comprising:

[0014] Particle protection check circuit, which is configured as follows:

[0015] Perform particle protection lookup based on the target physical address to identify particle protection information associated with a target particle that includes the target physical address; and

[0016] Based on this particle protection information, determine whether the selected physical address space, associated with the target physical address and chosen from multiple physical address spaces, is allowed to access the target particle's physical address; and

[0017] A prefetch circuit is configured to initiate a prefetch operation for a target physical address before the particle protection check circuit determines whether the selected physical address space is allowed to access the target particle of the physical address, so that the target data identified by the target physical address can be prefetched into the cache.

[0018] The computer-readable code may be stored on a computer-readable medium, which may be a non-transitory computer-readable medium.

[0019] Further aspects, features, and advantages of this technology will become apparent from the following description, which is taken in conjunction with the accompanying drawings. Attached Figure Description

[0020] Figure 1 An example of a data processing device is illustrated schematically;

[0021] Figure 2 An example of a data processing system having at least one requester device and at least one completer device is illustrated schematically;

[0022] Figure 3 This illustrates the concept of alias mapping from the corresponding physical address space (PAS) to physical memory;

[0023] Figure 4 This illustrates how the system's physical address space can be divided into chunks of access allocation within a specific architecture's physical address space;

[0024] Figure 5 This is a flowchart illustrating how the current operating domain is determined;

[0025] Figure 6 An example of a page table entry format is shown;

[0026] Figure 7 This is a flowchart illustrating a method for selecting a PAS based on the current domain and information from page table entries used to generate physical addresses for a given memory access request;

[0027] Figures 8 to 11 An example of a prefetchable cache line buffer that can be used to initiate multiple prefetch requests is provided;

[0028] Figure 12 This is a flowchart illustrating a method for issuing a prefetch request for a memory location protected by a chip protection check circuit;

[0029] Figure 13 This is a flowchart illustrating a method executed by an address translation circuit, including a prefetch circuit, in response to an on-demand access request;

[0030] Figure 14 This is a flowchart illustrating a method executed by an address translation circuit in response to a prefetch request;

[0031] Figure 15 This is a flowchart illustrating a method executed by an address translation circuit without prefetching circuitry in response to an on-demand access request;

[0032] Figure 16 This is a flowchart illustrating a method executed by a requester that issues an on-demand access request to an address translation circuit with prefetching circuitry;

[0033] Figure 17 This is a flowchart illustrating a method executed by a requester that issues an on-demand access request to an address translation circuit that does not have a prefetch circuit;

[0034] Figure 18 This is a flowchart illustrating the method executed by the prefetch engine that issues the prefetch request;

[0035] Figure 19 This is a flowchart illustrating a method of issuing a prefetch request to a set of target physical addresses using a prefetchable cache line buffer; and

[0036] Figure 20 Examples of systems and products containing chips are shown. Detailed Implementation

[0037] An apparatus includes a particle protection check circuit configured to perform a particle protection lookup based on a target physical address to obtain particle protection information associated with a target particle that includes the target physical address. The particle protection check circuit is configured to, based on the particle protection information, determine whether a selected physical address space, associated with the target physical address and chosen from a plurality of physical address spaces, is permitted to access the target particle containing the physical address.

[0038] Therefore, the system can provide multiple physical address spaces, and a physical address (e.g., specified by a memory access request) can be associated with one of these multiple physical address spaces. A particle protection check circuit can determine, based on particle protection information, whether a specific physical address space is allowed to access a specific target physical address. This allows control over which software processes are allowed to access specific locations in memory, as the hardware can restrict which physical address spaces are allowed to be used by software processes when accessing memory. Therefore, if a software process cannot specify a physical address in the physical address space that is allowed to access the target physical address, the software process may not be able to access the specific memory location identified by that target physical address.

[0039] A physical address can be associated with a physical address space in various ways. For example, one or more bits of a physical address (e.g., portions not used to identify a location in memory) can indicate which physical address space is associated with that physical address.

[0040] Particle protection lookups can be performed in a particle protection table (GPT) stored in memory. However, in some examples, one or more parts of the GPT (such as specific entries in the particle protection information (GPI)) can be cached in a location that is faster to access than memory, and therefore lookups can also or alternatively be performed in a cache structure.

[0041] GPIs can be assigned to all granules (e.g., contiguous blocks) of physical addresses that can be accessed via the same physical address space. It should be understood that, for the purposes of this invention, the details (e.g., size) of the physical address granules are not particularly limited. For example, the size of the granules can be configurable, such as 4KB (e.g., the same size as a storage page), 16KB, or 64KB.

[0042] Therefore, it prevents access to data stored at the target physical address from occurring at a physical address specified in a physical address space that is not permitted to access the target physical address. This provides a strong hardware-enforced barrier to prevent certain software processes from accessing data they are not allowed to access. Therefore, it may be considered that memory access must be delayed until the particle protection check circuit has determined whether the selected physical address space associated with the target physical address is permitted to access the target particle; otherwise, there is a risk that data may be accessed by processes that should not be able to access that data.

[0043] However, the inventors have recognized that requiring a chip protection check to be performed before initiating any memory access can result in high latency when accessing memory protected by the chip protection check circuitry.

[0044] One approach to overcome this problem could be to allow access to the target data before the particle protection check is complete, but prevent its use until it is known whether the selected physical address space associated with that target physical address is allowed to access the target particle. However, this approach might require adding complex logic components to track the state of data items and prevent data from being used until the particle protection check for that data has passed.

[0045] According to an example of this technology, the device includes a prefetch circuit configured to initiate a prefetch operation for a target physical address before a particle protection check circuit determines whether the selected physical address space is allowed to access the target particle of the physical address, such that target data identified by the target physical address (where it should be understood that the target data may include instructions or data) can be prefetched into the cache. As will be discussed below, the prefetch circuit is not particularly limited, and in various examples, the prefetch circuit may be provided by different system components.

[0046] The inventors have recognized that performance can be significantly improved if a prefetch operation to fetch target data into the cache can be initiated (and in some cases completed) even before the granular protection check is finished. In particular, this allows the latency of obtaining the target data (which can be long if the data is stored in memory) to overlap with the time spent performing the granular protection check (by performing a granular protection lookup and determining whether the selected physical address space is allowed to access the target physical address).

[0047] The inventors also recognized that as long as the target data is only prefetched into the cache, performing operations to access the target data in memory does not increase the risk of that data being accessed by a software process that should not have access to it, even without adding additional tracking mechanisms. For example, a mechanism can be provided to prevent data in the cache from being accessed by a software process until after the granularity protection check is completed.

[0048] Therefore, providing a prefetch circuit to initiate a prefetch operation at a time independent of whether the particle protection circuit has determined whether the selected physical address space is allowed to access the physical address of the target particle can improve performance without compromising security or adding complex logic components.

[0049] In some examples, the target physical address associated with the target physical address space can be directly specified in the access request used to access memory. However, in other examples, the device may include address translation circuitry that, in response to a memory access request specifying a target virtual address, translates the target virtual address into a target physical address associated with the selected physical address space. The mapping between virtual and physical addresses can be defined in one or more page table structures. Page table entries within the page table structure may also define access permission information that controls whether a given software procedure executing on the processing circuitry is allowed to access a specific address.

[0050] In some alternative processing systems, address translation circuitry can map all virtual addresses to a single physical address space, which the memory system uses to identify locations in memory to be accessed. In such systems, control over whether a particular address is accessible to a particular software process is based solely on the page table structure used to provide the virtual-to-physical address translation mapping. However, this page table structure is typically defined by the operating system and / or hypervisor. If the operating system or hypervisor is compromised, this can introduce security vulnerabilities, allowing attackers to access sensitive information.

[0051] Therefore, for systems requiring certain processes to be executed securely and isolated from other processes, supporting the translation from a target virtual address to a target physical address associated with a selected physical address space among multiple different physical address spaces (PASs) allows for a further level of control over memory protection beyond what is provided by the page table structure. In some examples, for at least some components of the memory system, memory access requests whose virtual addresses are translated to physical addresses in different PASs can be treated as if they were accessing completely separate addresses in memory, even if the physical address in the corresponding PAS actually corresponds to the same location in memory. By isolating accesses to different operational domains of the processing circuitry into corresponding different PASs as perceived by some memory system components, this provides stronger security guarantees independent of page table permission information set by the operating system or hypervisor.

[0052] In some examples, the address translation circuitry (e.g., the memory management unit (MMU)) may respond to an on-demand memory access request that returns target data associated with a target virtual address to the requester to control the prefetch circuitry to initiate a prefetch operation for the target physical address.

[0053] Therefore, address translation circuitry is an example of prefetching circuitry and can trigger prefetching operations in response to on-demand memory access requests. In some examples, address translation circuitry may trigger prefetching operations only if the access permission information defined in the page table entry indicates that a software process is allowed to access the target virtual address; however, it should be noted that this does not provide any information about whether granular protection information will indicate that the selected physical address space is allowed to access the target granular physical address.

[0054] Those skilled in the art may find it unusual to issue a prefetch operation in response to an on-demand access request, as the prefetch request may seem redundant if an on-demand access request has already been issued. However, before it has been determined whether the selected physical address space is permitted to access the target granule at the physical address, it may be impossible to continue an on-demand access request without increasing the risk that the target data may be available to software processes that should not have access to the target data. Issuing a prefetch operation, however, allows the target data to be retrieved from memory (if necessary), thus allowing the target data to be obtained more quickly in the future (e.g., via an on-demand access request) if it is determined that the target granule at the physical address space is permitted to access the physical address, without increasing the risk of the target data being leaked. Therefore, issuing a prefetch operation in response to an on-demand access request can, counterintuitively, improve performance when the target physical address is protected by granule protection circuitry.

[0055] In some examples, granular protection information can be cached along with cached address translation information in a Translation Lookahead (TLB). Accessing the data when the target virtual address does not have a valid TLB entry typically takes longer because page table roaming may be required to obtain the address translation information, and the target data is more likely not cached (and therefore needs to be fetched from memory). Accessing the granular protection information (which may already be cached in that TLB entry in other ways) can also be slower when the target virtual address does not have a TLB entry. Therefore, it is often the case that when a long granular protection lookup is required, this coincides with the longer time spent fetching the target data from memory. Therefore, requiring a granular protection check to be performed before accessing the target data in memory when the target virtual address does not have a valid TLB entry can have a significant performance impact. Therefore, providing prefetching circuitry to allow the process of obtaining granular protection information to overlap with fetching the target data from memory can significantly improve performance. Thus, this technique allows the latency of a TLB miss to be hidden after the granular protection lookup.

[0056] In some examples, the particle protection check circuit can be configured to prevent the return of target data to the requester in response to determining that the target particle's physical address is not allowed to access the physical address of the selected physical address space. Therefore, the particle protection check circuit can prevent target data from being accessed by a software procedure that issues an on-demand access request, for which the selected physical address space is not allowed to access the physical address of the target particle.

[0057] In some examples, the address translation circuitry can provide address translation responses in response to on-demand access requests. On-demand access requests can be received by the address translation circuitry, and in response, the address translation circuitry can provide the result of a physical address translation and a particle protection check back to the requester, which can then access the target data in memory based on this result. The result of the particle protection check can indicate whether the selected physical address space is allowed to access the target particle at that physical address. In the examples discussed below, the address translation circuitry can also provide translations for prefetch requests. The address translation circuitry can be configured to provide address translation responses for prefetch requests and on-demand access requests at different times.

[0058] Performance can be improved by configuring the address translation circuitry itself to initiate prefetching operations, without requiring any modifications to the external requester responsible for issuing on-demand access requests. The external requester can obtain data faster, but the address translation response may appear identical to the external requester.

[0059] In some examples, the address translation circuitry can be configured to provide one or more offset bits to the prefetch circuitry, which identify the offset of the target physical address within a memory page. The address translation circuitry can perform address translation at the granularity of a memory page. For example, a virtual address can be defined by a virtual page address and an offset, where the offset indicates the virtual address within the target page of the virtual memory defined by the virtual page address. The address translation circuitry can indicate the physical page corresponding to the virtual page, and the target physical address can be determined by applying the same offset in the target physical page as in the target virtual page, meaning that the address translation itself can be performed only against page addresses. Therefore, the target virtual address can typically be specified to the address translation circuitry at the granularity of a memory page (e.g., down to bit 12, where only the virtual page address is specified), since it is simply the page address being translated. Therefore, it is unusual for the address translation circuitry to specify the physical address of the translation, including offset bits. However, in the techniques discussed above, the address translation circuitry can initiate a prefetch operation against the target physical address. If the prefetch operation is initiated at the page granularity, it may be necessary to cache the entire memory page to ensure that the target data is prefetched, but this could potentially require unnecessarily large amounts of storage. Therefore, prefetching operations may require specifying the target physical address at the cache line granularity. Thus, in some examples, the address translation circuitry can be configured to also support receiving offset bits (e.g., bits 12 through 6) of the target virtual address in the translation request, propagating the offset bits to the target physical address of the translation, and providing offset bits for the prefetching operation. The requester can also be configured to provide offset bits to the address translation circuitry in the request to allow the address to be calculated for prefetching by the address translation circuitry.

[0060] In some examples, the apparatus may include a prefetchable cache line buffer configured to store multiple prefetchable cache line entries. The prefetchable cache line entries may be identified for a given on-demand memory access request awaiting translation by: at least an offset portion of a given target virtual address specified by the given on-demand memory access request, the offset portion identifying the offset of the given target virtual address within a memory page; and memory page identification information used to associate the prefetchable cache line entry with the target virtual address belonging to the same memory page. Address translation circuitry may be configured to initiate multiple prefetch operations to a set of target physical addresses, the set of target physical addresses being determined based on the offset portion of the target virtual address, which is identified as corresponding to the same memory page based on the memory page identification information.

[0061] Therefore, the information provided within the prefetchable cache line entry allows the prefetch circuitry to determine which pending translation requests have virtual addresses in the same virtual memory page, and can trigger a prefetch operation for the set of physical addresses in the same physical memory page. Each address to be accessed can be computed by adding an offset provided by the prefetchable cache line buffer to the underlying physical page address determined by translating the virtual page address (which has been determined to be the same for each physical address in the set of physical addresses).

[0062] This allows for more efficient prefetching by triggering a prefetch operation on a set of physical addresses within the same physical storage page. Performing a series of accesses to a specific physical storage page at once may be more efficient, and therefore combining all wait requests for a specific physical storage page may be more efficient. Additionally, by tracking and prefetching only the rows that actually receive access requests, this reduces storage compared to prefetching the entire physical storage page.

[0063] A typical scenario might involve receiving several translation requests for the same page (e.g., when the MMU is performing a table roaming). While the first received request remains pending, subsequent requests will miss in the TLB because the translation hasn't been performed yet, and will therefore be added to the queue of waiting translation requests. By tracking these requests in the prefetchable cache line buffer and issuing them together for the same page, the address translation circuitry can perform this series of prefetch operations more efficiently.

[0064] In some examples, a prefetchable cache line entry can provide the virtual address corresponding to the access request at the cache line granularity (e.g., down to bit 6). This will be used to provide both the offset portion of the target virtual address (bits 12 through 6) and storage page identification information, which can be provided by the virtual page bits of the target virtual address (e.g., the address down to bit 12), because the virtual page bits will match prefetchable cache line entries belonging to the same storage page.

[0065] In other examples, the complete virtual memory page address may not be provided by the prefetch cache line entry. Since the address translation circuitry may already know the virtual page address for a request (e.g., from a translation request queue), all that is needed is for the prefetch cache line buffer to identify which other waiting requests are in the same page, not where that page is located. Therefore, in some examples, the memory page identification information may include an identifier assigned to a specific virtual page, allowing each request within the same virtual page to be identified and grouped with other requests within the same page, while reducing the number of bits stored by the prefetch cache line buffer.

[0066] In some examples, the address translation circuitry may include a prefetch disable mode, where the address translation circuitry is configured to suppress control of prefetching operations. There may be workloads where issuing prefetches for on-demand access requests may not be efficient. For example, if, after initiating a prefetch operation, a high frequency of granular protection checks determines that the target physical address space is not allowed to access the target physical address (frequent granular protection failures), then (although this does impact security) it can be determined that continuing to initiate prefetch operations is inefficient, and therefore the address translation circuitry can enter a prefetch disable mode. Similarly, if on-demand access requests are speculatively issued and it is found that the speculation is generally incorrect, the address translation circuitry can enter a prefetch disable mode to reduce the number of unnecessary prefetch operations initiated.

[0067] In some examples, the address translation circuitry can be configured to indicate to the prefetch circuitry, when controlling the prefetch circuitry to initiate a prefetch operation for a target physical address, whether the on-demand memory access request is a load request or a store request. Therefore, the requester can also indicate to the address translation circuitry whether the on-demand access request is a load request or a store request. This information can also be stored in the prefetchable cache line buffer discussed above.

[0068] When a prefetch operation is triggered, the address translation circuitry knows whether it's a load request or a store request that might be useful. Specifically, this allows data to be prefetched in different consistency states depending on the type of the on-demand access request. If the target data is requested in a load request, the target data is unlikely to be modified, and therefore can be requested in a shared consistency state. In contrast, if the target data is requested in a store request, the data will be modified, and therefore can be requested in a unique consistency state (invalidating copies held by other sharers). If the request type is unknown, all prefetch operations can be performed by requesting a unique copy of the data if data modification is required, while indicating the request type allows data to be requested for a load request in a shared state. Requesting data for a load request in a shared consistency state reduces the amount of unnecessary invalidation of other copies of the target data that might be held elsewhere in the system, compared to requesting all data in a unique state.

[0069] As discussed above, in some examples, the address translation circuitry can be configured to initiate a prefetch operation to obtain the target data before knowing whether the selected physical address space is allowed to access the target granular physical address. In some alternative examples, the prefetch operation can be triggered by another element of the system besides the address translation circuitry.

[0070] Specifically, in some examples, the address translation circuitry may, in response to an on-demand memory access request, enable the return of a partial address translation response indicating the target physical address before the particle protection check circuitry determines whether the selected physical address space is permitted to access the target particle of the physical address. The prefetch circuitry may be configured to initiate a prefetch operation for the target physical address corresponding to the on-demand memory access request based on the partial address translation response.

[0071] Therefore, the requester can issue an on-demand access request to the address translation circuitry, providing a response indicating the physical address to be translated without specifying whether the target granular physical address space is allowed to access the physical address. The prefetch circuitry (e.g., at the requester) can then initiate a prefetch operation using the target physical address indicated by the partial address translation response. The benefit of this approach is similar to that of address translation circuitry triggering a prefetch operation, since the process of fetching the target data into the cache can begin before it has been determined whether the target granular physical address space is allowed to access the physical address, which can improve performance.

[0072] Compared to prefetching triggered by address translation circuitry, providing a partial address translation response means that the triggering of the prefetch operation is no longer invisible to the requester, and processing the partial address translation response may require modifications to the circuitry receiving the response. However, triggering the prefetch operation for entities other than address translation circuitry (e.g., load / memory cells that may have been configured to issue memory access requests) may be more efficient because it reduces the amount of modification required for system components. For example, this might mean less need to propagate offset bits to the address translation circuitry. Therefore, providing a partial address translation response can result in fewer overall system modifications to support prefetching operations triggered before the results of a particle protection check.

[0073] In some examples, partial address translation responses can be cached, for example, in a translation back buffer (TLB). The cached entry can, for example, indicate in a partial address translation field that the entry is one for which the result of a particle protection check is unknown. Therefore, on-demand access can be issued without relying on partial translation entries. For example, if a load instruction is received and a lookup in the TLB identifies a partial translation entry, the memory access circuitry can issue a prefetch operation to fetch the target data into the cache, instead of returning the target data in response to the load instruction.

[0074] In some examples, the address translation circuitry may return a granular protection check result response in response to the granular protection check circuitry determining whether the selected physical address space is permitted to access the target granular physical address. This granular protection check result response indicates whether the selected physical address space is permitted to access the target granular physical address. Therefore, instead of providing a single address translation response indicating both the address translation and the result of the granular protection check, the address translation circuitry may alternatively return a partial address translation response indicating the translated physical address, along with a subsequent response indicating the result of the granular protection check. By providing the granular protection check result response, this indicates whether the previously returned address translation can be used to return the target data to the requester.

[0075] For example, if part of the address translation response is cached in the TLB, the particle protection check result response can indicate whether the entry can be promoted to a normal TLB entry (which can be used to retrieve data for the requester from memory) if the particle protection check passes, or whether the entry should be invalidated if the particle protection check fails.

[0076] In some examples, the prefetch circuitry can be configured to speculatively initiate a prefetch operation in response to a predicted future on-demand memory access request for target data. This prefetch operation involves fetching the target data associated with the target physical address into the cache without returning it to the requester. For example, the prefetch circuitry can be provided by a prefetch engine configured to predict which addresses might be accessed in the future, for example, based on patterns of monitored memory accesses, and issue prefetch requests so that those predicted future on-demand accesses can be executed more quickly. Because the prefetch request does not involve returning the target data to the requester, it allows the prefetch request to fetch data from memory before the granular protection check is completed without compromising security, while performance can be improved because the prefetch operation is not unnecessarily delayed by the time spent performing the granular protection check.

[0077] A speculative prefetch request can initially specify the target address as either a virtual address or a physical address. If the address is specified as a virtual address, a prefetch request can be issued to the address translation circuitry to indicate the target physical address from which target data can be prefetched. The address translation circuitry can be configured to provide an address translation response indicating an address translation, and can also be configured to perform a granular protection check. However, the address translation response can be provided before the granular protection check circuitry determines whether the selected physical address space is allowed to access the target granular address, thereby allowing the prefetch operation to be initiated using the target physical address at a timing independent of whether the granular protection check circuitry has determined whether the selected physical address space is allowed to access the target granular address.

[0078] In some examples, prefetching operations may not be allowed until a particle protection check is completed for indirect prefetching.

[0079] In some examples, the device may include a translation back buffer (TLB) configured to cache address mapping information used by the address translation circuitry to translate a target virtual address into a target physical address, and a granular protection check circuitry configured to perform a granular protection lookup and store the identified granular protection information in the translation back buffer, regardless of whether the prefetch circuitry has initiated a prefetch operation for the target physical address.

[0080] For example, even after a partial address translation response or an address translation response to a prefetch request has been issued, the granular protection check circuit can continue the granular protection check to determine whether the selected physical address space is allowed to access the target granular physical address. By completing the granular protection check, this allows the result of the granular protection check to be cached in the TLB for processing future memory access requests, even if the result is not immediately available to process the initial memory access request.

[0081] In some examples, the apparatus may include a Physical Alias ​​Point (PoPA), which is a point that maps (de-aliases) aliased physical addresses from different physical address spaces (PAS) corresponding to the same memory system resource to a single physical address that uniquely identifies the memory system resource. The memory system may include at least one pre-PoPA memory system component provided upstream of the PoPA that treats the aliased physical addresses as corresponding to different memory system resources.

[0082] For example, at least one pre-PoPA memory system component may include a cache that caches data or program code for alias physical addresses in separate entries, such that if requests to access the same memory system resource are made from different PASs, these accesses will result in the allocation of separate cache entries. Furthermore, the pre-PoPA memory system component may include consistency control circuitry, such as consistency interconnects, snooping filters, or other mechanisms for maintaining consistency between cached information at the respective requester devices. The consistency control circuitry may assign separate consistency states to the corresponding alias physical addresses in different PASs. Therefore, for consistency purposes, alias physical addresses are treated as separate addresses, even though they actually correspond to the same underlying memory system resource. Although, superficially, tracking consistency separately for alias physical addresses may seem to cause a consistency penalty, this is not actually a problem because if processes operating in different domains do intend to share access to a particular memory system resource, these processes can use the same PAS to access that resource. Another example of a pre-PoPA memory system component could be a memory protection engine, which is provided to protect data stored in off-chip memory from confidentiality loss and / or tampering. For example, such a memory protection engine can use different encryption keys to individually encrypt data associated with a specific memory system resource based on which PAS the resource is accessed from, effectively treating alias physical addresses as corresponding to different memory system resources (e.g., an encryption scheme that makes encryption address-dependent can be used, and the PAS identifier can be considered as part of the address used for this purpose).

[0083] Regardless of the form of the pre-PoPA memory system components, it is useful for such PoPA memory system components to view alias physical addresses as corresponding to different memory system resources, because this provides hardware-enforced separation between accesses issued to different PASs, so that information associated with one domain cannot leak to another domain through features such as cache timing side channels or side channels involving consistency changes triggered by consistency control circuitry.

[0084] In some implementations, different digital physical address values ​​for different corresponding PASs can be used to represent alias physical addresses in different PASs. This approach may require a mapping table to determine at the PoPA which of the different physical address values ​​corresponds to the same memory system resource. However, the overhead of maintaining such a mapping table may be considered unnecessary, and therefore in some implementations, it may be simpler if the alias physical address includes the physical address represented by the same digital physical address value in each different PAS. If this approach is adopted, at the physical alias point, it is sufficient to simply discard the PAS identifier that identifies which PAS was accessed using memory access, and then provide the remaining physical address bits downstream as the de-alias physical address.

[0085] Therefore, the memory system may also include a PoPA memory system component configured to de-alias multiple aliased physical addresses to obtain a de-aliased physical address to be provided to at least one downstream memory system component. The PoPA memory system component may be a device that accesses a mapping table to find the de-aliased address corresponding to the aliased address in a specific address space, as described above. However, the PoPA component may also simply be the location within the memory system where the PAS identifier of the selected PAS associated with a given memory access is discarded, such that the physical address provided downstream uniquely identifies the corresponding memory system resource, regardless of which PAS it is provided with. Alternatively, in some cases, the PoPA memory system component may still provide a PAS identifier to at least one downstream memory system component (e.g., for completer-side filtering), but the PoPA may mark a point within the memory system beyond which downstream memory system components no longer treat the aliased physical address as a different memory system resource, but instead consider each aliased physical address in the aliased physical address to map to the same memory system resource. For example, if a downstream memory controller or hardware memory storage device of the PoPA receives a PAS identifier and physical address for a given memory access request, then if that physical address corresponds to the same physical address as a previously seen transaction, then any risk checks or performance improvements performed on corresponding transactions accessing the same physical address (such as merging accesses to the same address) can be applied, even if the corresponding transactions specify different PAS identifiers. In contrast, for memory system components upstream of the PoPA, if transactions accessing the same physical address specify the same physical address in different PASs, then such risk checks or performance improvement steps performed on these transactions may not be invoked.

[0086] In some examples, the device may have a PAS selection circuit for selecting a PAS for a target physical address based on at least one of the following: the current operating domain; and information specified in a page table entry, which also provides address mapping information used by address translation circuitry to translate the target virtual address into a target physical address. For example, the PAS selection circuit may be part of address translation circuitry or part of particle protection check circuitry. Where the processing circuitry supports different operating domains, the selection of the chosen PAS may depend on the current domain of the processing circuitry. At least for some operating domains, different PASs may also be accessible from within a single domain, and in this case, the information specified in the page table entry may be used to select the chosen PAS for a given memory access request.

[0087] In a specific example, the processing circuitry can process instructions in one of multiple operation domains, and those domains can include at least a non-secure domain, a secure domain, a domain of interest, and a root domain. In this case, the PAS can include:

[0088] • When the current domain of the processing circuit is the root domain, the root PAS can be selected as the selected PAS (when the current domain is the security domain, the neighboring domain, or the root domain, the root PAS can be prevented from being selected as the selected PAS).

[0089] • When the current domain of the processing circuit is any of the non-safe domain, safe domain, neighboring domain, and root domain, a non-safe PAS can be selected as the chosen PAS;

[0090] • When the current domain of the processing circuit is a secure domain or the root domain, a safe PAS can be selected as the chosen PAS (when the current domain is a non-secure domain or a neighboring domain, the selection of a safe PAS can be prohibited); and

[0091] • When the current domain of the processing circuit is a neighborhood domain or a root domain, the neighborhood PAS that can be selected as the selected PAS can be chosen (when the current domain is a non-secure domain or a secure domain, the neighborhood PAS that can be selected as the selected PAS can be prohibited).

[0092] This approach, which includes a root domain that can access all PASs, a non-secure domain that can only access its non-secure PASs, and secure PASs and domain PASs that can both access non-secure PASs and their own PASs but not each other's PASs or the root PAS, can be used to allow multiple mutually untrusted parties to implement code on a shared hardware platform, while each party is provided with some hardware-enforced guarantees that protect each party's code and data from access by other code operating on the same system, while preventing access to each other's code and data.

[0093] A specific example will now be described with reference to the accompanying drawings.

[0094] Figure 1 An example of a data processing apparatus 2 is illustrated schematically. The data processing apparatus has a processing pipeline 4 comprising multiple pipeline stages. In this example, the pipeline stages include: a fetch stage 6 for fetching instructions from an instruction cache 8; a decode stage 10 for decoding the fetched program instructions to generate micro-operations to be processed by the remaining stages of the pipeline; a release stage 12 for checking whether the operands required for the micro-operation are available in a register file 14, and releasing the micro-operation for execution once the operands required for a given micro-operation are available; an execution stage 16 for performing the data processing operation corresponding to the micro-operation by processing the operands read from the register file 14 to generate a result value; and a write-back stage 18 for writing the processed result back to the register file 14. It should be understood that this is merely one example of a possible pipeline architecture, and other systems may have additional stages or different stage configurations. For example, in an out-of-order processor, a register renaming stage may be included, which maps the architecture registers specified by program instructions or micro-operations to physical register specifiers of physical registers in the identifier register file 14.

[0095] Execution phase 16 includes multiple processing units for performing different types of processing operations. For example, the execution units may include: a scalar arithmetic / logic unit (ALU) 20, which performs arithmetic or logical operations on scalar operands read from register 14; a floating-point unit 22, which performs operations on floating-point values; a branch unit 24, which evaluates the result of a branch operation and adjusts the program counter representing the current execution point accordingly; and a load / store unit 26, which performs load / store operations to access data in memory systems 8, 30, 32, and 34. A memory management unit (MMU) 28 is provided, which performs address translation between the virtual address specified by the load / store unit 26 based on the operand of the data access instruction and the physical address identifying the storage location of the data in the memory system. The MMU has a Translation Lookahead (TLB) 29, which caches address translation data from page tables stored in the memory system. Page table entries define the address translation mapping and can also specify access permissions that control whether a given process executing on the pipeline is allowed to read, write, or execute instructions for a given memory region.

[0096] In this example, the memory system includes a tier-one data cache 30, a tier-one instruction cache 8, a shared tier-two cache 32, and main system memory 34. It should be understood that this is merely one example of a possible memory hierarchy, and other cache arrangements are also possible. The specific types of processing units 20 to 26 shown in execution phase 16 are only one example, and other implementations may have different sets of processing units or may include multiple instances of the same type of processing units, allowing multiple micro-operations of the same type to be processed in parallel. It should be understood that... Figure 1 This is merely a simplified representation of some components of a possible processor pipeline architecture, and the processor may include many other elements not shown for the sake of simplicity.

[0097] Figure 2 An example of a data processing system having at least one requester device 40 and at least one completer device 42 is schematically illustrated. Interconnect 44 provides communication between the requester device 40 and the completer device 42. The requester device is capable of issuing a memory access request for memory access to a specific addressable memory system location. The completer device 42 is the device responsible for servicing memory access requests directed to it. Although... Figure 2 Not shown, but some devices may be able to function as both a requester device and a completer device. Requester device 40 may, for example, include processing elements such as a central processing unit (CPU) or a graphics processing unit (GPU) or other host devices such as a bus host, network interface controller, display controller, etc. Requester device 40 may be provided, for example, as... Figure 1 The data processing apparatus shown. The completer device 42 may include a memory controller responsible for controlling access to the corresponding memory storage unit, a peripheral controller for controlling access to peripheral devices, etc. Figure 2 An example configuration of one of the requester devices 40 is shown in more detail, but it should be understood that other requester devices 40 may have similar configurations.

[0098] The requester device 40 has a processing circuit 4 for performing data processing in response to an instruction by referring to data stored in register 14 (e.g., such as...). Figure 1 (The pipeline shown). Register 14 may include general-purpose registers for storing operands and the results of processed instructions, and control registers for storing control data to configure how the processing circuitry performs processing. For example, the control data may include a current domain indicator 46 for selecting which operation domain is the current domain, and a current exception level indicator 48 for indicating which exception level is the current exception level that processing circuitry 4 is operating at. Although Figure 2The current domain indicator 46 and the current exception level indicator 48 are shown as different status values. However, it is also possible that the current domain and / or exception level can be determined based on the current value of a set of multiple control bits stored in one or more control registers. Therefore, it is not necessary to provide a single, distinct status value that encodes the current domain or the current exception level.

[0099] Processing circuit 4 may issue a memory access request specifying a virtual address (VA) identifying the addressable location to be accessed and a domain identifier (domain ID or "security state") identifying the current domain. The memory access request can be an on-demand access request requesting the return of target data to register 14, or a prefetch request issued by prefetch engine 54 requesting the return of target data to caches 30, 32. Address translation circuit 28 (e.g., a memory management unit (MMU)) translates the virtual address into a physical address (PA) through one or more stages of address translation based on page table data defined in a page table structure stored in the memory system. Translation lookup buffer (TLB) 29 acts as a lookup cache to cache some of the page table information in the page table information, thus enabling faster access than if page table information had to be fetched from memory every time an address translation is needed. In this example, in addition to generating the physical address, address translation circuit 28 selects one of a plurality of physical address spaces (PAS) associated with the physical address and outputs a physical address space (PAS) identifier identifying the selected physical address space. The choice of PAS will be discussed in more detail below.

[0100] The particle protection check circuit 50 acts as a requester-side filter circuit to check whether access to the physical address within the specified physical address space identified by the PAS identifier is permitted based on the physical address and the PAS identifier. This lookup is based on particle protection information (GPI) stored in the particle protection table structure stored within the memory system. Similar to the cache of page table data in TLB 29, the particle protection information can be cached in the particle protection information cache 52. Although the particle protection information cache 52 is in Figure 2 In the example shown, it is a structure separate from TLB 29, but in other examples, these types of lookup caches can be combined into a single lookup cache structure, or the GPI can optionally be cached in TLB 29. The particle protection information defines information restricting access to the physical address space from which a given physical address can be accessed, and based on this lookup, the particle protection check circuit 50 determines whether to allow memory access requests to continue being issued to one or more caches 8, 30, 32 and / or interconnect 44. If the specified PAS of the memory access request is not allowed to access the specified physical address, the particle protection check circuit 50 blocks the transaction and may signal a fault.

[0101] Therefore, the processing circuit 4 can send a memory access request to the address translation circuit 28, and in response, receive an address translation response from the chip protection check circuit 50, which includes address translation and an indication of whether the memory access request is allowed to continue.

[0102] Although Figure 2 An example of address translation circuitry 28 and particle protection check circuitry 50 provided within requester 40 is shown, but other types of requesters may use address translation functionality provided by a separate System Memory Management Unit (SMMU), a component separate from requester 40 itself. In this case, the SMMU may be coupled to an interconnect and may perform operations similar to... Figure 2 The address translation circuit 28 and the particle protection check circuit 50 shown have similar functions and can have a similar GPI cache 52.

[0103] Although Figure 2 An example is shown where address translation circuit 28 performs the selection of a PAS for a given request. However, in other examples, address translation circuit 28 may output information for determining which PAS to select, along with the PA, to particle protection check circuit 50, and particle protection check circuit 50 may select a PAS and check whether access to the PA is permitted within the selected PAS.

[0104] In some examples, processing circuit 4 may be able to issue a memory access request that directly specifies a physical address (PA) without memory translation, the PA identifying the addressable location to be accessed. Particle protection check circuit 50 may determine which PAS is associated with the requested PA based on the domain ID associated with the memory access request, and may provide processing circuit 4 with a response indicating whether the memory access request is allowed to proceed.

[0105] The provision of the particle protection check circuit 50 helps support systems that can operate in multiple operating domains, each associated with its own isolated physical address space, wherein for at least a portion of the memory system (e.g., for some cache or coherence implementation such as a snooping filter), even if addresses within these address spaces actually refer to the same physical location in the memory system, the individual physical address spaces are viewed as completely separate sets of addresses that refer to the locations of individual memory systems.

[0106] For example, the processing circuitry may support multiple operating domains, including a root domain, a secure (S) domain, a less secure domain, and a domain. For ease of reference, the less secure domain will be described hereinafter as an “unsecure” (NS) domain, but it should be understood that this is not intended to imply any particular level of security (or lack thereof). Rather, “unsecure” simply indicates that the unsecure domain is intended for code that is not as secure as code operating in a secure domain. The current domain may be selected based on the current exception level indicator 48 and / or the current domain indicator 46, which indicates which domain is active.

[0107] Non-security domains can be used for regular application-level processing and for operating system and hypervisor activities to manage such applications. Therefore, within a non-security domain, there can be application code operating at exception level 0 (EL0), operating system (OS) code operating at EL1, and hypervisor code operating at EL2.

[0108] Security domains allow certain on-chip security, media, or system services to be isolated into a separate physical address space from the physical address space used for insecure processing. Code in a non-security domain cannot access resources associated with a security domain, while a security domain can access both secure and insecure resources. In this sense, security domains and non-security domains are not equivalent.

[0109] Similar to a security domain, a domain can have its own allocated physical address space. However, while both the domain and security domains can issue memory access requests in a non-secure PAS associated with the non-secure domain, the domain and security domains cannot access each other's physical address spaces. This means that code executing in the domain and security domains is independent of each other.

[0110] A root domain can manage domain switching and can have its own isolated root physical address space. Even for systems with only non-secure and secure domains but no domain domains, the creation of a root domain and the isolation of its resources from secure domains allows for a more robust implementation, but it can also be used for implementations that do not support domain domains.

[0111] Figure 3 This illustrates the concept of mapping a corresponding physical address space (PAS) to an alias on the physical memory provided in the hardware. As previously described, each domain in a domain has its own corresponding physical address space 61.

[0112] At the point when the address translation circuit 28 generates the physical address, the physical address has a value within a certain range 62 supported by the system, which is the same regardless of which physical address space is selected. However, in addition to generating the physical address, the address translation circuit 28 can also select a specific physical address space (PAS) based on the current domain and / or information in the page table entries used to derive the physical address. Alternatively, instead of the address translation circuit 28 performing the selection of the PAS, the address translation circuit (e.g., the MMU) can output the physical address and information derived from the page table entries (PTE) for selecting the PAS, and then the particle protection check circuit 50 can use this information to select the PAS.

[0113] The selection of PAS for a given memory access request can be limited based on the current domain in which the processing circuit 4 is operating when the memory access request is issued.

[0114] For example, when processing circuit 4 is operating in a non-secure domain, it can select only non-secure PAS for memory access requests issued by the processing circuit.

[0115] When processing circuit 4 is operating in a secure domain, it can select either a non-secure PAS or a secure PAS for memory access requests issued by the processing circuit, but it cannot select a domain PAS or a root PAS.

[0116] When processing circuit 4 is operating in the domain, it can select a non-safe PAS or a domain PAS for memory access requests issued by the processing circuit, but not a safe PAS or a root PAS.

[0117] When processing circuit 4 is operating in the root domain, any PAS can be selected for memory access requests issued by the processing circuit.

[0118] For those domains where multiple physical address spaces are available, information from page table entries used to provide access to physical addresses can be used to select among the available PAS options.

[0119] Therefore, at the point in time when the particle protection check circuit 50 outputs a memory access request (assuming it has passed any filtering checks), the memory access request is associated with the physical address (PA) and the selected physical address space (PAS).

[0120] The Physical Alias ​​Point (PoPA) 60 is the location in the system where the PAS ID is stripped and the address is transformed back from the alias address to the system physical address. The PoPA can be located on the system's completer side below the cache, where physical DRAM is accessed (using the cryptographic context resolved via the PAS ID). Alternatively, it can be located above the cache to simplify system implementation at the cost of reduced security. An example of a PoPA is...Figure 2 as well as Figure 3 As shown in the image.

[0121] From the perspective of memory system components (such as caches, interconnects, snooping filters, etc.) operating prior to the Physical Alias ​​Point (PoPA) 60, the corresponding physical address space 61 is viewed as a completely separate address range corresponding to different system locations within memory. This means that, from the perspective of the pre-PoPA memory system components, the address range identified by the memory access request is actually four times the size of the range 62 that can be output in address translation, because the PAS identifier is actually treated as an additional address bit next to the physical address itself, so that the same physical address PAx can be mapped to multiple alias physical addresses 63 in different physical address spaces 61 depending on which PAS is selected. These alias physical addresses 63 all correspond to the same memory system location implemented in the physical hardware, but the pre-PoPA memory system components treat the alias address 63 as a separate address. Thus, if any pre-PoPA cache or snooping filter exists to allocate entries for such addresses, the alias address 63 will be mapped to a different entry with separate cache hit / miss decisions and separate consistency management. This reduces the likelihood or effectiveness of an attacker using a cache or consistency side channel as a mechanism to probe operations in other domains.

[0122] The system may include more than one PoPA 60. At each PoPA 60, the aliased physical address is shrunk to a single de-aliased address 65 in the system physical address space 64. The de-aliased address 65 is provided downstream of any subsequent PoPA component such that the system physical address space 64, which actually identifies the memory system location, is once again the same size as the range of physical addresses that can be output in the address translation performed on the requester side. For example, at PoPA 60, the PAS identifier may be stripped from these addresses, and for downstream components, these addresses may simply be identified using physical address values ​​without specifying the PAS. Alternatively, for some cases where some completer-side filtering is expected for memory access requests, the PAS identifier may still be provided downstream of PoPA 60, but may not be interpreted as part of the address, such that the same physical address appearing in different physical address spaces 60 will be interpreted downstream of the PoPA as involving the same memory system location, but the supplied PAS identifier can still be used to perform any completer-side security checks.

[0123] Figure 4This illustrates how a granular protection table (GPT) can be used to divide the system physical address space 64 into blocks of access allocations within a specific architecture physical address space 61. The granular protection table (GPT) defines which portions of the system physical address space 65 are allowed to be accessed from each architecture physical address space 61. For example, a GPT may include multiple entries, each corresponding to a physical address granule of a certain size (e.g., 4K pages), and may be defined as the PAS allocated to that granule, which can be selected from non-secure domains, secure domains, domains, and root domains. By design, if a particular granule or set of granules is allocated to a PAS associated with one of these domains, it can only be accessed within the PAS associated with that domain and not within PASs of other domains. However, it should be noted that while granules allocated to secure PASs (for example) cannot be accessed from within the root PAS, the root domain can access the physical address granule by specifying PAS selection information in its page table to ensure that the virtual address associated with a page in that region of physically addressed memory is translated into a physical address in the secure PAS (not the root PAS). Thus, the sharing of data across domains can be controlled at the point in time when a PAS is selected for a given memory access request (to the extent permitted by the accessibility / inaccessibility rules defined in the previously described table).

[0124] Figure 5 This is a flowchart illustrating how the current operating domain is determined, which can be performed by processing circuitry 4, address translation circuitry 28, or particle protection check circuitry 50. At step 100, it is determined whether the current exception level is EL3. If so, at step 102, the current domain is determined as the root domain. If the current exception level is not EL3, at step 104, the current domain is determined as one of the non-secure domain, secure domain, and safe domain, as indicated by at least two domain indicator bits 46 in the processor's EL3 control register (since the root domain is indicated by the current exception level of EL3, it may not be necessary to have an encoding of the domain indicator bits 46 corresponding to the root domain; therefore, at least one encoding of the domain indicator bits can be reserved for other purposes). The EL3 control register can be written to when operating at EL3 and cannot be written to from other exception levels EL2-EL0.

[0125] Figure 6An example of a Page Table Entry (PTE) format is shown that can be used for page table entries in a page table structure. These page table entries are used by address translation circuitry 28 to map virtual addresses to physical addresses, virtual addresses to intermediate addresses, or intermediate addresses to physical addresses (depending on whether the translation is performed in an operational state where a stage 2 translation is fully required, and whether the translation is a stage 1 translation or a stage 2 translation if a stage 2 translation is required). In general, a given page table structure can be defined as a multi-level table structure implemented as a page table tree, where the first level of the page table is identified based on a base address stored in the processor's translation table base address register, and an index for selecting a specific level 1 page table entry within the page table is derived from a subset of bits of the input address to which a translation lookup is performed (the input address can be a virtual address for stage 1 translation or an intermediate address for stage 2 translation). A level 1 page table entry can be a "table descriptor" 110 that provides a pointer 112 to the next level page table, from which further page table entries can be selected based on a further subset of bits of the input address. Finally, after one or more lookups at consecutive levels of the page table, block or page descriptors PTE 114, 116, and 118 can be identified, which provide an output address 120 corresponding to the input address. The output address can be an intermediate address (for a stage 1 transition performed while the operation is still in the state of performing a further stage 2 transition) or a physical address (for a stage 2 transition or a stage 1 transition when stage 2 is not required).

[0126] To support the different physical address spaces mentioned above, in addition to the next-level page table pointer 112 or output address 120 and any attributes 122 used to control access to the corresponding block of memory, the page table entry format also specifies some additional states for physical address space selection.

[0127] For table descriptor 110, the PTE used by any domain other than the non-secure domain includes a non-secure table indicator 124, which indicates whether the next-level page table will be accessed from the non-secure physical address space or from the physical address space of the current domain. This facilitates more efficient management of page tables. Typically, the page table structure used by the root domain, domain domain, or secure domain may only need to define special page table entries for a portion of the virtual address space, and the same page table entries used by the non-secure domain can be used for other portions. Therefore, by providing the non-secure table indicator 124, this allows higher levels of the page table structure to provide dedicated domain / secure table descriptors, while at certain points in the page table tree, the root domain domain or secure domain can switch to using page table entries from the non-secure domain for portions of the address space that do not require higher security. Other page table descriptors in other parts of the page table tree can still be obtained from the associated physical address space associated with the root domain, domain domain, or secure domain.

[0128] On the other hand, block / page descriptors 114, 116, and 118 may include physical address space selection information 126 depending on which domain they are associated with. Insecure block / page descriptors 118 used in insecure domains do not include any PAS selection information because insecure domains can only access insecure PASs. However, for other domains, block / page descriptors 114 and 116 include PAS selection information 126, which is used to select which PAS the input address will be translated to. For the root domain, EL3 page table entries may have PAS selection information 126, which includes at least two bits to indicate the selected PAS for which the corresponding physical address will be translated if the PAS associated with any of the four domains is specified. In contrast, for the domain domain and the secure domain, the corresponding block / page descriptor 116 only needs to include one bit of PAS selection information 126, which selects between a domain PAS and an insecure PAS for the domain domain, and between a secure PAS and an insecure PAS for the secure domain. To improve the efficiency of circuit implementation and avoid increasing the size of page table entries, the block / page descriptor 116 can encode the PAS selection information 126 at the same location within the PTE for both the domain and security domains, regardless of whether the current domain is the domain or the security domain, so that the PAS selection bit 126 can be shared.

[0129] thereby, Figure 7 This is a flowchart illustrating a method for selecting the PAS based on the current domain and information 124, 126 from the block / page PTE for generating a physical address for a given memory access request. PAS selection can be performed by address translation circuit 28, or by a combination of address translation circuit 28 and particle protection check circuit 50 if the address translation circuit forwards PAS selection information 126 to particle protection check circuit 50.

[0130] exist Figure 7At step 130, processing circuit 10 issues a memory access request specifying a given virtual address (VA) as the target VA. At step 132, address translation circuit 28 searches its TLB 29 for any page table entries (or cached information derived from such page table entries). If any required page table information is unavailable, address translation circuit 28 initiates a page table roaming to memory to obtain the required PTE (potentially requiring a series of memory accesses to progressively traverse the corresponding levels of the page table structure, and / or potentially requiring multiple stages of address translation to obtain a mapping from VA to intermediate address (IPA) and then from IPA to PA). Note that any memory access request issued by address translation circuit 28 during the page table roaming operation can itself undergo address translation and PAS filtering, so the request received at step 130 could be a memory access request for a page table entry from memory. Once the relevant page table information has been identified, the virtual address is translated into a physical address (possibly via IPA in two stages). At step 134, address translation circuit 28 or particle protection check circuit 50 uses Figure 5 The method shown is used to determine which domain is the current domain.

[0131] If the current domain is a non-secure domain, then at step 136, the output PAS selected for the memory access request is a non-secure PAS.

[0132] If the current domain is a secure domain, then at step 138, an output PAS is selected based on PAS selection information 126, which provides the physical address and is included in the block / page descriptor PTE, wherein the output PAS will be selected as a secure PAS or a non-secure PAS.

[0133] If the current domain is a domain domain, then at step 140, an output PAS is selected based on PAS selection information 126 included in the block / page descriptor PTE from its derived physical address, and in this case, the output PAS is selected as a domain PAS or a non-secure PAS.

[0134] If the current domain is determined to be the root domain at step 134, then at step 142, the output PAS is selected based on the PAS selection information 126 from which the physical address is derived in the root block / page descriptor PTE 114. In this case, the output PAS is selected as any physical address space in the physical address space associated with the root domain, the domain, the security domain, and the non-security domain.

[0135] Therefore, the data processing device provides a particle protection check circuit to perform a particle protection lookup based on a target physical address to obtain particle protection information associated with a target particle that includes the target physical address, and to determine, based on the particle protection information, whether a selected physical address space associated with the target physical address and selected from multiple physical address spaces is allowed to access the target particle that contains the physical address.

[0136] As previously discussed, conventional methods for implementing the particle protection check circuit 50 may require that the result of the particle protection check be known before the target data can be requested from the memory, as this ensures that the target data can only be accessed by the physical address space that the GPT allows access to the target data.

[0137] However, this approach means that the delay in obtaining the target data is added to the delay in performing the particle protection check, which may result in high latency for accessing the address space protected by the particle protection check circuit 50.

[0138] In an alternative approach, data can be returned to the requester before the GPC result is known (e.g., load / store unit 26 or fetch stage 6 can load the target data into register 14 of the specific requesting device 4 before the GPC result is known). This allows for faster access to the target data than waiting until after the GPC. In this alternative approach, a mechanism is needed to prevent the target data from being used by the requester before the GPC result is known, and to invalidate the data if the GPC fails, otherwise bypassing the security provided by the GPC. However, providing such a mechanism would require adding very complex logic to track which data at a particular requester can be used at a given time and delay operations as needed, increasing the risk that data may be used incorrectly. Providing such logic may be impractical if power, performance, and area requirements are to be met.

[0139] In this technology, the apparatus includes prefetch circuits 54 and 56, which initiate a prefetch operation for a target physical address before the particle protection check circuit determines whether the selected physical address space is allowed to access the target particle of the physical address. This allows the target data identified by the target physical address to be prefetched into the cache. This method also allows the latency of obtaining the target data to overlap with the latency of performing the particle protection check, and thus reduces the time spent accessing the memory protected by the particle protection check circuit 50. However, this method requires significantly fewer modifications compared to a method that returns the target data to the requester's register before the particle protection check is complete. In particular, for a requester accessing data from the cache, it may be necessary to issue an on-demand access request, which itself needs to pass the particle protection check (because all access requests may be subject to the check of the particle protection check circuit 50), and therefore data cannot be accessed from the cache until the particle protection check is complete. Therefore, there is no need to provide complex circuitry to prevent the target data from being used until after the particle protection check.

[0140] In some examples, prefetch circuit 56 may be provided by address translation circuit 28. In response to an on-demand access request for a specified VA, address translation circuit 28 may translate the VA to determine the PA. Address translation circuit 28 may then obtain particle protection information and initiate a particle protection check based on the PA to determine whether the PA is allowed to access the target particle at the physical address. Address translation circuit 28 may simultaneously cause prefetch circuit 56 to initiate a prefetch operation to fetch the target data (e.g., data or instructions) corresponding to the PA into caches 8, 30, and 32. Once the particle protection check is complete, address translation circuit 28 may return an address translation response indicating the PA and GPC results. LSU 26 can use the translated address to access the target data from the memory system, and doing so accesses the target data fetched into caches 8, 30, and 32 by prefetch circuit 56.

[0141] In an alternative example, address translation circuit 28 can convert VA to PA and initiate GPC based on the converted PA (and PAS). Address translation circuit 28 can return the converted PA as a partial address translation response to processing circuit 4 before the result of the GPC is known, instead of triggering the prefetch operation itself. The converted PA can, for example, be cached in a TLB associated with processing circuit 4, and the entry can, for example, indicate that the GPC result is still unknown for that entry. In response to a memory access request specifying a VA matching an entry for which the GPC result is unknown, a prefetch circuit within the processing circuit (such as load / store unit 26) can initiate a prefetch operation using the PA returned by address translation circuit 28 in the partial address translation response. Once the result of the GPC has been determined by particle protection check circuit 50, a further response indicating the result can be provided. If the GPC passes, the partial TLB entry can be updated to a full TLB entry, and in response to a future memory access request specifying a VA matching the full TLB entry, load / store unit 26 can retrieve the target data in on-demand access.

[0142] In some examples, the prefetch circuitry can be provided by prefetch engine 54. The prefetch engine can typically issue prefetch requests to addresses predicted to be accessed in the future, for example, based on patterns of monitored memory accesses. The prefetch engine can issue a prefetch request specifying a VA to address translation circuitry, which can provide a response indicating a PA before GPC completes. Prefetch engine 54 can use the translated PA to fetch target data into caches 8, 30, and 32, regardless of whether GPC has completed.

[0143] In some examples, memory access can initially be specified using a PA, and therefore no address translation is required. In this case, the prefetch operation can be triggered speculatively by the prefetch circuitry (e.g., in response to a prefetch request issued by the prefetch engine 54) or in response to the detection that an on-demand access request for the specified PA requires a GPC (in some examples, the prefetch circuitry can be provided by the particle protection check circuitry 50).

[0144] Figures 8 to 11 An example of a prefetchable cache line buffer is provided, which can be used to initiate multiple prefetch requests. The prefetchable cache line buffer 58 may be provided, for example, by address translation circuitry 56. The prefetchable cache line buffer 58 allows prefetch operations to be combined for multiple memory locations within the same memory page and issued together. This allows for more efficient prefetch operations with a single access to the memory page and also allows the address translation circuitry to specify prefetch operations at the granularity of cache lines.

[0145] like Figures 8 to 11As shown, the address translation circuit may have a translation request buffer 59, which includes entries for tracking virtual addresses for which memory access requests have been received by the translation circuit 28 to be translated into physical addresses. The translation request buffer (and prefetchable cache line buffer 58) can track entries corresponding to memory access requests that are missed in TLB 29 and therefore require page table roaming for translation. The virtual address used for translation can be indicated at the granularity of virtual memory pages (e.g., down bits 12), because translation can occur at the page granularity. Therefore, the translation request buffer may not track the offset bits of a given memory access request.

[0146] The prefetchable cache line buffer 58 also stores entries corresponding to memory access requests received by the translation circuitry. The entries in the prefetchable cache line buffer 58 may correspond to entries in the translation request buffer 59. For example, the translation request buffer may provide upper virtual address bits for a given memory access request, and the prefetchable cache line buffer may provide offset bits (e.g., bits 11 to 6) indicating the location of the cache line to be accessed within a memory page. Supporting the tracking of offset bits at the address translation circuitry 28 allows prefetching operations to be initiated by the address translation circuitry 28 at the cache line granularity, and tracking these bits in a separate structure (rather than within the translation request buffer) reduces modifications to the translation request buffer 59.

[0147] The prefetchable cache line buffer 58 can also associate memory access requests within the same memory page. For example, cache line buffer entries can provide memory page identification information, which can be used to associate entries in the prefetchable cache line buffer that are associated with the same memory page. These entries can also be associated with individual entries in the translation request buffer. The memory page identification information can simply be the virtual address of the memory page (as provided in the translation request buffer 59), but more efficient encoding can be provided by using an ID to associate the prefetchable cache line buffer entry associated with a specific memory page with the corresponding entry in the translation request buffer 59 indicating the virtual address of the memory page. When the prefetch circuit 56 issues a prefetch request, the prefetch circuit 56 can issue prefetch requests for a group of virtual addresses that are associated with each other within the same memory page at a time.

[0148] Figure 8The illustration shows the state of translation request buffer 59 and prefetchable cache line buffer 58 after receiving a memory access request for a specified virtual address (in hexadecimal) of 0xDEAD_B000. New entries can be allocated in translation request buffer 59 to track the virtual page address 0xDEAD_B used for translation, and attributes associated with the request (e.g., if it is a load request or a store request). New entries can also be allocated in prefetchable cache line buffer 58 to indicate the offset (000000) used for the request, thus identifying the cache line to be accessed within the virtual memory page.

[0149] Figure 9 The example illustrates the reception of a subsequent memory access request for the specified virtual address 0xDEAD_B100. This address is in the same virtual memory page as the previous address, and therefore no new entry is allocated in the translation request buffer 59, as an entry already exists in that buffer to track the virtual address to be translated. However, a new entry is allocated in the prefetchable cache line buffer, indicating the offset (000100) of the cache line to be accessed within the virtual memory page. Figure 9 In the example, two entries in the prefetchable cache line buffer 58 are associated with the same translation ID (0) because both entries correspond to the same entry in the translation request buffer, and therefore to the same virtual page address.

[0150] Figure 10 An example is shown of receiving a subsequent memory access request specifying virtual address 0xDEAD_C000. This address is in a different virtual memory page than the previous request, and therefore a new entry tracking the virtual address to be translated is allocated in translation request buffer 59. A new entry is also allocated in the prefetchable cache line buffer, indicating the offset (000000) of the cache line to be accessed within the virtual memory page. Since the new entry corresponds to a different virtual memory page than the previously allocated entry, the new entry has a different translation identifier (1) than the previous entry, indicating that the entry corresponds to a second entry in translation request buffer 59.

[0151] at last, Figure 11 This example illustrates the reception of a subsequent memory access request specifying virtual address 0xDEAD_BFF0. This address is related to... Figure 8 and Figure 9 The address is in the same virtual memory page, and therefore no new entry is allocated in the translation request buffer 59, since an entry already exists in that buffer that tracks the virtual address to be translated. A new entry is allocated in the prefetchable cache line buffer, which indicates the offset (111111) of the cache line to be accessed within the virtual memory page. Figure 11The example shows new entries in the prefetchable cache line buffer 58 and... Figure 8 and Figure 9 The entries allocated in the middle are associated with the same transformation ID (0) because these entries all correspond to the same entry (first entry) in the transformation request buffer 59, and therefore all correspond to the same virtual page address.

[0152] Address translation circuit 28 can process translation requests from translation request buffer 59 in a certain order (e.g., receiving order). When address translation circuit 28 translates a virtual memory page address from a given entry in translation request buffer 59, a lookup of a prefetchable cache line buffer can be performed to determine which entries in prefetchable cache line buffer 59 correspond to the virtual page address being translated. For example, a lookup can determine which entries have a translation ID corresponding to a translation entry in translation request buffer 59, or if the prefetchable cache line buffer stores at least a portion of virtual page addresses, it can determine which entries are associated with the same virtual page address being translated. Therefore, a set of prefetchable cache line buffer entries corresponding to the same virtual memory page can be obtained.

[0153] Once the address translation circuit 28 has obtained the translated physical page address (from the page table entry corresponding to the virtual page address), the prefetch circuit 56 can issue multiple prefetch requests corresponding to the set of prefetchable cache line buffer entries. Specifically, the offset provided by each entry in the identified set can be combined with the translated physical page address to obtain a set of physical addresses at the cache line granularity, all belonging to the same physical page, which can be used to issue multiple prefetch requests. Figure 11 In the example, if the virtual page address 0xDEAD_B is translated to the physical page address 0x8888, then a prefetch request can be issued to, for example, physical addresses 0x888_8000, 0x888_8100, and 0x888_8FF0.

[0154] Figure 12 This is a flowchart illustrating a method for issuing a prefetch request for a memory location protected by the particle protection check circuit 50. At step 1200, the target physical address for the memory access request is obtained. This memory access request can be an on-demand access request or a prefetch request. The target physical address can be obtained from the access request itself (directly specifying the PA) or from address translation circuit 28, which translates the VA specified by the memory access request into the PA (and for page-level translations, combines the translated PA with an offset bit from the specified VA).

[0155] At step 1202, the obtained PA is used to initiate a particulate protection check. The particulate protection check involves determining which PAS is associated with the PA obtained at step 1200. This can be based, for example, on one or more PAS identifier bits in the PA, or on the domain in which the PA was issued, such as... Figure 7 As shown. The particle protection check then involves determining whether a PAS is allowed to access a target particle containing the physical address of that PA. This check is based on entries in the Particle Protection Table (GPT) associated with the target particle's physical address, which can be obtained based on the target PA, and indicates which PASs are allowed to access the target particle's physical address. Therefore, initiating the particle protection check at step 1202 may include obtaining particle protection information corresponding to the target PA.

[0156] For example, at a timing independent of the particle protection check process, a prefetch operation is initiated at step 1204 to fetch target data at the memory location identified by PA into a cache, such as an L1 data cache, an L1 instruction cache, or an L2 cache.

[0157] Once the particle protection information has been obtained, at step 1206, the extracted particle protection information is used to determine whether the selected PAS is allowed to access the target particle, including the physical address of the target PA.

[0158] Therefore, it should be understood that the latency of executing GPC can overlap with the latency of retrieving target data from memory without compromising system security or requiring complex logic components to monitor which data values ​​are accessible at a given time. Although Figure 12 Steps 1202 and 1204 are shown to be executed simultaneously; however, it should be understood that the timing of these steps is independent of each other, and any step may be executed before the other. Furthermore, the timing of steps 1204 and 1206 is unrelated, and in some cases, the particle protection check may be completed before the prefetch operation is finished.

[0159] Figure 13 This is a flowchart illustrating a method performed by address translation circuit 28, including prefetch circuit 56, in response to an on-demand access request.

[0160] At step 1300, the address translation circuitry receives a translation request from the requester corresponding to the on-demand access request. This request specifies the target virtual address (VA) at the granularity of a cache line (i.e., including offset bits) and is issued within a specific domain. Although in Figure 13 It is not indicated in the text, but at this step, if no transformation is provided in the TLB entry, the request can be added to the transformation request buffer 59 and the prefetchable cache line buffer 58.

[0161] At step 1302, when the target VA is translated, for example if it is the next address in the translation request buffer 59, the address translation circuit translates the target VA to a target physical address in the selected physical address space. The request in the translation request buffer may have already missed in the TLB, and therefore the translation may involve page table roaming to obtain page table information from memory.

[0162] After the target PA has been obtained, at step 1304, a prefetch operation is initiated to fetch the target data corresponding to the target PA into the cache. This may involve combining the offset bits from the target VA with the translated physical page address to determine the target PA for prefetching at the granularity of cache lines. At this stage, if multiple entries corresponding to the target virtual memory page exist in the prefetchable cache line buffer 58, several prefetch requests can be issued to the memory.

[0163] Independent of the initiation of the prefetch operation, at step 1306, a particle protection check is initiated for the target PA in the selected PAS (e.g., as described with reference to step 1202).

[0164] At step 1308, it is determined whether the particle protection check has been completed. If so, at step 1310, it is determined whether the selected PAS is allowed to access the target particle, including the physical address of the target PA.

[0165] If the selected PAS is not allowed to access the target particle including the physical address of the target PA, then at step 1312, an address translation response indicating a particle protection failure is provided to the requester.

[0166] If the selected PAS is allowed to access the target granular memory including the physical address of the target PA, then at step 1314, an address translation response is provided to the requester indicating that there is no granular protection fault and that the PA being translated (at the granularity of a storage page). The translation response and the result of the granular protection check can be assigned to the TLB, allowing future memory access requests to be processed more quickly.

[0167] Figure 14 This is a flowchart illustrating the method executed by address translation circuit 28 in response to a prefetch request.

[0168] At step 1400, the address translation circuit receives a translation request corresponding to a prefetch request issued by the prefetch engine 54. This request specifies a target virtual address (VA) and is issued within a specific domain.

[0169] At step 1402, when the target VA is translated, for example if it is the next address in the translation request buffer 59, the address translation circuit translates the target VA into a target physical address in the selected physical address space.

[0170] After the target PA has been obtained, at step 1404, an address translation response instructing the translation of the PA is provided (e.g., to the prefetch engine). This allows the prefetch engine to initiate a prefetch operation to fetch the target data into the cache even before the GPC result is known. Figure 14 In this method, an address translation response is returned before GPC completes, while... Figure 13 In this method, an address translation response is returned after the GPC, and therefore the same address translation circuit can be configured to provide address translation responses at different times depending on the type of request.

[0171] Independent of the transmit address translation response, at step 1406, a particle protection check is initiated for the target PA in the selected PAS (e.g., as described with reference to step 1202).

[0172] At step 1408, it is determined whether the particle protection check has been completed. If so, at step 1410, it is determined whether the selected PAS is allowed to access the target particle, including the physical address of the target PA.

[0173] If the selected PAS is not allowed to access the target granularity including the physical address of the target PA, a further response indicating a granular protection fault can be provided at step 1412. If the selected PAS is allowed to access the target granularity including the physical address of the target PA, an address translation response is provided at step 1414 indicating that no granular protection fault exists and including the PA to be translated (at the granularity of a storage page). The translation response and the result of the granular protection check can be allocated to the TLB, allowing future memory access requests to be processed more quickly. Therefore, even after an address translation response has been provided, continuing GPC for prefetch requests can be used to allow the results of the GPC to be cached in the TLB, allowing future memory access requests to be processed more quickly.

[0174] Figure 15 This is a flowchart illustrating a method performed by address translation circuit 28, which does not provide prefetch circuit 56, in response to an on-demand access request.

[0175] Steps 1500 and 1502 are the same as steps 1300 and 1302.

[0176] At step 1504, since the address translation circuit 28 does not provide the prefetch circuit 565, it cannot initiate a prefetch operation. Instead, at step 1504, a partial address translation response is returned to the requester, thereby providing a physical address translation of the target virtual address (at least at the granularity of a storage page, without requiring the address translation circuit to consider offset bits), but not providing the result of the granularity protection check.

[0177] Independent of issuing a partial address translation response, at step 1506, a particle protection check is initiated for the target PA in the selected PAS (e.g., as described with reference to step 1202).

[0178] At step 1508, it is determined whether the particle protection check has been completed. If so, at step 1510, it is determined whether the selected PAS is allowed to access the target particle, including the physical address of the target PA.

[0179] If the selected PAS is not allowed to access the target granules including the physical address of the target PA, then at step 1512, a response indicating a granule protection failure is provided to the requester. This response may allow the requester to internally indicate that the converted PA cannot be used to access the target data in the selected PAS, or it may, for example, allow the requester to invalidate any conversions of the PAs in the selected PAS (because these conversions would not be useful).

[0180] If the selected PAS is permitted to access the target granules including the physical address of the target PA, then at step 1514, a response indicating that no granule protection fault exists is provided to the requester. This allows the requester to internally indicate that the target PA can be used to access target data in the selected PAS, and may, for example, allow the requester to internally cache translation for future memory access requests.

[0181] Figure 16 This is a flowchart illustrating a method executed by a requester 40 responsible for issuing on-demand access requests to an address translation circuit 28 having a prefetch circuit 56.

[0182] At step 1600, an address translation request is sent to address translation circuit 28 for the on-demand access request. This address translation request specifies the VA (Version Address) issued in a specific domain. The address translation circuit processes the request, as follows: Figure 13 As shown.

[0183] At step 1602, a conversion response is received from the address translation circuit, which provides the results of the converted PA and GPC.

[0184] At step 1604, it is determined whether a particle protection fault exists. If so, the converted PA cannot access the target data in the selected PAS, and therefore no further memory access is performed at step 1606.

[0185] If it is determined at step 1604 that there is no particle protection fault and therefore the selected PAS is allowed to access the target particle of the PA, then at step 1608, the on-demand access request can be reloaded into the micro TLB of the storage address translation (a local copy of the address translation information provided at the load / store unit 26 in fetch phase 6), hit in the micro TLB, and thus trigger a cache access to access the target data.

[0186] Cache accesses can hit the target data in the cache (if the prefetch operation has already completed), and therefore allow faster access to the target data compared to if the prefetch operation has not yet been performed. If the prefetch operation has not yet completed, on-demand access requests can be merged with the prefetch operation (which still allows data to be obtained faster than if the prefetch operation has not even started).

[0187] Figure 17 This is a flowchart illustrating a method executed by a requester 40, which is responsible for issuing on-demand access requests to an address translation circuit 28 that does not have a prefetch circuit 56.

[0188] At step 1700, in response to an on-demand access request, an address translation request is sent to address translation circuit 28, specifying the VA issued in a specific domain. The address translation circuit processes the request, as follows: Figure 15 As shown.

[0189] At step 1702, a partial address translation response is received from the address translation circuit. This partial address translation response provides the PA of the translation but does not provide the result of the GPC.

[0190] At step 1704, a partial TLB entry may be allocated (e.g., in the micro TLB local to LSU 26 or the requester's fetch circuit 6). This partial TLB entry records address translations but not GPC results. The partial TLB entry may be used only to initiate prefetch requests and not for on-demand access requests, since it is not yet known whether the target data is accessible by the PA in the selected PAS.

[0191] At step 1706, the requester initiates a prefetch operation based on the PA returned in the partial address translation response. For example, an on-demand access request can be replayed and a partial entry in the micro TLB can be hit to initiate a prefetch operation to the target PA.

[0192] At step 1708, the result of a particle protection check is received from address translation circuit 28 or particle protection check circuit 50. At step 1710, it is determined whether a particle protection fault exists. If so, the translated PA cannot access the target data in the selected PAS, and therefore at step 1712, the partial TLB entry allocated to the translated PA is invalidated because it is not a useful translation.

[0193] If it is determined at step 1710 that there is no particle protection fault and therefore the selected PAS is allowed to access the target particles of the PA, then at step 1714, a partial TLB entry can be upgraded to a full TLB entry that records the results of the PA and GPC.

[0194] Therefore, in response to future on-demand access requests (e.g., a replay of the on-demand access request issued at step 1700), a cache access request can be issued to PA to access the target data. The cache access can hit the target data in the cache (if the prefetch operation initiated at step 1706 has completed), and thus allows for faster access to the target data compared to requesting data only after the GPC result has been received if the prefetch operation has not yet been performed. If the prefetch operation has not yet completed, the on-demand access request can be merged with the prefetch operation.

[0195] Figure 18 This is a flowchart illustrating the method executed by the prefetch engine 54 that issues the prefetch request.

[0196] At step 1800, a prefetch request for the specified virtual address is issued. An address translation request is sent to the address translation circuit to request the physical address for translation in response to the prefetch request. The prefetch request can be issued speculatively, for example, in response to the prediction that the target virtual address will be accessed by future on-demand access instructions, and therefore performance can be improved by prefetching the target data into a cache. The address translation circuit... Figure 14 The method handles the request.

[0197] At step 1802, the prefetch circuit receives an address translation response that provides a PA corresponding to the target VA. At step 1804, the prefetch engine initiates a prefetch operation based on the PA of the translation to fetch the target data into the cache (e.g., by replaying the prefetch request and hitting the entry in the prefetch engine's local micro TLB and storing the returned PA).

[0198] At step 1806, independent of the timing of the prefetch operation, a GPC result response is provided by address translation circuit 28 or particle protection check circuit 50, and the GPC result response can be used at step 1808 to allocate an entry in the TLB to cache the GPC result of the PA in the selected PAS.

[0199] Figure 19 This is a flowchart illustrating a method performed by address translation circuit 28, including prefetch circuit 56, to issue a prefetch request to a set of target physical addresses using a prefetchable cache line buffer 58.

[0200] At step 1900, address translation circuit 28 translates the target VA (e.g., from an on-demand access request or a prefetch request) into the target PA in the selected PAS.

[0201] At step 1902, a lookup is performed in the prefetchable cache line buffer 58 to identify the set of entries corresponding to the same virtual memory page as the target VA (and therefore the same physical memory page as the target PA).

[0202] At step 1904, a physical address is calculated for each entry among the entries identified in step 1902. Specifically, the offset bits indicated in each entry are added to the physical memory page address determined in step 1900, thus determining multiple physical addresses within the same memory page at the cache line granularity.

[0203] At step 1906, multiple prefetch requests are issued using the addresses calculated in step 1904 to fetch target data corresponding to multiple access requests belonging to the same storage page in the address translation queue into the cache.

[0204] The concepts described herein can be specifically embodied in a system comprising at least one packaged chip. The previously described device is implemented in this at least one packaged chip (either in a specific chip of the system or distributed across more than one packaged chip). The at least one packaged chip is assembled on a board along with at least one system component. Chip-containing products may include systems assembled on additional boards with at least one other product component. The system or chip-containing product may be assembled into a housing or onto a structural support (such as a frame or blade).

[0205] like Figure 20As shown, one or more packaged chips 400 are manufactured by a semiconductor chip manufacturer, wherein the devices described above are implemented on a single chip or distributed across two or more chips. In some examples, the chip product 400 manufactured by the semiconductor chip manufacturer may be provided as a semiconductor package, which includes a protective housing (e.g., made of metal, plastic, glass, or ceramic) housing the semiconductor device implementing the aforementioned devices, and connectors such as pads, solder balls, or pins for connecting the semiconductor device to the external environment. Where more than one chip 400 is provided, these chips may be provided as separate integrated circuits (provided as separate packages), or may be packaged by a semiconductor provider into a multi-chip semiconductor package (e.g., using interposers, or by using three-dimensional integration to provide a multi-layer chip product comprising two or more vertically stacked integrated circuit layers).

[0206] In some examples, an assembly of chiplets (i.e., modular chips that provide chip functionality when combined) may be referred to as a chip itself. Chipslets may be packaged individually in a semiconductor package and / or packaged together with other chiplets in a multi-chiplet semiconductor package (e.g., using interpolators, or by using three-dimensional integration to provide a multi-layer chiplet product comprising two or more vertically stacked integrated circuit layers).

[0207] One or more packaged chips 400 are mounted on a board 402 together with at least one system component 404 to provide system 406. For example, the board may include a printed circuit board. The board substrate may be made of any of a variety of materials, such as plastic, glass, ceramic, or flexible substrate materials such as paper, plastic, or textile materials. At least one system component 404 includes one or more external components that are not part of the one or more packaged chips 400. For example, at least one system component 404 may include any or more of the following: another packaged chip (e.g., supplied by a different manufacturer or manufactured at a different process node), an interface module, a resistor, a capacitor, an inductor, a transformer, a diode, a transistor, and / or a sensor.

[0208] A chip-containing product 416 is manufactured, comprising a system 406 (including a board 402, one or more chips 400, and at least one system component 404) and one or more product components 412. Product components 412 include one or more additional components that are not part of system 406. As an example, in a non-exhaustive list, one or more product components 412 may include user input / output devices such as keyboards, touchscreens, microphones, speakers, displays, haptic devices, etc.; wireless communication transmitters / receivers; sensors; actuators for actuating mechanical motion; thermal control devices; additional packaged chips; interface modules; resistors; capacitors; inductors; transformers; diodes; and / or transistors. System 406 and one or more product components 412 may be assembled on an additional board 414.

[0209] Plate 402 or another plate 414 may be disposed on or within the equipment housing or other structural support (e.g., frame or blade) to provide a product that can be handled by a user and / or intended for operational use by personnel or company.

[0210] System 406 or chip-containing product 416 can be at least one of the following: end-user product, machine, medical device, computing or telecommunications infrastructure product, or automated control system. For example, as a non-exhaustive list, a chip-containing product can be any of the following: telecommunications equipment, mobile phone, tablet computer, laptop computer, computer, server (e.g., rack server or blade server), infrastructure equipment, networking equipment, vehicle or other automotive product, industrial machine, consumer device, smart card, credit card, smart glasses, avionics equipment, robotic equipment, camera, television, smart TV, DVD player, set-top box, wearable device, home appliance, smart meter, medical device, heating / lighting control equipment, sensor, and / or control system for controlling public infrastructure equipment (such as smart highways or traffic lights).

[0211] The concepts described herein may be embodied in computer-readable code used to manufacture devices embodying the described concepts. For example, the computer-readable code may be used in one or more stages of the semiconductor design and manufacturing process, including the electronic design automation (EDA) stage, to manufacture integrated circuits comprising devices embodying these concepts. The aforementioned computer-readable code may additionally or alternatively enable the definition, modeling, simulation, verification, and / or testing of devices embodying the concepts described herein.

[0212] For example, computer-readable code for manufacturing a device embodying the concepts described herein may be embodied in code that defines the hardware description language (HDL) representation of these concepts. For instance, the code may define a register-transfer level (RTL) abstraction of one or more logic circuits for defining a device embodying these concepts. The code may define an HDL representation of one or more logic circuits embodying the device using Verilog, SystemVerilog, Chisel, or VHDL (Very High Speed ​​Integrated Circuit Hardware Description Language) and intermediate representations such as FIRRTL. Computer-readable code may provide definitions of the concepts or other behavioral representations of the concepts embodying the concepts using system-level modeling languages ​​such as SystemC and SystemVerilog, which can be interpreted by a computer to enable simulation, functional and / or formal verification and testing of the concepts.

[0213] Additionally or alternatively, computer-readable code may define a low-level description of an integrated circuit component embodying the concepts described herein, such as one or more netlists or integrated circuit layout definitions, including representations such as GDSII. One or more netlists or other computer-readable representations of the integrated circuit component may be generated by applying one or more logic synthesis processes to the RTL representation to generate a definition for manufacturing a device embodying the invention. Alternatively or additionally, one or more logic synthesis processes may generate a bitstream from the computer-readable code to be loaded into a field-programmable gate array (FPGA) to configure the FPGA to embody the described concepts. The FPGA may be deployed for the purpose of verifying and testing the concepts prior to manufacturing integrated circuits, or the FPGA may be deployed directly in a product.

[0214] Computer-readable code may include a mixture of code representations for manufacturing apparatus, such as one or more of RTL representations, netlist representations, or other computer-readable definitions used in the semiconductor design and manufacturing process for manufacturing apparatus embodying the present invention. Alternatively or additionally, the concept may be defined in a combination of computer-readable definitions used in the semiconductor design and manufacturing process for manufacturing apparatus and computer-readable code defining instructions that will be executed by the defined apparatus once manufactured.

[0215] Such computer-readable code can be contained in any known transient computer-readable medium (such as wired or wireless transmission of code over a network) or non-transitory computer-readable medium such as semiconductors, magnetic disks, or optical disks. Integrated circuits made using computer-readable code may include components such as one or more of the following: a central processing unit, a graphics processing unit, a neural processing unit, a digital signal processor, or other components that embody the concept individually or collectively.

[0216] Some examples are illustrated in the following clauses:

[0217] 1. An apparatus, the apparatus comprising:

[0218] Particle protection check circuit, wherein the particle protection check circuit is configured as follows:

[0219] Perform a particle protection lookup based on the target physical address to obtain particle protection information associated with a target particle containing the target physical address; and

[0220] Based on the particle protection information, determine whether the target particle, associated with the target physical address and selected from multiple physical address spaces, is allowed to access the physical address; and

[0221] A prefetch circuit is configured to initiate a prefetch operation for the target physical address before the particle protection check circuit determines whether the selected physical address space is allowed to access the target particle of the physical address, so that the target data identified by the target physical address can be prefetched into the cache.

[0222] 2. The apparatus according to Clause 1, the apparatus comprising address translation circuitry that, in response to a memory access request specifying a target virtual address, translates the target virtual address into a target physical address associated with a selected physical address space.

[0223] 3. The apparatus according to Clause 2, wherein the address translation circuit responds to an on-demand memory access request that returns target data associated with the target virtual address to a requester to control the prefetch circuit to initiate the prefetch operation for the target physical address.

[0224] 4. The apparatus according to Clause 3, wherein the particle protection check circuit is configured to prevent the return of the target data to the requester in response to determining that the target particle is not allowed to access the physical address of the selected physical address space.

[0225] 5. The apparatus according to any one of clauses 3 and 4, wherein the address translation circuit is configured to provide one or more offset bits to the prefetch circuit, the one or more offset bits identifying the offset of the target physical address within a storage page.

[0226] 6. The apparatus according to any one of claims 3 to 5, the apparatus comprising a prefetchable cache line buffer configured to store a plurality of prefetchable cache line entries, each prefetchable cache line entry being identified in relation to a given on-demand memory access request waiting for translation:

[0227] At least an offset portion of a given target virtual address specified by the given on-demand memory access request, the offset portion identifying the offset of the given target virtual address within a memory page; and

[0228] Storage page identification information, which is used to associate prefetchable cache line entries, wherein the target virtual address belongs to the same storage page for the prefetchable cache line entries;

[0229] The address translation circuit is configured to initiate multiple prefetch operations to a target physical address, the target physical address being determined based on the offset portion of a target virtual address, the offset portion of the target virtual address being identified as corresponding to the same storage page based on the storage page identification information.

[0230] 7. The apparatus according to Clause 6, wherein fewer bits than the portion of the target virtual address that identifies the virtual storage page are used to specify the storage page identification information.

[0231] 8. The apparatus according to any one of clauses 3 to 7, wherein the address translation circuit includes a prefetch disable mode, wherein the address translation circuit is configured to suppress control of the prefetch circuit to initiate the prefetch operation.

[0232] 9. The apparatus according to any one of claims 3 to 8, wherein the address translation circuit is configured to indicate to the prefetch circuit whether the on-demand memory access request is a load request or a store request when controlling the prefetch circuit to initiate the prefetch operation for the target physical address.

[0233] 10. The apparatus according to Clause 2, wherein:

[0234] The address translation circuit responds to an on-demand memory access request, which returns target data associated with the target virtual address to the requester, to return a partial address translation response indicating the target physical address before the particle protection check circuit determines whether the selected physical address space is allowed to access the target particle of the physical address; and

[0235] The prefetch circuit is configured to initiate a prefetch operation for the target physical address corresponding to the on-demand memory access request based on the partial address translation response.

[0236] 11. The apparatus according to Clause 10, wherein the address translation circuit responds to the particle protection check circuit determining whether the selected physical address space is allowed to access the target particle of the physical address to return a particle protection check result response;

[0237] The particle protection check result response indicates whether the selected physical address space is allowed to access the target particle's physical address.

[0238] 12. The apparatus according to any of the preceding clauses, wherein the prefetch circuitry is configured to speculatively initiate the prefetch operation in response to a prediction that the target data will be requested by a future on-demand memory access request, the prefetch operation including fetching the target data associated with the target physical address into the cache without returning to the requester.

[0239] 13. The apparatus according to any one of claims 2 to 12, the apparatus comprising a translation backup buffer configured to cache address mapping information used by the address translation circuit to translate the target virtual address into the target physical address, wherein the granular protection check circuit is configured to perform the granular protection lookup and store identified granular protection information in the translation backup buffer, regardless of whether the prefetch circuit has initiated the prefetch operation for the target physical address.

[0240] 14. The apparatus according to any of the preceding clauses, the apparatus comprising: a Physical Alias ​​Point (PoPA) memory system component, the PoPA memory system component being configured to dealias a plurality of aliased physical addresses corresponding to the same memory system location from different physical address spaces, mapping any one of the plurality of aliased physical addresses to a dealiased physical address to be provided to at least one downstream memory system component; and

[0241] At least one pre-PoPA memory system component is provided upstream of the PoPA memory system component, wherein the at least one pre-PoPA memory system component is configured to treat the aliased physical address from a different physical address space as the aliased physical address corresponding to a different memory system location.

[0242] 15. The apparatus according to any of the preceding clauses, the apparatus comprising a physical address space selection circuit, the physical address space selection circuit being configured to select a selected physical address space for the target physical address based on at least one of the following:

[0243] Current operating domain; and

[0244] The information specified in the page table entry also provides address mapping information used by address translation circuitry to translate the target virtual address into the target physical address.

[0245] 16. The apparatus according to Clause 15, the apparatus comprising processing circuitry for processing instructions in one of a plurality of operation domains, the plurality of operation domains including at least a non-secure domain, a secure domain, a neighboring domain, and a root domain;

[0246] The plurality of physical address spaces include:

[0247] A root physical address space, which can be selected as the selected physical address space when the current domain of the processing circuit is the root domain;

[0248] A non-secure physical address space, which can be selected as the selected physical address space when the current domain of the processing circuit is any one of the non-secure domain, the secure domain, the neighboring domain, and the root domain;

[0249] A secure physical address space, which can be selected as the selected physical address space when the current domain of the processing circuit is the secure domain or the root domain; and

[0250] A domain physical address space, which can be selected as the selected physical address space when the current domain of the processing circuit is the domain domain or the root domain.

[0251] 17. A system comprising:

[0252] An apparatus according to any of the foregoing clauses implemented in at least one packaged chip;

[0253] At least one system component; and

[0254] plate,

[0255] The at least one packaged chip and the at least one system component are assembled on the board.

[0256] 18. A chip-containing product comprising the system described in Clause 17, wherein the system is assembled on an additional board together with at least one other product component.

[0257] 19. A method comprising:

[0258] Perform particle protection lookup based on the target physical address to identify particle protection information associated with a target particle that includes the target physical address;

[0259] Based on the particle protection information, determine whether the target particle, whose physical address space is associated with the target physical address and selected from multiple physical address spaces, is allowed to access the physical address; and

[0260] Before the particle protection check circuit determines whether the selected physical address space is allowed to access the target particle at the physical address, a prefetch operation is initiated for the target physical address, so that the target data identified by the target physical address can be prefetched into the cache.

[0261] 20. Computer-readable code for manufacturing an apparatus, the apparatus comprising:

[0262] Particle protection check circuit, wherein the particle protection check circuit is configured as follows:

[0263] Perform particle protection lookup based on the target physical address to identify particle protection information associated with a target particle that includes the target physical address; and

[0264] Based on the particle protection information, determine whether the target particle, associated with the target physical address and selected from multiple physical address spaces, is allowed to access the physical address; and

[0265] A prefetch circuit is configured to initiate a prefetch operation for the target physical address before the particle protection check circuit determines whether the selected physical address space is allowed to access the target particle of the physical address, so that the target data identified by the target physical address can be prefetched into the cache.

[0266] In this application, the phrase "configured as..." is used to mean that the elements of the device have a configuration capable of performing the defined operation. In this context, "configuration" means the arrangement or manner of interconnection of hardware or software. For example, the device may have dedicated hardware that provides the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured as" does not mean that the elements of the device need to be changed in any way to provide the defined operation.

[0267] In this application, a list of features beginning with the phrase “at least one of” means that any one or more of those features may be provided individually or in combination. For example, “at least one of the following: [A], [B], and [C]” covers any of the following options: A only (without B or C), B only (without A or C), C only (without A or B), a combination of A and B (without C), a combination of A and C (without B), a combination of B and C (without A), or a combination of A, B, and C.

[0268] While exemplary embodiments of the invention have been described in detail herein with reference to the accompanying drawings, it should be understood that the invention is not limited to those precise embodiments, and various changes and modifications can be made therein by those skilled in the art without departing from the scope of the invention as defined by the appended claims.

Claims

1. An apparatus, the apparatus comprising: Particle protection check circuit, wherein the particle protection check circuit is configured as follows: Perform a particle protection lookup based on the target physical address to obtain particle protection information associated with a target particle containing the target physical address; and Based on the particle protection information, determine whether the target particle, which is associated with the target physical address and selected from multiple physical address spaces, is allowed to access the physical address; and A prefetch circuit is configured to initiate a prefetch operation for the target physical address before the particle protection check circuit determines whether the selected physical address space is allowed to access the target particle of the physical address, so that the target data identified by the target physical address can be prefetched into the cache.

2. The apparatus of claim 1, the apparatus comprising an address translation circuit, the address translation circuit responding to a memory access request for a specified target virtual address by translating the target virtual address into the target physical address associated with a selected physical address space.

3. The apparatus of claim 2, wherein the address translation circuit responds to an on-demand memory access request that returns target data associated with the target virtual address to a requester to control the prefetch circuit to initiate the prefetch operation for the target physical address.

4. The apparatus of claim 3, wherein the particle protection check circuit is configured to prevent the return of the target data to the requester in response to determining that the target particle for which access to the physical address space is not permitted.

5. The apparatus of claim 3, wherein the address translation circuit is configured to provide one or more offset bits to the prefetch circuit, the one or more offset bits identifying the offset of the target physical address within a storage page.

6. The apparatus of claim 3, further comprising a prefetchable cache line buffer configured to store a plurality of prefetchable cache line entries, each prefetchable cache line entry being identified in relation to a given on-demand memory access request waiting for translation: At least an offset portion of a given target virtual address specified by the given on-demand memory access request, the offset portion identifying the offset of the given target virtual address within a memory page; and Storage page identification information, which is used to associate prefetchable cache line entries, wherein the target virtual address belongs to the same storage page for the prefetchable cache line entries; The address translation circuit is configured to initiate multiple prefetch operations to a target physical address, the target physical address being determined based on the offset portion of a target virtual address, the offset portion of the target virtual address being identified as corresponding to the same storage page based on the storage page identification information.

7. The apparatus of claim 6, wherein the storage page identification information is specified using fewer bits than the portion of the target virtual address that identifies the virtual storage page.

8. The apparatus of claim 3, wherein the address translation circuit includes a prefetch disable mode, wherein the address translation circuit is configured to suppress control of the prefetch circuit to initiate the prefetch operation.

9. The apparatus of claim 3, wherein the address translation circuit is configured to indicate to the prefetch circuit, when controlling the prefetch circuit to initiate the prefetch operation for the target physical address, whether the on-demand memory access request is a load request or a store request.

10. The apparatus according to claim 2, wherein: The address translation circuit responds to an on-demand memory access request, which returns target data associated with the target virtual address to the requester, to return a partial address translation response indicating the target physical address before the particle protection check circuit determines whether the selected physical address space is allowed to access the target particle of the physical address; and The prefetch circuit is configured to initiate a prefetch operation for the target physical address corresponding to the on-demand memory access request based on the partial address translation response.

11. The apparatus of claim 10, wherein the address translation circuit responds to the particle protection check circuit determining whether the selected physical address space is allowed to access the target particle of the physical address to return a particle protection check result response; The particle protection check result response indicates whether the selected physical address space is allowed to access the target particle's physical address.

12. The apparatus of claim 1, wherein the prefetch circuitry is configured to speculatively initiate the prefetch operation in response to a prediction that the target data will be requested by a future on-demand memory access request, the prefetch operation comprising fetching the target data associated with the target physical address into the cache without returning a request to the requester.

13. The apparatus of claim 2, the apparatus comprising a translation backup buffer configured to cache address mapping information used by the address translation circuit to translate the target virtual address into the target physical address, wherein the granular protection check circuit is configured to perform the granular protection lookup and store identified granular protection information in the translation backup buffer, regardless of whether the prefetch circuit has initiated the prefetch operation for the target physical address.

14. The apparatus of claim 1, wherein the apparatus comprises: A Physical Alias ​​Point (PoPA) memory system component is configured to dealias multiple alias physical addresses corresponding to the same memory system location from different physical address spaces, mapping any one of the multiple alias physical addresses to a dealiased physical address to be provided to at least one downstream memory system component; and At least one pre-PoPA memory system component is provided upstream of the PoPA memory system component, wherein the at least one pre-PoPA memory system component is configured to treat the aliased physical address from a different physical address space as the aliased physical address corresponding to a different memory system location.

15. The apparatus of claim 1, further comprising a physical address space selection circuit, the physical address space selection circuit being configured to select a selected physical address space for the target physical address based on at least one of the following: Current operating domain; and The information specified in the page table entry also provides address mapping information used by address translation circuitry to translate the target virtual address into the target physical address.

16. The apparatus of claim 15, the apparatus comprising a processing circuit for processing an instruction in one of a plurality of operation domains, the plurality of operation domains including at least a non-secure domain, a secure domain, a neighboring domain, and a root domain; The plurality of physical address spaces include: A root physical address space, which can be selected as the selected physical address space when the current domain of the processing circuit is the root domain; A non-secure physical address space, which can be selected as the selected physical address space when the current domain of the processing circuit is any one of the non-secure domain, the secure domain, the neighboring domain, and the root domain; A secure physical address space, which can be selected as the selected physical address space when the current domain of the processing circuit is the secure domain or the root domain; and A domain physical address space, which can be selected as the selected physical address space when the current domain of the processing circuit is the domain or the root domain.

17. A system comprising: The apparatus of claim 1 implemented in at least one packaged chip; At least one system component; and plate, The at least one packaged chip and the at least one system component are assembled on the board.

18. A chip-containing product comprising the system of claim 17, wherein the system is assembled on an additional board together with at least one other product component.

19. A method comprising: Perform particle protection lookup based on the target physical address to identify particle protection information associated with a target particle that includes the target physical address; Based on the particle protection information, determine whether the target particle, which is associated with the target physical address and selected from multiple physical address spaces, is allowed to access the physical address; as well as Before the particle protection check circuit determines whether the selected physical address space is allowed to access the target particle at the physical address, a prefetch operation is initiated for the target physical address, so that the target data identified by the target physical address can be prefetched into the cache.

20. A non-transitory computer-readable medium storing computer-readable code for manufacturing an apparatus, the apparatus comprising: Particle protection check circuit, wherein the particle protection check circuit is configured as follows: Perform particle protection lookup based on the target physical address to identify particle protection information associated with a target particle that includes the target physical address; and Based on the particle protection information, determine whether the target particle, which is associated with the target physical address and selected from multiple physical address spaces, is allowed to access the physical address; and A prefetch circuit is configured to initiate a prefetch operation for the target physical address before the particle protection check circuit determines whether the selected physical address space is allowed to access the target particle of the physical address, so that the target data identified by the target physical address can be prefetched into the cache.

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