Computing system architecture and integrated circuit package including same

Abstract

The invention relates to a computing system architecture and an integrated circuit package including the same. A computing system includes a base die, a host device, and a stacked memory structure. The base die has a first surface and a second surface, and includes a first circuit block and a second circuit block. The host device is disposed to overlap at least a portion of the first circuit block of the base die. The stacked memory structure is disposed to overlap at least a portion of the second circuit block of the base die. The host device and the first circuit block of the base die are coupled through a first signal transmission path. Coupling is performed between the first circuit block and the second circuit block and between the second circuit block and the stacked memory structure through a second signal transmission path.

Description

[0001] Cross-references to related applications

[0002] This application is a partial continuation of U.S. Patent Application No. 18 / 955,468, filed November 21, 2024, and U.S. Provisional Application No. 63 / 697758, filed September 23, 2024, which are incorporated herein by reference in their entirety. Technical Field

[0003] The various embodiments generally relate to integrated circuit technology, and more specifically to computing system architectures with effective bus connectivity and integrated circuit packages including therein. Background Technology

[0004] Generally, a computing system may have a structure in which a host device and a memory device are electrically connected. The host device may include a processing core and a memory controller. The memory device may include a memory cell array. The host device may be electrically connected to the memory device via a memory channel, where the memory channel uses serial data transmission. Serial data transmission minimizes the number of data signal transmission lines included in the memory channel and reduces the deviation between the data signal and the clock signal. However, for serial data transmission, the host device may require a controller physical interface (e.g., a Double Data Rate (DDR) PHY), while the memory device may require a memory physical interface. For example, both the controller physical interface and the memory physical interface may include a serializer-deserializer (SerDes).

[0005] The controller physical interface can convert parallel data generated by the processing core and memory controller into serial data, and can transmit the serial data to the memory device via memory channels. Furthermore, the controller physical interface can convert serial data transmitted from the memory device into parallel data, and provide the parallel data to the memory controller and host device. The memory physical interface can convert parallel data output from the memory cell array into serial data, and transmit the serial data to the host device via memory channels. The memory physical interface can convert serial data transmitted from the host device through memory channels into parallel data, and can provide the parallel data to the memory cell array. In environments where both the host device and memory device are manufactured as single chips or in single packages, the above-described structure of traditional computing systems may be the optimal signal transmission structure. However, in environments where advanced packaging technologies increase the number of signal transmission lines electrically connecting the host device and memory device, and where host devices and memory devices are manufactured in chiplets, a computing system architecture capable of more efficiently connecting the host device and memory device is needed. Summary of the Invention

[0006] In one embodiment, a computing system can include a base die, a host device, a stacked memory structure, a first signal transmission path, and a second signal transmission path. The base die can have a first surface and a second surface, and can include a first circuit block and a second circuit block. The host device can be disposed to overlap at least a portion of the first circuit block of the base die. The stacked memory structure can be disposed to overlap at least a portion of the second circuit block of the base die. The host device and the first circuit block of the base die can be coupled by the first signal transmission path, and the first circuit block and the second circuit block, and the second circuit block and the stacked memory structure can be coupled by the second signal transmission path.

[0007] In one embodiment, an integrated circuit package can include a substrate, a base die, a host device, a stacked memory structure, a first signal transmission path, and a second signal transmission path. The base die can be mounted on a top of the substrate, and can include a first circuit block and a second circuit block. The host device can be bonded to overlap at least a portion of the first circuit block of the base die. The stacked memory structure can be bonded to overlap at least a portion of the second circuit block of the base die. The host device and the first circuit block of the base die can be coupled by the first signal transmission path, and the first circuit block and the second circuit block, and the second circuit block and the stacked memory structure can be coupled by the second signal transmission path. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 A diagram to show a configuration of a computing system according to an embodiment of the present disclosure.

[0009] Figure 2 A diagram to show Figure 1 A diagram to show a connection relationship between a memory controller, an interface circuit, and a memory device shown in

[0010] Figure 3 A diagram to show Figure 2 A block diagram to show a configuration of an address control circuit shown in

[0011] Figure 4 A block diagram to show Figure 2 A block diagram to show a configuration of a data input / output circuit shown in

[0012] Figure 5 A block diagram to show Figure 2 A block diagram to show a configuration of a clock control circuit shown in

[0013] Figure 6 A diagram to show a configuration of a memory die according to an embodiment of the present disclosure.

[0014] Figure 7 A diagram to show a configuration of a computing system according to an embodiment of the present disclosure.

[0015] Figure 8 FIG. 1 is a diagram showing a configuration of a computing system according to an embodiment of the present disclosure.

[0016] Figure 9A FIG. 2 is a diagram showing a configuration and connection relationship of an integrated circuit package according to an embodiment of the present disclosure.

[0017] Figure 9B FIG. 3 is a diagram showing a configuration and connection relationship of an integrated circuit package according to an embodiment of the present disclosure.

[0018] Figure 9C FIG. 4 is a diagram showing a configuration and connection relationship of an integrated circuit package according to an embodiment of the present disclosure.

[0019] Figure 9D FIG. 5 is a diagram showing a configuration and connection relationship of an integrated circuit package according to an embodiment of the present disclosure.

[0020] Figure 9E FIG. 6 is a diagram showing a configuration and connection relationship of an integrated circuit package according to an embodiment of the present disclosure.

[0021] Figure 10A FIG. 7 is a diagram showing a configuration and connection relationship of an integrated circuit package according to an embodiment of the present disclosure.

[0022] Figure 10B FIG. 8 is a diagram showing a configuration and connection relationship of an integrated circuit package according to an embodiment of the present disclosure.

[0023] Figure 10C FIG. 9 is a diagram showing a configuration and connection relationship of an integrated circuit package according to an embodiment of the present disclosure.

[0024] Figure 10D FIG. 10 is a diagram showing a configuration and connection relationship of an integrated circuit package according to an embodiment of the present disclosure.

[0025] Figure 10E FIG. 11 is a diagram showing a configuration and connection relationship of an integrated circuit package according to an embodiment of the present disclosure.

[0026] Figure 10F FIG. 12 is a diagram showing a configuration and connection relationship of an integrated circuit package according to an embodiment of the present disclosure.

[0027] Figure 10G FIG. 13 is a diagram showing a configuration and connection relationship of an integrated circuit package according to an embodiment of the present disclosure.

[0028] Figure 10H FIG. 14 is a diagram showing a configuration and connection relationship of an integrated circuit package according to an embodiment of the present disclosure.

[0029] Figure 101FIG. 1 is a diagram showing a configuration of an integrated circuit package according to an embodiment of the present disclosure.

[0030] Figure 10J FIG. 1 is a diagram showing a configuration of an integrated circuit package according to an embodiment of the present disclosure.

[0031] Figure 10K FIG. 1 is a diagram showing a configuration of an integrated circuit package according to an embodiment of the present disclosure.

[0032] Figure 10L FIG. 1 is a diagram showing a configuration of an integrated circuit package according to an embodiment of the present disclosure.

[0033] Figure 10M FIG. 1 is a diagram showing a configuration of an integrated circuit package according to an embodiment of the present disclosure.

[0034] Figure 10N FIG. 1 is a diagram showing a configuration of an integrated circuit package according to an embodiment of the present disclosure.

[0035] Figure 11 FIG. 1 is a diagram showing a configuration of an integrated circuit package according to an embodiment of the present disclosure.

[0036] Figure 12 FIG. 1 is a diagram showing a configuration of an integrated circuit package according to an embodiment of the present disclosure.

[0037] Figures 13A-13C FIG. 1 is a diagram showing a configuration of an integrated circuit package according to an embodiment of the present disclosure.

[0038] Figures 14A-14C FIG. 1 is a diagram showing a configuration of an integrated circuit package according to an embodiment of the present disclosure.

[0039] Figures 15A-15C FIG. 1 is a diagram showing a configuration of an integrated circuit package according to an embodiment of the present disclosure.

[0040] Figures 16A-16C FIG. 1 is a diagram showing a configuration of an integrated circuit package according to an embodiment of the present disclosure.

[0041] Figures 17A-17C FIG. 1 is a diagram showing a configuration of an integrated circuit package according to an embodiment of the present disclosure.

[0042] Figure 18 FIG. 1 is a diagram showing a configuration of an integrated circuit package according to an embodiment of the present disclosure.

[0043] Figure 19 FIG. 1 is a diagram showing a configuration of an integrated circuit package according to an embodiment of the present disclosure.

[0044] Figure 20A FIG. 1 is a diagram showing a configuration of an integrated circuit package according to an embodiment of the present disclosure.

[0045] Figure 20B is a diagram illustrating a cross-sectional view of a computing system taken along line A-A' of Figure 20A

[0046] Figure 20C is a diagram illustrating a schematic block diagram of a computing system according to embodiments of the present disclosure.

[0047] Figure 20D is a diagram illustrating a schematic plan view of a base die structure of Figure 20A

[0048] Figure 20E is a diagram illustrating a perspective view of a main portion of a signal transmission path of a computing system according to embodiments of the present disclosure. Figure 20A

[0049] Figure 21A is a diagram illustrating a schematic block diagram of a computing system according to embodiments of the present disclosure.

[0050] Figure 21B is a diagram illustrating a perspective view of a main portion of a computing system according to embodiments of the present disclosure.

[0051] Figure 22A is a diagram illustrating a perspective view of a main portion of a computing system according to embodiments of the present disclosure.

[0052] Figure 22B is a diagram illustrating a schematic plan view of a base die structure of Figure 22A

[0053] Figure 22C is a diagram illustrating a plan view of a base die structure including an extended base die according to embodiments of the present disclosure.

[0054] Figure 23A is a diagram illustrating a perspective view of a main portion of a computing system according to embodiments of the present disclosure.

[0055] Figure 23B is a diagram illustrating a schematic plan view of a base die structure of Figure 23A

[0056] Figure 24 is a diagram illustrating a schematic plan view of a base die structure including an extended base die according to embodiments of the present disclosure.

[0057] Figure 25 is a diagram illustrating a schematic plan view of an extended monolithic base die according to embodiments of the present disclosure.

[0058] ​​​​​Figures 26-28 This is a schematic perspective view illustrating a computing system according to an embodiment of the present disclosure. Detailed Implementation

[0059] Figure 1 This is a diagram illustrating the configuration of a computing system according to an embodiment of the present disclosure. See also... Figure 1 The computing system 100 may include a host 110, a memory controller 120, interface circuitry 130, and a memory device 140. The host 110 may generate an access request to the memory device 140 in response to input from a user (e.g., the execution of an application or software). The access request may include write requests and read requests. The host 110 may include any computing architecture best suited for executing the application required by the user. For example, the host 110 may include at least one of the following: a central processing unit (CPU), a graphics processing unit (GPU), a multimedia processor (MMP), a digital signal processor (DSP), an application processor (AP), a data processing unit (DPU), a neural processing unit (NPU), a system-on-a-chip (SoC), or any combination of two or more of the above. The host 110 may be electrically connected to the memory controller 120 via a first bus 150. The first bus 150 may be any set of signal transmission lines for electrically connecting the host 110 and the memory controller 120. For example, the first bus 150 may include at least one of Advanced Scalable Interface (AXI), Universal Chip Interconnect (UCIe), Advanced Microcontroller Bus Architecture (AMBA), Super Path Interconnect (UPI), Infinite Architecture, and NVLINK.

[0060] The memory controller 120 can be electrically connected to the host 110 through a first bus 150. The memory controller 120 can facilitate data transfer between the host 110 and the memory device 140. The memory controller 120 can receive write requests and read requests from the host 110 through the first bus 150, and can generate or receive various control signals for accessing the memory device 140 based on the requests. For example, the various control signals can include address signals, command signals, write data signals, read data signals, clock signals, and the like. The memory controller 120 can be electrically connected to the interface circuit 130 through a second bus 160. The second bus 160 can include a first data bus 161. The first data bus 161 can transfer write data signals from the memory controller 120 to the interface circuit 130, and can transfer read data signals from the interface circuit 130 to the memory controller 120. The memory controller 120 and the interface circuit 130 can communicate data in parallel through the first data bus 161. In an embodiment, the memory controller 120 and the interface circuit 130 can communicate data partially in parallel through the first data bus 161, i.e., a combination of serial data communication and parallel data communication. The remaining portion of the second bus 160, i.e., other than the first data bus 161, can transfer address signals, command signals, clock signals, and the like from the memory controller 120 to the interface circuit 130.

[0061] The interface circuit 130 can be electrically connected between the memory controller 120 and the memory device 140. The interface circuit 130 can relay data transmissions between the memory controller 120 and the memory device 140 and signal transmissions to and from the memory controller 120 and the memory device 140. The interface circuit 130 can convert a variety of signals received from the memory controller 120 to generate signals suitable for use by the memory device 140 (e.g., serialization or deserialization). The interface circuit 130 can convert signals received from the memory device 140 to generate signals suitable for use by the memory controller 120 (e.g., serialization or deserialization). The interface circuit 130 can be electrically connected to the memory controller 120 by a second bus 160. The interface circuit 130 can receive address signals, command signals, clock signals, and write data signals from the memory controller 120 by the second bus 160, and can transmit read data signals to the memory controller 120. The interface circuit 130 can receive write data signals from the memory controller 120 by a first data bus 161, and can transmit read data signals to the memory controller 120 by the first data bus 161. The interface circuit 130 can be electrically connected to the memory device 140 by a third bus 170. Through the third bus 170, the interface circuit 130 can provide address signals, command signals, clock signals, and memory data signals received from the memory controller 120 to the memory device 140, and can receive memory data signals from the memory device 140. The third bus 170 can include a second data bus 171. The second data bus 171 can transmit memory data signals from the interface circuit 130 to the memory device 140, and can transmit memory data signals from the memory device 140 to the interface circuit 130. The third bus 170, other than the second data bus 171, can transmit address signals, command signals, clock signals, and the like from the interface circuit 130 to the memory device 140. The interface circuit 130 can generate memory data signals based on write data signals received from the memory controller 120, and can generate read data signals based on memory data signals received from the memory device 140. The interface circuit 130 and the memory device 140 can perform parallel data communication through the second data bus 171. The interface circuit 130 and the memory device 140 can perform full parallel data communication through the second data bus 171.

[0062] The memory device 140 can be electrically connected to the interface circuit 130 through a third bus 170. Through the third bus 170, the memory device 140 can receive an address signal, a command signal, a clock signal, and a memory data signal from the interface circuit 130, and can transmit a memory data signal to the interface circuit 130. The memory device 140 can transmit a memory data signal to the interface circuit 130 through a second data bus 171, and can receive a memory data signal transmitted from the interface circuit 130 through the second data bus 171. The memory device 140 can include a memory cell array, and a specific region of the memory cell array can be accessed based on an address signal. The memory device 140 can perform a write operation and a read operation based on a command signal. The write operation can be an operation of storing a memory data signal transmitted from the interface circuit 130 in an accessed region of the memory cell array based on an address signal. The read operation can be an operation of providing data stored in an accessed region of the memory cell array to the interface circuit 130 as a memory data signal based on an address signal.

[0063] The memory device 140 can include at least one memory die. The memory device 140 can include one memory die, or can include two or more memory dies disposed on one interposer and / or substrate. When the memory device includes two or more memory dies, the two or more memory dies can independently form a plurality of channels, and the plurality of channels can be independently electrically connected to the interface circuit 130. There can be a plurality of third buses 170 corresponding to the number of channels. In an embodiment, two or more memory dies can form one common channel, and can be electrically connected to the interface circuit 130 in common. In an embodiment, the memory device 140 can include a plurality of memory groups, a memory group including two or more memory dies, and the plurality of memory groups can form a plurality of channels. The memory dies included in the plurality of memory groups can form a common channel. A plurality of third buses 170 corresponding to the number of channels can be provided.

[0064] In a conventional computing system, a memory controller and a memory device are electrically connected through a high-speed serial bus, and the memory controller and the memory device perform high-speed serial data communication. The high-speed serial bus has an advantage of lower implementation cost and a reduced number of signal transmission lines required. However, the high-speed serial bus has limitations in expanding data bandwidth, and the integrity of a signal transmitted through the high-speed serial bus can be degraded as the frequency of a computing system increases. In addition, in order to perform serial data communication through the high-speed serial bus, the memory controller and the memory device must be equipped with a serializer-deserializer (SerDes). In addition, in order to transmit a symbol-based data signal, such as PAM (Pulse Amplitude Modulation), the memory controller and the memory device must be equipped with a dedicated data encoder and a data decoder in addition to the SerDes. As the trend of miniaturization of integrated circuits continues, the additional circuitry required for serial data communication can impose a heavy burden on a host device and a memory device including the memory controller.

[0065] By using a substrate and / or an interposer having a plurality of signal transmission lines and development of advanced packaging technology, the physical limitation of the number of signal transmission lines can be alleviated. For example, in the computing system 100, the memory controller 120 can be electrically connected to the memory device 140 through a parallel bus via the interface circuit 130, and can perform parallel data communication with the memory device 140. When performing parallel data communication between the memory controller 120 and the memory device 140, the data bandwidth can be greatly increased, and the memory device 140 can provide data required for performing a computing operation to the host 110 faster. As artificial intelligence (AI) technology advances, the amount of data that the host 110 needs to process at a time is increasing, and thus increasing the data bandwidth between the memory controller 120 and the memory device 140 can be a key factor in optimizing the performance of the host 110. In addition, when the memory controller 120 and the memory device 140 perform parallel data communication via the interface circuit 130, the memory controller 120 and the memory device 140 can not require additional circuitry, such as a SerDes, a data encoder, and a data decoder. Accordingly, the number and / or size of computing circuits can be increased, and the increment of the computing circuits can improve the computing performance of the host 110. In addition, by forming a larger number of memory cells using the same area, the area of a memory die can be reduced, or the data storage capacity of the memory die can be increased.

[0066] In computing system 100, the clock rate of second bus 160 can be greater than or equal to the clock rate of third bus 170. The clock rate of a bus can refer to the clock frequency of the bus and / or the clock period of the bus. The clock frequency of a bus and / or the clock period of a bus can define the duration of a signal transmitted over the bus. The higher the clock frequency of a bus and the shorter the clock period of a bus, the shorter the duration of a signal transmitted over the bus. The lower the clock frequency of a bus and the longer the clock period of a bus, the longer the duration of a signal transmitted over the bus. Second bus 160 can operate based on system clock signal CCK, while third bus 170 can operate based on memory clock signal MCK. Computing system 100 can set the ratio of the clock rate of second bus 160 to the clock rate of third bus 170 in a number of ways to ensure the efficiency of the operation of computing system 100. For example, the ratio of the clock rate of second bus 160 to the clock rate of third bus 170 can be selected to be one of 1 : 1, 2: 1, or 4: 1. In an embodiment, system clock signal CCK can have the same frequency as memory clock signal MCK. In an embodiment, system clock signal CCK can have twice the frequency of memory clock signal MCK. In an embodiment, system clock signal CCK can have four times the frequency of memory clock signal MCK.

[0067] In the computing system 100, the first data bus 161 and the second data bus 171 can be parallel data buses that transfer parallel data. The width of the first data bus 161 can be less than or equal to the width of the second data bus 171. The width of a data bus can define the number of data signals and / or the number of bits of data that can be transferred at one time through the data bus. In an embodiment, the width of a data bus can also define the number of signal transmission lines that carry the data signals. In an embodiment, the width of the second data bus 171 can be substantially the same as the width of the first data bus 161, and the number of data signals and bits of data that can be transferred at one time through the second data bus 171 can be substantially the same as the number of data signals and bits of data that can be transferred at one time through the first data bus 161. In an embodiment, the width of the second data bus 171 can be twice the width of the first data bus 161, and the number of data signals and bits of data that can be transferred at one time through the second data bus 171 can be twice the number of data signals and bits of data that can be transferred at one time through the first data bus 161. In an embodiment, the width of the second data bus 171 can be four times the width of the first data bus 161, and the number of data signals and bits of data that can be transferred at one time through the second data bus 171 can be four times the number of data signals and bits of data that can be transferred at one time through the first data bus 161. For example, the first data bus 161 can include n signal transmission lines, and n bits of data can be transferred at one time through the first data bus 161. Here, n can be a multiple of two. The second data bus 171 can include m signal transmission lines, and m bits of data can be transferred at one time through the second data bus 171. Here, m can be equal to n, or can be a multiple of n. The clock rates of the second bus 160 and the third bus 170, and the widths of the first data bus 161 and the second data bus 171 can be varied so that the second data bus 171 can have substantially the same data bandwidth as the first data bus 161.

[0068] In one embodiment, the host 110, memory controller 120, and interface circuit 130 can be integrated into a first device, and the memory device 140 can be a second device. The first bus 150 and the second bus 160 can be internal buses, while the third bus 170 can be an external bus. The host 110, memory controller 120, and interface circuit 130 can be disposed on a first interposer and / or a first substrate, while the memory device 140 can be disposed on a second interposer and / or a second substrate. In another embodiment, the host 110 and memory controller 120 can be integrated into a first device, while the interface circuit 130 and memory device 140 can be integrated into a second device. The first and third buses 150 and 170 can be internal buses, while the second bus 160 can be an external bus. The host 110 and memory controller 120 can be disposed on the first interposer and / or the first substrate, while the interface circuit 130 and memory device 140 can be disposed on the second interposer and / or the second substrate. In one embodiment, host 110 may be a first device, while memory controller 120, interface circuitry 130, and memory device 140 may be integrated into a second device. First bus 150 may be an external bus, while second bus 160 and third bus 170 may be internal buses. Host 110 may be disposed on a first interposer and / or a first substrate, while memory controller 120, interface circuitry 130, and memory device 140 may be disposed on a second interposer and / or a second substrate. In one embodiment, host 110, memory controller 120, interface circuitry 130, and memory device 140 may be integrated into a single device. First to third buses 150, 160, and 170 may be internal buses. Host 110, memory controller 120, interface circuitry 130, and memory device 140 may be disposed on the same interposer and / or substrate. In one embodiment, some or all of host 110, memory controller 120, interface circuitry 130, and memory device 140 may be manufactured as a chip.

[0069] Figure 2 This is a diagram illustrating the connection relationships between a memory controller 220, an interface circuit 230, and a memory device 240 according to an embodiment of the present disclosure. The memory controller 220 can be applied as... Figure 1 The memory controller 120 and interface circuit 230 shown can be applied as Figure 1 The interface circuit 130 and memory device 240 shown can be used as Figure 1 The memory device 140 shown is illustrated. (Reference) Figure 2 The memory controller 220 can respond to the... Figure 1The interface circuit 230 generates or receives various control signals in response to the access request provided from the host 110 shown in FIG. 1. The various control signals can include an address signal ADD, a bank group signal BG, a bank address signal BK, a command signal CMD, a write data signal WTD, and a read data signal RDD, etc. The address signal ADD can be a signal for accessing a row and a column of the memory cell array of the memory device 240. The bank group signal BG can be an address signal for accessing one of a plurality of bank groups included in the memory device 240. The bank address signal BK can be an address signal for accessing one of a plurality of banks constituting one bank group. The memory controller 220 can be electrically connected to the interface circuit 230 through an address bus 251. The address bus 251 can be a unidirectional bus from the memory controller 220 to the interface circuit 230. The address signal ADD, the bank group signal BG, and the bank address signal BK can be provided from the memory controller 220 to the interface circuit 230 through the address bus 251. The address bus 251 can include a plurality of signal transmission lines, and the address signal ADD, the bank group signal BG, and the bank address signal BK can be transmitted through the respective signal transmission lines. The address bus 251 can be included in a portion of the second bus 160 shown in FIG. 1, which does not include the first data bus 161. Figure 1 The second bus 160 can include the first data bus 161, the address bus 251, and a command bus 252. The command bus 252 can be a bidirectional bus between the memory controller 220 and the interface circuit 230. The command signal CMD can be transmitted from the memory controller 220 to the interface circuit 230 through the command bus 252. The command signal CMD can be transmitted from the interface circuit 230 to the memory controller 220 through the command bus 252. The command bus 252 can include a plurality of signal transmission lines, and the command signal CMD can be transmitted through the respective signal transmission lines. The command bus 252 can be included in a portion of the second bus 160 shown in FIG. 1, which does not include the first data bus 161.

[0070] The command signals CMD can include a plurality of signals. By way of non-limiting example, the command signals CMD can include an activate command signal ACT, a row access command signal RAS, a column access command signal CAS, and a write enable signal WE. The activate command signal ACT can be a command signal instructing the memory device 240 to enter an active mode from a standby mode, or to enter the standby mode from the active mode. The memory device 240 can perform write and read operations in the active mode, while the standby mode can be a low power consumption mode of the memory device 240. The row access command signal RAS can be a row address strobe signal, and can be a command signal indicating access to a row of the memory device 240. The column access command signal CAS can be a column address strobe signal, and can be a command signal indicating access to a column of the memory device 240. The write enable signal WE can be a signal determining whether an operation to be performed by the memory device is a write operation or a read operation. For example, when the column access command signal CAS is enabled and the write enable signal WE has a first logic level, the write enable signal WE can be a command signal instructing the memory device 240 to perform a write operation. When the column access command signal CAS is enabled and the write enable signal WE has a second logic level, the write enable signal WE can be a command signal instructing the memory device 240 to perform a read operation. The memory controller 220 can be electrically connected to the interface circuit 230 through a command bus 252. The command bus 252 can be a unidirectional bus from the memory controller 220 to the interface circuit 230. The command signals CMD can be provided from the memory controller 220 to the interface circuit 230 through the command bus 252. The command bus 252 can include a plurality of signal transmission lines, and the activate command signal ACT, the row access command signal RAS, the column access command signal CAS, and the write enable signal WE can be transmitted through respective signal transmission lines. The command bus 252 can be included in the portion of the second bus 160 as shown in FIG. 1 that can not be included in the first data bus 161. Although not shown, the memory controller 220 can also generate control signals such as a chip select signal, a clock enable signal, and a reset signal, and can provide the control signals to the interface circuit 230 through other signal transmission lines. Figure 1 The command signals CMD can include a plurality of signals. By way of non-limiting example, the command signals CMD can include an activate command signal ACT, a row access command signal RAS, a column access command signal CAS, and a write enable signal WE. The activate command signal ACT can be a command signal instructing the memory device 240 to enter an active mode from a standby mode, or to enter the standby mode from the active mode. The memory device 240 can perform write and read operations in the active mode, while the standby mode can be a low power consumption mode of the memory device 240. The row access command signal RAS can be a row address strobe signal, and can be a command signal indicating access to a row of the memory device 240. The column access command signal CAS can be a column address strobe signal, and can be a command signal indicating access to a column of the memory device 240. The write enable signal WE can be a signal determining whether an operation to be performed by the memory device is a write operation or a read operation. For example, when the column access command signal CAS is enabled and the write enable signal WE has a first logic level, the write enable signal WE can be a command signal instructing the memory device 240 to perform a write operation. When the column access command signal CAS is enabled and the write enable signal WE has a second logic level, the write enable signal WE can be a command signal instructing the memory device 240 to perform a read operation. The memory controller 220 can be electrically connected to the interface circuit 230 through a command bus 252. The command bus 252 can be a unidirectional bus from the memory controller 220 to the interface circuit 230. The command signals CMD can be provided from the memory controller 220 to the interface circuit 230 through the command bus 252. The command bus 252 can include a plurality of signal transmission lines, and the activate command signal ACT, the row access command signal RAS, the column access command signal CAS, and the write enable signal WE can be transmitted through respective signal transmission lines. The command bus 252 can be included in the portion of the second bus 160 as shown in FIG. 1 that can not be included in the first data bus 161. Although not shown, the memory controller 220 can also generate control signals such as a chip select signal, a clock enable signal, and a reset signal, and can provide the control signals to the interface circuit 230 through other signal transmission lines.

[0071] The write data signal WTD can be a data signal provided from the memory controller 220 to the memory device 240 when the memory controller 220 instructs the memory device 240 to perform a write operation, and can be a data signal to be stored in the memory device 240. The memory controller 220 can generate the write data signal WTD based on data transferred from the host 110 with an access request. The read data signal RDD can be a data signal provided from the memory device 240 to the memory controller 220 when the memory controller 220 instructs the memory device 240 to perform a read operation. The memory controller 220 can generate data to be transferred to the host 110 based on the read data signal RDD. The memory controller 220 can be electrically connected to the interface circuit 230 through a write bus 253 and a read bus 254. The write bus 253 can be a unidirectional bus from the memory controller 220 to the interface circuit 230, and the read bus 254 can be a unidirectional bus from the interface circuit 230 to the memory controller 220. The write data signal WTD can be provided from the memory controller 220 to the interface circuit 230 through the write bus 253. The read data signal RDD can be provided from the interface circuit 230 to the memory controller 220 through the read bus 254. The write bus 253 and the read bus 254 can be included in the first data bus 161 shown in FIG. 1. The width of the write bus 253 and the width of the read bus 254 can be substantially the same, and the clock rate of the write bus 253 and the clock rate of the read bus 254 can be substantially the same. In an embodiment, the write bus 253 and the read bus 254 can be integrated as a single data bus, and the integrated data bus can be implemented as a bidirectional bus between the memory controller 220 and the interface circuit 230. The integrated data bus can have substantially the same width and clock rate as each of the write bus 253 and the read bus 254. Figure 1

[0072] In an embodiment, the memory controller 220 can further provide the write selection signal WTEN and the read selection signal RDEN to the interface circuit 230 and the memory device 240. The write selection signal WTEN can be a signal for enabling buffers of the interface circuit 230 and the memory device 240 to transfer and receive signals related to a write operation when the memory controller 220 instructs the memory device 240 to perform a write operation. The read selection signal RDEN can be a signal for enabling buffers of the interface circuit 230 and the memory device 240 to transfer and receive signals related to a read operation when the memory controller 220 instructs the memory device 240 to perform a read operation. In an embodiment, the memory controller 220 can not separately provide the write selection signal WTEN and the read selection signal RDEN to the interface circuit 230, and the interface circuit 230 can generate the write selection signal WTEN and the read selection signal RDEN based on the command signal CMD.

[0073] ​The interface circuit 230 can be electrically connected to the memory controller 220 and can receive the address signal ADD, the bank group signal BG, the bank address signal BK, the command signal CMD, the write data signal WTD from the memory controller 220, and can transfer the read data signal RDD to the memory controller 220. The interface circuit 230 can be electrically connected to the memory controller 220 through an address bus 251, a command bus 252, a write bus 253, and a read bus 254. The interface circuit 230 can receive the address signal ADD, the bank group signal BG, and the bank address signal BK from the memory controller 220 through the address bus 251. The interface circuit 230 can receive the active command signal ACT, the row access command signal RAS, the column access command signal CAS, and the write enable signal WE through the command bus 252. The interface circuit 230 can receive the write data signal WTD from the memory controller 220 through the write bus 253. The interface circuit 230 can transfer the read data signal RDD to the memory controller 220 through the read bus 254. The interface circuit 230 can be electrically connected to the memory device 240 and can provide the signals received from the memory controller 220 to the memory device 240. The interface circuit 230 can buffer and convert the signals received from the memory controller 220 to generate signals suitable for use in the memory device 240 (e.g., serialization or deserialization).

[0074] The interface circuit 230 can provide the bank group signal BG, the bank address signal BK, the row address signal RADD, the column address signal CADD, the command signal CMD, and the memory data signal DQ to the memory device 240. The interface circuit 230 can buffer the bank group signal BG and the bank address signal BK received from the memory controller 220. The interface circuit 230 can generate the row address signal RADD and the column address signal CADD based on the address signal ADD and the command signal CMD received from the memory controller 220. The interface circuit 230 can be electrically connected to the memory device 240 through an address bus 261 and can provide the bank group signal BG, the bank address signal BK, the row address signal RADD, and the column address signal CADD to the memory device 240 through the address bus 261. The address bus 261 can be a unidirectional bus from the interface circuit 230 to the memory device 240. The address bus 261 can include a plurality of signal transmission lines, and the bank group signal BG, the bank address signal BK, the row address signal RADD, and the column address signal CADD can be transmitted through respective signal transmission lines. The address bus 261 can be included as a part of the third bus 170 shown in FIG. 1B, but not as a part of the second data bus 171. Figure 1 The interface circuit 230 can be electrically connected to the memory device 240 and can provide the bank group signal BG, the bank address signal BK, the row address signal RADD, the column address signal CADD, the command signal CMD, and the memory data signal DQ to the memory device 240. The interface circuit 230 can buffer the bank group signal BG and the bank address signal BK received from the memory controller 220. The interface circuit 230 can generate the row address signal RADD and the column address signal CADD based on the address signal ADD and the command signal CMD received from the memory controller 220. The interface circuit 230 can be electrically connected to the memory device 240 through an address bus 261 and can provide the bank group signal BG, the bank address signal BK, the row address signal RADD, and the column address signal CADD to the memory device 240 through the address bus 261. The address bus 261 can be a unidirectional bus from the interface circuit 230 to the memory device 240. The address bus 261 can include a plurality of signal transmission lines, and the bank group signal BG, the bank address signal BK, the row address signal RADD, and the column address signal CADD can be transmitted through respective signal transmission lines. The address bus 261 can be included as a part of the third bus 170 shown in FIG. 1B, but not as a part of the second data bus 171.

[0075] The interface circuit 230 can buffer the command signals CMD received from the memory controller 220. The interface circuit 230 can be electrically connected to the memory device 240 through a command bus 262, and can provide the activation command signal ACT, the row access command signal RAS, the column access command signal CAS, and the write enable signal WE to the memory device 240 through the command bus 262. The command bus 262 can be a unidirectional bus from the interface circuit 230 to the memory device 240. The command bus 262 can include a plurality of signal transmission lines, and the activation command signal ACT, the row access command signal RAS, the column access command signal CAS, and the write enable signal WE can be transmitted through respective signal transmission lines. The command bus 262 can be included as a part of the third bus 170, except for the second data bus 171, as illustrated in FIG. 2. Figure 1

[0076] The interface circuit 230 can generate the memory data signals DQ based on the write data signals WTD received from the memory controller 220, and can generate the read data signals RDD based on the memory data signals DQ received from the memory device 240. The interface circuit 230 can be electrically connected to the memory device 240 through a memory data bus 263, and can transmit or receive the memory data signals DQ to or from the memory device 240 through the memory data bus 263. The memory data bus 263 can be a bidirectional bus between the interface circuit 230 and the memory device 240. The width of the memory data bus 263 can be greater than or equal to the width of the write bus 253 or the width of the read bus 254, and the clock rate of the memory data bus 263 can be less than or equal to the clock rate of the write bus 253 or the clock rate of the read bus 254.

[0077] ​The interface circuit 230 can include an address control circuit 231, a command buffer 232, and a data input / output circuit 233. The address control circuit 231 can receive the bank group signal BG, the bank address signal BK, and the address signal ADD from the memory controller 220. The address control circuit 231 can buffer the bank group signal BG and the bank address signal BK, and can provide the buffered bank group signal BG and the buffered bank address signal BK to the memory device 240. The address control circuit 231 can generate a row address signal RADD and a column address signal CADD based on the address signal ADD and the command signal CMD. The address control circuit 231 can generate the row address signal RADD based on the address signal ADD and the row access command signal RAS, and can generate the column address signal CADD based on the address signal ADD and the column access command signal CAS. For example, the address control circuit 231 can generate the address signal ADD as the row address signal RADD when the row access command signal RAS is enabled. The address control circuit 231 can generate the address signal ADD as the column address signal CADD when the column access command signal CAS is enabled. The address control circuit 231 can transfer the row address signal RADD and the column address signal CADD to the memory device 240 through an address bus 261.

[0078] The command buffer 232 can be electrically connected to the command bus 252 to receive the command signal CMD transmitted from the memory controller 220. The command buffer 232 can buffer the command signal CMD, and can transmit the buffered command signal CMD to the memory device 240 through the command bus 262. The command buffer 232 can buffer the activation command signal ACT, the row access command signal RAS, the column access command signal CAS, and the write enable signal WE, respectively, and can provide the buffered activation command signal ACT, the buffered row access command signal RAS, the buffered column access command signal CAS, and the buffered write enable signal WE to the memory device 240. The command buffer 232 can provide the buffered row access command signal RAS and the buffered column access command signal CAS to the address control circuit 231. The address control circuit 231 can generate a row address signal RADD and a column address signal CADD based on the address signal ADD and the row access command signal RAS and the column access command signal CAS received from the command buffer 232. In an embodiment, the command buffer 232 can be modified to generate a write selection signal WTEN and a read selection signal RDEN based on the write enable signal WE. When the column access command signal CAS is enabled and the write enable signal WE has a first logic level, i.e., when a write operation is performed, the command buffer 232 can enable the write selection signal WTEN and disable the read selection signal RDEN. When the column access command signal CAS is enabled and the write enable signal WE has a second logic level, i.e., when a read operation is performed, the command buffer 232 can enable the read selection signal RDEN and disable the write selection signal WTEN. The command buffer 232 can provide the write selection signal WTEN and the read selection signal RDEN to the data input / output circuit 233 and the memory device 240.

[0079] The data input / output circuit 233 can be electrically connected to the memory controller 220 by a write bus 253 and a read bus 254, and can be electrically connected to the memory device 240 by a memory data bus 263. The data input / output circuit 233 can receive a write data signal WTD from the memory controller 220 by the write bus 253, and can generate a memory data signal DQ based on the write data signal WTD. The data input / output circuit 233 can transmit the memory data signal DQ to the memory device 240 by the memory data bus 263. The data input / output circuit 233 can receive the memory data signal DQ from the memory device 240 by the memory data bus 263, and can generate a read data signal RDD based on the memory data signal DQ. The data input / output circuit 233 can transmit the read data signal RDD to the memory controller 220 by the read bus 254. The data input / output circuit 233 can selectively electrically connect the memory data bus 263 with one of the write bus 253 and the read bus 254 based on a write enable signal WE of the command signal CMD (i.e., based on whether the signal indicates a write operation or a read operation). The data input / output circuit 233 can receive a write select signal WTEN and a read select signal RDEN transmitted from the memory controller 220. In an embodiment, the data input / output circuit 233 can receive the write select signal WTEN and the read select signal RDEN from the command buffer 232. The data input / output circuit 233 can electrically connect the write bus 253 with the memory data bus 263 based on the write select signal WTEN, and can electrically connect the read bus 254 with the memory data bus 263 based on the read select signal RDEN. When the write select signal WTEN is enabled, the data input / output circuit 233 can buffer the write data signal WTD, and can output the buffered write data signal WTD as the memory data signal DQ. When the read select signal RDEN is enabled, the data input / output circuit 233 can receive the memory data signal DQ, buffer the memory data signal DQ, and output the buffered memory data signal DQ as the read data signal RDD. In an embodiment, the data input / output circuit 233 can convert a data rate of the write data signal WTD to generate the memory data signal DQ. For example, the data input / output circuit 233 can reduce a data rate of the write data signal WTD to generate the memory data signal DQ. The data input / output circuit 233 can convert a data rate of the memory data signal DQ to generate the read data signal RDD. For example, the data input / output circuit 233 can increase a data rate of the memory data signal DQ to generate the read data signal RDD. The data input / output circuit 233 can generate a data strobe signal DQS, transmit the data strobe signal DQS to the memory device 240, and transmit the memory data signal DQ to the memory device 240 in synchronization with the data strobe signal DQS.The data input / output circuit 233 can receive a data strobe signal DQS transferred from the memory device 240, and can receive a memory data signal DQ transferred from the memory device 240 in synchronization with the data strobe signal DQS. The data strobe signal DQS transferred by the data input / output circuit 233 to the memory device 240 can be a write data strobe signal WDQS. The data strobe signal DQS received by the data input / output circuit 233 from the memory device 240 can be a read data strobe signal RDQS. The data input / output circuit 233 can transfer the write data strobe signal WDQS to the memory device 240 through a strobe bus 264, and can receive the read data strobe signal RDQS transferred from the memory device 240 through the strobe bus 264. The data input / output circuit 233 can generate the write data strobe signal WDQS based on a memory clock signal MCK, which will be described later.

[0080] The memory controller 220 and the interface circuit 230 can receive a system clock signal CCK, and can operate in synchronization with the system clock signal CCK. Figure 1 The host 110 shown in FIG. 1 can generate the system clock signal CCK, and can provide the system clock signal CCK to the memory controller 220 and the interface circuit 230. In an embodiment, the memory controller 220 can generate the system clock signal CCK, and the memory controller 220 can provide the system clock signal CCK to the interface circuit 230. The memory controller 220 can provide a write data signal WTD to the interface circuit 230 in synchronization with the system clock signal CCK, and can receive a read data signal RDD in synchronization with the system clock signal CCK. The memory controller 220 can further include a clock frequency control circuit 221. The clock frequency control circuit 221 can set and / or change an operating speed of the interface circuit 230 and the memory device 240. The clock frequency control circuit 221 can receive a frequency control signal FS from the host 110. The clock frequency control circuit 221 can generate a clock frequency set signal CFS based on the frequency control signal FS. The clock frequency set signal CFS can include information for setting a clock rate of a bus electrically connecting the memory controller 220 and the interface circuit 230, and a clock rate of a bus electrically connecting the interface circuit 230 and the memory device 240.

[0081] The interface circuit 230 can also include a clock control circuit 234. The clock control circuit 234 can generate an interface clock signal ICCK and a memory clock signal MCK based on a system clock signal CCK and a clock frequency setting signal CFS. The clock control circuit 234 can generate the interface clock signal ICCK by buffering the system clock signal CCK, and the interface clock signal ICCK can have substantially the same frequency as the system clock signal CCK. The clock control circuit 234 can selectively delay the system clock signal CCK to generate the interface clock signal ICCK, taking into account delays that occur within the interface circuit 230. The clock control circuit 234 can vary the frequency of the memory clock signal MCK based on the clock frequency setting signal CFS. For example, the memory clock signal MCK generated by the clock control circuit 234 based on the clock frequency setting signal CFS can have substantially the same frequency as the interface clock signal ICCK, or can have a frequency that is 1 / 2 or 1 / 4 of the interface clock signal ICCK. The clock control circuit 234 can vary the frequency of the memory clock signal MCK to set the clock rate ratio of the write bus 253 and the read bus 254 to the memory data bus 263. The interface circuit 230 can be electrically connected to the memory device 240 through the memory clock bus 265, and the clock control circuit 234 can transmit the memory clock signal MCK to the memory device 240 through the memory clock bus 265. The clock control circuit 234 can provide the memory clock signal MCK with a complementary signal, or can provide the memory clock signal MCK with a complementary signal as a differential clock signal to the memory device 240.

[0082] The data input / output circuit 233 can also receive a clock frequency setting signal CFS, an interface clock signal ICCK, and a memory clock signal MCK. The data input / output circuit 233 can perform a data conversion operation based on the clock frequency setting signal CFS. When it is determined from the clock frequency setting signal CFS that the frequencies of the interface clock signal ICCK and the memory clock signal MCK are substantially the same, the data input / output circuit 233 can buffer the write data signal WTD to generate the memory data signal DQ and can buffer the memory data signal DQ to generate the read data signal RDD. When it is determined from the clock frequency setting signal CFS that the frequency of the interface clock signal ICCK is higher than the memory clock signal MCK, the data input / output circuit 233 can perform a deserialization operation and a serialization operation and can perform an operation similar to a SerDes. The data input / output circuit 233 can deserialize the write data signal WTD to generate the memory data signal DQ and can serialize the memory data signal DQ to generate the read data signal RDD. For example, the data input / output circuit 233 can latch the write data signal WTD based on the interface clock signal ICCK and transfer the latched write data signal WTD as the memory data signal DQ to the memory device 240 in synchronization with a write data strobe signal WDQS. The data input / output circuit 233 can latch the memory data signal DQ based on a read data strobe signal RDQS and transfer the latched memory data signal DQ as the memory data signal DQ to the memory controller 220 in synchronization with the interface clock signal ICCK.

[0083] The interface circuit 230 can also include a training circuit 235. When the computing system is initialized or upon request of the host 110, the memory controller 220 can provide a training signal TRS to the interface circuit 230. The training circuit 235 enables a training operation to be performed on internal circuits provided in the interface circuit 230 based on the training signal TRS. The internal circuits that perform the training operation will be described in more detail below.

[0084] Figure 3 is a block diagram illustrating a configuration of the address control circuit 231 shown in Figure 2 Referring to Figure 2 and Figure 3 , the address control circuit 231 can include a bank address buffer 310, a row address generation circuit 320, and a column address generation circuit 330. The bank address buffer 310 can buffer the bank group signal BG and the bank address signal BK received from the memory controller 220 to generate the bank group signal BG and the bank address signal BK transferred to the memory device 240. In Figure 3In the embodiment shown in FIG. 3, the bank group signal and the bank address signal input from the memory controller 220 to the bank address buffer 310 are denoted as BG(in) and BK(in), respectively, and the bank group signal and the bank address signal output from the bank address buffer 310 to the memory device 240 are denoted as BG(out) and BK(out), respectively. The bank address buffer 310 can perform a general buffering operation without changing the characteristics of the bank group signal BG and the bank address signal BK.

[0085] The row address generation circuit 320 can receive the address signal ADD from the memory controller 220, and can receive the row access command signal RAS from the command buffer 232. When the row access command signal RAS is enabled, the row address generation circuit 320 can output the address signal ADD as a row address signal RADD. When the row access command signal RAS is disabled, the row address generation circuit 320 can not output the address signal ADD as the row address signal RADD. The row address generation circuit 320 can transfer the row address signal RADD to the memory device 240.

[0086] The column address generation circuit 330 can receive the address signal ADD from the memory controller 220, and can receive the column access command signal CAS from the command buffer 232. When the column access command signal CAS is enabled, the column address generation circuit 330 can output the address signal ADD as a column address signal CADD. When the column access command signal CAS is disabled, the column address generation circuit 330 can not output the address signal ADD as the column address signal CADD. The column address generation circuit 330 can transfer the column address signal CADD to the memory device 240.

[0087] Figure 4 is a diagram illustrating Figure 2 In the embodiment shown in FIG. 3, the bank group signal and the bank address signal input from the memory controller 220 to the bank address buffer 310 are denoted as BG(in) and BK(in), respectively, and the bank group signal and the bank address signal output from the bank address buffer 310 to the memory device 240 are denoted as BG(out) and BK(out), respectively. The bank address buffer 310 can perform a general buffering operation without changing the characteristics of the bank group signal BG and the bank address signal BK. Figure 2 and Figure 4 The data input / output circuit 233 can include a write control circuit 410 and a read control circuit 420. The write control circuit 410 can receive a write selection signal WTEN, a write data signal WTD, and an interface clock signal ICCK, and can generate a memory data signal DQ and a write data strobe signal WDQS. The write control circuit 410 can be selectively activated based on the write selection signal WTEN. The write control circuit 410 can generate the write data strobe signal WDQS based on the interface clock signal ICCK. The write control circuit 410 can latch the write data signal WTD based on the interface clock signal ICCK, and can output the latched write data signal WTD as the memory data signal DQ based on the write data strobe signal WDQS.

[0088] The write control circuit 410 can include a write strobe circuit 411, a strobe transmitter 412 (TX2), a write pipe circuit 413, and a data transmitter 414 (TX1). The write strobe circuit 411 can receive the memory clock signal MCK and generate a pre-write data strobe signal WDQSP based on the memory clock signal MCK. The write strobe circuit 411 can buffer or divide the memory clock signal MCK to generate the pre-write data strobe signal WDQSP. In an embodiment, the write strobe circuit 411 can buffer the memory clock signal MCK to generate the pre-write data strobe signal WDQSP including differential clock signals having a 180-degree phase difference. In an embodiment, the write strobe circuit 411 can divide the memory clock signal MCK to generate the pre-write data strobe signal WDQSP including multi-phase clock signals having a 90-degree phase difference. The write strobe circuit 411 can selectively delay the interface clock signal ICCK to enable the memory data signal DQ and the pre-write data strobe signal WDQSP to be synchronized, and then generate the pre-write data strobe signal WDQSP based on the delayed interface clock signal ICCK. The strobe transmitter 412 can be electrically connected to the write strobe circuit 411 to receive the pre-write data strobe signal WDQSP. The strobe transmitter 412 can receive a write select signal WTEN and can be activated when the write select signal WTEN is enabled. The strobe transmitter 412 can transmit a write strobe signal WDQS to the memory device 240 based on the pre-write data strobe signal WDQSP. The write strobe signal WDQS can be substantially the same signal as the pre-write data strobe signal WDQSP.

[0089] The write pipe circuit 413 can receive the write data signals WTD, the interface clock signals ICCK, and the pre-write data strobe signals WDQSP. The write pipe circuit 413 can sequentially store the write data signals WTD in synchronization with the interface clock signals ICCK. The write pipe circuit 413 can output the sequentially stored write data signals WTD as the memory data signals DQ in synchronization with the pre-write data strobe signals WDQSP. The write pipe circuit 413 can be implemented with a deserializer that converts a duration ratio of the write data signals WTD and the memory data signals DQ to 1:1, 1:2, or 1:4 according to a frequency ratio of the interface clock signals ICCK to the pre-write data strobe signals WDQSP and / or the write data strobe signals WDQS. The write pipe circuit 413 can further receive the clock frequency setting signals CFS. Based on the clock frequency setting signals CFS, the write pipe circuit 413 can determine the frequency ratio of the interface clock signals ICCK to the write data strobe signals WDQS, and can change the duration ratio of the write data signals WTD and the memory data signals DQ. The data transmitter 414 can be electrically connected with the write pipe circuit 413 to receive output signals of the write pipe circuit 413. The data transmitter 414 can receive the write select signals WTEN, and can be activated when the write select signals WTEN are enabled. The data transmitter 414 can drive the memory data bus 263 based on the output signals of the write pipe circuit 413 to transmit the memory data signals DQ to the memory device 240.

[0090] The read control circuit 420 can receive the read select signals RDEN, the memory data signals DQ, the interface clock signals ICCK, and the read data strobe signals RDQS, and can generate the read data signals RDD. The read control circuit 420 can be selectively activated based on the read select signals RDEN. The read control circuit 420 can latch the memory data signals DQ based on the read data strobe signals RDQS, and can output the latched memory data signals DQ as the read data signals RDD based on the interface clock signals ICCK.

[0091] The read control circuit 420 can include a strobe receiver 421 (RX1), a read strobe circuit 422, a data receiver 423 (RX2), and a read pipeline circuit 424. The strobe receiver 421 can receive a read selection signal RDEN and a read data strobe signal RDQS. The strobe receiver 421 can be activated when the read selection signal RDEN is enabled. The strobe receiver 421 can receive the read data strobe signal RDQS from the memory device 240. The read data strobe signal RDQS can include differential clock signals having a 180 degree phase difference, or can include multi-phase clock signals having a 90 degree phase difference. The read strobe circuit 422 can be electrically connected to the strobe receiver 421 to receive an output signal of the strobe receiver 421, and can buffer the output signal of the strobe receiver 421. The read strobe circuit 422 can selectively delay the output signal of the strobe receiver 421 to match a delay time of the memory data signal DQ with a delay time of the read data strobe signal RDQS. The read strobe circuit 422 can generate a delayed read data strobe signal RDQSD from the output signal of the strobe receiver 421. The delayed read data strobe signal RDQSD can have substantially the same frequency characteristics as the read data strobe signal RDQS.

[0092] The data receiver 423 can receive a read selection signal RDEN and a memory data signal DQ. The data receiver 423 can be selectively activated based on the read selection signal RDEN. The data receiver 423 can receive the memory data signal DQ using a reference voltage VREF. The reference voltage VREF can have an appropriate voltage level based on a voltage level range over which the memory data signal DQ swings. For example, when the memory data signal DQ is an NRZ (non-return-to-zero) signal, the reference voltage VREF can have a voltage level corresponding to a middle of a voltage level range over which the memory data signal DQ swings. The read pipeline circuit 424 can receive the memory data signal DQ, a delayed read data strobe signal RDQSD, and an interface clock signal ICCK. The read pipeline circuit 424 can sequentially store the memory data signal DQ in synchronization with the delayed read data strobe signal RDQSD. The read pipeline circuit 424 can output the sequentially stored memory data signal DQ as a read data signal RDD in synchronization with the interface clock signal ICCK. The read pipeline circuit 424 can be implemented with a serializer that converts a time duration ratio of the memory data signal DQ to the read data signal RDD to 1:1, 2:1, or 4:1 according to a frequency ratio of the delayed read data strobe signal RDQSD and / or the read data strobe signal RDQS to the interface clock signal ICCK. The read pipeline circuit 424 can further receive a clock frequency setting signal CFS. The read pipeline circuit 424 can determine a frequency ratio of the interface clock signal ICCK to the read strobe signal RDQS based on the clock frequency setting signal CFS, and can change a time duration ratio of the memory data signal DQ to the read data signal RDD.

[0093] Figure 5 is a diagram illustrating a configuration of the clock control circuit 234 shown in Figure 2 FIG. 6 is a diagram illustrating a configuration of the clock control circuit 234 shown in Figure 5The clock control circuit 234 can include a clock delay circuit 510, a clock buffer circuit 520, a first clock division circuit 530, a second clock division circuit 540, and a clock selection circuit 550. The clock delay circuit 510 can receive the system clock signal CCK and can buffer the system clock signal CCK. The system clock signal CCK can be selectively delayed to generate the interface clock signal pair ICCK, ICCKB. The clock delay circuit 510 can generate the interface clock signal pair ICCK, ICCKB without substantially delaying the system clock signal CCK (except for delay caused by buffering operations). The clock delay circuit 510 can also delay the system clock signal CCK by any delay time to generate the interface clock signal pair ICCK, ICCKB having a lagging phase relative to the system clock signal CCK (in addition to the delay time caused by buffering operations). The clock delay circuit 510 can include digital and / or analog variable delay lines, and the delay time of the clock delay circuit 510 can be varied based on any digital and / or analog control signals.

[0094] The clock buffer circuit 520 can receive the system clock signal CCK and can buffer the system clock signal CCK to generate the first clock signal pair CCK11. The first clock signal pair CCK11 can have substantially the same frequency as the system clock signal CCK. The first clock division circuit 530 can receive the system clock signal CCK and can divide the frequency of the system clock signal CCK by two to generate the second clock signal pair CCK21. The frequency of the second clock signal pair CCK21 can be 1 / 2 of the frequency of the system clock signal CCK. The second clock division circuit 540 can divide the frequency of the second clock signal pair CCK21 by two to generate the third clock signal pair CCK41. The frequency of the third clock signal pair CCK41 can be 1 / 2 of the frequency of the second clock signal pair CCK21 and can be 1 / 4 of the frequency of the system clock signal CCK.

[0095] The clock selection circuit 550 can receive the first clock signal pair CCK11, the second clock signal pair CCK21, the third clock signal pair CCK41, and a clock frequency setting signal CFS. The clock selection circuit 550 can output one of the first to third clock signal pairs CCK11, CCK21, CCK41 as the memory clock signal pair MCK, MCKB based on the clock frequency setting signal CFS. The clock frequency setting signal CFS can be a digital signal having at least two bits. When the clock frequency setting signal CFS has a first logic value, the clock selection circuit 550 can output the first clock signal pair CCK11 as the memory clock signal pair MCK, MCKB including the memory clock signal MCK and the complementary memory clock signal MCKB having logic levels that are inverted from each other. When the clock frequency setting signal CFS has a second logic value, the clock selection circuit 550 can output the second clock signal pair CCK21 as the memory clock signal pair MCK, MCKB. When the clock frequency setting signal CFS has a third logic value, the clock selection circuit 550 can output the third clock signal pair CCK41 as the memory clock signal pair MCK, MCKB. The clock selection circuit 550 can be implemented using a 3-to-1 multiplexer using the clock frequency setting signal CFS as a control signal. Referring again to Figure 2 The training circuit 235 can perform a training operation on the components shown in FIG. 2B based on the training signal TRS. For example, based on the training signal TRS, the training circuit 235 can adjust the driving strength and / or the delay time of the bank address buffer 310, the data transmitter 414, the write gating circuit 411, the gating transmitter 412, the gating receiver 421, the read gating circuit 422, the data receiver 423, the clock delay circuit 510, the clock buffer circuit 520, etc. Figures 3-5

[0096] Figure 6 A diagram to illustrate a configuration of a memory die 600 according to an embodiment of the disclosure. Figure 2 The memory device 240 shown in FIG. 2A can include the memory die 600. When the memory device 240 includes a plurality of memory dies, the plurality of memory dies can each have substantially the same configuration as the memory die 600. Referring to Figure 2 and Figure 6 ​The memory die 600 can receive the bank group signal BG, the bank address signal BK, the row address signal RADD, the column address signal CADD, the command signal CMD, the memory clock signals MCK, MCKB, and the memory data signal DQ from the interface circuit 230. The memory die 600 can include a plurality of bank groups MBG1 to MBG4, a first address receiver 641, a second address receiver 642, a third address receiver 643, a command receiver 644, a clock receiver 645, a command control circuit 650, an input / output drive circuit 660, and an input / output buffer circuit 670. The memory die 600 can include first to fourth bank groups MBG1 to MBG4. Although the number of bank groups included in the memory die 600 is four, the number of bank groups included in the memory die 600 can be two, eight, or more. Each of the first to fourth bank groups can include a plurality of banks BANK0, BANK1, BANK2, …, BANK7. For example, the first to fourth bank groups MBG1 to MBG4 can each include two banks. The first bank group MBG1 can include a first bank BANK0 and a second bank BANK1, the second bank group MBG2 can include a third bank BANK2 and a fourth bank BANK3, the third bank group MBG3 can include a fifth bank BANK4 and a sixth bank BANK5, and the fourth bank group MBG4 can include a seventh bank BANK6 and an eighth bank BANK7. In the embodiment, each bank group includes two banks, but the number of banks included in each bank group can be four or more. Each of the first to eighth banks BANK0, BANK2, BANK3, …, BANK7 can include a memory cell array 610, a row decode circuit 620, and a column decode circuit 630. The number of memory cell arrays 610, row decode circuits 620, and column decode circuits 630 can be as many as the number of banks. A plurality of row lines WL can be disposed in the row direction of each memory cell array, a plurality of column lines BL can be disposed in the column direction of each memory cell array, and a plurality of memory cells can be electrically connected at points where the plurality of row lines and the plurality of column lines cross. Figure 6 Although the number of bank groups included in the memory die 600 is four, the number of bank groups included in the memory die 600 can be two, eight, or more. Each of the first to fourth bank groups can include a plurality of banks BANK0, BANK1, BANK2, …, BANK7. For example, the first to fourth bank groups MBG1 to MBG4 can each include two banks. The first bank group MBG1 can include a first bank BANK0 and a second bank BANK1, the second bank group MBG2 can include a third bank BANK2 and a fourth bank BANK3, the third bank group MBG3 can include a fifth bank BANK4 and a sixth bank BANK5, and the fourth bank group MBG4 can include a seventh bank BANK6 and an eighth bank BANK7. In the embodiment, each bank group includes two banks, but the number of banks included in each bank group can be four or more. Each of the first to eighth banks BANK0, BANK2, BANK3, …, BANK7 can include a memory cell array 610, a row decode circuit 620, and a column decode circuit 630. The number of memory cell arrays 610, row decode circuits 620, and column decode circuits 630 can be as many as the number of banks. A plurality of row lines WL can be disposed in the row direction of each memory cell array, a plurality of column lines BL can be disposed in the column direction of each memory cell array, and a plurality of memory cells can be electrically connected at points where the plurality of row lines and the plurality of column lines cross. Figure 6 Although the number of bank groups included in the memory die 600 is four, the number of bank groups included in the memory die 600 can be two, eight, or more. Each of the first to fourth bank groups can include a plurality of banks BANK0, BANK1, BANK2, …, BANK7. For example, the first to fourth bank groups MBG1 to MBG4 can each include two banks. The first bank group MBG1 can include a first bank BANK0 and a second bank BANK1, the second bank group MBG2 can include a third bank BANK2 and a fourth bank BANK3, the third bank group MBG3 can include a fifth bank BANK4 and a sixth bank BANK5, and the fourth bank group MBG4 can include a seventh bank BANK6 and an eighth bank BANK7. In the embodiment, each bank group includes two banks, but the number of banks included in each bank group can be four or more. Each of the first to eighth banks BANK0, BANK2, BANK3, …, BANK7 can include a memory cell array 610, a row decode circuit 620, and a column decode circuit 630. The number of memory cell arrays 610, row decode circuits 620, and column decode circuits 630 can be as many as the number of banks. A plurality of row lines WL can be disposed in the row direction of each memory cell array, a plurality of column lines BL can be disposed in the column direction of each memory cell array, and a plurality of memory cells can be electrically connected at points where the plurality of row lines and the plurality of column lines cross.

[0097] Each of the row decode circuits 620 can receive the internal bank signal IBG, the internal bank address signal IBK, the internal row address signal IRADD, and the activation signal ACTS. When the activation signal ACTS is enabled, each of the row decode circuits 620 can select and / or enable a row line of the array of memory cells 610 provided in the first through eighth memory banks. Each of the row decode circuits 620 can decode the internal bank signal IBG to select and / or access at least one of the plurality of memory banks in the selected one of the plurality of memory banks MBG1-MBG4. Each of the row decode circuits 620 can decode the internal bank address signal IBK to select and / or access at least one of the plurality of memory banks in the selected memory bank. Each of the row decode circuits 620 can select and / or enable at least one of the plurality of row lines provided in each array of memory cells 610 based on the internal row address signal IRADD. Each of the column decode circuits 630 can receive the internal column address signal ICADD. Each of the column decode circuits 630 can decode the internal column address signal ICADD to select and / or access at least one of the plurality of column lines provided in each array of memory cells 610.

[0098] The first address receiver 641 can receive the bank group signal BG and the bank address signal BK transferred from the interface circuit 230 through the address bus 261. The first address receiver 641 can receive the bank group signal BG and the bank address signal BK to generate the internal bank group signal IBG and the internal bank address signal IBK. The first address receiver 641 can generate the internal bank group signal IBG and the internal bank address signal IBK having substantially the same characteristics as the bank group signal BG and the bank address signal BK without changing the characteristics of the bank group signal IBG and the bank address signal IBK. The first address receiver 641 can provide the internal bank group signal IBG and the internal bank address signal IBK to the corresponding row decode circuit 620. The second address receiver 642 can receive the row address signal RADD transferred from the interface circuit 230 through the address bus 261. The second address receiver 642 can receive the row address signal RADD to generate the internal row address signal IRADD. The second address receiver 642 can generate the internal row address signal IRADD having substantially the same characteristics as the row address signal RADD without changing the characteristics of the row address signal RADD. The second address receiver 642 can provide the internal row address signal IRADD to the corresponding row decode circuit 620. The third address receiver 643 can receive the column address signal CADD transferred from the interface circuit 230 through the address bus 261. The third address receiver 643 can receive the column address signal CADD to generate the internal column address signal ICADD. The third address receiver 643 can generate the internal column address signal ICADD having substantially the same characteristics as the column address signal CADD without changing the characteristics of the column address signal CADD. The third address receiver 643 can provide the internal column address signal ICADD to the corresponding column decode circuit 630. The command receiver 644 can receive the command signal CMD transferred from the interface circuit 230 through the command bus 262. The command receiver 644 can receive the command signal CMD to generate the internal command signal ICMD. The internal command signal ICMD can include an internal active command signal IACT, an internal row access command signal IRAS, an internal column access command signal ICAS, and an internal write enable signal IWE. The command receiver 644 can provide the internal command signal ICMD to the command control circuit 650. The clock receiver 645 can receive the memory clock signal pair MCK, MCKB transferred from the interface circuit 230 through the memory clock bus 265. The clock receiver 645 can receive the memory clock signal pair MCK, MCKB to generate the internal memory clock signal pair IMCK, IMCKB.

[0099] The command control circuit 650 can receive an internal command signal I CMD and an internal memory clock signal pair IMCK, IMCKB. The command control circuit 650 can latch the internal command signal I CMD in synchronization with the internal memory clock signal pair IMCK, IMCKB. The command control circuit 650 can generate a converted command signal C CMD based on the internal command signal I CMD. The command control circuit 650 can combine logic levels of at least one internal command signal I CMD to generate the converted command signal C CMD. The converted command signal C CMD can include at least an activate signal ACTS, a write signal WTS, and a read signal RDS. The activate signal ACTS can be a signal instructing an activate operation of the memory die 600, and the activate operation can be an operation of selecting and / or enabling a row line of the memory cell array 610. The write signal WTS can be a signal instructing a write operation of the memory die 600, and the write operation can be an operation of the memory die 600 storing a memory data signal DQ received through the memory data bus 263 into the memory cell array 610. The read signal RDS can be a signal instructing a read operation of the memory die 600, and the read operation can be an operation of the memory die 600 outputting data stored in the memory cell array 610 as a memory data signal DQ through the memory data bus 263. The command control circuit 650 can delay the internal command signal I CMD by a time corresponding to a latency to generate the converted command signal C CMD. The latency can refer to a delay time from when a command signal CMD is received from the memory die 600 until the memory die 600 actually performs an operation indicated by the command signal CMD. For example, the latency can include a CAS latency, a write latency, or a read latency, etc. The latency can be defined as 1 or an integer of 1 or more, and a delay of the command control circuit 650 according to the latency can be set to an integer multiple of a clock period of the memory clock signal pair MCK, MCKB. The command control circuit 650 can provide the converted command signal C CMD to internal circuits of the memory die 600. The command control circuit 650 can provide the activate signal ACTS to the corresponding row decode circuit 620. The command control circuit 650 can provide the write signal WTS and the read signal RDS to the input / output driving circuit 660.

[0100] The input / output driver circuit 660 can be electrically connected to the plurality of column lines of the respective memory cell array 610 through each column decode circuit 630. The input / output driver circuit 660 can receive a write signal WTS and a read signal RDS. Based on the write signal WTS, the input / output driver circuit 660 can provide internal data signals IDQ0, IDQ1, IDQ2, …, IDQm-1 (where m is an integer of 4 or greater) transferred through the global data line GIO to each memory cell array 610 through each column decode circuit 630, and the internal data signals IDQ0, IDQ1, IDQ2, …, IDQm-1 can be stored in memory cells electrically connected to the column lines accessed by each column decode circuit 630. The input / output driver circuit 660 can include a write driver circuit to provide the internal data signals IDQ0, IDQ1, IDQ2, …, IDQm-1 to the respective memory cell array 610 based on the write signal WTS. The input / output driver circuit 660 can receive data signals output from each memory cell array 610 based on the read signal RDS. The input / output driver circuit 660 can generate the internal data signals IDQ0, IDQ1, IDQ2, …, IDQm-1 by receiving the output data signals output from the respective memory cell array 610 via the respective column decode circuit 630. The input / output driver circuit 660 can output the internal data signals IDQ0, IDQ1, IDQ2, …, IDQm-1 through the global data line GIO. The input / output driver circuit 660 can include a read driver circuit to provide the data signals output from the respective memory cell array 610 to the global data line GIO based on the read signal RDS. The input / output driver circuit 660 can operate based on the internal memory clock signal pair IMCK, IMCKB. The memory die 600 can further include an internal clock generation circuit 680. The internal clock generation circuit 680 can receive the internal memory clock signal pair IMCK, IMCKB, and can delay the internal memory clock signal pair IMCK, IMCKB to generate a delayed memory clock signal pair IMCKD, IMCKDB. The internal clock generation circuit 680 can provide the delayed memory clock signal pair IMCKD, IMCKDB to the input / output driver circuit 660, and the input / output driver circuit 660 can receive the internal data signals IDQ0, IDQ1, IDQ2, …, IDQm-1 in synchronization with the delayed memory clock signal pair IMCKD, IMCKDB, and can output the internal data signals IDQ0, IDQ1, IDQ2, …, IDQm-1 in synchronization with the delayed memory clock signal pair IMCKD, IMCKDB.

[0101] The input / output buffer circuit 670 can be electrically connected with the interface circuit 230 through the memory data bus 263, and can be electrically connected with the input / output driver circuit 660 through the global data line GIO. During a write operation, the input / output buffer circuit 670 can generate internal data signals IDQ0, IDQ1, IDQ2, …, IDQm-1 based on memory data signals DQ0, DQ1, DQ2, …, DQm-1 transferred from the interface circuit 230 through the memory data bus 263, and output the internal data signals IDQ0, IDQ1, IDQ2, …, IDQm-1 to the global data line GIO. During a read operation, the input / output buffer circuit 670 receives internal data signals IDQ0, IDQ1, IDQ2, …, IDQm-1 transferred from the input / output driver circuit 660 through the global data line GIO, generates memory data signals DQ0, DQ1, DQ2, …, DQm-1 based on the internal data signals IDQ0, IDQ1, DQ2, …, DQm-1, and transfers the memory data signals DQ0, DQ1, DQ2, …, DQm-1 to the interface circuit 230 through the memory data bus 263. The input / output buffer circuit 670 can buffer the memory data signals DQ0, DQ1, DQ2, …, DQm-1 during a write operation to generate the internal data signals IDQ0, IDQ1, IDQ2, …, IDQm-1, and buffer the internal data signals IDQ0, IDQ1, IDQ2, …, IDQm-1 during a read operation to generate the memory data signals DQ0, DQ1, DQ2, …, DQm-1. The internal data signals IDQ0, IDQ1, IDQ2, …, IDQm-1 and the memory data signals DQ0, DQ1, DQ2, …, DQm-1 can be substantially the same type or same characteristic data signals, and the type or characteristic of the internal data signals IDQ0, IDQ1, IDQ2, …, IDQm-1 and the memory data signals DQ0, DQ1, DQ2, …, DQm-1 can not be changed by the input / output buffer circuit 670.

[0102] For example, the internal data signals IDQ0, IDQ1, IDQ2,..., IDQm-1 and the memory data signals DQ0, DQ1, DQ2,..., DQm-1 can be parallel data signals having the same number of bits. The number of signal transmission lines included in the global data lines GIO can be substantially the same as the number of signal transmission lines included in the memory data bus 263. The width of the data signals stored in each memory cell array 610 by a single write operation can be substantially the same as the width of the internal data signals IDQ0, IDQ1, IDQ2,..., IDQm-1 and the width of the memory data signals DQ0, DQ1, DQ2,..., DQm-1. The width of the data signals output from each memory cell array 610 in a single read operation can be substantially the same as the width of the internal data signals IDQ0, IDQ1, IDQ2,..., IDQm-1 and the width of the memory data signals DQ0, DQ1, DQ2,..., DQm-1. The width of the data signals can represent the number of data signals and / or the number of bits of the data signals. The input / output buffer circuit 670 can receive a write data strobe signal WDQS and generate a read data strobe signal RDQS. During a write operation, the input / output buffer circuit 670 can output the memory data signals DQ0, DQ1, DQ2,..., DQm-1 to the interface circuit 230 in response to the write data strobe signal WDQS. During a read operation, the input / output buffer circuit 670 can generate the read data strobe signal RDQS based on the write data strobe signal WDQS. The input / output buffer circuit 670 can output the memory data signals DQ0, DQ1, DQ2,..., DQm-1 to the interface circuit 230 in response to the read data strobe signal RDQS. The input / output buffer circuit 670 can output the read data strobe signal RDQS with the memory data signals DQ0, DQ1, DQ2,..., DQm-1 to the interface circuit 230. The input / output buffer circuit 670 can also receive a write select signal WTEN and a read select signal RDEN. The input / output buffer circuit 670 can activate a write path of the input / output buffer circuit 670 based on the write select signal WTEN and can activate a read path of the input / output buffer circuit 670 based on the read select signal RDEN. For example, the input / output buffer circuit 670 can include a transmitter for outputting the memory data signals DQ0, DQ1, DQ2,..., DQm-1 to the interface circuit 230 and a receiver for receiving the memory data signals DQ0, DQ1, DQ2,..., DQm-1 transmitted from the interface circuit 230. The transmitter of the input / output buffer circuit 670 can be activated based on the write select signal WTEN. The receiver of the input / output buffer circuit 670 can be activated based on the read select signal RDEN. Figure 2 The interface circuit 230 receives the write data strobe signal WDQS and can receive the memory data signals DQ0, DQ1, DQ2,..., DQm-1 transmitted from the interface circuit 230 in synchronization with the write data strobe signal WDQS. During a read operation, the input / output buffer circuit 670 can generate the read data strobe signal RDQS based on the write data strobe signal WDQS. The input / output buffer circuit 670 can output the memory data signals DQ0, DQ1, DQ2,..., DQm-1 to the interface circuit 230 in synchronization with the read data strobe signal RDQS. The input / output buffer circuit 670 can output the read data strobe signal RDQS with the memory data signals DQ0, DQ1, DQ2,..., DQm-1 to the interface circuit 230. The input / output buffer circuit 670 can also receive a write select signal WTEN and a read select signal RDEN. The input / output buffer circuit 670 can activate a write path of the input / output buffer circuit 670 based on the write select signal WTEN and can activate a read path of the input / output buffer circuit 670 based on the read select signal RDEN. For example, the input / output buffer circuit 670 can include a transmitter for outputting the memory data signals DQ0, DQ1, DQ2,..., DQm-1 to the interface circuit 230 and a receiver for receiving the memory data signals DQ0, DQ1, DQ2,..., DQm-1 transmitted from the interface circuit 230. The transmitter of the input / output buffer circuit 670 can be activated based on the write select signal WTEN. The receiver of the input / output buffer circuit 670 can be activated based on the read select signal RDEN.

[0103] Since the memory die 600 receives the row address signal RADD and the column address signal CADD from the interface circuit 230, the memory die 600 can not have a circuit for converting the address signal ADD to the row address signal RADD and the column address signal CADD according to the command signal CMD and a circuit for latching the converted address signal. For example, the input / output buffer circuit 670 can not include a SerDes for serializing the internal data signals IDQ0, IDQ1, IDQ2, …, IDQm-1 or for deserializing the memory data signals DQ0, DQ1, DQ2, …, DQm-1. With the large amount of detachable circuit, the memory die 600 can have a larger data storage capacity compared to a conventional memory die, and the memory die 600 can be smaller than a conventional memory die while maintaining the same data storage capacity. In addition, when the input / output buffer circuit 670 does not perform the serialization and deserialization operations on the data signals, the timing delay of the command control circuit 650, i.e., the latency of the memory die 600 and the memory device including the memory die 600, can be very short compared to a conventional memory die and memory device. Accordingly, the memory die 600 can perform the write and read operations on more data signals in a shorter period of time compared to a conventional device.

[0104] Figure 7 is a diagram illustrating a configuration of a computing system 700 according to an embodiment of the disclosure. Referring to Figure 7 , the computing system 700 can include a host 710, a memory controller 720, a first interface circuit 731, a second interface circuit 732, a first memory device 741, and a second memory device 742. The host 710 can be electrically connected to the memory controller 720 through a host bus 750. The memory controller 720 can be electrically connected to the first interface circuit 731 through a first controller bus 761, and can be electrically connected to the second interface circuit 732 through a second controller bus 762. The first interface circuit 731 can be electrically connected to the first memory device 741 through a first memory bus 771. The second interface circuit 732 can be electrically connected to the second memory device 742 through a second memory bus 772. The host 710 can have substantially the same configuration as the host 110 shown in Figure 1 and can perform substantially the same functions. The memory controller 720 can have substantially the same configuration as the memory controller 120 shown in Figure 1The illustrated memory controller 120 has substantially the same configuration and performs substantially the same functions. However, the memory controller 720 can be electrically connected to the first controller bus 761 and the second controller bus 762 to enable data communication with multiple memory devices. The host 710 can access either of the first memory device 741 and the second memory device 742 through the memory controller 720 and the first controller bus 761 and the second controller bus 762, or can access both the first memory device 741 and the second memory device 742 simultaneously. The host 710 can independently generate an access request to the first memory device 741 and an access request to the second memory device 742 to access the first memory device 741 and the second memory device 742, respectively, or simultaneously. The memory controller 720 can independently generate a control signal for accessing the first memory device 741 and a control signal for accessing the second memory device 742 to access the first memory device 741 and the second memory device 742, respectively, or simultaneously.

[0105] The host bus 750 can have substantially the same type and characteristics as the first bus 150 illustrated in Figure 1 The first controller bus 761 can have substantially the same type and characteristics as the second bus 160 illustrated in Figure 1 The first controller bus 761 can have substantially the same type and characteristics as the second bus 160 illustrated in Figure 1 The first controller bus 761 can have substantially the same type and characteristics as the second bus 160 illustrated in In an embodiment, the width of a data bus included in the first controller bus 761 can be less than or equal to the width of a data bus included in the first memory bus 771. The first interface circuit 731 can have substantially the same configuration as and can perform substantially the same functions as the interface circuit 130, 230 illustrated in Figure 1 and Figure 2 The first controller bus 761 can have substantially the same type and characteristics as the second bus 160 illustrated in The first controller bus 761 can have substantially the same type and characteristics as the second bus 160 illustrated in Figure 1 and Figure 2 The first controller bus 761 can have substantially the same type and characteristics as the second bus 160 illustrated in The first controller bus 761 can have substantially the same type and characteristics as the second bus 160 illustrated in

[0106] The second controller bus 762 can have substantially the same type and characteristics as the first controller bus 761. The second memory bus 772 can have substantially the same type and characteristics as the first memory bus 771. In an embodiment, the width of a data bus included in the second controller bus 762 can be less than or equal to the width of a data bus included in the second memory bus 772. The second interface circuit 732 can have substantially the same configuration as the first interface circuit 731 and can perform substantially the same functions. The second memory device 742 can have substantially the same configuration as the first memory device 741 and can perform substantially the same functions.

[0107] In an embodiment, the second memory bus 772 can have a different type and characteristics from the first memory bus 771. For example, the second memory bus 772 can include a serial data bus. The width of the data bus included in the second memory bus 772 can be smaller than the width of the data bus included in the second controller bus 762. The clock rate of the second memory bus 772 can be higher than the clock rate of the second controller bus 762. In this case, the second interface circuit 732 can have a different configuration and perform a different function from the first interface circuit 731, and the second memory device 742 can have a different configuration and perform a different function from the first memory device 741. For example, the first interface circuit 731 and the first memory device 741 can perform parallel data communication, while the second interface circuit 732 and the second memory device 742 can perform serial data communication. The first interface circuit 731 and the first memory device 741 do not need to perform data conversion, and thus can not be equipped with a SerDes. The second interface circuit 732 and the second memory device 742 need to perform data conversion for serial data communication, and thus can include a SerDes.

[0108] In an embodiment, the host 710, the memory controller 720, the first interface circuit 731, and the second interface circuit 732 can be integrated as a first device, and the first memory device 741 and the second memory device 742 can be integrated as a second device. Alternatively, the first memory device 741 can constitute the second device, and the second memory device 742 can constitute a third device. The host 710, the memory controller 720, the first interface circuit 731, and the second interface circuit 732 can be disposed on a first interposer and / or a first substrate. The first memory device 741 and the second memory device 742 can be disposed on a second interposer and / or a second substrate. The host bus 750, the first controller bus 761, and the second controller bus 762 can be internal buses, and the first memory bus 771 and the second memory bus 772 can be external buses. In an embodiment, the first memory device 741 can be disposed on the second interposer and / or the second substrate, and the second memory device 742 can be disposed on a third interposer and / or a third substrate.

[0109] In an embodiment, the host 710 and the memory controller 720 can be integrated as a first device, and the first interface circuit 731 and the second interface circuit 732 and the first memory device 741 and the second memory device 742 can be integrated as a second device. Alternatively, the first interface circuit 731 and the first memory device 741 can be integrated as a second device, and the second interface circuit 732 and the second memory device 742 can be integrated as a third device. The host 710 and the memory controller 720 can be disposed on a first interposer and / or a first substrate. The first interface circuit 731, the second interface circuit 732, the first memory device 741, and the second memory device 742 can be disposed on a second interposer and / or a second substrate. The host bus 750, the first memory bus 771, and the second memory bus 772 can be internal buses, and the first controller bus 761 and the second controller bus 762 can be external buses. In an embodiment, the first interface circuit 731 and the first memory device 741 can be disposed on the second interposer and / or the second substrate, and the second interface circuit 732 and the second memory device 742 can be disposed on a third interposer and / or a third substrate.

[0110] In an embodiment, the host 710 can constitute a first device, and the memory controller 720, the first interface circuit 731, the second interface circuit 732, the first memory device 741, and the second memory device 742 can be integrated as a second device. The host 710 can be disposed on a first interposer and / or a first substrate. The memory controller 720, the first interface circuit 731, the second interface circuit 732, the first memory device 741, and the second memory device 742 can be disposed on a second interposer and / or a second substrate. The host bus 750 can be an external bus, and the first controller bus 761 and the second controller bus 762 and the first memory bus 771 and the second memory bus 772 can be internal buses. In an embodiment, the host 710, the memory controller 720, the first interface circuit 731, and the second interface circuit 732 and the first memory device 741 and the second memory device 742 can be disposed on a single interposer and / or a single substrate. The host bus 750, the first controller bus 761 and the second controller bus 762 and the first memory bus 771 and the second memory bus 772 can all be internal buses. In an embodiment, some or all of the host 710, the memory controller 720, the first interface circuit 731, and the second interface circuit 732 and the first memory device 741 and the second memory device 742 can be fabricated as a chiplet.

[0111] Figure 8 FIG. 8 is a diagram illustrating a configuration of a computing system 800 according to an embodiment of the disclosure. Referring to FIG. 8, Figure 8The computing system 800 can include a host 810, a first memory controller 821, a second memory controller 822, a first interface circuit 831, a second interface circuit 832, a first memory device 841, and a second memory device 842. The first memory controller 821 can be electrically connected to the host 810 through a first host bus 851. The second memory controller 822 can be electrically connected to the host 810 through a second host bus 852. The first interface circuit 831 can be electrically connected to the first memory controller 821 through a first controller bus 861. The second interface circuit 832 can be electrically connected to the second memory controller 822 through a second controller bus 862. The first memory device 841 can be electrically connected to the first interface circuit 831 through a first memory bus 871. The second memory device 842 can be electrically connected to the second interface circuit 832 through a second memory bus 872. The host 810 can be electrically connected to the first memory controller 821 and the second memory controller 822 independently for independent access to the first memory device 841 and the second memory device 842. The host 810 can generate a first access request to the first memory device 841 and a second access request to the second memory device 842 independently. In an embodiment, the host 810 can include a plurality of processing cores to generate the first access request and the second access request independently. The host 810 can provide the first access request to the first memory controller 821 through the first host bus 851, and can provide the second access request to the second memory controller 822 through the second host bus 852.

[0112] The first host bus 851 and the second host bus 852 can each have substantially the same type and characteristics as the first bus 150 shown in Figure 1 The first controller bus 861 and the second controller bus 862 can each have substantially the same type and characteristics as the second bus 160 shown in Figure 1 The first memory bus 871 can have substantially the same type and characteristics as the third bus 170 shown in Figure 1 In an embodiment, a width of a data bus included in the first controller bus 861 can be less than or equal to a width of a data bus included in the first memory bus 871. The first interface circuit 831 can have substantially the same configuration and perform substantially the same functions as the interface circuit 130, 230 shown in Figure 1 and Figure 2 The first memory device 841 can have substantially the same configuration and perform substantially the same functions as the memory device 140, 240 shown in Figure 1 and Figure 2 The first memory device 841 can have substantially the same configuration and perform substantially the same functions as the memory device 140, 240 shown in

[0113] The second controller bus 862 can be of substantially the same type and characteristics as the first controller bus 861. The second memory bus 872 can be of substantially the same type and characteristics as the first memory bus 871. In one embodiment, the width of the data bus included in the second controller bus 862 can be less than or equal to the width of the data bus included in the second memory bus 872. The second interface circuit 832 can have substantially the same configuration as the first interface circuit 831 and can perform substantially the same functions. The second memory device 842 can have substantially the same configuration as the first memory device 841 and can perform substantially the same functions. In one embodiment, the second memory bus 872 can be of a different type and characteristics than the first memory bus 871. For example, the second memory bus 872 can include a serial data bus. The width of the data bus included in the second memory bus 872 can be less than the width of the data bus included in the second controller bus 862. The clock rate of the second memory bus 872 can be higher than the clock rate of the second controller bus 862. In this case, the second interface circuit 832 can have a different configuration and perform different functions than the first interface circuit 831, and the second memory device 842 can have a different configuration and perform different functions than the first memory device 841. For example, the first interface circuit 831 and the first memory device 841 can communicate data in parallel, while the second interface circuit 832 and the second memory device 842 can communicate data in serial. The first interface circuit 831 and the first memory device 841 need not convert data, and therefore can not be equipped with SerDes. The second interface circuit 832 and the second memory device 842 need to convert data for serial data communication, and therefore can include SerDes.

[0114] In one embodiment, the host 810, the first memory controller 821, the second memory controller 822, the first interface circuit 831, and the second interface circuit 832 can be integrated as a first device. The first memory device 841 and the second memory device 842 can be integrated as a second device. Alternatively, the first memory device 841 can constitute the second device, and the second memory device 842 can constitute a third device. The host 810, the first memory controller 821, and the second memory controller 822, and the first interface circuit 831 and the second interface circuit 832 can be disposed on a first interposer and / or a first substrate. The first memory device 841 and the second memory device 842 can be disposed on a second interposer and / or a second substrate. The first host bus 851 and the second host bus 852, the first controller bus 861 and the second controller bus 862 can be internal buses, and the first memory bus 871 and the second memory bus 872 can be external buses. In one embodiment, the first memory device 841 can be disposed on the second interposer and / or the second substrate, and the second memory device 842 can be disposed on a third interposer and / or a third substrate.

[0115] In one embodiment, the host 810, the first memory controller 821, and the second memory controller 822 can be integrated as a first device. The first interface circuit 831 and the second interface circuit 832, the first memory device 841 and the second memory device 842 can be integrated as a second device. Alternatively, the first interface circuit 831 and the first memory device 841 can be integrated as a second device, and the second interface circuit 832 and the second memory device 842 can be integrated as a third device. The host 810, the first memory controller 821, and the second memory controller 822 can be disposed on a first interposer and / or a first substrate. The first interface circuit 831 and the second interface circuit 832, the first memory device 841 and the second memory device 842 can be disposed on a second interposer and / or a second substrate. The first host bus 851 and the second host bus 852, the first memory bus 871 and the second memory bus 872 can be internal buses, and the first controller bus 861 and the second controller bus 862 can be external buses. In one embodiment, the first interface circuit 831 and the first memory device 841 can be disposed on the second interposer and / or the second substrate, and the second interface circuit 832 and the second memory device 842 can be disposed on a third interposer and / or a third substrate.

[0116] In an embodiment, the host 810 can constitute a first device, and the first memory controller 821 and the second memory controller 822, the first interface circuit 831 and the second interface circuit 832, and the first memory device 841 and the second memory device 842 can be integrated as a second device. Alternatively, the first memory controller 821, the first interface circuit 831, and the first memory device 841 can be integrated as a second device, and the second memory controller 822, the second interface circuit 832, and the second memory device 842 can be integrated as a third device. The host 810 can be disposed on a first interposer and / or a first substrate. The first memory controller 821 and the second memory controller 822, the first interface circuit 831 and the second interface circuit 832, and the first memory device 841 and the second memory device 842 can be disposed on a second interposer and / or a second substrate. The first host bus 851 and the second host bus 852 can be external buses, and the first controller bus 861 and the second controller bus 862 and the first memory bus 871 and the second memory bus 872 can be internal buses. In an embodiment, the first memory controller 821, the first interface circuit 831, and the first memory device 841 can be disposed on the second interposer and / or the second substrate, and the second memory controller 822, the second interface circuit 832, and the second memory device 842 can be disposed on a third interposer and / or a third substrate.

[0117] In an embodiment, the host 810, the first memory controller 821 and the second memory controller 822, the first interface circuit 831 and the second interface circuit 832, and the first memory device 841 and the second memory device 842 can be arranged on a single interposer and / or a single substrate. The first host bus 851 and the second host bus 852, the first controller bus 861 and the second controller bus 862, and the first memory bus 871 and the second memory bus 872 can all be internal buses. In an embodiment, some or all of the host 810, the first memory controller 821 and the second memory controller 822, the first interface circuit 831 and the second interface circuit 832, and the first memory device 841 and the second memory device 842 can be manufactured as a chiplet.

[0118] Figure 9A is a diagram illustrating a configuration and a connection relationship of an integrated circuit package 900a according to an embodiment of the present disclosure. Referring to Figure 9AThe integrated circuit package can include a substrate 901a, a memory controller 910a, an interface circuit 920a, and a memory device 930a. The memory controller 910a, the interface circuit 920a, and the memory device 930a can be fabricated as separate dies and / or cores. Some or all of the memory controller 910a, the interface circuit 920a, and the memory device 930a can be fabricated using process technologies having different characteristics. The memory controller 910a, the interface circuit 920a, and the memory device 930a can be disposed on the substrate 901a. The memory controller 910a can be disposed in a first region on the substrate 901a. The interface circuit 920a can be disposed in a second region on the substrate 901a. The memory device 930a can be disposed in a third region on the substrate 901a. The first region and the third region can not overlap, and the second region can be between the first region and the third region. The memory device 930a is shown to include a single memory die. For example, the memory controller 910a, the interface circuit 920a, and the memory device 930a can be attached to the substrate 901a using an adhesive. The substrate 901a can include any substrate having pads capable of wire bonding, and can be one of, for example, a package substrate, an organic substrate, and a module substrate. The substrate 901a can include external terminals 902a under the substrate for electrical connection with external devices. The external terminals 902a can include solder balls or package balls.

[0119] The memory controller 910a can be electrically connected to the substrate 901a by wire bonding pads formed on a first side (e.g., left side) of the memory controller 910a to pads formed on the substrate 901a. The wire bonds between the memory controller 910a and the substrate 901a can be first wire bonds. The memory controller 910a can be electrically connected to the substrate 901a by wire bonding pads formed on a second side (e.g., right side) of the memory controller 910a to pads formed on the substrate 901a. The wire bonds between the memory controller 910a and the substrate 901a can be second wire bonds. Figure 9A Figure 9A ​The pads on the right side of the interface circuit 920a are wire-bonded to the pads formed on the first side of the interface circuit 920a, thereby electrically connecting the interface circuit 920a to the interface circuit 920a. The wire bonding between the memory controller 910a and the interface circuit 920a can be a second wire bonding. The interface circuit 920a can be electrically connected to the memory device 930a by wire bonding the pads formed on the second side of the interface circuit 920a to the pads formed on the first side of the memory device 930a. The wire bonding between the interface circuit 920a and the memory device 930a can be a third wire bonding. The memory device 930a can be electrically connected to the substrate 901a by wire bonding the pads formed on the second side of the memory device 930a to the pads formed on the substrate 901a. The wire bonding between the memory device 930a and the substrate 901a can be a fourth wire bonding. The substrate 901a, the memory controller 910a, the interface circuit 920a, and the memory device 930a can be packaged in a single package. Since the memory controller 910a, interface circuit 920a, and memory device 930a are electrically connected by wire bonding, a low-cost substrate can be used, and the manufacturing cost of the integrated circuit package can be reduced. The first wire bonding between the memory controller 910a and the substrate 901a can correspond to... Figure 1 Part or all of the first bus 150 shown. The second lead bonding between the memory controller 910a and the interface circuit 920a may correspond to Figure 1 The second bus 160 shown. The third lead bonding between the interface circuit 920a and the memory device 930a can correspond to Figure 1 The third bus 170 is shown. The fourth wire bond between the memory device 930a and the substrate 901a can correspond to a direct access path for an external device to access the memory device 930a. The frequency of the signal transmitted via the second wire bond can be greater than or equal to the frequency of the signal transmitted via the third wire bond. The frequency of the signal transmitted via the wire bond can be related to a clock rate or clock frequency. The signal can be transmitted via the second wire bond at a first clock rate, and the signal can be transmitted via the third wire bond at a second clock rate. The first clock rate can be greater than or equal to the second clock rate. The second wire bond may include a first data bus, and the third wire bond may include a second data bus. The number of data signals transmitted at one time via the first data bus can be less than or equal to the number of data signals transmitted at one time via the second data bus.

[0120] Figure 9B A diagram illustrating the configuration and interconnections of an integrated circuit package 900b according to an embodiment of this disclosure. See also... Figure 9BThe integrated circuit package 900b can include a first substrate 901b, a memory controller 910b, an interface circuit 920b, and a memory device 930b. The memory controller 910b, the interface circuit 920b, and the memory device 930b can be disposed on the first substrate 901b. The first substrate 901b can include an interposer. The memory controller 910b can be disposed in a first region on the first substrate 901b. The interface circuit 920b can be disposed in a second region on the first substrate 901b. The memory device 930b can be disposed in a third region on the first substrate 901b. The first region and the third region can not overlap, and the second region can be between the first region and the third region. The memory device 930b is shown to include a single memory die. The integrated circuit package 900b can further include a second substrate 905b. The second substrate 905b can include a redistribution layer or an interposer. The second substrate 905b can be disposed to electrically connect the memory device 930b and the first substrate 901b, and the second substrate 905b can be disposed on the first substrate 901b. The second substrate 905b can be disposed in the third region on the first substrate 901b. The second substrate 905b can include a plurality of signal paths to electrically connect the memory device 930b to the first substrate 901b. The memory device 930b can be disposed on the second substrate 905b. When the second substrate 905b is an interposer, the memory device 930b can be electrically connected to the second substrate 905b by micro bumps. When the second substrate 905b is a redistribution layer, the memory device 930b can be electrically connected to the second substrate 905b by micro bumps or can be electrically connected to the second substrate 905b without micro bumps. In an embodiment, the memory device 930b can be directly electrically connected to the first substrate 901b without the second substrate 905b. The first substrate 901b can include external terminals 902b below the first substrate 901b for electrical connection with external devices. The external terminals 902b can include micro bumps or bumps. In an embodiment, the integrated circuit package 900b can further include another substrate on which the first substrate 901b can be disposed. The another substrate can include another interposer or a package substrate. When the another substrate is provided, the first substrate 901b can be electrically connected to the another substrate by micro bumps or bumps, and can be electrically connected to external devices through the another substrate.

[0121] The first substrate 901b can include a plurality of signal paths 911b, 921b, 931b, 941b for electrically connecting components disposed on the first substrate 901b. The memory controller 910b can be electrically connected to the first substrate 901b by micro-bumps 903b. The interface circuit 920b can be electrically connected to the first substrate 901b by micro-bumps 904b. The memory device 930b can be electrically connected to the first substrate 901b by micro-bumps 906b. The memory controller 910b can be electrically connected with the signal paths 911b and the external terminals 902b of the first substrate 901b by the micro-bumps 903b on the first side of the memory controller 910b. The memory controller 910b can be electrically connected with the micro-bumps 904b on the first side of the interface circuit 920b and the signal paths 921b of the first substrate 901b by the micro-bumps 903b on the second side of the memory controller 910b. The interface circuit 920b can be electrically connected with the micro-bumps 906b on the first side of the second substrate 905b by the micro-bumps 904b on the second side of the interface circuit 920b and the signal paths 931b of the first substrate 901b. The memory device 930b can be electrically connected with the external terminals 902b by the micro-bumps 906b on the second side of the second substrate 905b and the signal paths 941b of the first substrate 901b.

[0122] The first substrate 901b, the memory controller 910b, the interface circuit 920b, and the memory device 930b can be packaged in a single package. Disposing the memory controller 910b, the interface circuit 920b, and the memory device 930b on the first substrate 901b can facilitate integrated circuit package manufacturing and reduce integrated circuit package size because no wire bonding is needed. The electrical connection between the memory controller 910b and the signal paths 911b of the first substrate 901b can correspond to part or all of the first bus 150 shown in FIG. 1. Figure 1 The electrical connection of the memory controller 910b and the signal paths 921b of the first substrate 901b can correspond to the second bus 160 shown in FIG. 1. Figure 1 The electrical connection of the interface circuit 920b and the signal paths 931b of the first substrate 901b can correspond to the third bus 170 shown in FIG. 1. Figure 1The third bus 170 is shown. The electrical connection between the memory device 930b and the signal path 941b of the first substrate 901b can correspond to a direct access path to the memory device 930b. The frequency of signals transmitted through the signal path 921b can be greater than or equal to the frequency of signals transmitted through the signal path 931b. The signals can be transmitted through the signal path 921b at a first clock rate, and the signals can be transmitted through the signal path 931b at a second clock rate. The first clock rate can be greater than or equal to the second clock rate. The signal path 921b can include a first data bus, and the signal path 931b can include a second data bus. The number of data signals transmitted through the first data bus at one time can be less than or equal to the number of data signals transmitted through the second data bus at one time.

[0123] Figure 9C is a diagram illustrating a configuration and a connection relationship of an integrated circuit package 900c according to an embodiment of the present disclosure. Referring to Figure 9CThe integrated circuit package 900c can include a first substrate 901c, a memory controller 910c, an interface circuit 920c, and a memory device 930c. The memory controller 910c, the interface circuit 920c, and the memory device 930c can be disposed on the first substrate 901c. The first substrate 901c can include an interposer. The memory controller 910c can be disposed in a first region on the first substrate 901c. The interface circuit 920c can be disposed in a second region on the first substrate 901c. The memory device 930c can be disposed in a third region on the first substrate 901c. The first region and the third region can not overlap, and the second region can be between the first region and the third region. The memory device 930c can include one or more memory dies. The number of memory dies included by the memory device 930c can be two, four, eight, or more. For example, the memory device 930c can include first through fourth memory dies. The number of memory dies included by the memory device 930c can be two, or can be eight or more. The integrated circuit package 900c can also include a second substrate 905c. The second substrate 905c can include a redistribution layer or an interposer. The second substrate 905c can be disposed to electrically connect the memory device 930c and the first substrate 901c, and the second substrate 905c can be disposed on the first substrate 901c. The second substrate 905c can be disposed in the third region on the first substrate 901c. The second substrate 905c can include a plurality of signal paths to electrically connect the memory device 930c to the first substrate 901c. The first through fourth memory dies can be disposed on the second substrate 905c. The memory controller 910c can be electrically connected to the first substrate 901c by micro bumps 903c. The interface circuit 920c can be electrically connected to the first substrate 901c by micro bumps 904c. The second substrate 905c can be electrically connected to the first substrate 901c by micro bumps 906c. The first substrate 901c can include external terminals 902c below the first substrate 901c to electrically connect to external devices. The external terminals 902c can include micro bumps or bumps. In an embodiment, the integrated circuit package 900c can also include another substrate on which the first substrate 901c can be disposed. The another substrate can include another interposer or a package substrate. When the another substrate is disposed, the first substrate 901c can be electrically connected to the another substrate by micro bumps or bumps, and can be electrically connected to external devices by the another substrate.

[0124] The memory controller 910c can be electrically connected to the signal path 911c and the external terminal 902c of the first substrate 901c through the micro bumps 903c on the first side of the memory controller 910c. The memory controller 910c can be electrically connected with the micro bumps 904c on the first side of the interface circuit 920c and the signal path 921c of the first substrate 901c through the micro bumps 903c on the second side of the memory controller 910c. The interface circuit 920c can be electrically connected with the micro bumps 906c on the first side of the second substrate 905c through the micro bumps 904c on the second side of the interface circuit 920c and the signal path 931c of the first substrate 901c. The second substrate 905c can be electrically connected to the external terminal 902c through the micro bumps 906c on the second side of the second substrate 905c and the signal path 941c of the first substrate 901c. The first to fourth memory dies can be sequentially stacked on the second substrate 905c. The DAFs (die attach films) 907c can be respectively disposed between the first memory die and the second memory die, between the second memory die and the third memory die, and between the third memory die and the fourth memory die, and the first to fourth memory dies can be adhered using the DAFs 907c. The DAFs 907c can increase the strength of the memory dies to prevent the memory dies from warping and to leave space for wire bonding. The first to fourth memory dies can be stacked in a stepped manner. The pads of the fourth memory die can be wire-bonded to the pads of the third memory die, the pads of the third memory die can be wire-bonded to the pads of the second memory die. The pads of the second memory die can be wire-bonded to the pads of the first memory die, and the pads of the first memory die can be wire-bonded to the pads formed on the second substrate 905c. In an embodiment, the pads of the first memory die can be wire-bonded to the pads formed on the second substrate 905c, and the pads of the second memory die can be wire-bonded to the pads formed on the second substrate 905c. The pads of the third memory die can be wire-bonded to the pads formed on the second substrate 905c, and the pads of the fourth memory die can be wire-bonded to the pads formed on the second substrate 905c. The pads of the first memory die and the fourth memory die can be commonly wire-bonded to the same pads on the second substrate 905c, and the first memory die and the fourth memory die can form a common channel. In an embodiment, the pads of the first to fourth memory dies can be wire-bonded to different pads of the second substrate 905c, and the first to fourth memory dies can form independent channels from each other.

[0125] The first substrate 901c, the memory controller 910c, the interface circuit 920c, and the memory device 930c can be packaged in a single package. The signal path 911c between the memory controller 910c and the first substrate 901c can correspond toFigure 1 Part or all of the first bus 150 shown. The signal path 921c of the first substrate 901c electrically connecting the memory controller 910c and the interface circuit 920c can correspond to Figure 1 The second bus 160 shown. The electrical connection interface circuit 920c of the first substrate 901c and the signal path 931c of the second substrate 905c, as well as the wire bonding connecting the second substrate 905c to the first to fourth memory dies, can correspond to Figure 1 The third bus 170 is shown. Signal path 941c of the first substrate 901c can correspond to a direct access path to the memory device 930c. The frequency of the signal transmitted through signal path 921c can be greater than or equal to the frequency of the signal transmitted through signal path 931c. Signals can be transmitted through signal path 921c at a first clock rate, and signals can be transmitted through signal path 931c at a second clock rate. The first clock rate can be greater than or equal to the second clock rate. Signal path 921c may include a first data bus, and signal path 931c may include a second data bus. The number of data signals transmitted at one time through the first data bus can be less than or equal to the number of data signals transmitted at one time through the second data bus.

[0126] Figure 9D A diagram illustrating the configuration and connection relationships of an integrated circuit package 900d according to an embodiment of the present disclosure. See also... Figure 9DThe integrated circuit package 900d can include a first substrate 901d, a memory controller 910d, an interface circuit 920d, and a memory device 930d. The memory controller 910d, the interface circuit 920d, and the memory device 930d can be disposed on the first substrate 901d. The first substrate 901d can include an interposer. The memory controller 910d can be disposed in a first region on the first substrate 901d. The interface circuit 920d can be disposed in a second region on the first substrate 901d. The memory device 930d can be disposed in a third region on the first substrate 901d. The first region can not overlap the third region, and the second region can be between the first region and the third region. The memory device 930d can include one or more memory dies. The number of memory dies included by the memory device 930d can be two, four, eight, or more. For example, the memory device 930d can include first through fourth memory dies. The integrated circuit package 900d can further include a second substrate 905d. The second substrate 905d can include a redistribution layer or an interposer. The second substrate 905d can be disposed to electrically connect the memory device 930c and the first substrate 901d, and the second substrate 905d can be disposed on the first substrate 901d. The second substrate 905d can be disposed in the third region on the first substrate 901d. The second substrate 905d can include a plurality of signal paths to electrically connect the memory device 930d to the first substrate 901d. The first through fourth memory dies can be stacked on the second substrate 905d. The first substrate 901d can include external terminals 902d below the first substrate 901d to electrically connect with external devices. The external terminals 902d can include micro bumps or bumps. In an embodiment, the integrated circuit package 900d can further include another substrate, and the first substrate 901d can be disposed on the another substrate. The another substrate can include another interposer or a package substrate. When the another substrate is provided, the first substrate 901d can be electrically connected to the another substrate by micro bumps or bumps, and to external devices through the another substrate.

[0127] The memory controller 910d can be electrically connected to the first substrate 901d through micro-bumps 903d. The interface circuit 920d can be electrically connected with the first substrate 901d through micro-bumps 904d. The second substrate 905d can be electrically connected with the first substrate 901d through micro-bumps 906d. The memory controller 910d can be electrically connected with the signal path 911d and the external terminals 902d of the first substrate 901d through the micro-bumps 903d on the first side of the memory controller 910d. The memory controller 910d can be electrically connected with the micro-bumps 904d on the first side of the interface circuit 920d and the signal path 921d of the first substrate 901d through the micro-bumps 903d on the second side of the memory controller 910d. The interface circuit 920d can be electrically connected with the micro-bumps 906d on the first side of the second substrate 905d and the signal path 931d of the first substrate 901d through the micro-bumps 904d on the second side of the interface circuit 920d. The second substrate 905d can be electrically connected with the external terminals 902d and the signal path 941d of the first substrate 901d through the micro-bumps 906d on the second side of the second substrate 905d. The first to fourth memory dies can be sequentially stacked on the second substrate 905d. The first to fourth memory dies can be vertically aligned and stacked. The vias 907d can be formed in the first to fourth memory dies, and the first to fourth memory dies can be electrically connected to each other through the vias 907d and the micro-bumps 908d. When the first to fourth memory dies are electrically connected through the vias 907d, the first to fourth memory dies do not need to be stacked in a stepped manner as shown in Figure 9C FIG. 1, but can be stacked in a vertically aligned manner. Accordingly, the area of the second substrate 905d and the integrated circuit package size can be reduced. The first to fourth memory dies can be electrically connected with a common signal path of the second substrate 905d, and the first to fourth memory dies can form a common channel. In an embodiment, the first to fourth memory dies can be electrically connected with the second substrate 905d in different signal paths, and the first to fourth memory dies can form independent channels from each other.

[0128] The first substrate 901d, the memory controller 910d, the interface circuit 920d, and the memory device 930d can be packaged in a single package. The signal path 911d between the memory controller 910d and the first substrate 901d can correspond to part or all of the first bus 150 shown in Figure 1 FIG. 1. The signal path 921d of the first substrate 901d electrically connecting the memory controller 910d and the interface circuit 920d can correspond to part or all of the second bus 160 shown in Figure 1The second bus 160 shown. The electrical connection interface circuit 920d of the first substrate 901d and the signal path 931d of the second substrate 905d, as well as the microbumps 908d and vias 907d that electrically connect the second substrate 905d and the first to fourth memory dies, can correspond to Figure 1 The third bus 170 is shown. Signal path 941d of the first substrate 901d can correspond to a direct access path to the memory device 930d. The frequency of the signal transmitted via signal path 921d can be greater than or equal to the frequency of the signal transmitted via signal path 931d. Signals can be transmitted via signal path 921d at a first clock rate, and signals can be transmitted via signal path 931d at a second clock rate. The first clock rate can be greater than or equal to the second clock rate. Signal path 921d may include a first data bus, and signal path 931d may include a second data bus. The number of data signals transmitted at one time via the first data bus can be less than or equal to the number of data signals transmitted at one time via the second data bus.

[0129] Figure 9E A diagram illustrating the configuration and interconnections of an integrated circuit package 900e according to an embodiment of the present disclosure. (See reference...) Figure 9E The integrated circuit package 900e may include a substrate 901e, a die 91e, and a memory device 930e. The die 91e may include a memory controller 910e and interface circuitry 920e. The memory controller 910e and interface circuitry 920e may be internal circuitry of the die 91e. The die 91e and memory device 930e may be manufactured as separate dies and / or chips. The die 91e and memory device 930e may be manufactured using process technologies with different characteristics, or using process technologies with the same characteristics. The die 91e and memory device 930e may be disposed on the substrate 901e. The substrate 901e may include an interposer layer. The die 91e may be disposed in a first region on the substrate 901e, while the memory device 930e may be disposed in a second region on the substrate 901e. The first and second regions may not overlap. The memory device 930e is shown as comprising a single memory die. The substrate 901e may include an external terminal 902e located beneath the substrate 901e, the external terminal 902e being used for electrical connection to an external device. The external terminal 902e may include microbumps or bumps. In one embodiment, the integrated circuit package 900e may further include another substrate, on which the substrate 901e may be disposed. The other substrate may include another interposer or package substrate. When the other substrate is provided, the substrate 901e may be electrically connected to the other substrate via microbumps or bumps, and electrically connected to an external device via the other substrate.

[0130] The substrate 901e may include multiple signal paths 911e, 931e, and 941e for electrically connecting components disposed on the substrate 901e. The memory controller 910e may be electrically connected to the signal path 911e and the external terminal 902e via a microbump 903e on a first side of the die 91e. The memory controller may be electrically connected to the interface circuit 920e via a signal transmission line 921e inside the die 91e. Hereinafter, an electrical connection component for electrically connecting internal circuitry formed within a die may be referred to as a signal transmission line, and an electrical connection component formed on the interposer and / or substrate may be referred to as a signal path. The interface circuit 920e may be electrically connected to the signal path 931e via a microbump 904e on a second side of the die 91e. The memory device 930e may be electrically connected to the signal path 931e via a microbump 905e on a first side of the memory device 930e. The memory device 930b can be electrically connected to the external terminal 902e via a micro-bump 905e on the second side of the memory device 930b and a signal path 941e.

[0131] The substrate 901e, die 91e, and memory device 930e can be packaged in a single package. Placing the die 91e and memory device 930e on the substrate 901e facilitates integrated circuit package manufacturing and reduces the package size because wire bonding is not required. The electrical connection between the memory controller 910e and the signal path 911e can correspond to... Figure 1 Part or all of the first bus 150 shown. The signal transmission line 921e, which electrically connects the memory controller 910e and the interface circuit 920e, may correspond to... Figure 1 The second bus 160 shown. The signal path 931e of the electrical connection interface circuit 920e and the memory device 930e can correspond to Figure 1 The third bus 170 is shown. The electrical connection between memory device 930e and signal path 941e can correspond to a direct access path to memory device 930e. The frequency of the signal transmitted via signal transmission line 921e can be greater than or equal to the frequency of the signal transmitted via signal path 931e. Signal transmission line 921e may include a first data bus, and signal path 931e may include a second data bus. Signals can be transmitted via signal transmission line 921e at a first clock rate, and signals can be transmitted via signal path 931e at a second clock rate. The first clock rate can be greater than or equal to the second clock rate. The number of data signals transmitted at one time via the first data bus can be less than or equal to the number of data signals transmitted at one time via the second data bus.

[0132] Figure 10A This is a diagram illustrating the configuration and connection relationships of an integrated circuit package 1000a according to an embodiment of the present disclosure. (See reference...)Figure 10A The integrated circuit package 1000a may include a first substrate 1001a, a second substrate 1002a, a host 1010a, a memory controller 1020a, an interface circuit 1030a, and a memory device 1040a. The memory device 1040a may include... Figures 9B-9D Any one of the memory devices 930b to 930d shown. The host 1010a, memory controller 1020a, interface circuit 1030a, and memory device 1040a can be manufactured as separate dies and / or chips. Some or all of the host 1010a, memory controller 1020a, interface circuit 1030a, and memory device 1040a can be manufactured using process technologies with different characteristics. The host 1010a, memory controller 1020a, and interface circuit 1030a can be disposed on a first substrate 1001a. The first substrate 1001a may include a first interposer layer. The host 1010a can be disposed in a first region on the first substrate 1001a. The memory controller 1020a can be disposed in a second region on the first substrate 1001a. The interface circuit 1030a can be disposed in a third region on the first substrate 1001a. The first and third regions may not overlap, and the second region may be located between the first and third regions. The host 1010a can be electrically connected to the first substrate 1001a via microbumps. The memory controller 1020a can be electrically connected to the first substrate 1001a via microbumps. The interface circuit 1030a can be electrically connected to the first substrate 1001a via microbumps. The memory device 1040a can be disposed on the second substrate 1002a. The second substrate 1002a may include a second interposer. The memory device 1040a can be electrically connected to the second substrate 1002a via microbumps. The first substrate 1001a and the second substrate 1002a can be disposed on a third substrate 1003a. The third substrate 1003a may include another interposer or a package substrate. The first substrate 1001a can be disposed in a first region on the third substrate 1003a, and the second substrate 1002a can be disposed in a second region on the third substrate 1003a. The first region and the second region may not overlap. The first substrate 1001a and the second substrate 1002a can be electrically connected to the third substrate 1003a through microbumps or bumps in the first substrate 1001a and the second substrate 1002a, respectively. The third substrate 1003a can be electrically connected to an external device through external terminals of the third substrate 1003a. The external terminals may include microbumps, bumps, solder balls, or encapsulation balls.

[0133] The host 1010a can be electrically connected to the memory controller 1020a via a signal path 1011a formed in the first substrate 1001a. The memory controller 1020a can be electrically connected to the interface circuit 1030a via the signal path 1021a of the first substrate 1001a. The interface circuit 1030a can be electrically connected to the memory device 1040a via the signal path 1031a of the first substrate 1001a, the signal path 1032a formed in the third substrate 1003a, and the signal path 1033a of the second substrate 1002a. The signal path 1011a between the host 1010a and the memory controller 1020a can correspond to... Figure 1 The first bus 150 is shown. The signal path 1021a between the memory controller 1020a and the interface circuit 1030a can correspond to... Figure 1 The second bus 160 shown. The signal paths 1031a, 1032a, and 1033a between the interface circuit 1030a and the memory device 1040a can correspond to Figure 1 The third bus 170 is shown. The frequency of the signal transmitted through signal path 1021a can be greater than or equal to the frequency of the signal transmitted through signal paths 1031a, 1032a, and 1033a. The signal can be transmitted through signal path 1021a at a first clock rate, and the signal can be transmitted through signal paths 1031a, 1032a, and 1033a at a second clock rate. The first clock rate can be greater than or equal to the second clock rate. Signal path 1021a may include a first data bus, while signal paths 1031a, 1032a, and 1033a may include a second data bus. The number of data signals transmitted at one time through the first data bus can be less than or equal to the number of data signals transmitted at one time through the second data bus. In one embodiment, the first substrate 1001a, the host 1010a, the memory controller 1020a, and the interface circuit 1030a on the first substrate 1001a can be packaged in a first package. The memory device 1040a on the second substrate 1002a can be packaged in a second package. The first package and the second package can be disposed on the third substrate 1003a and encapsulated in the third package, while the integrated circuit package 1000a can be manufactured in a PIP (package in package) structure.

[0134] Figure 10B This is a diagram illustrating the configuration and connection relationships of an integrated circuit package 1000b according to an embodiment of the present disclosure. (See reference...) Figure 10B The integrated circuit package 1000b may include a first substrate 1001b, a second substrate 1002b, a host 1010b, a memory controller 1020b, an interface circuit 1030b, and a memory device 1040b. The memory device 1040b may include... Figures 9B-9DThe memory controller 1020b can be electrically connected to the second substrate 1002b by micro bumps of the memory controller 1020b. The interface circuit 1030b can be electrically connected to the second substrate 1002b by micro bumps of the interface circuit 1030b. The memory device 1040b can be electrically connected to the second substrate 1002b by micro bumps of the memory device 1040b. The first substrate 1001b and the second substrate 1002b can be disposed on a third substrate 1003b. The third substrate 1003b can include another interposer or a package substrate. The first substrate 1001b can be disposed in a first area on the third substrate 1003b, and the second substrate 1002b can be disposed in a second area on the third substrate 1003b. The first area and the second area can not overlap each other. The first substrate 1001b and the second substrate 1002b can be electrically connected to the third substrate 1003b by micro bumps or bumps in the first substrate 1001b and the second substrate 1002b, respectively. The third substrate 1003b can be electrically connected to an external device by external terminals of the third substrate 1003b. The external terminals can include micro bumps, bumps, solder balls, or package balls.

[0135] The host 1010b can be electrically connected to the memory controller 1020b by a signal path 1011b formed in the first substrate 1001b, a signal path 1012b formed in the third substrate 1003b, and a signal path 1013b formed in the second substrate 1002b. The memory controller 1020b can be electrically connected to the interface circuit 1030b by a signal path 1021b of the second substrate 1002b. The interface circuit 1030b can be electrically connected to the memory device 1040b by a signal path 1031b of the second substrate 1002b. The signal paths 1011b, 1012b, 1013b between the host 1010b and the memory controller 1020b can correspond to the signal paths 1011a, 1012a, 1013a of FIG. 1A, respectively. The signal paths 1021b, 1031b of the second substrate 1002b can correspond to the signal paths 1021a, 1031a of FIG. 1A, respectively. Figure 1The first bus 150 is shown. The signal path 1021b between the memory controller 1020b and the interface circuit 1030b can correspond to Figure 1 The second bus 160 is shown. The signal path 1031b between the interface circuit 1030b and the memory device 1040b can correspond to Figure 1 The third bus 170 is shown. The frequency of the signals transmitted through the signal path 1021b can be greater than or equal to the frequency of the signals transmitted through the signal path 1031b. The signals can be transmitted through the signal path 1021b at a first clock rate, and the signals can be transmitted through the signal path 1031b at a second clock rate. The first clock rate can be greater than or equal to the second clock rate. The signal path 1021b can include a first data bus, and the signal path 1031b can include a second data bus. The number of data signals transmitted through the first data bus at one time can be less than or equal to the number of data signals transmitted through the second data bus at one time. In an embodiment, the first substrate 1001b and the host 1010b can be packaged in a first package. The second substrate 1002b, the memory controller 1020b located on the second substrate 1002b, the interface circuit 1030b, and the memory device 1040b can be packaged in a second package. The first package and the second package can be disposed on a third substrate 1003b and packaged in a third package, and the integrated circuit package 1000b can be manufactured in a PIP (Package In Package) structure.

[0136] Figure 10C is a diagram showing a configuration and a connection relationship of an integrated circuit package 1000c according to an embodiment of the present disclosure. Referring to Figure 10C , the integrated circuit package 1000c can include a first substrate 1001c, a second substrate 1002c, a host 1010c, a memory controller 1020c, an interface circuit 1030c, and a memory device 1040c. The memory device 1040c can include Figures 9B-9DThe memory controller 1020c can be electrically connected to the interface circuit 1030c through a signal path 1021c of the first substrate 1001c, a signal path 1022c formed in the third substrate 1003c, and a signal path 1023c formed in the second substrate 1002c. The interface circuit 1030c can be electrically connected with the memory device 1040c through a signal path 1031c formed in the second substrate 1002c. The signal path 1011c between the host 1010c and the memory controller 1020c can correspond to the signal path 1011a of FIG. 10A. The signal path 1021c of the first substrate 1001c can correspond to the signal path 1011a of FIG. 10A. The signal path 1022c formed in the third substrate 1003c can correspond to the signal path 1011b of FIG. 10A. The signal path 1023c formed in the second substrate 1002c can correspond to the signal path 1011c of FIG. 10A. The signal path 1031c formed in the second substrate 1002c can correspond to the signal path 1011d of FIG. 10A.

[0137] The host 1010c can be electrically connected to the memory controller 1020c through a signal path 1011c formed in the first substrate 1001c. The memory controller 1020c can be electrically connected to the interface circuit 1030c through a signal path 1021c of the first substrate 1001c, a signal path 1022c formed in the third substrate 1003c, and a signal path 1023c formed in the second substrate 1002c. The interface circuit 1030c can be electrically connected with the memory device 1040c through a signal path 1031c formed in the second substrate 1002c. The signal path 1011c between the host 1010c and the memory controller 1020c can correspond to Figure 1The first bus 150 is shown. The signal paths 1021c, 1022c, 1023c between the memory controller 1020c and the interface circuit 1030c can correspond to Figure 1 The second bus 160 is shown. The signal path 1031c between the interface circuit 1030c and the memory device 1040c can correspond to Figure 1 The third bus 170 is shown. The frequency of the signals transmitted through the signal paths 1021c, 1022c, 1023c can be greater than or equal to the frequency of the signals transmitted through the signal path 1031c. The signals can be transmitted through the signal paths 1021c, 1022c, 1023c at a first clock rate, and the signals can be transmitted through the signal path 1031c at a second clock rate. The first clock rate can be greater than or equal to the second clock rate. The signal paths 1021c, 1022c, 1023c can include a first data bus, and the signal path 1031c can include a second data bus. The number of data signals transmitted at any one time through the first data bus can be less than or equal to the number of data signals transmitted at any one time through the second data bus. In an embodiment, the first substrate 1001c, the host 1010c, and the memory controller 1020c can be packaged in a first package. The second substrate 1002c, the interface circuit 1030c, and the memory device 1040c can be packaged in a second package. The first package and the second package can be disposed on a third substrate 1003c and packaged in a third package, and the integrated circuit package 1000c can be manufactured in a PIP (Package In Package) structure.

[0138] Figure 10D A diagram showing the configuration and connection relationship of an integrated circuit package 1000d according to an embodiment of the present disclosure. Referring to Figure 10D , the integrated circuit package 1000d can include a substrate 1001d, a host 1010d, a memory controller 1020d, an interface circuit 1030d, and a memory device 1040d. The memory device 1040d can include Figures 9B-9DAny of the memory devices 930b-930d shown. The host 1010d, the memory controller 1020d, the interface circuit 1030d, and the memory device 1040d can be disposed on a substrate 1001d. The substrate 1001d can be an interposer and / or a glass substrate that includes a variety of signal paths. The host 1010d can be disposed in a first region on the substrate 1001d. The memory controller 1020d can be disposed in a second region on the substrate 1001d. The interface circuit 1030d can be disposed in a third region on the substrate 1001d. The memory device 1040d can be disposed in a fourth region on the substrate 1001d. The first region and the fourth region can not overlap each other. The second region can be between the first region and the third region, and the third region can be between the second region and the fourth region. The host 1010d can be electrically connected to the substrate 1001d by micro bumps of the host 1010d. The memory controller 1020d can be electrically connected to the substrate 1001d by micro bumps of the memory controller 1020d. The interface circuit 1030d can be electrically connected to the substrate 1001d by micro bumps of the interface circuit 1030d. The memory device 1040d can be electrically connected to the substrate 1001d by micro bumps of the memory device 1040d. The substrate 1001d can include external terminals below the substrate 1001d for electrical connection with external devices. The external terminals can include micro bumps, bumps, solder balls, or package balls. The host 1010d, the memory controller 1020d, the interface circuit 1030d, and the memory device 1040d disposed on the substrate 1001d can be packaged in a single package.

[0139] The host 1010d can be electrically connected to the memory controller 1020d by a signal path 1011d formed in the substrate 1001d. The memory controller 1020d can be electrically connected to the interface circuit 1030d by a signal path 1021d formed in the substrate 1001d. The interface circuit 1030d can be electrically connected to the memory device 1040d by a signal path 1031d formed in the substrate 1001d. The signal path 1011d between the host 1010d and the memory controller 1020d can correspond to the first bus 150 shown in FIG. 1. Figure 1 The signal path 1021d between the memory controller 1020d and the interface circuit 1030d can correspond to the second bus 160 shown in FIG. 1. The signal path 1031d between the interface circuit 1030d and the memory device 1040d can correspond to the third bus 170 shown in FIG. 1. Figure 1 The signal path 1021d between the memory controller 1020d and the interface circuit 1030d can correspond to the second bus 160 shown in FIG. 1. The signal path 1031d between the interface circuit 1030d and the memory device 1040d can correspond to the third bus 170 shown in FIG. 1. Figure 1The third bus 170 is shown. The frequency of the signal transmitted through signal path 1021d can be greater than or equal to the frequency of the signal transmitted through signal path 1031d. The signal can be transmitted through signal path 1021d at a first clock rate, and the signal can be transmitted through signal path 1031d at a second clock rate. The first clock rate can be greater than or equal to the second clock rate. Signal path 1021d may include a first data bus, and signal path 1031d may include a second data bus. The number of data signals transmitted at one time through the first data bus can be less than or equal to the number of data signals transmitted at one time through the second data bus.

[0140] Figure 10E This is a diagram illustrating the configuration and connection relationships of an integrated circuit package 1000e according to an embodiment of the present disclosure. (See reference...) Figure 10E The integrated circuit package 1000e may include a first tile 1010e, a second tile 1020e, a third tile 1030e, and a fourth tile 1040e. Figure 10E In this context, a wafer can refer to a bare die, structure, unit module, or chip of a single device. The first wafer 1010e can correspond to... Figure 1 The host 110 is shown. The second fragment 1020e can correspond to... Figure 1 The memory controller 120 is shown. The third segment 1030e can correspond to... Figure 1 The interface circuit 130 is shown. The fourth segment 1040e can correspond to... Figure 1 The memory device 140 shown. First to fourth shards 1010e, 1020e, 1030e, and 1040e can be mounted on a base shard 1001e. The base shard 1001e may include multiple shard slots or connectors to allow the first to fourth shards 1010e, 1020e, 1030e, and 1040e and an additional shard (i.e., a fifth shard 1050e) to be mounted on the base shard 1001e. The base shard 1001e may include signal paths for electrically connecting the multiple shards mounted to the base shard 1001e. Although not shown, multiple signal paths may be formed within the base shard 1001e to electrically connect each of the first to fourth shards 1010e, 1020e, 1030e, and 1040e. The base shard 1001e may be disposed on a substrate 1002e. The substrate 1002e may include any one of an interposer, a packaging substrate, an organic substrate, and a re-slicing layer. The signal path between the first slice 1010e and the second slice 1020e may correspond to... Figure 1 The first bus 150 is shown. The signal path between the second segment 1020e and the third segment 1030e can correspond to... Figure 1The second bus 160 is shown. The signal path between the third tile 1030e and the fourth tile 1040e can correspond to Figure 1 The third bus 170 is shown. The integrated circuit package 1000e can further include a fifth tile 1050e. The fifth tile 1050e can be a logic tile that performs the same or different function as any of the first through fourth tiles 1010e, 1020e, 1030e, 1040e. Some or all of the first through fifth tiles 1010e, 1020e, 1030e, 1040e, 1050e can be fabricated using different process technologies. In an embodiment, the first and second tiles 1010e, 1020e can be integrated as a single tile, and the integrated tile can be mounted to the base tile 1001e through a single socket or connector. In an embodiment, the second and third tiles 1020e, 1030e can be integrated as a single tile, and the integrated tile can be mounted to the base tile 1001e through a single socket or connector.

[0141] Figure 10F is a diagram illustrating a configuration and connection relationship of an integrated circuit package 1000f according to an embodiment of the present disclosure. Referring to Figure 10F , the integrated circuit package 1000f can include a first substrate 1001f, a host die 101f, and a memory device 1040f. The memory device 1040f can include any of the memory devices 930b to 930d shown in Figures 9B-9D . The host die 101f can include a host 1010f, a memory controller 1020f, and an interface circuit 1030f. The host 1010f, the memory controller 1020f, and the interface circuit 1030f can be internal circuits of the host die 101f. The host die 101f and the memory device 1040f can be fabricated as separate dies and / or chiplets. The host die 101f and the memory device 1040f can be fabricated using process technologies having different characteristics, or can be fabricated using process technologies having the same characteristics. The host die 101f and the memory device 1040f can be disposed on the first substrate 1001f. The first substrate 1001f can include an interposer. The host die 101f can be disposed in a first region on the first substrate 1001f, and the memory device 1040f can be disposed in a second region on the first substrate 1001f. The first and second regions can not overlap each other.

[0142] The host die 101f can be electrically connected to the first substrate 1001f through micro bumps of the host die 101f. The memory device 1040f can be electrically connected with the first substrate 1001f through micro bumps of the memory device 1040f. The integrated circuit package 1000f can further include a second substrate 1002f. The first substrate 1001f can be disposed on the second substrate 1002f. The second substrate can include another interposer or a package substrate. The first substrate 1001f can be electrically connected to the second substrate 1002f through micro bumps or bumps of the first substrate 1001f. The second substrate 1002f can be electrically connected to an external device through external terminals of the second substrate 1002f. The external terminals can include micro bumps, bumps, solder balls, or package balls.

[0143] The host 1010f can be electrically connected to the memory controller 1020f through a signal transmission line 1011f inside the host die 101f. The memory controller 1020f can be electrically connected with the interface circuit 1030f through a signal transmission line 1021f inside the host die 101f. The interface circuit 1030f can be electrically connected to the memory device 1040f through micro bumps of the host die 101f and a signal path 1031f formed in the first substrate 1001f. The memory device 1040f can be electrically connected to the signal path 1031f through micro bumps of the memory device 1040f. In an embodiment, the host 1010f can be directly electrically connected to an external device through a signal path formed in the first substrate 1001f, a signal path formed in the second substrate 1002f, and external terminals of the second substrate 1002f. The memory device 1040f can be directly electrically connected to an external device through a signal path formed in the first substrate 1001f, a signal path formed in the second substrate 1002f, and external terminals of the second substrate 1002f. The signal transmission line 1011f electrically connecting the host 1010f and the memory controller 1020f can correspond to a first bus 150 as illustrated in FIG. 1. The signal transmission line 1021f electrically connecting the memory controller 1020f and the interface circuit 1030f can correspond to a second bus 160 as illustrated in FIG. 1. The signal path 1031f between the interface circuit 1030f and the memory device 1040f can correspond to a third bus 170 as illustrated in FIG. 1. Figure 1 Figure 1 Figure 1 ​​The third bus 170 is shown. The frequency of the signal transmitted through the signal transmission line 1021f can be greater than or equal to the frequency of the signal transmitted through the signal path 1031f. The signal can be transmitted through the signal transmission line 1021f at a first clock rate, and the signal can be transmitted through the signal path 1031f at a second clock rate. The first clock rate can be greater than or equal to the second clock rate. The signal transmission line 1021f can include a first data bus, and the signal path 1031f can include a second data bus. The number of data signals transmitted at a time through the first data bus can be less than or equal to the number of data signals transmitted at a time through the second data bus. The first substrate 1001f, the second substrate 1002f, the host die 101f, and the memory device 1040f can be packaged in a single package.

[0144] Figure 10G is a diagram illustrating a configuration and a connection relationship of an integrated circuit package 1000g according to an embodiment of the disclosure. Referring to Figure 10G , the integrated circuit package 1000g can include a first substrate 1001g-1, a second substrate 1001g-2, a first host die 101g, a second host die 102g, a first memory device 1040g-1, and a second memory device 1040g-2. The first memory device 1040g-1 and the second memory device 1040g-2 can each include Figures 9B-9DThe first host die 101g can include a host 1010g-1, a memory controller 1020g-1, and an interface circuit 1030g-1. The host 1010g-1, the memory controller 1020g-1, and the interface circuit 1030g-1 can be internal circuits of the first host die 101g. The first host die 101g and the first memory device 1040g-1 can be disposed on a first substrate 1001g-1. The first substrate 1001g-1 can include a first interposer. The first host die 101g can be disposed in a first region on the first substrate 1001g-1, and the first memory device 1040g-1 can be disposed in a second region on the first substrate 1001g-1. The first region and the second region can not overlap. The first host die 101g can be electrically connected to the first substrate 1001g-1 by micro bumps of the first host die 101g. The first memory device 1040g-1 can be electrically connected to the first substrate 1001g-1 by micro bumps of the first memory device 1040g-1. The integrated circuit package 1000g can further include a third substrate 1002g. The first substrate 1001g-1 can be disposed on the third substrate 1002g. The third substrate 1002g can include another interposer or a package substrate. The first substrate 1001g-1 can be electrically connected to the third substrate 1002g by micro bumps or bumps of the first substrate 1001g-1. The third substrate 1002g can be electrically connected to an external device by external terminals of the third substrate 1002g. The external terminals can include micro bumps, bumps, solder balls, or package balls.

[0145] The host 1010g-1 can be electrically connected to the memory controller 1020g-1 by a signal transmission line 1011g-1 internal to the first host die 101g. The memory controller 1020g-1 can be electrically connected to the interface circuit 1030g-1 by a signal transmission line 1021g-1 internal to the first host die 101g. The interface circuit 1030g-1 can be electrically connected with the first memory device 1040g-1 by micro bumps of the first host die 101g and a signal path 1031g-1 formed in the first substrate 1001g-1. The first memory device 1040g-1 can be electrically connected to the signal path 1031g-1 by micro bumps of the first memory device 1040g-1. The signal transmission line 1011g-1 electrically connecting the host 1010g-1 with the memory controller 1020g-1 can correspond to Figure 1 The signal transmission line 1021g-1 electrically connecting the memory controller 1020g-1 with the interface circuit 1030g-1 can correspond to Figure 1The second bus 160 is shown. The signal path 1031g-1 between the interface circuit 1030g-1 and the first memory device 1040g-1 can correspond to Figure 1 The third bus 170 is shown. The frequency of the signals transmitted through the signal transmission line 1021g-1 can be greater than or equal to the frequency of the signals transmitted through the signal path 1031g-1. The signals can be transmitted through the signal transmission line 1021g-1 at a first clock rate, and the signals can be transmitted through the signal path 1031g-1 at a second clock rate. The first clock rate can be greater than or equal to the second clock rate. The signal transmission line 1021g-1 can comprise a first data bus, and the signal path 1031g-1 can comprise a second data bus. The number of data signals transmitted at a time through the first data bus can be less than or equal to the number of data signals transmitted at a time through the second data bus. The first substrate 1001g-1, the first host die 101g, and the first memory device 1040g-1 can be packaged in a first package.

[0146] The second host die 102g can include a host 1010g-2, a memory controller 1020g-2, and an interface circuit 1030g-2. The host 1010g-2, the memory controller 1020g-2, and the interface circuit 1030g-2 can be internal circuits of the second host die 102g. The second host die 102g and the second memory device 1040g-2 can be disposed on a second substrate 1001g-2. The second substrate 1001g-2 can include a second interposer. The second host die 102g can be disposed in a first region on the second substrate 1001g-2, and the second memory device 1040g-2 can be disposed in a second region on the second substrate 1001g-2. The first region and the second region can not overlap. The second host die 102g can be electrically connected to the second substrate 1001g-2 by micro-bumps of the second host die 102g. The second memory device 1040g-2 can be electrically connected to the second substrate 1001g-2 by micro-bumps of the second memory device 1040g-2. The second substrate 1001g-2 can be disposed on a third substrate 1002g. The second substrate 1001g-2 can be disposed on the third substrate 1002g in a region different from a region in which the first substrate 1001g-1 is disposed. The second substrate 1001g-2 can be electrically connected to the third substrate 1002g by micro-bumps or bumps of the second substrate 1001g-2.

[0147] The host 1010g-2 can be electrically connected to the memory controller 1020g-2 by signal transmission lines 1011g-2 internal to the second host die 102g. The memory controller 1020g-2 can be electrically connected to the interface circuit 1030g-2 by signal transmission lines 1021g-2 internal to the second host die 102g. The interface circuit 1030g-2 can be electrically connected to the second memory device 1040g-2 by micro bumps of the second host die 102g and signal paths 1031g-2 formed in the second substrate 1001g-2. The second memory device 1040g-2 can be electrically connected to the signal paths 1031g-2 by micro bumps of the second memory device 1040g-2. The signal transmission lines 1011g-2 electrically connecting the host 1010g-2 to the memory controller 1020g-2 can correspond to the first bus 150 shown in FIG. 1. Figure 1 The signal transmission lines 1021g-2 electrically connecting the memory controller 1020g-2 to the interface circuit 1030g-2 can correspond to the second bus 160 shown in FIG. 1. Figure 1 The signal paths 1031g-2 between the interface circuit 1030g-2 and the second memory device 1040g-2 can correspond to the memory device bus 170 shown in FIG. 1. Figure 1The third bus 170 is shown. The frequency of the signal transmitted through the signal transmission line 1021g-2 can be greater than or equal to the frequency of the signal transmitted through the signal path 1031g-2. The signal can be transmitted through the signal path 1021g-2 at a third clock rate, and the signal can be transmitted through the signal path 1031g-2 at a fourth clock rate. The third clock rate can be greater than or equal to the fourth clock rate. The third clock rate can be equal to or different from the first clock rate. The fourth clock rate can be equal to or different from the second clock rate. The signal transmission line 1021g-2 can include a third data bus, and the signal path 1031g-2 can include a fourth data bus. The number of data signals transmitted at one time through the third data bus can be less than or equal to the number of data signals transmitted at one time through the fourth data bus. In an embodiment, the first substrate 1001g-1, the first host die 101g, and the first memory device 1040g-1 can be packaged in a first package. The second substrate 1001g-2, the second host die 102g, and the second memory device 1040g-2 can be packaged in a second package. The first package and the second package can be disposed on the third substrate 1002g and packaged in a third package, and the integrated circuit package 1000g can be manufactured in a PIP (package-in-package) structure. The host 1010g-1 can be electrically connected with the host 1010g-2 through the micro bumps of the first host die 101g, the signal paths formed in the first substrate 1001g-1, the micro bumps of the first substrate 1001g-1, the signal paths of the third substrate 1002g, the micro bumps of the second substrate 1001g-2, the signal paths of the second substrate 1001g-2, and the micro bumps of the second host die 102g.

[0148] Figure 10H A diagram to show the configuration and connection relationship of the integrated circuit package 1000h according to an embodiment of the disclosure is shown. Referring to Figure 10H , the integrated circuit package 1000h can include a first substrate 1001h, a host 1010h, a memory controller 1020h, an interface circuit 1030h, and a memory device 1040h. The memory device 1040h can include Figures 9B-9DThe memory device 1040h can be electrically connected to the first substrate 1001h through micro bumps of the memory device 1040h. The integrated circuit package 1000h can further include a second substrate 1002h. The first substrate 1001h can be disposed on the second substrate 1002h. The second substrate 1002h can include an interposer or a package substrate. The first substrate 1001h can be electrically connected to the second substrate 1002h through micro bumps or bumps of the first substrate 1001h. The second substrate 1002h can be electrically connected to an external device through external terminals of the second substrate 1002h. The external terminals can include micro bumps, bumps, solder balls, or package balls. The memory controller 1020h and the interface circuit 1030h can be formed within the first substrate 1001h. The memory controller 1020h and the interface circuit 1030h can be fabricated with the first substrate 1001h as internal circuits of the first substrate 1001h. The memory controller 1020h and the interface circuit 1030h can be electrically connected to the host 1010h and the memory device 1040h through a plurality of signal paths formed within the first substrate 1001h. The second substrate 1002h, the first substrate 1001h, and the host 1010h and the memory device 1040h disposed on the first substrate 1001h can be encapsulated in a single package. In an embodiment, a first region of the first substrate 1001h in which the host 1010h is disposed can be closer to a region in which the memory controller 1020h is disposed than a region in which the interface circuit 1030h is disposed in the first substrate 1001h. A second region of the first substrate 1001h in which the memory device 1040h is disposed can be closer to the region in which the interface circuit 1030h is disposed than the region in which the memory controller 1020h is disposed in the first substrate 1001h.

[0149] The memory controller 1020h can be electrically connected to the host 1010h through a signal path 1011h and a micro bump of the host 1010h. The memory controller 1020h can be electrically connected to the interface circuit 1030h through a signal path 1021h. The interface circuit 1030h can be electrically connected to the memory device 1040h through a signal path 1031h and a micro bump of the memory device 1040h. The signal path 1011h between the host 1010h and the memory controller 1020h can correspond to the first bus 150 illustrated in FIG. 1. The signal path 1021h between the memory controller 1020h and the interface circuit 1030h can correspond to the second bus 160 illustrated in FIG. 1. The signal path 1031h between the interface circuit 1030h and the memory device 1040h can correspond to the third bus 170 illustrated in FIG. 1. Figure 1 The signal path 1011h between the host 1010h and the memory controller 1020h can correspond to the first bus 150 illustrated in FIG. 1. The signal path 1021h between the memory controller 1020h and the interface circuit 1030h can correspond to the second bus 160 illustrated in FIG. 1. The signal path 1031h between the interface circuit 1030h and the memory device 1040h can correspond to the third bus 170 illustrated in FIG. 1. Figure 1 The signal path 1011h between the host 1010h and the memory controller 1020h can correspond to the first bus 150 illustrated in FIG. 1. The signal path 1021h between the memory controller 1020h and the interface circuit 1030h can correspond to the second bus 160 illustrated in FIG. 1. The signal path 1031h between the interface circuit 1030h and the memory device 1040h can correspond to the third bus 170 illustrated in FIG. 1. Figure 1 The signal path 1011h between the host 1010h and the memory controller 1020h can correspond to the first bus 150 illustrated in FIG. 1. The signal path 1021h between the memory controller 1020h and the interface circuit 1030h can correspond to the second bus 160 illustrated in FIG. 1. The signal path 1031h between the interface circuit 1030h and the memory device 1040h can correspond to the third bus 170 illustrated in FIG. 1.

[0150] Figure 101 FIG. 1 is a diagram illustrating a configuration and a connection relationship of an integrated circuit package 1000i according to an embodiment of the disclosure. Referring to FIG. 1, the integrated circuit package 1000i can include a first substrate 1001i, a host 1010i, a controller die 101i, and a memory device 1040i. The memory device 1040i can include a memory controller 1020i and an interface circuit 1030i. Figure 101 Figures 9B-9D ​The controller die 101i can include a memory controller 1020i and an interface circuit 1030i. The controller die 101i can be fabricated as a die or chip separate from the host 1010i. The memory controller 1020i and the interface circuit 1030i can be internal circuits of the controller die 101i. The host 1010i, the controller die 101i, and the memory devices 1040i can be disposed on a first substrate 1001i. The first substrate 1001i can include an interposer. The host 1010i can be disposed in a first region on the first substrate 1001i. The controller die 101i can be disposed in a second region on the first substrate 1001i. The memory devices 1040i can be disposed in a third region on the first substrate 1001i. The first region and the third region can not overlap each other. The host 1010i can be electrically connected to the first substrate 1001i by micro bumps of the host 1010i. The controller die 101i can be electrically connected to the first substrate 1001i by micro bumps of the controller die 101i. The memory devices 1040i can be electrically connected with the first substrate 1001i by micro bumps of the memory devices 1040i. The integrated circuit package 1000i can further include a second substrate 1002i. The first substrate 1001i can be disposed on the second substrate 1002i. The second substrate 1002i can include an interposer or a package substrate. The first substrate 1001i can be electrically connected to the second substrate 1002i by micro bumps or bumps of the first substrate 1001i. The second substrate 1002i can be electrically connected to an external device by external terminals of the second substrate 1002i. The external terminals can include micro bumps, bumps, solder balls, or package balls. The memory controller 1020i can be electrically connected with the first substrate 1001i by micro bumps on a first side of the controller die 101i. The interface circuit 1030i can be electrically connected to the first substrate 1001i by micro bumps on a second side of the controller die 101i. The second substrate 1002i, the first substrate 1001i, the host 1010i, the controller die 101i, and the memory devices 1040i can be packaged in a single package.

[0151] The host 1010i can be electrically connected to the memory controller 1020i by signal paths 1011i formed in the first substrate 1001i. The memory controller 1020i and the interface circuit 1030i can be electrically connected by signal paths 1021i internal to the controller die 101i. The interface circuit 1030i can be electrically connected to the memory devices 1040i by signal paths 1031i formed in the first substrate 1001i. The signal paths 1011i between the host 1010i and the memory controller 1020i can correspond to the memory channels 1010a-1010d of FIG. 1. The signal paths 1021i between the memory controller 1020i and the interface circuit 1030i can correspond to the memory channels 1020a-1020d of FIG. 1. The signal paths 1031i between the interface circuit 1030i and the memory devices 1040i can correspond to the memory channels 1030a-1030d of FIG. 1. Figure 1The first bus 150 is shown. The signal path 1021i that electrically connects the memory controller 1020i to the interface circuit 1030i can correspond to... Figure 1 The second bus 160 shown. The signal path 1031i between the interface circuit 1030i and the memory device 1040i can correspond to Figure 1 The third bus 170 is shown. The frequency of the signal transmitted through signal path 1021i can be greater than or equal to the frequency of the signal transmitted through signal path 1031i. The signal can be transmitted through signal path 1021i at a first clock rate, and the signal can be transmitted through signal path 1031i at a second clock rate. The first clock rate can be greater than or equal to the second clock rate. Signal path 1021i may include a first data bus, and signal path 1031i may include a second data bus. The number of data signals transmitted at one time through the first data bus can be less than or equal to the number of data signals transmitted at one time through the second data bus.

[0152] Figure 10J A diagram illustrating the configuration and interconnections of an integrated circuit package 1000j according to an embodiment of this disclosure. See also... Figure 10J The integrated circuit package 1000j may include a substrate 1001j, a host die 101j, and a memory device 1040j. The memory device 1040j may include... Figure 9B and Figure 9D Either of the memory devices 940b and 940d shown is considered. A through-hole may be formed in the memory device 1040j. The host die 101j may include a host 1010j, a memory controller 1020j, and an interface circuit 1030j. The host 1010j, memory controller 1020j, and interface circuit 1030j may be internal circuitry of the host die 101j. The host die 101j and the memory device 1040j may be disposed on the substrate 1001j. The memory device 1040j may be disposed on the substrate 1001j, and the host die 101j may be disposed on the memory device 1040j. The host die 101j may be electrically connected to the memory device 1040j through microbumps in the host die 101j. The host die 101j may be electrically connected to the substrate 1001j and the memory device 1040j through a through-hole 1041j formed in the memory device 1040j. The memory device 1040j can be electrically connected to the substrate 1001j via microbumps. The substrate 1001j may include at least one of an interposer, a redistribution layer, and a glass substrate. In one embodiment, the integrated circuit package 1000j may further include another substrate, and the substrate 1001j may be disposed on this other substrate. The substrate 1001j can be electrically connected to an external device via this other substrate. This other substrate may include another interposer or a package substrate.

[0153] The host 1010j can be electrically connected to the memory controller 1020j through a signal transmission line 1011j inside the host die 101j. The host 1010j can be electrically connected to a signal path formed in the substrate 1001j through a micro bump of the host die 101j, a via 1041j formed in the memory device 1040j, and a micro bump of the memory device 1040j. The signal path can be electrically connected to another substrate or an external device through a micro bump, a bump, a solder ball, or a package ball on the substrate 1001j. The memory controller 1020j can be electrically connected to the interface circuit 1030j through a signal transmission line 1021j inside the host die 101j. The interface circuit 1030j can be electrically connected to the memory device 1040j through a micro bump of the host die 101j and a via 1031j formed in the memory device 1040j. The signal transmission line 1011j electrically connecting the host 1010j and the memory controller 1020j can correspond to a first bus 150 as illustrated in Figure 1 Figure 1 Figure 1

[0154] Figure 10K To show the configuration and connection relationship of the integrated circuit package 1000k according to an embodiment of the present disclosure. Referring to Figure 10K , the integrated circuit package 1000k can include a substrate 1001k, a host die 101k, and a memory device 1040k. The memory device 1040k can include Figures 9B-9D ​​​Any of the memory devices 930b-930d shown. The host die 101k can include a host 1010k, a memory controller 1020k, and an interface circuit 1030k. The host 1010k, the memory controller 1020k, and the interface circuit 1030k can be internal circuits of the host die 101k. The host die 101k and the memory device 1040k can be disposed on a substrate 1001k. The substrate 1001k can include a package substrate. The host die 101k can be disposed on the substrate 1001k, and the memory device 1040k can be disposed on the host die 101k. The memory device 1040k can be electrically connected to the host die 101k by micro bumps of the memory device 1040k. The host die 101k can be electrically connected to the substrate 1001k by wire bonds. In an embodiment, the substrate 1001k can be replaced by an interposer, and the host die 101k can include micro bumps. The host die 101k can be electrically connected to the interposer by micro bumps instead of wire bonds, or can be electrically connected to a redistribution layer with or without micro bumps. The substrate 1001k can be electrically connected to external devices by external terminals, such as solder balls or package balls.

[0155] The host 1010k can be electrically connected to the memory controller 1020k by a signal transmission line 1011k internal to the host die 101k. The host 1010k can be electrically connected to external devices by wire bonds between the host die 101k and the substrate 1001k. The memory controller 1020k can be electrically connected to the interface circuit 1030k by a signal transmission line 1021k internal to the host die 101k. The interface circuit 1030k can be electrically connected to the memory device 1040k by a signal transmission line 1031k internal to the host die 101k and micro bumps of the memory device 1040k. The signal transmission line 1011k electrically connecting the host 1010k and the memory controller 1020k can correspond to the first bus 150 shown. Figure 1 The signal transmission line 1021k electrically connecting the memory controller 1020k and the interface circuit 1030k can correspond to the second bus 160 shown. Figure 1 The signal transmission line 1031k and the micro bumps electrically connecting the interface circuit 1030k and the memory device 1040k can correspond to the third bus 170 shown. Figure 1A third bus 170 is shown. The frequency of the signals transmitted through the signal transmission line 1021k can be greater than or equal to the frequency of the signals transmitted through the signal transmission line 1031k. The signals can be transmitted through the signal transmission line 1021k at a first clock rate, and the signals can be transmitted through the signal transmission line 1031k at a second clock rate. The first clock rate can be greater than or equal to the second clock rate. The signal transmission line 1021k can include a first data bus, and the signal transmission line 1031k can include a second data bus. The number of data signals transmitted at one time through the first data bus can be less than or equal to the number of data signals transmitted at one time through the second data bus. The substrate 1001k, the host die 101k, and the memory device 1040k can be packaged in a single package.

[0156] Figure 10L is a diagram illustrating a configuration and a connection relationship of an integrated circuit package 1000l according to an embodiment of the disclosure. Referring to Figure 10L , the integrated circuit package 1000l can include a host tile 101l and a memory tile 1040l. In Figure 10L , a tile can refer to a die, a structure, a unit module, or a core particle of a single device. The host tile 101l can include a host 1010l, a memory controller 1020l, and an interface circuit 1030l. The memory tile 1040l can include at least one memory die, and can include any one of the memory devices 930a to 930d shown in Figures 9A-9D . The host tile 101l and the memory tile 1040l can be disposed on and electrically connected to a base tile 1001l. The base tile 1001l can include a signal path for electrically connecting a plurality of tiles mounted on the base tile 1001l. The base tile 1001l can be disposed on a substrate 1002l. The substrate 1002l can include any one of an interposer, a package substrate, an organic substrate, and a redistribution layer. The host 1010l and the memory controller 1020l can be electrically connected through a signal transmission line inside the host tile 101l, and the memory controller 1020l and the interface circuit 1030l can be electrically connected through a signal transmission line inside the host tile 101l. The interface circuit 1030l can be electrically connected to the memory tile 1040l through a signal path 1031l formed inside the base tile 1001l. The signal transmission line electrically connecting the host 1010l and the memory controller 1020l can correspond to a first bus 150 shown in Figure 1 . The signal transmission line electrically connecting the memory controller 1020l and the interface circuit 1030l can correspond to a second bus 160 shown in Figure 1a second bus 160 is shown. The signal path 1031l formed inside the base tile 1001l and electrically connecting the interface circuit 1030l with the memory tile 1040l can correspond to Figure 1 a third bus 170 is shown. Some or all of the host tile 101l and the memory tile 1040l can be fabricated using different process technologies. The host tile 101l, the memory tile 1040l, the base tile 1001l, and the substrate 1002l can be packaged in one package to form a single semiconductor device.

[0157] Figure 10M is a diagram showing a configuration and a connection relationship of an integrated circuit package 1000m according to an embodiment of the present disclosure. Referring to Figure 10M , the integrated circuit package 1000m can include a plurality of host tiles and a plurality of memory tiles. The integrated circuit package 1000m can include a first host tile 101m-1, a second host tile 101m-2, a first memory tile 1040m-1, and a second memory tile 1040m-2. The first host tile 101m-1 can include a first host 1010m-1, a first memory controller 1020m-1, and a first interface circuit 1030m-1. The second host tile 101m-2 can include a second host 1010m-2, a second memory controller 1020m-2, and a second interface circuit 1030m-2. The first memory tile 1040m-1 can include at least one memory die, and can include any one of the memory devices 930a to 930d shown in Figures 9B-9D . The second memory tile 1040m-2 can include at least one memory die, and can include any one of the memory devices 930a to 930d shown in Figures 9A-9D . The second memory tile 1040m-2 can have substantially the same structure as the first memory tile 1040m-1, or can have a different structure from the first memory tile 1040m-1. In an embodiment, the first host tile 101m-1 can further include a first host interface 1050m-1, and the second host tile 101m-2 can further include a second host interface 1050m-2. The first host tile 101m-1 and the second host tile 101m-2 can be electrically connected through the first host interface 1050m-1 and the second host interface 1050m-2.

[0158] The first host tile 101m-1, the second host tile 101m-2, the first memory tile 1040m-1, and the second memory tile 1040m-2 can be disposed on and electrically connected with the base tile 1001m. The base tile 1001m can include signal paths for electrically connecting the plurality of tiles mounted on the base tile 1001m. Although not shown, a plurality of signal paths can be formed within the base tile 1001m for electrically connecting the first host tile 101m-1 and the second host tile 101m-2, the first host tile 101m-1 and the first memory tile 1040m-1, and the second host tile 101m-2 and the second memory tile 1040m-2. The base tile 1001m can be disposed on the substrate 1002m. The substrate 1002m can include any one of an interposer, a package substrate, an organic substrate, and a redistribution layer. The first host 1010m-1 and the first memory controller 1020m-1 can be electrically connected through signal transmission lines inside the first host tile 101m-1, and the first memory controller 1020m-1 and the first interface circuit 1030m-1 can be electrically connected through signal transmission lines inside the first host tile 101m-1. The first interface circuit 1030m-1 can be electrically connected to the first memory tile 1040m-1 through the signal path 1031m-1 formed in the base tile 1001m. The second host 1010m-2 and the second memory controller 1020m-2 can be electrically connected through signal transmission lines inside the second host tile 101m-2, and the second memory controller 1020m-2 and the second interface circuit 1030m-2 can be electrically connected through signal transmission lines inside the second host tile 101m-2. The second interface circuit 1030m-2 can be electrically connected to the second memory tile 1040m-2 through the signal path 1031m-2 formed in the base tile 1001m. The first host tile 101m-1 can be electrically connected to the second host tile 101m-2 through the signal path 1051m formed in the base tile 1001m. The signal path 1051m can be electrically connected between the first host interface 1050m-1 and the second host interface 1050m-2. The signal transmission lines electrically connecting the first host 1010m-1 and the first memory controller 1020m-1 and the signal transmission lines electrically connecting the second host 1010m-2 and the second memory controller 1020m-2 can correspond to the first bus 150 shown in FIG. 1, respectively. The signal transmission lines electrically connecting the first memory controller 1020m-1 and the first interface circuit 1030m-1 and the signal transmission lines electrically connecting the second memory controller 1020m-2 and the second interface circuit 1030m-2 can correspond to the second bus 250 shown in FIG. 2, respectively. Figure 1 The signal transmission lines electrically connecting the first memory controller 1020m-1 and the first interface circuit 1030m-1 and the signal transmission lines electrically connecting the second memory controller 1020m-2 and the second interface circuit 1030m-2 can correspond to the second bus 250 shown in FIG. 2, respectively. Figure 1The second bus 160 is shown. The signal path electrically connecting the first interface circuit 1030m-1 and the first memory tile 1040m-1 formed in the base tile 1001m and the signal path electrically connecting the second interface circuit 1030m-2 and the second memory tile 1040m-2 can correspond to Figure 1 The third bus 170 is shown. The first host tile 101m-1, the second host tile 101m-2, the first memory tile 1040m-1, the second memory tile 1040m-2, the base tile 1001m, and the substrate 1002m can be packaged in a single package to form a single semiconductor device.

[0159] Figure 10N A diagram showing the configuration and connection relationship of the integrated circuit package 1000n according to an embodiment of the present disclosure. Referring to Figure 10N , the integrated circuit package 1000n can include at least one host, a plurality of controller dies, and a plurality of memory devices. In Figure 10NIn particular embodiments, integrated circuit package 1000n is shown to include six controller dies and six memory devices, but this example illustration is not intended to limit the number of controller dies and memory devices included in integrated circuit package 1000n. Integrated circuit package 1000n can include two, four, or eight or more controller dies, and can include two, four, or eight or more memory devices electrically connected to each controller die. In an embodiment, the number of memory devices electrically connected to one controller die can be two or more. Integrated circuit package 1000n can include host 1010n, first controller die 101n-1, second controller die 101n-2, third controller die 101n-3, fourth controller die 101n-4, fifth controller die 101n-5, sixth controller die 101n-6, first memory device 1040n-1, second memory device 1040n-2, third memory device 1040n-3, fourth memory device 1040n-4, fifth memory device 1040n-5, and sixth memory device 1040n-6. Host 1010n can be fabricated in a single die or in a split, and can include multiple processing cores. Host 1010n can be fabricated as a core complex die that includes at least two processing cores. Each of first through sixth controller dies 101n-1, 101n-2, 101n-3, 101n-4, 101n-5, 101n-6 can be fabricated in a single die or in a split. Each of first through sixth controller dies 101n-1, 101n-2, 101n-3, 101n-4, 101n-5, 101n-6 can include a memory controller MC and an interface circuit IF. The memory controller MC and the interface circuit IF of first through sixth controller dies 101n-1, 101n-2, 101n-3, 101n-4, 101n-5, 101n-6 can be electrically connected by signal transmission paths within first through sixth controller dies 101n-1, 101n-2, 101n-3, 101n-4, 101n-5, 101n-6, respectively. First through sixth memory devices 1040n-1, 1040n-2, 1040n-3, 1040n-4, 1040n-5, 1040n-6 can each include at least one memory die. Each of first through sixth memory devices 1040n-1, 1040n-2, 1040n-3, 1040n-4, 1040n-5, 1040n-6 can include Figures 9A-9DAt least one of the memory devices 940a to 940d shown in FIG. 10 can be included in the first to sixth memory devices 1040n-1, 1040n-2, 1040n-3, 1040n-4, 1040n-5, 1040n-6. All of the first to sixth memory devices 1040n-1, 1040n-2, 1040n-3, 1040n-4, 1040n-5, 1040n-6 can have the same structure, or some or all of the first to sixth memory devices 1040n-1, 1040n-2, 1040n-3, 1040n-4, 1040n-5, 1040n-6 can have different structures.

[0160] The host 1010n, the first to sixth controller dies 101n-1, 101n-2, 101n-3, 101n-4, 101n-5, 101n-6, and the first to sixth memory devices 1040n-1, 1040n-2, 1040n-3, 1040n-4, 1040n-5, 1040n-6 can be disposed on a first substrate 1001n. The first substrate 1001n can include an interposer. The first substrate 1001n can include signal paths for electrically connecting the host 1010n and the first to sixth controller dies 101n-1, 101n-2, 101n-3, 101n-4, 101n-5, 101n-6, respectively, and signal paths for electrically connecting the first to sixth controller dies 101n-1, 101n-2, 101n-3, 101n-4, 101n-5, 101n-6 and the first to sixth memory devices 1040n-1, 1040n-2, 1040n-3, 1040n-4, 1040n-5, 1040n-6, respectively, in one embodiment, the first substrate 1001n can be replaced by a base tile, and the host 1010n, the first to sixth controller dies 101n-1, 101n-2, 101n-3, 101n-4, 101n-5, 101n-6, and the first to sixth memory devices 1040n-1, 1040n-2, 1040n-3, 1040n-4, 1040n-5, 1040n-6 can each be fabricated as a separate and independent tile that is electrically connected to the base tile. The integrated circuit package 1000n can further include a second substrate 1002n, and the first substrate 1001n can be disposed on the second substrate 1002n. The second substrate 1002n can include an interposer or a package substrate. The memory controller MC of the host 1010n and the first controller die 101n-1 can be electrically connected by signal paths formed in the first substrate 1001n. The interface circuit IF of the first controller die 101n-1 and the first memory device 1040n-1 can be electrically connected by signal paths formed in the first substrate 1001n. The memory controller MC of the host 1010n and the second controller die 101n-2 can be electrically connected by signal paths formed in the first substrate 1001n. The interface circuit IF of the second controller die 101n-2 and the second memory device 1040n-2 can be electrically connected by signal paths formed in the first substrate 1001n. The memory controller MC of the host 1010n and the third controller die 101n-3 can be electrically connected by signal paths formed in the first substrate 1001n. The interface circuit IF of the third controller die 101n-3 and the third memory device 1040n-3 can be electrically connected by signal paths formed in the first substrate 1001n.The host 1010n and the memory controller MC of the fourth controller die 101n-4 can be electrically connected by a signal path formed in the first substrate 1001n. The interface circuit IF of the fourth controller die 101n-4 and the fourth memory device 1040n-4 can be electrically connected by a signal path formed in the first substrate 1001n. The host 1010n and the memory controller MC of the fifth controller die 101n-5 can be electrically connected by a signal path formed in the first substrate 1001n. The interface circuit IF of the fifth controller die 101n-5 and the fifth memory device 1040n-5 can be electrically connected by a signal path formed in the first substrate 1001n. The host 1010n and the memory controller MC of the sixth controller die 101n-6 can be electrically connected by a signal path formed in the first substrate 1001n. The interface circuit IF of the sixth controller die 101n-6 and the sixth memory device 1040n-6 can be electrically connected by a signal path formed in the first substrate 1001n. The signal paths electrically connecting the host 1010n and the memory controller MC of the first to sixth controller dies 101n-1, 101n-2, 101n-3, 101n-4, 101n-5, 101n-6, respectively, can each correspond to the first bus 150 shown. Figure 1 The signal transmission lines electrically connecting the memory controller MC and the interface circuit IF of the first to sixth controller dies 101n-1, 101n-2, 101n-3, 101n-4, 101n-5, 101n-6, respectively, can each correspond to the second bus 160 shown. Figure 1 The signal paths electrically connecting the interface circuit IF of the first to sixth controller dies 101n-1, 101n-2, 101n-3, 101n-4, 101n-5, 101n-6 and the first to sixth memory devices 1040n-1, 1040n-2, 1040n-3, 1040n-4, 1040n-5, 1040n-6, respectively, can each correspond to the third bus 170 shown. Figure 1 The host 1010n, the first to sixth controller dies 101n-1, 101n-2, 101n-3, 101n-4, 101n-5, 101n-6, the first to sixth memory devices 1040n-1, 1040n-2, 1040n-3, 1040n-4, 1040n-5, 1040n-6, the first substrate 1001n, and the second substrate 1002n can be packaged in one package to form a single semiconductor device.

[0161] Figure 11 is a diagram illustrating a configuration of a computing system 1100 according to an embodiment of the present disclosure. Referring to FIG. 11, the computing system 1100 can include a host 1010, a first controller die 101-1, a second controller die 101-2, a third controller die 101-3, a fourth controller die 101-4, a fifth controller die 101-5, a sixth controller die 101-6, a first memory device 1040-1, a second memory device 1040-2, a third memory device 1040-3, a fourth memory device 1040-4, a fifth memory device 1040-5, a sixth memory device 1040-6, a first substrate 1001, and a second substrate 1002. Figure 11The computing system 1100 can be a computing logic hardware including at least one of a system on a chip (SoC), a central processing unit (CPU), a graphics processing unit (GPU), a field-programmable gate array (FPGA), a data processing unit (DPU), a vision processing unit (VPU), a neural processing unit (NPU), and an application-specific integrated circuit (ASIC) as a computing architecture suitable for executing a variety of application programs performed by a user. The computing system 1100 can include a host 1110, a first memory controller 1121, a second memory controller 1122, a third memory controller 1123, a fourth memory controller 1124, a first interface circuit 1131, a second interface circuit 1132, a third interface circuit 1133, a fourth interface circuit 1134, a first memory device 1141, a second memory device 1142, a third memory device 1143, and a fourth memory device 1144. The host 1110 can generate access requests to access the first to fourth memory devices 1141, 1142, 1143, 1144 for data communication. The host 1110 can selectively access at least one of the first to fourth memory devices 1141, 1142, 1143, 1144, and can simultaneously access at least two of the first to fourth memory devices 1141, 1142, 1143, 1144. The host 1110 can include a processing core 1111 and a cache 1112. The processing core 1111 can generate a plurality of access requests to access each of the first to fourth memory devices 1141, 1142, 1143, 1144 to perform a computing operation required for running an application program. The processing core 1111 can include at least one core. The processing core 1111 can include one core which can generate a plurality of access requests to access the first to fourth memory devices 1141, 1142, 1143, 1144 one by one or simultaneously. The processing core 1111 can include two or more cores, and the two or more cores can independently generate a plurality of access requests for accessing one or more of the first to fourth memory devices 1141, 1142, 1143, 1144. The cache 1112 can be configured as a computer memory buffer for mitigating a running speed difference between the host 1110 and the first to fourth memory devices 1141, 1142, 1143, 1144. The cache 1112 can improve a running speed and / or performance of the host 1110 because the processing core 1111 does not need to access the first to fourth memory devices 1141, 1142, 1143, 1144 if data or a computing result required by the processing core 1111 is stored in the cache 1112.

[0162] The host 1110 can be electrically connected to the first memory controller 1121 through the first host bus 1151. The host 1110 can transmit an access request and data to the first memory controller 1121 through the first host bus 1151 to access the first memory device 1141, and can receive data from the first memory controller 1121. The host 1110 can be electrically connected to the second memory controller 1122 through the second host bus 1152. The host 1110 can transmit an access request and data to the second memory controller 1122 through the second host bus 1152 to access the second memory device 1142, and can receive data from the second memory controller 1122. The host 1110 can be electrically connected to the third memory controller 1123 through the third host bus 1153. The host 1110 can transmit an access request and data to the third memory controller 1123 through the third host bus 1153 to access the third memory device 1143, and can receive data from the third memory controller 1123. The host 1110 can be electrically connected to the fourth memory controller 1124 through the fourth host bus 1154. The host 1110 can transmit an access request and data to the fourth memory controller 1124 through the fourth host bus 1154 to access the fourth memory device 1144, and can receive data from the fourth memory controller 1124. Figure 1 The first bus 150 shown in FIG. 1 can be used as each of the first to fourth host buses 1151, 1152, 1153, 1154, and each of the first to fourth host buses 1151, 1152, 1153, 1154 can have substantially the same characteristics as the first bus 150.

[0163] The first memory controller 1121 can be electrically connected to the first interface circuit 1131 through the first controller bus 1161. The first memory controller 1121 can generate command signals, address signals, and write data signals based on access requests and data received from the host 1110. The first memory controller 1121 can transmit the command signals, the address signals, and the write data signals to the first interface circuit 1131 through the first controller bus 1161, and can receive read data signals from the first interface circuit 1131. The first memory controller 1121 can generate data transmitted to the host 1110 through the first host bus 1151 based on the read data signals. The second memory controller 1122 can be electrically connected to the second interface circuit 1132 through the second controller bus 1162. The second memory controller 1122 can generate command signals, address signals, and write data signals based on access requests and data received from the host 1110. The second memory controller 1122 can transmit the command signals, the address signals, and the write data signals to the second interface circuit 1132 through the second controller bus 1162, and can receive read data signals from the second interface circuit 1132. The second memory controller 1122 can generate data transmitted to the host 1110 through the second host bus 1152 based on the read data signals. The third memory controller 1123 can be electrically connected to the third interface circuit 1133 through the third controller bus 1163. The third memory controller 1123 can generate command signals, address signals, and write data signals based on access requests and data received from the host 1110. The third memory controller 1123 can transmit the command signals, the address signals, and the write data signals to the third interface circuit 1133 through the third controller bus 1163, and can receive read data signals from the third interface circuit 1133. The third memory controller 1123 can generate data transmitted to the host 1110 through the third host bus 1153 based on the read data signals. The fourth memory controller 1124 can be electrically connected to the fourth interface circuit 1134 through the fourth controller bus 1164. The fourth memory controller 1124 can generate command signals, address signals, and write data signals based on access requests and data received from the host 1110. The fourth memory controller 1124 can transmit the command signals, the address signals, and the write data signals to the fourth interface circuit 1134 through the fourth controller bus 1164, and can receive read data signals from the fourth interface circuit 1134. The fourth memory controller 1124 can generate data transmitted to the host 1110 through the fourth host bus 1154 based on the read data signals. Figure 1The second bus 160 shown in the middle can be applied to each of the first to fourth controller buses 1161, 1162, 1163, 1164, and each of the first to fourth controller buses 1161, 1162, 1163, 1164 can have substantially the same characteristics as the second bus 160.

[0164] The first interface circuit 1131 can be electrically connected to the first memory device 1141 through the first memory bus 1171. The first interface circuit 1131 can generate a row address signal, a column address signal, a command signal, and a memory data signal based on a command signal, an address signal, and a write data signal received from the first memory controller 1121 through the first controller bus 1161. The first interface circuit 1131 can transfer the row address signal, the column address signal, the command signal, and the memory data signal to the first memory device 1141 through the first memory bus 1171. The first interface circuit 1131 can receive a memory data signal transferred from the first memory device 1141 through the first memory bus 1171, and can generate a read data signal based on the memory data signal. The first interface circuit 1131 can transfer the read data signal to the first memory controller 1121 through the first controller bus 1161. The second interface circuit 1132 can be electrically connected to the second memory device 1142 through the second memory bus 1172. The second interface circuit 1132 can generate a row address signal, a column address signal, a command signal, and a memory data signal based on a command signal, an address signal, and a write data signal received from the second memory controller 1122 through the second controller bus 1162. The second interface circuit 1132 can transfer the row address signal, the column address signal, the command signal, and the memory data signal to the second memory device 1142 through the second memory bus 1172. The second interface circuit 1132 can receive a memory data signal transferred from the second memory device 1142 through the second memory bus 1172, and can generate a read data signal based on the memory data signal. The second interface circuit 1132 can transfer the read data signal to the second memory controller 122 through the second controller bus 1162. The third interface circuit 1133 can be electrically connected to the third memory device 1143 through the third memory bus 1173. The third interface circuit 1133 can generate a row address signal, a column address signal, a command signal, and a memory data signal based on a command signal, an address signal, and a write data signal received from the third memory controller 1123 through the third controller bus 1163. The third interface circuit 1133 can transfer the row address signal, the column address signal, the command signal, and the memory data signal to the third memory device 1143 through the third memory bus 1173. The third interface circuit 1133 can receive a memory data signal transferred from the third memory device 1143 through the third memory bus 1173, and can generate a read data signal based on the memory data signal. The third interface circuit 1133 can transfer the read data signal to the third memory controller 1123 through the third controller bus 1163. The fourth interface circuit 1134 can be electrically connected to the fourth memory device 1144 through the fourth memory bus 1174.The fourth interface circuit 1134 can generate row address signals, column address signals, command signals, and memory data signals based on command signals, address signals, and write data signals received from the fourth memory controller 1124 over the fourth controller bus 1164. The fourth interface circuit 1134 can transmit the row address signals, the column address signals, the command signals, and the memory data signals to the fourth memory device 1144 over the fourth memory bus 1174. The fourth interface circuit 1134 can receive memory data signals transmitted from the fourth memory device 1144 over the fourth memory bus 1174, and can generate read data signals based on the memory data signals. The fourth interface circuit 1134 can transmit the read data signals to the fourth memory controller 1124 over the fourth controller bus 1164. Figure 1 The third bus 170 shown can be used as each of the first to fourth memory buses 1171, 1172, 1173, 1174, and each of the first to fourth memory buses 1171, 1172, 1173, 1174 can have substantially the same characteristics as the third bus 170.

[0165] Each of the first to fourth memory devices 1141, 1142, 1143, 1144 can include at least one memory die. When the first to fourth memory devices 1141, 1142, 1143, 1144 each include two or more memory dies, the first to fourth memory devices 1141, 1142, 1143, 1144 can each have a stacked chip structure. The two or more memory dies can be electrically connected to each other by wire bonding or by through-holes.

[0166] In an embodiment, the host 1110, the first to fourth memory controllers 1121, 1122, 1123, 1124, and the first to fourth interface circuits 1131, 1132, 1133, 1134 can be integrated as a first device, and the first to fourth memory devices 1141, 1142, 1143, 1144 can constitute second to fifth devices, respectively. In an embodiment, the host 1110 and the first to fourth memory controllers 1121, 1122, 1123, 1124 can be integrated as a first device, and the first interface circuit 1131 and the first memory device 1141 can be integrated as a second device. The second interface circuit 1132 and the second memory device 1142 can be integrated as a third device, the third interface circuit 1133 and the third memory device 1143 can be integrated as a fourth device, and the fourth interface circuit 1134 and the fourth memory device 1144 can be integrated as a fifth device. In an embodiment, the host 1110 can constitute a first device, and the first memory controller 1121, the first interface circuit 1131, and the first memory device 1141 can be integrated as a second device. The second memory controller 1122, the second interface circuit 1132, and the second memory device 1142 can be integrated as a third device. The third memory controller 1123, the third interface circuit 1133, and the third memory device 1143 can be integrated as a fourth device. The fourth memory controller 1124, the fourth interface circuit 1134, and the fourth memory device 1144 can be integrated as a fifth device. In an embodiment, the host 1110, the first to fourth memory controllers 1121, 1122, 1123, 1124, the first to fourth interface circuits 1131, 1132, 1133, 1134, and the first to fourth memory devices 1141, 1142, 1143, 1144 can each be manufactured as an independent semiconductor device. The host 1110, the first to fourth memory controllers 1121, 1122, 1123, 1124, the first to fourth interface circuits 1131, 1132, 1133, 1134, and the first to fourth memory devices 1141, 1142, 1143, 1144 can be manufactured as a die or a chip, and mounted on at least one base die or base chip.

[0167] The first memory device 1141 can perform parallel data communication with the first interface circuit 1131 and the first memory controller 1121 through the first memory bus 1171. The second memory device 1142 can perform parallel data communication with the second interface circuit 1132 and the second memory controller 1122 through the second memory bus 1172. The third memory device 1143 can perform parallel data communication with the third interface circuit 1133 and the third memory controller 1123 through the third memory bus 1173. The fourth memory device 1144 can perform parallel data communication with the fourth interface circuit 1134 and the fourth memory controller 1124 through the fourth memory bus 1174. In an embodiment, at least one of the first to fourth memory buses 1171, 1172, 1173, 1174 can have different characteristics from the third bus 170. For example, the width of the fourth memory bus 1174 can be smaller than the width of the fourth controller bus 1164, and the clock rate of the fourth memory bus 1174 can be higher than the clock rate of the fourth controller bus 1164. When the first to third memory devices 1141, 1142, 1143 perform parallel data communication through the first to third memory buses 1171, 1172, 1173, the fourth memory device 1144 can perform serial data communication through the fourth memory bus 1174. When the fourth memory device 1144 performs serial data communication, the fourth memory device 1144 and the fourth interface circuit 1134 can be equipped with a SerDes for converting parallel data into serial data or converting serial data into parallel data.

[0168] Figure 12 is a diagram illustrating a configuration of a computing system 1200 according to an embodiment of the disclosure. Referring to Figure 12 , the computing system 1200 can include a main host 1211, a sub-host 1212, a first memory controller 1221, a first interface circuit 1231, a first memory device 1241, a second memory controller 1222, a second interface circuit 1232, and a second memory device 1242. The main host 1211 can generate an access request for accessing the first memory device 1241, and can provide the access request to the first memory controller 1221. The main host 1211 can be electrically connected to the first memory controller 1221 through a first host bus 1251, and can provide the access request to the first memory controller 1221 through the first host bus 1251. The first host bus 1251 can have different characteristics from the third bus 170. Figure 1The main host 1211 can perform a variety of computing operations, and can access the sub-host 1212 to perform all or part of the computing operations in parallel. For example, the main host 1211 can perform a portion of a total workload, and the sub-host 1212 can be controlled by the main host 1211 to perform a remaining workload in the total workload. The sub-host 1212 can have the same type of processing core as the main host 1211, or can have a different type of processing core than the main host 1211. In an embodiment, the sub-host 1212 can be controlled by the main host 1211 to perform a function that increases a memory capacity available to the main host 1211. The sub-host 1212 can speed up a computing performance and / or speed of the main host 1211 by providing additional data required for a computing operation of the main host 1211. The sub-host 1212 can be, for example, a Compute eXpress Link (CXL) core. The main host 1211 can be electrically connected to the sub-host 1212 through the system bus 1201, and can provide a control signal for controlling the sub-host 1212 to the sub-host 1212 through the system bus 1201. The sub-host 1212 can generate an access request for accessing the second memory device 1242 based on the control signal provided from the main host 1211, and can provide the access request to the second memory controller 1222. The system bus 1201 can include a standard protocol for electrically connecting the main host 1211 and the sub-host 1212.

[0169] The sub-host 1212 can generate an access request for accessing the second memory device 1242, and can provide the access request to the second memory controller 1222. The sub-host 1212 can be electrically connected to the second memory controller 1222 through the second host bus 1252, and can transmit the access request to the second memory controller 1222 through the second host bus 1252. The second host bus 1252 can have substantially the same characteristics as the first host bus 1251. In an embodiment, the second host bus 1252 can have different characteristics from the first host bus 1251, and can use a standard protocol having a different specification compared to the first host bus 1251.

[0170] The first memory controller 1221 can be electrically connected to the first interface circuit 1231 through the first controller bus 1261. The first interface circuit 1231 can be electrically connected to the first memory device 1241 through the first memory bus 1271. The first controller bus 1261 can have substantially the same characteristics as the second bus 160 shown in FIG. 1, and the first memory bus 1271 can have substantially the same characteristics as the second bus 160 shown in FIG. 1. Figure 1 The first memory controller 1221 can be electrically connected to the first interface circuit 1231 through the first controller bus 1261. The first interface circuit 1231 can be electrically connected to the first memory device 1241 through the first memory bus 1271. The first controller bus 1261 can have substantially the same characteristics as the second bus 160 shown in FIG. 1, and the first memory bus 1271 can have substantially the same characteristics as the second bus 160 shown in FIG. 1. Figure 1The third bus 170 is shown to have substantially the same characteristics. In one embodiment, the width of the data bus included in the first controller bus 1261 can be less than or equal to the width of the data bus included in the first memory bus 1271. The second memory controller 1222 can be electrically connected to the second interface circuit 1232 via a second controller bus 1262. The second interface circuit 1232 can be electrically connected to the second memory device 1242 via a second memory bus 1272. The second controller bus 1262 can have substantially the same characteristics as the first controller bus 1261, and the second memory bus 1272 can have substantially the same characteristics as the first memory bus 1271. In one embodiment, the width of the data bus included in the second controller bus 1262 can be less than or equal to the width of the data bus included in the second memory bus 1272.

[0171] In one embodiment, the first controller bus 1261 and the first memory bus 1271 can have substantially the same characteristics as the second bus 160 and the third bus 170, respectively, and the second controller bus 1262 and the second memory bus 1272 can have different characteristics than the first controller bus 1261 and the first memory bus 1271. For example, the first memory device 1241 can communicate data in parallel with the first interface circuit 1231, and the second memory device 1242 can communicate data in series with the second interface circuit 1232. The width of the data bus included in the second memory bus 1272 can be less than the width of the data bus included in the second controller bus 1262. The clock rate of the second memory bus 1272 can be higher than the clock rate of the second controller bus 1262. In one embodiment, the second controller bus 1262 and the second memory bus 1272 can have substantially the same characteristics as the second bus 160 and the third bus 170, respectively, and the first controller bus 1261 and the first memory bus 1271 can have different characteristics than the second controller bus 1262 and the second memory bus 1272. For example, the second memory device 1242 can communicate data in parallel with the second interface circuit 1232, and the first memory device 1241 can communicate data in series with the first interface circuit 1231. The width of the first memory bus 1271 can be less than the width of the first controller bus 1261, and the clock rate of the first memory bus 1271 can be higher than the clock rate of the first controller bus 1261.

[0172] In an embodiment, the sub-host 1212, the second memory controller 1222, the second interface circuit 1232, and the second memory device 1242 can be disposed on a single interposer and / or substrate, and can be fabricated as a single semiconductor device. The sub-host 1212, the second memory controller 1222, and the second interface circuit 1232 can perform the functions of a dedicated controller device to allow the second memory device 1242 to communicate data with an external host device (e.g., the main host 1211). The single semiconductor device can be fabricated as a dual in-line memory module (DIMM) to provide a large amount of data storage space to the main host 1211. For example, the single semiconductor device can be a managed DRAM solution (MDS). In an embodiment, the sub-host 1212, the second memory controller 1222, the second interface circuit 1232, and the second memory device 1242 can be fabricated as independent dies, slices, or cores.

[0173] Figures 13A-13C is a diagram illustrating a configuration of a semiconductor device 1300a according to an embodiment of the present disclosure. Figure 13A is a conceptual plan view of the semiconductor device 1300a, Figure 13B is a cross-sectional view of the semiconductor device 1300a, and Figure 13C is a perspective view of the semiconductor device 1300a. The semiconductor device 1300a can be a memory system, such as a CXL module or a CXL device. The semiconductor device 1300a can include a controller device 1310a and a plurality of memory media MD. The semiconductor device 1300a can include a module substrate 1301a. The module substrate 1301a can include module pins 1304a, and can communicate with an external device through the module pins 1304a. For example, the external device can be the main host 1211 shown in Figure 12 , and the module pins 1304a can be electrically connected to Figure 12The semiconductor device 1300a can be electrically connected to the external device via the module pins 1304a by inserting the module pins 1304a into sockets and / or channels formed in a motherboard. The package substrate 1303a can be mounted on the module substrate 1301a, and the package substrate 1303a can be electrically connected to the module substrate 1301a by package balls and / or solder balls. On the package substrate 1303a, the interposer 1302a can be stacked. The interposer 1302a can be electrically connected to the package substrate 1303a using bumps. The controller device 1310a and the plurality of memory media MD can be disposed on the interposer 1302a. The package substrate 1303a, the interposer 1302a, the controller device 1310a, and the plurality of memory media MD can be encapsulated in a single package, and the single package can be mounted on the module substrate 1301a. The controller device 1310a can be disposed on the interposer 1302a and electrically connected to the interposer 1302a by micro bumps. The plurality of memory media MD can be disposed on the interposer 1302a. The controller device 1310a can be disposed in a first region on the interposer 1302a, and the plurality of memory media MD can be disposed in a second region on the interposer 1302a. The first region and the second region can not overlap each other.

[0174] The host H can be electrically connected to the module substrate 1301a and the external device through the system bus 1340a. The host H can be electrically connected to the memory controller MC through the host bus 1311a. The memory controller MC can be electrically connected to the interface circuit IF through the controller bus 1321a, and the interface circuit IF can be electrically connected to each of the plurality of memory media MD through the plurality of memory buses 1331a. The controller bus 1321a can have substantially the same characteristics as the second bus 160 shown in FIG. 1, and each of the plurality of memory buses 1331a can have substantially the same characteristics as the third bus 170 shown in FIG. 1. Figure 1 Figure 1 The controller bus 1321a can have substantially the same characteristics as the second bus 160 shown in FIG. 1, and each of the plurality of memory buses 1331a can have substantially the same characteristics as the third bus 170 shown in FIG. 1. Each of the plurality of memory media MD can perform parallel data communication with the interface circuit IF. The interface circuit IF can perform parallel data communication with the memory controller MC, or can perform partial parallel data communication. The width of each of the plurality of memory buses 1331a can be greater than or equal to the width of the controller bus 1321a, and the clock rate of each of the plurality of memory buses 1331a can be less than or equal to the clock rate of the controller bus 1321a.

[0175] The controller device 1310a can relay data communication between the external device and the plurality of memory media MD. The controller device 1310a can include the host H, the memory controller MC, and the interface circuit IF. The host H can correspond to Figure 12 ​The memory controller MC shown in the sub-host 1212 can correspond to Figure 12 The second memory controller 1222 shown, and the interface circuit IF can correspond to Figure 12 The second interface circuit 1232 shown. Redundant descriptions of corresponding components will be omitted. The controller device 1310a can be electrically connected to, and can be in data communication with, a plurality of memory media MD. The controller device 1310a can be electrically connected to each of the plurality of memory media MD through the interface circuit IF. Each of the plurality of memory media MD can correspond to Figure 12 The second memory device 1242 shown. The plurality of memory media MD can form independent channels and can be electrically connected to the interface circuit IF of the controller device 1310a respectively through independent memory buses. In Figures 13A-13C The semiconductor device 1300a is shown as having eight memory media, but the semiconductor device 1300a can have fewer than eight or more than eight memory media. Each of the plurality of memory media MD can include at least one memory die. When each of the plurality of memory media MD includes two or more memory dies, the two or more memory dies can be stacked to form a single memory medium. In Figure 13B and Figure 13C One memory medium includes eight memory dies, but one memory medium can include fewer than or more than eight memory dies.

[0176] The controller device 1310a can be electrically connected to the module substrate 1301a through the signal path 1342a formed in the interposer 1302a and the signal path 1351a formed in the package substrate 1303a. The controller device 1310a can be electrically connected to the pad 1305a formed in the interposer 1302a through the signal path 1341a formed in the interposer 1302a. The host H can be electrically connected to the module substrate 1301a through the signal path 1342a and the signal path 1351a. The interface circuit IF can be electrically connected to the pad 1305a through the signal path 1341a. The plurality of memory media MD can be electrically connected to the pad 1305a respectively through the wire bonds W1a. The plurality of memory media MD can be electrically connected to the controller device 1310a through the wire bonds W1a and the signal path 1341a. The interface circuit IF can be electrically connected to the plurality of memory media MD respectively through the signal path 1341a and the wire bonds W1a. The signal path 1341a and the wire bonds W1a can correspond to the plurality of memory buses 1331a.

[0177] The first memory die Dl of the memory media MD can be bonded to the interposer 1302a with DAFs. The second through eighth memory dies D2, D3, D4, D5, D6, D7, D8 can also be sequentially bonded with the first through seventh memory dies Dl, D2, D3, D4, D5, D6, D7, respectively, with DAFs. The first through eighth memory dies Dl, D2, D3, D4, D5, D6, D7, D8 can be electrically connected using wire bonds. The first through eighth memory dies Dl, D2, D3, D4, D5, D6, D7, D8 can be electrically connected to the interposer 1302a by wire bonding with the pads 1305a. The pads 1305a can be electrically connected to the controller device 1310a through the signal path 1341a. The interface circuit IF can be electrically connected with the signal path 1341a through micro bumps, such that an electrical connection can be formed between the interface circuit IF and the memory dies. The frequency of signals transmitted through the controller bus 1321a between the memory controller MC and the interface circuit IF can be greater than or equal to the frequency of signals transmitted through the signal path 1341a and the wire bonds Wla between the interface circuit IF and the memory media MD. The controller bus 1321a can include a first data bus electrically connecting the memory controller MC and the interface circuit IF, and the signal path 1341a can include a second data bus electrically connecting the interface circuit IF and the memory media MD. The width of the first data bus can be less than or equal to the width of the second data bus.

[0178] The semiconductor device 1300a can further include a power management integrated circuit PMIC 1330a. The power management integrated circuit PMIC can be disposed on the module substrate 1301a. In an embodiment, the power management integrated circuit PMIC can be disposed on the interposer 1302a. The power management integrated circuit PMIC can receive an externally applied power voltage through the module pins 1304a, and can generate a plurality of internal voltages according to the power voltage. The power management integrated circuit PMIC can generate the plurality of internal voltages by changing or adjusting the voltage level of the externally applied power voltage. The plurality of internal voltages can be applied to the host H, the memory controller MC, the interface circuit IF, and the memory media MD, and can be used as operating power voltages for the components of the semiconductor device 1300a. The power management integrated circuit PMIC can independently generate the internal voltages for the host H, the memory controller MC, the interface circuit IF, and the memory media MD, and the internal voltages can have different voltage levels. In an embodiment, at least two of the internal voltages can have the same voltage level, and the remaining internal voltages can have different voltage levels.

[0179] In one embodiment, the first to eighth memory dies D1, D2, D3, D4, D5, D6, D7, and D8 can be stacked vertically using vias and electrically connected to the interposer 1302a and adjacent memory dies via microbumps. When the first to eighth memory dies D1, D2, D3, D4, D5, D6, D7, and D8 are stacked on the interposer 1302a using microbumps, the interposer 1302a should be implemented as a silicon interposer. However, if the first to eighth memory dies D1, D2, D3, D4, D5, D6, D7, and D8 are stacked using wire bonding, and the multiple memory media MDs communicate in parallel with the controller device 1310a, then the interposer 1302a can be an organic interposer instead of a silicon interposer, as organic interposers are cheaper than silicon interposers. Therefore, if the multiple memory media MDs are stacked using wire bonding, the manufacturing cost of the semiconductor device 1300a can be reduced. Furthermore, if multiple memory media MDs communicate with the controller device 1310a in parallel, the bandwidth of the memory bus 1331a can be extended, thereby enabling more data to be received from or transmitted to the controller device 1310a in a shorter time.

[0180] Figures 14A-14C This is a diagram illustrating the configuration of a semiconductor device 1300b according to an embodiment of the present disclosure. Figure 14A It could be a conceptual plan view of a semiconductor device 1300b. Figure 14B It can be a cross-sectional view of semiconductor device 1300b, and Figure 14C This may be a perspective view of semiconductor device 1300b. Semiconductor device 1300b may be a memory system, such as a CXL module or CXL device. Semiconductor device 1300b may include controller device 1310b and multiple memory media MDs. Semiconductor device 1300b may include module substrate 1301b. Module substrate 1301b may include module pins 1304b, and may communicate with external devices via module pins 1304b. For example, the external device may be... Figure 12 The host 1211 is shown, and module pin 1304b can be electrically connected to... Figure 12The system bus 1201 is illustrated. The semiconductor device 1300b can be electrically connected to an external device via a motherboard by inserting the module pins 1304b into slots and / or channels formed in the motherboard. The package substrate 1303b can be mounted on the module substrate 1301b, and the package substrate 1303b can be electrically connected with the module substrate 1301b by package balls and / or solder balls. On the package substrate 1303b, the interposer 1302b can be stacked. The interposer 1302b can be electrically connected to the package substrate 1303b using bumps. The controller device 1310b and the plurality of memory media MD can be disposed on the interposer 1302b. The package substrate 1303b, the interposer 1302b, the controller device 1310b, and the plurality of memory media MD can be encapsulated in a single package, which can be mounted on the module substrate 1301b. The controller device 1310b can be disposed on the interposer 1302b and electrically connected to the interposer 1302b by micro bumps. The plurality of memory media MD can be disposed on the interposer 1302b. The controller device 1310b can be disposed in a first area on the interposer 1302b, and the plurality of memory media MD can be disposed in a second area and a third area on the interposer 1302b. The first area, the second area, and the third area can not overlap each other. For example, some of the plurality of memory media MD can be disposed in the second area, and the rest of the plurality of memory media MD can be disposed in the third area.

[0181] The controller device 1310b can relay data communication between an external device and the plurality of memory media MD. The controller device 1310b can include a host H, a memory controller MC, and an interface circuit IF. The host H can correspond to Figure 12 The memory controller MC can correspond to Figure 12 The second memory controller 1222, and the interface circuit IF can correspond to Figure 12 The second interface circuit 1232. Repetitive description of corresponding components will be omitted. The controller device 1310b can be electrically connected with the plurality of memory media MD and can perform data communication with the plurality of memory media MD. The controller device 1310b can be electrically connected to each of the plurality of memory media MD through the interface circuit IF. Each of the plurality of memory media MD can correspond to Figure 12 The second memory device 1242. The plurality of memory media MD can form independent channels and can each be electrically connected with the interface circuit IF of the controller device 1310b through independent memory buses. In Figures 14A-14CIn the semiconductor device 1300b, sixteen memory media are shown, but the semiconductor device 1300b can have fewer than sixteen or more than sixteen memory media. Each of the plurality of memory media MD can include at least one memory die. When each of the plurality of memory media includes two or more memory dies, the two or more memory dies can be stacked to form a single memory medium. In Figure 14B and Figure 14C In the semiconductor device 1300b, sixteen memory media are shown, but the semiconductor device 1300b can have fewer than sixteen or more than sixteen memory media. Each of the plurality of memory media MD can include at least one memory die. When each of the plurality of memory media includes two or more memory dies, the two or more memory dies can be stacked to form a single memory medium. In

[0182] The host H can be electrically connected to the module substrate 1301b and the external device through the system bus 1340b. The host H can be electrically connected to the memory controller MC through the host bus 1311b. The memory controller MC can be electrically connected to the interface circuit IF through the controller bus 1321b, and the interface circuit IF can be electrically connected to the plurality of memory media MD through the plurality of memory buses 1331b, 1332b, respectively. The controller bus 1321b can have substantially the same characteristics as the second bus 160 shown in Figure 1 , and each of the plurality of memory buses 1331b, 1332b can have substantially the same characteristics as the third bus 170 shown in Figure 1 . Each of the plurality of memory media MD can perform parallel data communication with the interface circuit IF. The interface circuit IF can perform parallel data communication with the memory controller MC, or can perform partial parallel data communication. Each of the plurality of memory buses 1331b, 1332b can have a width greater than or equal to the width of the controller bus 1321b, and each of the plurality of memory buses 1331b, 1332b can have a clock rate less than or equal to the clock rate of the controller bus 1321b.

[0183] The controller device 1310b can be electrically connected to the module substrate 1301b through the signal path 1343b formed in the interposer 1302b and the signal path 1351b formed in the package substrate 1303b. The controller device 1310b can be electrically connected to the first pad 1305b formed in the interposer 1302b through the first signal path 1341b formed in the interposer 1302b. The controller device 1310b can be electrically connected to the second pad 1306b formed in the interposer 1302b through the second signal path 1342b formed in the interposer 1302b. The host H can be electrically connected to the module substrate 1301b through the signal path 1343b and the signal path 1351b. The interface circuit IF can be electrically connected to the first pad 1305b through the first signal path 1341b and to the second pad 1306b through the second signal path 1342b. The plurality of memory media MD can be electrically connected to the first pad 1305b and the second pad 1306b, respectively, through wire bonds. The plurality of memory media MD can be electrically connected to the controller device 1310b through the wire bonds and the first signal path 1341b and the second signal path 1342b. The first memory medium MD1 can be electrically connected to the first pad 1305b through the wire bond W1b and to the controller device 1310b through the first pad 1305b and the first signal path 1341b. The second memory medium MD2 can be electrically connected to the second pad 1306b through the wire bond W2b and to the controller device 1310b through the second pad 1306b and the second signal path 1342b. The interface circuit IF can be electrically connected to the first memory medium MD1 through the first signal path 1341b and the wire bond W1b. The interface circuit IF can be electrically connected to the second memory medium MD2 through the second signal path 1342b and the wire bond W2b. The first signal path 1341b and the wire bond W1b can correspond to the first memory bus 1331b, and the second signal path 1342b and the wire bond W2b can correspond to the second memory bus 1332b.

[0184] The first memory die D1 of the first memory medium MD1 can be bonded with the interposer 1302b using DAF. The second through fourth memory dies D2, D3, D4 can also be sequentially bonded with the first through third memory dies D1, D2, D3 using DAF. The first through fourth memory dies D1, D2, D3, D4 can be electrically connected using wire bonds. The first through fourth memory dies D1, D2, D3, D4 can be electrically connected to the interposer 1302b by wire bonding to first pads 1305b formed on the interposer 1302b. The first pads 1305b can be electrically connected to the controller device 1310b through first signal paths 1341b formed in the interposer 1302b. The first memory die D5 of the second memory medium MD2 can be bonded with the interposer 1302b using DAF. The second through fourth memory dies D6, D7, D8 can also be sequentially bonded with the first through third memory dies D5, D6, D7, respectively, using DAF. The first through fourth memory dies D5, D6, D7, D8 can be electrically connected using wire bonds. The first through fourth memory dies D5, D6, D7, D8 can be electrically connected to the interposer 1302b by wire bonding to second pads 1306b formed on the interposer 1302b. The second pads 1306b can be electrically connected to the controller device 1310b through second signal paths 1342b formed in the interposer 1302b. The interface circuit IF can be electrically connected to the first signal paths 1341b and the second signal paths 1342b through micro bumps, such that electrical connections can be formed between the interface circuit IF and the first memory medium MD1 and the second memory medium MD2. The frequency of signals transmitted through the controller bus 1321b between the memory controller MC and the interface circuit IF can be greater than or equal to the frequency of signals transmitted through the first signal paths 1341b and the wire bonds W1b between the interface circuit IF and the first memory medium MD1 and the frequency of signals transmitted through the second signal paths 1342b and the wire bonds W2b between the interface circuit IF and the second memory medium MD2. The controller bus 1321b can include a first data bus electrically connecting the memory controller MC and the interface circuit IF. The first signal paths 1341b can include a second data bus electrically connecting the interface circuit IF and the first memory medium MD1. The second signal paths 1342b can include a third data bus electrically connecting the interface circuit IF and the second memory medium MD2. The width of the first data bus can be less than or equal to the width of the second data bus and the width of the third data bus. The semiconductor device 1300b can also include a power management integrated circuit PMIC 1330b. The power management integrated circuit PMIC can be disposed on the module substrate 1301b, and in one embodiment, the power management integrated circuit PMIC can be disposed on the interposer 1302b.

[0185] InFigure 13A and Figure 13C In the semiconductor device 1300a, four memory media MD can be disposed on a first side of the controller device 1310a, and another four memory media MD can be disposed on a second side of the controller device 1310a. In the semiconductor device 1300b, eight memory media MD can be disposed in two rows of four on a first side of the controller device 1310b, and eight memory media MD can be disposed in two rows of four on a second side of the controller device 1310b. The data bandwidth of the memory bus of the semiconductor device 1300a can be substantially the same as the data bandwidth of the memory bus of the semiconductor device 1300b. The structure of the semiconductor device 1300a can reduce the area of the interposer 1302a and the package substrate 1303a, while the structure of the semiconductor device 1300b can increase the area of the interposer 1302b and the package substrate 1303b but reduce the height of the package.

[0186] Figures 15A-15C is a diagram illustrating a configuration of a semiconductor device 1300c according to an embodiment of the present disclosure. Figure 15A may be a conceptual plan view of the semiconductor device 1300c, Figure 15B may be a cross-sectional view of the semiconductor device 1300c, and Figure 15C may be a perspective view of the semiconductor device 1300c. The semiconductor device 1300c can be a memory system, such as a CXL module or a CXL device. The semiconductor device 1300c can include a controller device 1310c and a plurality of memory media MD. The semiconductor device 1300c can include a module substrate 1301c. The module substrate 1301c can include module pins 1304c and can communicate with an external device through the module pins 1304c. For example, the external device can be a host 1211 as illustrated in Figure 12 may be electrically connected to the host 1211 as illustrated in Figure 12The system bus 1201 is shown. The semiconductor device 1300c can be electrically connected to external devices via a motherboard by inserting the module pins 1304c into slots and / or channels formed in the motherboard. The package substrate 1303c can be mounted on the module substrate 1301c, and the package substrate 1303c can be electrically connected with the module substrate 1301c by package balls and / or solder balls. The semiconductor device 1300c can not include an interposer. The package substrate 1303c, the controller device 1310c, and the plurality of memory media MD can be packaged in a single package, and the single package can be mounted on the module substrate 1301c. The controller device 1310c can be disposed on the package substrate 1303c. First pads 1361c on the controller device 1310c can be wire-bonded with pads 1305c on the package substrate 1303c, and the controller device 1310c can be electrically connected to the package substrate 1303c by wire-bonding. The plurality of memory media MD can be disposed on the package substrate 1303c. The controller device 1310c can be disposed in a first region on the package substrate 1303c, and the plurality of memory media MD can be disposed in a second region on the package substrate 1303c. The first region and the second region can not overlap each other.

[0187] The controller device 1310c can relay data communications between external devices and the plurality of memory media MD. The controller device 1310c can include a host H, a memory controller MC, and an interface circuit IF. The host H can correspond to Figure 12 the sub-host 1212 shown, the memory controller MC can correspond to Figure 12 the second memory controller 1222 shown, and the interface circuit IF can correspond to Figure 12 the second interface circuit 1232 shown. Repetitive description of corresponding components will be omitted. The controller device 1310c can be electrically connected with and can communicate data with the plurality of memory media MD. The controller device 1310c can be electrically connected to each of the plurality of memory media MD by the interface circuit IF. Each of the plurality of memory media MD can correspond to Figure 12 the second memory device 1242 shown. The plurality of memory media MD can form independent channels and can be electrically connected with the interface circuit IF of the controller device 1310c by independent memory buses. In Figures 15A-15C the semiconductor device 1300c is shown as having eight memory media, but the number of memory media that the semiconductor device 1300c has can be less than eight or more than eight. Each of the plurality of memory media MD can include at least one memory die. When each of the plurality of memory media includes two or more memory dies, the two or more memory dies can be stacked to form a single memory medium.Figure 15B and Figure 15C In the example shown, a memory media is shown as including eight memory dies, but a memory media can include fewer or more than eight memory dies.

[0188] The host H can be electrically connected to external devices through the system bus 1340c, and can be electrically connected to the memory controller MC through the host bus 1311c. The memory controller MC can be electrically connected to the interface circuit IF through the controller bus 1321c, and the interface circuit IF can be electrically connected to each of the plurality of memory media MD through a plurality of memory buses. The controller bus 1321c can have substantially the same characteristics as the second bus 160 shown in Figure 1 Each of the plurality of memory buses can have substantially the same characteristics as the third bus 170 shown in Figure 1 Each of the plurality of memory media MD can perform parallel data communication with the interface circuit IF. The interface circuit IF can perform parallel data communication with the memory controller MC, or can perform partial parallel data communication. Each of the plurality of memory buses can have a width greater than or equal to the width of the controller bus 1321c, and each of the plurality of memory buses can have a clock rate less than or equal to the clock rate of the controller bus 1321c.

[0189] The controller device 1310c can be electrically connected to the module substrate 1301c through the wire bonding W1c between the first pad 1361c and the pad 1305c, and the signal path 1351c formed in the package substrate 1303c. The controller device 1310c can be electrically connected to the plurality of memory media MD through the second pad 1362c. The host H can be electrically connected to the module substrate 1301a through the wire bonding W1c and the signal path 1351c. The interface circuit IF can be electrically connected to the memory media MD through the second pad 1362c. The memory media MD can be electrically connected to the second pad 1362c through the wire bonding W2c. The interface circuit IF can be electrically connected to the memory media MD through the wire bonding W2c. The wire bonding W2c can correspond to one of the plurality of memory buses.

[0190] The first memory die D1 of the memory media MD can be bonded to the package substrate 1303c using DAFs. The second to eighth memory dies D2, D3, D4, D5, D6, D7, D8 can also be sequentially bonded with the first to seventh memory dies D1, D2, D3, D4, D5, D6, D7, respectively, using DAFs. The first to eighth memory dies D1, D2, D3, D4, D5, D6, D7, D8 can be electrically connected using wire bonds. The first to eighth memory dies D1, D2, D3, D4, D5, D6, D7, D8 can be electrically connected to the interface circuit IF of the controller device 1310c by wire bonding with the second pads 1362c formed on the controller device 1310c. If multiple memory media MD are wire bonded directly to the second pads 1362c of the controller device 1310c, the manufacturing cost of the semiconductor device 1300c can be further reduced because the semiconductor device 1300c does not need to use an interposer.

[0191] The frequency of signals transmitted through the controller bus 1321c between the memory controller MC and the interface circuit IF can be greater than or equal to the frequency of signals transmitted through the wire bond W2c between the interface circuit IF and the memory media MD. The controller bus 1321a can include a first data bus electrically connecting the memory controller MC and the interface circuit IF, while the wire bond W2c can include a second data bus electrically connecting the interface circuit IF and the memory media MD. The width of the first data bus can be less than or equal to the width of the second data bus. The semiconductor device 1300c can further include a power management integrated circuit PMIC 1330c. The power management integrated circuit PMIC can be disposed on the module substrate 1301c.

[0192] Figures 16A-16C is a diagram illustrating a configuration of a semiconductor device 1300d according to an embodiment of the disclosure. Figure 16A may be a conceptual plan view of the semiconductor device 1300d, Figure 16B may be a cross-sectional view of the semiconductor device 1300d, and Figure 16C may be a perspective view of the semiconductor device 1300d. Redundant descriptions of corresponding components will be omitted. The semiconductor device 1300d can be a memory system such as a CXL module or a CXL device. The semiconductor device 1300d can include a controller device 1310d and a plurality of memory media MD. The semiconductor device 1300d can include a module substrate 1301d. The module substrate 1301d can include module pins 1304d and can communicate with an external device through the module pins 1304d. For example, the external device can be Figure 12 the host 1211 as illustrated, and the module pins 1304d can be electrically connected to Figure 12The semiconductor device 1300d can be electrically connected to external devices via a motherboard by inserting module pins 1304d into slots and / or channels formed in the motherboard. The package substrate 1303d can be mounted on the module substrate 1301d, and the package substrate 1303d can be electrically connected with the module substrate 1301d by package balls and / or solder balls. The semiconductor device 1300d can not include an interposer. The package substrate 1303d, the controller device 1310d, and the plurality of memory media MD can be encapsulated in a single package, and the single package can be mounted on the module substrate 1301d. The controller device 1310d can be disposed on the package substrate 1303d. The controller device 1310d can be disposed in a first area on the package substrate 1303d. The controller device 1310d can be electrically connected to the package substrate 1303d using wire bonding. First pads 1361d of the controller device 1310d can be electrically connected to pads 1305d on the package substrate 1303d by wire bonding. The pads 1305d can be electrically connected to signal paths 1351d formed in the package substrate 1303d. Some of the plurality of memory media MD can be disposed on the package substrate 1303d, and the rest of the plurality of memory media MD can be disposed on the controller device 1310d. Some of the plurality of memory media MD can be disposed in a second area on the package substrate 1303d. The first area and the second area can not overlap each other. The rest of the plurality of memory media MD can be disposed in the first area on the controller device 1310d. For example, eight memory media can be disposed on the package substrate 1303d, and the rest of eight memory media can be disposed on the controller device 1310d.

[0193] The controller device 1310d can relay data communication between external devices and the plurality of memory media MD. Although not shown, the controller device 1310d can include a host, a memory controller, and an interface circuit, and have substantially the same configuration as the controller device 1310c shown in FIG. 12B. Figure 15A The controller device 1310d can be electrically connected with the plurality of memory media MD and can have data communication with the plurality of memory media MD. The controller device 1310d can be electrically connected to each of the plurality of memory media MD through the interface circuit. Each of the plurality of memory media MD can correspond to Figure 12 The plurality of memory media MD can form independent channels, and can each be electrically connected with the interface circuit of the controller device 1310d through independent memory buses. In Figures 16A-16CIn some embodiments, the semiconductor device 1300d is shown as having sixteen memory media, but the semiconductor device 1300d can have fewer than sixteen or more than sixteen memory media. Each of the plurality of memory media MD can include at least one memory die. When each of the plurality of memory media MD includes two or more memory dies, the two or more memory dies can be stacked to form a single memory medium. In some embodiments, the semiconductor device 1300d is shown as having sixteen memory media, but the semiconductor device 1300d can have fewer than sixteen or more than sixteen memory media. Each of the plurality of memory media MD can include at least one memory die. When each of the plurality of memory media MD includes two or more memory dies, the two or more memory dies can be stacked to form a single memory medium. In Figure 16B and Figure 16C In some embodiments, one memory medium includes eight memory dies, but one memory medium can include fewer than or more than eight memory dies.

[0194] The controller device 1310d can be electrically connected to the module substrate 1301d through wire bonds W1d between the first pads 1361d and the pads 1305d and signal paths 1351d formed in the package substrate 1303d. The controller device 1310d can be electrically connected to the plurality of memory media MD through the second pads 1362d and the third pads 1363d. The host can be electrically connected to the module substrate 1301d through the wire bonds W1d and the signal paths 1351d. The interface circuit IF can be electrically connected to the plurality of memory media MD through the second pads 1362d and the third pads 1363d. The host can be electrically connected to the memory controller through a host bus. The memory controller can be electrically connected to the interface circuit through a controller bus. The interface circuit can be electrically connected to the plurality of memory media MD through wire bonds between the second and third pads 1362d, 1363d and the plurality of memory media MD. The wire bonds between the second and third pads 1362d, 1363d and the plurality of memory media MD can correspond to a plurality of memory buses. For example, the first memory medium MD1 can be electrically connected to the interface circuit through a wire bond W2d between the first memory medium MD1 and the second pad 1362d. The second memory medium MD2 can be electrically connected to the interface circuit through a wire bond W3d between the second memory medium MD2 and the third pad 1363d.

[0195] The first memory die D11 of the first memory medium MD1 can be bonded to the package substrate 1303d using DAF. The second through eighth memory dies D12, D13, D14, D15, D16, D17, D18 can also be sequentially bonded with the first through seventh memory dies D11, D12, D13, D14, D15, D16, D17, respectively, using DAF. The first through eighth memory dies D11, D12, D13, D14, D15, D16, D17, D18 can be electrically connected using wire bonding. The first through eighth memory dies D11, D12, D13, D14, D15, D16, D17, D18 can be electrically connected to the controller device 1310d by wire bonding with the second pad 1362d. The first memory die D21 of the second memory medium MD2 can be bonded to the top surface of the controller device 1310d using DAF. The second through eighth memory dies D22, D23, D24, D25, D26, D27, D28 can also be sequentially bonded with the first through seventh memory dies D21, D22, D23, D24, D25, D26, D27, respectively, using DAF. The first through eighth memory dies D21, D22, D23, D24, D25, D26, D27, D28 can be electrically connected using wire bonding. The first through eighth memory dies D21, D22, D23, D24, D25, D26, D27, D28 can be electrically connected to the controller device 1310d by wire bonding with the third pad 1363d. When multiple memory media MD are disposed on the controller device 1310d, the capacity of the semiconductor device 1300d can be increased without increasing the package area. The semiconductor device 1300d can further include a power management integrated circuit PMIC 1330d. The power management integrated circuit PMIC can be disposed on the module substrate 1301d. In an embodiment, the power management integrated circuit PMIC can be disposed on the package substrate 1303d.

[0196] Figures 17A-17C FIG. 13 is a diagram illustrating a configuration of a semiconductor device 1300e according to an embodiment of the disclosure. Figure 17A may be a conceptual plan view of the semiconductor device 1300e, Figure 17B may be a cross-sectional view of the semiconductor device 1300e, and Figure 17CThis may be a perspective view of semiconductor device 1300e. Redundant descriptions of corresponding components will be omitted. Semiconductor device 1300e may be a memory system, such as a CXL module or CXL device. Semiconductor device 1300e may include controller device 1310e and multiple memory media MDs. Semiconductor device 1300e may include module substrate 1301e. Module substrate 1301e may include module pins 1304e and may communicate with external devices through module pins 1304e. For example, the external device may be... Figure 12 The host 1211 is shown, and module pin 1304e can be electrically connected to... Figure 12 The system bus 1201 is shown. The semiconductor device 1300e can be electrically connected to an external device via the motherboard by inserting module pins 1304e into slots and / or channels formed in the motherboard. A package substrate 1303e can be mounted on the module substrate 1301e, and the package substrate 1303e can be electrically connected to the module substrate 1301e via package balls and / or solder balls. The semiconductor device 1300e may not include an interposer. The package substrate 1303e, the controller device 1310e, and a plurality of memory media MDs can be packaged in a single package, and the single package can be mounted on the module substrate 1301e. The controller device 1310e can be disposed on the package substrate 1303e. The controller device 1310e can be electrically connected to the package substrate 1303e via wire bonding. A first pad 1361e formed in the controller device 1310e can be electrically connected to a pad 1305e formed in the package substrate 1303e via wire bonding. Pad 1305e can be electrically connected to signal path 1351e formed in package substrate 1303e. All of the multiple memory media MDs can be disposed on controller device 1310e. Some of the multiple memory media MDs can be disposed in a first region on controller device 1310e, while the remaining multiple memory media MDs can be disposed in a second region on controller device 1310e. The first and second regions do not need to overlap. For example, when semiconductor device 1300e includes sixteen memory media, eight memory media can be disposed in the first region on controller device 1310e, while the other eight memory media can be disposed in the second region on controller device 1310e.

[0197] The controller device 1310e can relay data communication between an external device and multiple memory media MDs. Although not shown, the controller device 1310e may include a host, a memory controller, and interface circuitry, and may have... Figure 15AThe controller device 1310c can be electrically connected to and can be in data communication with a plurality of memory media MD. The controller device 1310c can be electrically connected to each of the plurality of memory media MD through an interface circuit. Each of the plurality of memory media MD can correspond to Figure 12 The second memory device 1242 is shown in FIG. 12B. The plurality of memory media MD can form independent channels and can each be electrically connected to the interface circuit of the controller device 1310e through an independent memory bus. In Figures 17A-17C In FIG. 12C, the semiconductor device 1300e is shown as having eight memory media, but the semiconductor device 1300e can have fewer than eight or more than eight memory media. Each of the plurality of memory media MD can include at least one memory die. When each of the plurality of memory media MD includes two or more memory dies, the two or more memory dies can be stacked to form a single memory medium. In Figure 17B and Figure 17C In FIG. 12C, the semiconductor device 1300e is shown as having eight memory media, but the semiconductor device 1300e can have fewer than eight or more than eight memory media. Each of the plurality of memory media MD can include at least one memory die. When each of the plurality of memory media MD includes two or more memory dies, the two or more memory dies can be stacked to form a single memory medium. In

[0198] The controller device 1310e can be electrically connected to the module substrate 1301e through a wire bond W1e between the first pad 1361e and the pad 1305e and a signal path 1351e formed in the package substrate 1303d. The controller device 1310e can be electrically connected to the plurality of memory media MD through the second pad 1362e and the third pad 1363e. The host can be electrically connected to the module substrate 1301e through the wire bond W1e and the signal path 1351e. The host can be electrically connected to the memory controller through a host bus. The memory controller can be electrically connected to the interface circuit through a controller bus. The interface circuit can be electrically connected to the plurality of memory media MD through the second pad 1362e and the third pad 1363e. The interface circuit can be electrically connected to the plurality of memory media MD through wire bonds between the second and third pads 1362e, 1363e and the plurality of memory media MD. The wire bonds between the second and third pads 1362e, 1363e and the plurality of memory media MD can correspond to a plurality of memory buses. For example, the first memory medium MD1 can be electrically connected to the interface circuit through a wire bond W2e between the first memory medium MD1 and the second pad 1362e. The second memory medium MD2 can be electrically connected to the interface circuit through a wire bond W3e between the second memory medium MD2 and the third pad 1363e.

[0199] The first memory die D11 of the first memory medium MD1 can be bonded to the controller device 1310e using DAF bonding. The second to eighth memory dies D12, D13, D14, D15, D16, D17, and D18 can also be sequentially bonded to the first to seventh memory dies D11, D12, D13, D14, D15, D16, and D17 using DAF bonding, respectively. The first to eighth memory dies D11, D12, D13, D14, D15, D16, D17, and D18 can be electrically connected using wire bonding. The first to eighth memory dies D11, D12, D13, D14, D15, D16, D17, and D18 can be electrically connected to the controller device 1310e by wire bonding to the second pad 1362e formed on the controller device 1310e. The first memory die D21 of the second memory medium MD2 can be bonded to the top surface of the controller device 1310e using DAF bonding. The second to eighth memory dies D22, D23, D24, D25, D26, D27, and D28 can also be sequentially bonded to the first to seventh memory dies D21, D22, D23, D24, D25, D26, and D27 using DAF bonding, respectively. The first to eighth memory dies D21, D22, D23, D24, D25, D26, D27, and D28 can be electrically connected using wire bonding. The first to eighth memory dies D21, D22, D23, D24, D25, D26, D27, and D28 can be electrically connected to the controller device 1310e by wire bonding to the third pad 1363e formed on the controller device 1310e. When multiple memory media (MDs) are mounted on the controller device 1310e, the capacity of the semiconductor device 1300e can be increased without increasing the package area. Furthermore, if multiple memory dies are vertically aligned rather than stacked in a stepped manner, wire bonding can be performed on all four sides of the memory dies, such as... Figure 17C As shown. Therefore, the semiconductor device can have a large capacity and a much lower manufacturing cost. The semiconductor device 1300e may also include a power management integrated circuit (PMIC) 1330e. The PMIC may be disposed on the module substrate 1301e. In one embodiment, the PMIC may be disposed on the package substrate 1303e.

[0200] Figure 18 This is a diagram illustrating the configuration of a semiconductor device 1400 according to an embodiment of the present disclosure. (See reference...) Figure 18Semiconductor device 1400 may be a memory system, such as a CXL module or CXL device. Semiconductor device 1400 may include a host 1410, a memory controller 1420, interface circuitry 1430, and multiple memory media MD1, MD2, MD3, and MD4. Host 1410 can be electrically connected to external devices (such as…) via system bus 1401. Figure 12 The host computer 1211 is shown. The memory controller 1420 is electrically connected to the host computer 1410 via a host bus 1450. The memory controller 1420 may include enhanced error correction code (ECC) circuitry. The memory controller 1420 may correct fault bit errors in data signals provided to the interface circuit 1430 and in data signals received from the interface circuit 1430 via enhanced ECC circuitry 1480. If the memory controller 1420 includes enhanced ECC circuitry 1480, it is able to detect and correct a greater number of fault bits generated by the memory media MD1, MD2, MD3, MD4. In one embodiment, enhanced ECC circuitry 1480 may correct fault bit errors in command signals and address signals provided from the memory controller 1420 to the interface circuit 1430 along with the data signals. In one embodiment, enhanced ECC circuitry 1480 may be located external to the memory controller 1420. For example, the enhanced ECC circuit 1480 can be configured to be electrically connected between the memory controller 1420 and the interface circuit 1430. The interface circuit 1430 can be electrically connected to the memory controller 1420 via a controller bus 1460, and can be electrically connected to multiple memory media MD1, MD2, MD3, and MD4 via multiple memory buses 1471, 1472, 1473, and 1474. Figure 18 In this embodiment, semiconductor device 1400 is shown to include four memory media, but the number of memory media included by semiconductor device 1400 may be less than four or more than four. Interface circuit 1430 is electrically connected to first memory medium MD1 via first memory bus 1471, to second memory medium MD2 via second memory bus 1472, to third memory medium MD3 via third memory bus 1473, and to fourth memory medium MD4 via fourth memory bus 1474. Interface circuit 1430 can perform parallel data communication or partially parallel data communication with memory controller 1420 via controller bus 1460. Interface circuit 1430 can perform parallel data communication with first to fourth memory media MD1, MD2, MD3, and MD4 via first to fourth memory buses 1471, 1472, 1473, and 1474, respectively. Controller bus 1460 may have... Figure 1The second bus 160 shown in FIG. 1 can have substantially the same characteristics as the third bus 170 shown in FIG. 1. Figure 1 The third bus 170 shown in FIG. 1 can have substantially the same characteristics as the second bus 160 shown in FIG. 1.

[0201] Each of the first to fourth memory media MD1, MD2, MD3, MD4 can include a plurality of memory dies. The plurality of memory dies can have a simplified structure compared to a conventional memory die. In the plurality of memory dies, the number of storage cells can increase, while the number of row address decoders and redundancy units can decrease. Accordingly, the size of the plurality of memory dies can be smaller than that of the conventional memory die. Further, since the plurality of memory dies can be stacked by wire bonding, a memory medium having a large data storage capacity can be implemented at a low manufacturing cost. However, as the number of row address decoders and redundancy units decreases, the number of faulty bits in data signals stored in or output from the storage cell region can increase. Typically, the memory die and the memory controller have ECC logic for correcting faulty bits in data signals. The memory controller 1420 can further include an enhanced ECC circuit 1480 (i.e., enhanced ECC performance) to further mitigate the increased faulty bits in the memory die by the ECC circuit 1480, thereby improving the reliability of the semiconductor device 1400. The host 1410, the memory controller 1420, and the interface circuit 1430 can be integrated as a controller device. Since the interface circuit 1430 performs parallel data communication with the memory controller 1420 and the plurality of memory media MD1, MD2, MD3, MD4, respectively, the memory controller 1420 can have no SerDes or a SerDes of minimal size. Accordingly, with part or all of the area allocated for the SerDes, the controller device can add the enhanced ECC circuit 1480 without increasing the total area of the controller device. Thus, the semiconductor device 1400 can have a reduced total area and manufacturing cost compared to a conventional semiconductor device, while still providing a memory system having the same or improved performance as the conventional semiconductor device.

[0202] Figure 19 is a diagram illustrating a configuration of a semiconductor device 1500 according to an embodiment of the disclosure. Referring to Figure 19 , the semiconductor device 1500 can be a memory system such as a CXL module or a CXL device. The semiconductor device 1500 can include a first host 1511, a second host 1512, a memory controller 1520, an interface circuit 1530, and a plurality of memory media MD1, MD2, MD3, MD4. The first host 1511 and the second host 1512 can each be electrically connected to an external device such as a host through a system bus 1501. Figure 12The first host 1511 and the second host 1512 can perform different functions. Basically, the first host 1511 can perform a data communication operation between the semiconductor device 1500 and an external device, and the second host 1512 can perform a computing operation of the semiconductor device 1500. Based on a first request from the external device, the first host 1511 can generate an access request to the plurality of memory media MD1, MD2, MD3, MD4, thereby providing data stored on the plurality of memory media MD1, MD2, MD3, MD4 and / or computation data to the external device through the system bus 1501, and the first host 1511 can provide the data transferred through the system bus 1501 to the plurality of memory media MD1, MD2, MD3, MD4 or as data for a computing operation. By generating a computation request based on a second request from the external device, the second host 1512 can perform a computing operation on data output from the plurality of memory media MD1, MD2, MD3, MD4 and / or data provided from the external device through the system bus 1501.

[0203] The memory controller 1520 can be electrically connected to the first host 1511 through the first host bus 1541, and can be electrically connected to the second host 1512 through the second host bus 1542. The memory controller 1520 can generate command signals and address signals for accessing the plurality of memory media MD1, MD2, MD3, MD4 based on an access request provided by the first host 1511. The memory controller 1520 can generate command signals and address signals for instructing a computing operation of the plurality of memory media MD1, MD2, MD3, MD4 based on a computing request provided from the second host 1512. The semiconductor device 1500 can further include a global buffer 1580. The global buffer 1580 can be electrically connected between the memory controller 1520 and the interface circuit 1530. The global buffer 1580 can store and output data corresponding to a vector so that the plurality of memory media MD1, MD2, MD3, MD4 can perform a matrix operation. The global buffer 1580 can receive data corresponding to a vector from the memory controller 1520, and can store the data corresponding to the vector. The global buffer 1580 can output the data corresponding to the vector to the interface circuit 1530, and the interface circuit 1530 can provide the data corresponding to the vector to the plurality of memory media MD1, MD2, MD3, MD4. In an embodiment, the global buffer 1580 can be implemented with a register or a static random access memory (SRAM). The interface circuit 1530 can be electrically connected to the memory controller 1520 through the controller bus 1560, and can be electrically connected to the plurality of memory media MD1, MD2, MD3, MD4 through the plurality of memory buses 1571, 1572, 1573, 1574. In FIG. 19, although the semiconductor device 1500 is illustrated as including four memory media, the number of memory media included by the semiconductor device 1500 can be less than four or more than four. The interface circuit 1530 can be electrically connected with the first memory medium MD1 through the first memory bus 1571, with the second memory medium MD2 through the second memory bus 1572, with the third memory medium MD3 through the third memory bus 1573, and with the fourth memory medium MD4 through the fourth memory bus 1574. The interface circuit 1530 can perform parallel data communication or partial parallel data communication with the memory controller 1520 through the controller bus 1560. The interface circuit 1530 can perform parallel data communication with the first to fourth memory media MD1, MD2, MD3, MD4 through the first to fourth memory buses 1571, 1572, 1573, 1574, respectively. The controller bus 1560 can have substantially the same characteristics as the second bus 160 illustrated in FIG. 18. Each of the first to fourth memory buses 1571, 1572, 1573, 1574 can have substantially the same characteristics as the first bus 161 illustrated in FIG. 18. Figure 1 ​Figure 1 The third bus 170 shown in FIG. 1 has substantially the same characteristics as the first bus 110.

[0204] Each of the first to fourth memory media MD1, MD2, MD3, MD4 can include a plurality of memory dies. Since each of the plurality of memory dies performs parallel data communication with the interface circuit 1530, they can not include additional circuits such as SerDes. The area from which the SerDes is removed can be provided with a processing unit PU. The processing unit PU can include a MAC (Multiply and Accumulate) unit. Each of the plurality of memory dies can include an array of storage units and the processing unit PU to perform a computation operation requested from the second host 1512. The first host 1511, the second host 1512, the memory controller 1520, the global buffer 1580, and the interface circuit 1530 can be integrated into a controller device. Since the interface circuit 1530 performs parallel data communication with the memory controller 1520 and the plurality of memory media MD1, MD2, MD3, MD4, respectively, the memory controller 1520 can have no SerDes or only a minimum size of SerDes. Thus, with part or all of the area allocated for the SerDes, the controller device can add the second host 1512 and the global buffer 1580 without increasing the total area of the controller device. Accordingly, the semiconductor device 1500 can implement a memory system performing a PIM (Processing-In-Memory) function in substantially the same area as a conventional semiconductor device.

[0205] Figure 20A FIG. 1 is a perspective view illustrating a computing system according to an embodiment of the disclosure. Figure 20B FIG. 2 is a perspective view illustrating a computing system according to an embodiment of the disclosure. Figure 20A FIG. 3 is a cross-sectional view illustrating the computing system of FIG. 2 taken along line A-A' of FIG. 2. Figure 20C FIG. 4 is a schematic block diagram illustrating a computing system according to an embodiment of the disclosure. Figure 20D FIG. 5 is a schematic plan view illustrating a base die structure of the computing system of FIG. 4. Figure 20A FIG. 6 is a perspective view illustrating a main portion of a signal transmission path of the computing system of FIG. 4. For reference, the computing system of FIG. 4 is shown. Figure 20E FIG. 7 is a perspective view illustrating a main portion of a signal transmission path of the computing system of FIG. 4. For reference, the computing system of FIG. 4 is shown. Figure 20A FIG. 8 is a perspective view illustrating a main portion of a signal transmission path of the computing system of FIG. 4. For reference, the computing system of FIG. 4 is shown. Figure 20E FIG. 9 is a perspective view illustrating a main portion of a signal transmission path of the computing system of FIG. 4. For reference, the computing system of FIG. 4 is shown. Figure 20A FIG. 10 is a perspective view illustrating a main portion of a signal transmission path of the computing system of FIG. 4. For reference, the computing system of FIG. 4 is shown.

[0206] Referring to FIG. 11, Figures 20A-20EThe computing system 3000A can include a substrate 3010, a base die structure 3100, a host device 3200, and at least one stacked memory structure 3300. The substrate 3010, the base die structure 3100, and the host device 3200 can be sequentially stacked along a first direction D1. Further, the substrate 3010, the base die structure 3100, and the stacked memory structure 3300 can also be stacked along the first direction D1. In the following embodiments, “stacked” or “disposed along the first direction D1” will be understood to mean formed or disposed in three dimensions, for example, in a vertical direction of the substrate 3010.

[0207] The substrate 3010 can support the base die structure 3100, the host device 3200, and the stacked memory structure 3300. The substrate 3010 can be a substrate for a semiconductor package including, for example, a printed circuit board (PCB), a ceramic substrate, a glass substrate, or a tape-automated bonding (TAB) substrate. The substrate 3010 can include a first surface S1 and a second surface S2 facing each other. The first surface S1 can be referred to as a top surface or a front surface, and the second surface S2 can be referred to as a bottom surface, a rear surface, or a back surface. The substrate 3010 can include a plurality of first pads P1 disposed on the first surface S1 and a plurality of second pads P2 disposed on the second surface S2. The plurality of first pads P1 can be coupled to first connection terminals BP1, such as bumps, of the base die structure 3100. The plurality of second pads P2 can be coupled to external connection terminals SB, such as solder balls. Sizes of the plurality of first pads P1 and sizes of the plurality of second pads P2 can be different from each other. The substrate 3010 can include a plurality of traces T. The plurality of first pads P1 and the plurality of second pads P2 can be coupled by the plurality of traces T, respectively, to communicate a plurality of electrical signals between the first pads P1 and the second pads P2.

[0208] The base die structure 3100 can be mounted on the first surface S1 of the substrate 3010. For example, the base die structure 3100 can include at least one base die 3120. For example, the base die structure 3100 can include as many base dies 3120 as the number of the stacked memory structures 3300. In an embodiment, when the computing system 3000A includes four stacked memory structures 3300A to 3300D, the base die structure 3100 can include four base dies 3120A to 3120D. As will be described in detail later, each of the base dies 3120A to 3120D can be configured to overlap with (or be bonded to) a portion of the host device 3200 and a portion of the corresponding stacked memory structure 3300A to 3300D, respectively. The base dies 3120A to 3120D can also be referred to as various terms such as a logic die (logic chip), a logic base, a control die (control chip), a master die (master chip), a buffer die (buffer chip), or an interface die (interface chip).

[0209] The base die structure 3100 can include a first surface S11 and a second surface S12 facing each other. The first surface S11 can correspond to a top surface or a front surface of the base die structure 3100, and the second surface S12 can correspond to a bottom surface or a rear surface of the base die structure 3100. For example, the second surface S12 can face the first surface S1 of the substrate 3010. A plurality of third pads P3 can be arranged on the first surface S11 of the base die structure 3100, and a plurality of fourth pads P4 can be arranged on the second surface S12 to be coupled to the first connection terminal BP1.

[0210] In an embodiment, each of the base dies 3120A to 3120D can include at least one first circuit block CB1 and at least one second circuit block CB2. For example, the first circuit block CB1 can be electrically coupled to the host device 3200. The first circuit block CB1 can include, for example, an interface circuit block 3122. The second circuit block CB2 can be electrically coupled to one of the stacked memory structures 3300A to 3300D. For example, the second circuit block CB2 can include a TSV circuit block 3124 and a test circuit block 3126.

[0211] The interface circuit block 3122 and the host device 3200 can be coupled through the first bus B1. The interface circuit block 3122 can convert various signals received from the host device 3200 into signals having a form suitable for being provided to the stacked memory structure 3300. The interface circuit block 3122 can include Figures 1-6 the interface circuit configuration described in the

[0212] Referring to Figure 20E To shorten the physical length of the first bus B1, at least a portion of the interface circuit block 3122 can be located in an overlap region OV_B in which the base dies 3120A to 3120D overlap the host device 3200 in the first direction.

[0213] The TSV circuit block 3124 can receive a signal output from the interface circuit block 3122, or can provide a signal output from the stacked memory structure 3300 to the interface circuit block 3122. The TSV circuit block 3124 can be coupled to a plurality of TSVs disposed inside the stacked memory structure 3300.

[0214] The test circuit block 3126 can include a plurality of test circuits for testing the stacked memory structure 3300. In some cases, the test circuit block 3126 can be omitted.

[0215] The first circuit block CB1 and the second circuit block CB2 can be connected through a second bus B2. Also, the first circuit block CB1 can be coupled to the second circuit block CB2 and the stacked memory structure 3300 through the second bus B2, respectively. The second bus B2 can have substantially the same configuration as the third bus 170 of Figure 1 The second bus B2 can be a signal transmission path capable of transmitting and receiving input / output signals of the stacked memory structure 3300. For example, a global input / output signal (GIO) can be transmitted through the second bus B2. However, the present application is not limited thereto.

[0216] The base die structure 3100 can further include an interconnect block ICB. The interconnect block ICB can be located around the base dies 3120A to 3120D and can insulate and support the base dies 3120A to 3120D. The interconnect block ICB can couple electrical elements of the substrate 3010 and electrical components of the host device 3200. The interconnect block ICB can be located around the base dies 3120A to 3120D, for example, around at least one side of the base dies 3120A to 3120D. The interconnect block ICB can include a plurality of bridges BR and a molding layer EN. The plurality of bridges BR can electrically connect the third pads P3 located on the first surface S11 of the base die structure 3100 and the fourth pads P4 located on the second surface S12 of the base die structure 3100. For example, the plurality of bridges BR can extend through all of the base die structure 3100 along the first direction D1. The plurality of bridges BR can include at least one of a conductive post, a conductive rod, a wire lead, or a conductive stud. The molding layer EN can be disposed between the plurality of bridges BR and can encapsulate side surfaces of the base dies 3120A to 3120D while insulating the plurality of bridges BR. The molding layer EN can include an epoxy resin with filler, an epoxy acrylate with filler, PBO (polybenzoxazole), or polyimide. The interconnect block ICB can further include at least one buildup interconnection layer MLM. For example, the buildup interconnection layer MLM can be located between the plurality of bridges BR and the third pads P3 or between the plurality of bridges BR and the fourth pads P4. The buildup interconnection layer MLM can include at least one of a vertical conductive line or a horizontal conductive line, or a redistribution layer. Signals directly transmitted from the substrate 3010 to the host device 3200 can be directly transmitted through the plurality of bridges BR and the buildup interconnection layer MLM. In an embodiment, the interconnect block ICB can be located between the host device 3200 and the substrate 3010. The thickness of the i...

Claims

1. A computing system, comprising: A base die has a first surface and a second surface, and includes a first circuit block and a second circuit block; A host device configured to overlap at least a portion of the first circuit block of the base die; as well as A stacked memory structure configured to overlap at least a portion of the second circuit block of the base die. Wherein, the host device and the first circuit block of the basic die are coupled through a first signal transmission path, and The first circuit block and the second circuit block are coupled through a second signal transmission path, as are the second circuit block and the stacked memory structure.

2. The computing system according to claim 1, wherein, A first bonding surface exists between the base die and the host device, and A second bonding surface exists between the base die and the stacked memory structure.

3. The computing system according to claim 1, wherein, The host device includes a memory controller. The first circuit block includes an interface circuit block, and The first signal transmission path is coupled to the memory controller and the interface circuit block.

4. The computing system according to claim 3, wherein, The data transmission format of the signal transmitted through the first signal transmission path is the same as the data transmission format of the signal transmitted through the second signal transmission path within a set range.

5. The computing system according to claim 4, wherein, The first signal transmission path includes a first bus based on DFI, where DFI refers to the DDR physical layer interface. The second signal transmission path includes a second bus for transmitting and receiving input / output signals of the stacked memory structure, and The interface circuit block converts the signals transmitted through the first bus into signals transmitted through the second bus.

6. The computing system according to claim 1, wherein, The host device includes at least one component. The first circuit block includes a memory controller, an interface circuit block, and a third signal transmission path coupled to the memory controller and the interface circuit block. The first signal transmission path is coupled to the component and the memory controller.

7. The computing system according to claim 6, wherein, The data transmission format of the signal transmitted through the third signal transmission path is the same as the data transmission format of the signal transmitted through the second signal transmission path within a set range.

8. The computing system according to claim 7, wherein, The first signal transmission path includes a first bus based on at least one of AXI, UCIe, AMBA, UPI, Infinite Fabric, and NVLINK, where AXI stands for Advanced Scalable Interface, UCIe stands for Universal Chipset High-Speed ​​Interconnect, AMBA stands for Advanced Microcontroller Bus Architecture, and UPI stands for Hyperpath Interconnect. The second signal transmission path includes a second bus for transmitting and receiving input / output signals of the stacked memory structure, and The third signal transmission path includes a third bus based on DFI, where DFI refers to the DDR physical layer interface.

9. The computing system according to claim 1, wherein, The second circuit block includes a TSV circuit block and a test circuit block.

10. The computing system according to claim 1, further comprising: A substrate, configured to be adjacent to the second surface of the base die and supporting the base die, the host device, and the stacked memory structure; and A connecting block, which is located around the base die and electrically connects the host device and the substrate.

11. The computing system according to claim 10, wherein, The connecting block includes: Multiple bridges coupling the electrical components of the host device and the electrical components of the substrate, and A molded layer insulating between the plurality of bridging elements.

12. The computing system according to claim 1, wherein, The shortest vertical distance between the base die and the host device is the same as the shortest vertical distance between the base die and the stacked memory structure.

13. The computing system according to claim 1, wherein, The host device and the stacked memory structure are arranged side by side in the horizontal direction on the first surface of the base die.

14. The computing system according to claim 1, wherein, The stacked memory structure and the host device are sequentially stacked on the first surface of the base die.

15. The computing system according to claim 1, wherein, The host device is configured to face the first surface of the base die, and The stacked memory structure is configured to face the second surface of the base die.

16. The computing system according to claim 15, wherein, The first signal transmission path is located on the first surface of the base die, and The second signal transmission path is located on the second surface of the base die.

17. The computing system according to claim 1, wherein, The base die has dimensions that overlap the entire bottom surface of the stacked memory structure.

18. An integrated circuit package, comprising: substrate; A base die, which is mounted on top of the substrate, and includes a first circuit block and a second circuit block; A host device, which is bonded to overlap with the first circuit block of the base die; A stacked memory structure, which is bonded to overlap with the second circuit block of the base die; A first signal transmission path is coupled to the host device and the base die; as well as A second signal transmission path is coupled between the first circuit block and the second circuit block, and between the second circuit block and the stacked memory structure.

19. The integrated circuit package according to claim 18, wherein, The host device includes a memory controller. The first circuit block includes an interface circuit block, and The data transmission format of the signal transmitted through the first signal transmission path is the same as the data transmission format of the signal transmitted through the second signal transmission path within a set range.

20. The integrated circuit package according to claim 18, wherein, The host device includes at least one component. The first circuit block includes a memory controller, an interface circuit block, and a third signal transmission path coupled to the memory controller and the interface circuit block. The first signal transmission path couples the component and the memory controller, and The data transmission format of the signal transmitted through the third signal transmission path is the same as the data transmission format of the signal transmitted through the second signal transmission path within a set range.

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