Timing sequence driven chip design cross-stage acceleration system and method

Abstract

The invention provides a time sequence driven chip design cross-stage acceleration system and method, and the system comprises a time sequence prediction module which is used for executing time sequence prediction and evaluation operation on received chip design related input data at the pre-layout stage and / or the pre-wiring stage of chip design; the constraint analysis module is used for analyzing the reasonability of the time sequence constraint by adopting a constraint search method according to the time sequence prediction and evaluation result of the time sequence prediction module and generating the optimal clock period constraint; and the integrated optimization module is used for integrating the optimal clock period constraint to a layout stage and / or wiring stage chip design process, interacting with an electronic design automation tool to complete chip design iteration, and evaluating a design acceleration effect. According to the invention, acceleration of chip design optimization and improvement of design efficiency are realized.

Description

Technical Field

[0001] This invention relates to the field of chip design technology, and in particular to a timing-driven chip design cross-stage acceleration system and method. Background Technology

[0002] Existing electronic design automation (EDA) tools divide the chip design process into multiple stages, including high-level synthesis, logic synthesis, layout planning, placement, clock tree synthesis, and routing. For example... Figure 1 As shown, at each stage, the electronic design automation (EDA) tool first generates the design for the current stage based on the design and constraints of the previous stage. Subsequently, the design for the current stage is evaluated for correctness, reliability, and performance, and then validated and optimized. Only after multiple iterations of evaluation and optimization can the design proceed to the next stage.

[0003] However, the existing chip design flow faces challenges in design efficiency, primarily because the high time cost of repetitive design significantly reduces efficiency, especially during the placement and routing stage, which becomes a bottleneck. Existing electronic design automation (EDA) tools, such as Synopsys IC Compiler, often only identify design failures at the approval stage due to the tolerance for soft constraints (such as timing violations), leading to repetitive design and wasted resources. Furthermore, designers pursuing larger design margins may cause additional repetitive design due to trial adjustments. In addition, the existing chip design flow is not aligned with cross-stage timing prediction; even with high-precision static timing analysis results, these results are difficult to apply to state-of-the-art EDA tools to guide circuit optimization. This is because the workflows of mainstream EDA tools, such as the Synopsys, Cadence, and Mentor series, are fixed and difficult to modify. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention proposes a timing-driven chip design cross-stage acceleration system and method. Before placement or routing, it predicts the final timing result of the circuit and designs reasonable timing constraints without performing placement or routing, thereby accelerating chip design optimization and improving design efficiency.

[0005] This invention provides a timing-driven chip design cross-stage acceleration system, comprising:

[0006] The timing prediction module is used to perform timing prediction and evaluation operations on the received chip design-related input data in the pre-placement and / or pre-routing stages of chip design.

[0007] The constraint analysis module is used to analyze the rationality of timing constraints based on the timing prediction and evaluation results of the timing prediction module, and generate the optimal clock cycle constraint by using the constraint search method.

[0008] An integrated optimization module is used to integrate the optimal clock cycle constraint into the chip design flow during the placement and / or routing stages, and interact with electronic design automation tools to complete chip design iterations and evaluate the design acceleration effect.

[0009] In one embodiment of the present invention, the timing prediction module integrates at least one static timing analysis method, including a pre-layout static timing analysis method based on machine learning (APPSTA) and a multi-modal, multi-angle static timing analysis method based on transfer learning (GM). 3 One or more combinations of STA, Lightweight Static Time Series Analysis Method Based on Time Series Pessimism Elimination (LightSTA).

[0010] In one embodiment of the present invention, the timing prediction module invokes a machine learning-based pre-layout static timing analysis method (APPSTA) to perform preliminary timing prediction during the pre-layout stage, and then uses a transfer learning-based multi-modal multi-angle static timing analysis method (GM) to perform further timing prediction. 3 Fine-tuning is performed using STA, and then the critical path relaxation accuracy is optimized using the Lightweight Static Temporal Analysis (LightSTA) method based on temporal pessimism elimination.

[0011] In the pre-routing stage, a multi-modal, multi-angle static timing analysis method (GM) based on transfer learning is invoked. 3 A combination of Static Time Series Analysis (STA) and Lightweight Static Time Series Analysis (LightSTA) based on time series pessimism elimination is used for time series prediction.

[0012] In one embodiment of the present invention, the constraint search method includes the doubling method and the half-break method. The constraint analysis module uses the doubling method and the half-break method to search for time-series constraints based on the results of the time-series prediction and evaluation. By iteratively approximating the optimal clock cycle constraint, a set of time-series constraints that satisfy the design margin is generated.

[0013] In one embodiment of the present invention, the design acceleration effect is evaluated by the speedup ratio, and the formula for calculating the speedup ratio is:

[0014] .

[0015] In one embodiment of the present invention, the electronic design automation tool includes at least one of Synopsys tools and Cadence tools;

[0016] In one embodiment of the present invention, the chip design-related input data includes circuit design files, timing constraint files, process-related files, and configuration parameters;

[0017] The circuit design file includes a netlist file after logic synthesis, as well as layout planning, placement, or clock tree synthesis information for the corresponding chip design stage; the timing constraint file includes timing constraint information such as initial clock definition and path constraints; the process-related file includes a standard cell library and parasitic parameter file for the target process node; and the configuration parameters include prediction mode, multi-mode multi-angle definition, and relaxation tolerance threshold.

[0018] In one embodiment of the present invention, the system supports advanced process nodes, is suitable for timing-sensitive high-performance circuit designs, covers small- to large-scale integrated circuits, and supports very large-scale integrated circuits through distributed computing.

[0019] Another aspect of the present invention provides a timing-driven method for accelerating chip design across stages, comprising:

[0020] Receive chip design-related input data and perform timing prediction and evaluation operations on the chip design-related input data;

[0021] Based on the results of timing prediction and evaluation, a constraint search method is used to analyze the rationality of timing constraints and generate the optimal clock cycle constraint.

[0022] The optimal clock cycle constraint is integrated into the chip design flow during the placement and / or routing phases, and interacts with electronic design automation tools to complete chip design iterations and evaluate the design acceleration effect.

[0023] In one embodiment of the present invention, at least one static timing analysis method is integrated when performing timing prediction and evaluation operations. The static timing analysis method includes a machine learning-based pre-layout static timing analysis method (APPSTA) and a transfer learning-based multimodal multi-angle static timing analysis method (GM). 3 One or more of the following: STA, Lightweight Static Time Series Analysis Method Based on Time Series Pessimism Elimination (LightSTA);

[0024] In the pre-layout stage, a machine learning-based pre-layout static timing analysis method (APPSTA) is invoked for preliminary timing prediction, followed by a transfer learning-based multi-modal multi-angle static timing analysis method (GM). 3 Fine-tuning is performed using STA, and then the critical path relaxation accuracy is optimized using the Lightweight Static Temporal Analysis (LightSTA) method based on temporal pessimism elimination.

[0025] In the pre-routing stage, a multi-modal, multi-angle static timing analysis method (GM) based on transfer learning is invoked.3 A combination of Static Time Series Analysis (STA) and Lightweight Static Time Series Analysis (LightSTA) based on time series pessimism elimination is used for time series prediction.

[0026] As can be seen from the above solutions, the advantages of the present invention are:

[0027] This invention provides a timing-driven chip design cross-stage acceleration system, comprising: a timing prediction module for performing timing prediction and evaluation operations on received chip design-related input data in the pre-placement and / or pre-routing stages of chip design; a constraint analysis module for analyzing the rationality of timing constraints using constraint search methods based on the timing prediction and evaluation results of the timing prediction module, and generating optimal clock cycle constraints; and an integration optimization module for integrating the optimal clock cycle constraints into the chip design flow in the placement and / or routing stages, and interacting with electronic design automation tools to complete chip design iterations and evaluate the design acceleration effect. This system integrates multiple static timing analysis methods, allowing the selection of the optimal analysis tool according to specific design requirements. It achieves accurate prediction and optimization of complex timing problems such as multi-mode multi-corner and critical path relaxation, exhibiting strong compatibility and scalability. Furthermore, it designs reasonable timing constraints without performing placement or routing, thereby saving time required for repeated placement or routing. This system accelerates chip design optimization and improves design efficiency. Attached Figure Description

[0028] Figure 1 A schematic diagram of the chip design flow in the prior art is shown;

[0029] Figure 2 This diagram illustrates the overall system architecture of a timing-driven chip design cross-stage acceleration system according to an embodiment of the present invention.

[0030] Figure 3 A flowchart illustrating a timing-driven chip design cross-stage acceleration method according to another embodiment of the present invention is shown.

[0031] The attached figures are labeled as follows:

[0032] 100: Timing-driven chip design acceleration systems across stages;

[0033] 110: Time series prediction module;

[0034] 120: Constraint Analysis Module;

[0035] 130: Integration and optimization module. Detailed Implementation

[0036] It should be noted that, in this invention, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus.

[0037] In the absence of further restrictions, an element defined by the phrase "comprising a..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0038] A detailed performance analysis of existing chip design flows revealed that placement and routing account for an average of 79.7% of the entire process time, while routing accounts for an average of 51.3%. This result indicates that avoiding repetitive placement or routing designs can minimize runtime and improve design efficiency. To address this, this invention provides a timing-driven, multi-stage acceleration system for chip design. Before chip placement or routing, and under specified library conditions, the system predicts the final timing characteristics of the circuit, analyzes timing constraints, and designs reasonable timing constraints without performing placement or routing.

[0039] For details, please refer to [link / reference]. Figure 2 As shown, Figure 2 The diagram shows the overall system architecture of a timing-driven chip design cross-stage acceleration system provided by an embodiment of the present invention.

[0040] A timing-driven chip design cross-stage acceleration system 100 comprises three parts: a timing prediction module 110, a constraint analysis module 120, and an integration optimization module 130.

[0041] Specifically, the timing prediction module 110 is used to perform timing prediction and evaluation operations on the received chip design-related input data in the pre-layout and / or pre-routing stages of chip design.

[0042] The constraint analysis module 120 is used to analyze the rationality of timing constraints based on the timing prediction and evaluation results of the timing prediction module, and generate the optimal clock cycle constraint by using a constraint search method.

[0043] The integration optimization module 130 is used to integrate the optimal clock cycle constraint into the chip design flow of the placement and / or routing stages, and interact with electronic design automation tools to complete chip design iterations and evaluate the design acceleration effect.

[0044] In this embodiment, the timing-driven chip design cross-stage acceleration system 100 can be deployed in stages such as pre-layout (after layout planning, before layout) and pre-routing (after clock tree synthesis, before routing), seamlessly connecting with the workflow of mainstream electronic design automation tools.

[0045] In existing technologies, a single static timing analysis method is typically used. This method suffers from low timing prediction accuracy before placement, failing to accurately assess the final timing performance of the circuit and resulting in insufficient reliability for design constraint optimization. It also struggles to quickly adapt to diverse process conditions (such as different operating modes, process corners, and parasitic corners), making efficient prediction difficult in complex design scenarios. Furthermore, its insufficient accuracy in critical path relaxation prediction makes it difficult to provide reasonable timing constraints, further impacting the overall optimization effect of the design. To address this, in one embodiment of the present invention, the timing prediction module integrates at least one static timing analysis method for chip design. This static timing analysis method includes a machine learning-based pre-placement static timing analysis method (APPSTA) and a transfer learning-based multi-mode multi-angle static timing analysis method (GM). 3 One or more combinations of STA, Lightweight Static Time Series Analysis Method Based on Time Series Pessimism Elimination (LightSTA).

[0046] APPSTA, a machine learning-based pre-layout static timing analysis method, addresses the challenge of low accuracy in early-stage static timing analysis, providing accurate and efficient timing predictions before layout. Compared to Synopsys IC Compiler, an electronic design automation tool, APPSTA reduces local delay errors by an average of 50%, relaxation errors by 64%, and runtime by 21%.

[0047] GM 3 STA is a multimodal, multi-angle static time series analysis method based on transfer learning. It addresses the challenge of poor generalization of static time series analysis to multimodal, multi-angle scenarios, achieving complete multimodal, multi-angle analysis. GM 3 STA outperforms Synopsys ICCompiler, one of the most advanced electronic design automation tools, in terms of accuracy across different operating modes, process angles, and parasitic angles. Furthermore, on circuits with unobserved angles, GM... 3 STA does not require repeated model training and only requires a few seconds of inference time.

[0048] LightSTA is a lightweight static timing analysis method based on timing pessimism elimination. It addresses the challenge of large biases in predicting critical path relaxation in static timing analysis, efficiently achieving accurate predictions of both critical path relaxation and worst-case relaxation. Before placement, LightSTA's runtime is only 0.09% longer than APPSTA, yet it reduces the mean absolute error of worst-case relaxation by 65.6%. Before routing, LightSTA's runtime is only slightly longer than GM... 3 An increase of 0.17% in STA reduces the mean absolute error of the worst relaxation by 60.8%.

[0049] In one specific implementation, the timing prediction module invokes a machine learning-based pre-layout static timing analysis method (APPSTA) to perform preliminary timing prediction during the pre-layout stage, and then uses a transfer learning-based multi-modal multi-angle static timing analysis method (GMSTA) to perform further timing prediction. 3 The timing analysis system (STA) is fine-tuned, and then the lightweight static timing analysis method based on timing pessimism elimination (LightSTA) is used to optimize the critical path relaxation accuracy. Before routing, a combination of the multi-mode, multi-angle static timing analysis method (GM3STA) based on transfer learning and the lightweight static timing analysis method based on timing pessimism elimination (LightSTA) is used for timing prediction, achieving comprehensive multi-mode, multi-angle timing analysis and critical path optimization. This flexibility allows the timing-driven chip design cross-stage acceleration system to be applied to different stages of chip design, including pre-placement (post-layout planning, pre-placement) and pre-routing (post-clock tree synthesis, pre-routing), and can be further extended to earlier design stages (such as high-level synthesis), thereby further improving design efficiency and increasing the speedup ratio.

[0050] Ultimately, the timing prediction module outputs timing prediction and evaluation results including: critical path relaxation accuracy prediction results, multi-mode multi-angle analysis results, etc.

[0051] Compared to existing electronic design automation (EDA) chip design flows, this timing-driven, multi-stage chip design acceleration system can accurately predict and evaluate the final timing results of the chip before placement or routing, and analyze the rationality of timing constraints. Without performing placement or routing, TAFrame designs reasonable timing constraints, thereby saving time required for repeated placement or routing and significantly improving design efficiency.

[0052] Furthermore, in one embodiment, the time-series prediction module can integrate not only APPSTA and GM 3The STA and LightSTA methods are also compatible with static timing analysis methods in mainstream electronic design automation tools (such as Synopsys' PrimeTime and Cadence's Tempus), demonstrating strong technical compatibility and scalability. This integration capability enables this timing-driven chip design cross-stage acceleration system framework to adapt to different process nodes and design requirements. It allows for the selection of the optimal static timing analysis method for specific industrial design scenarios, achieving accurate prediction and optimization of complex timing problems such as multi-mode, multi-angle, and critical path relaxation.

[0053] The constraint analysis module 120 is used to determine the rationality of timing constraints based on the timing prediction and evaluation results of the timing prediction module, and to generate optimal clock cycle constraints using a constraint search method. In one embodiment, the constraint search method adopts a timing constraint analysis method based on LightSTA, which obtains the optimal clock cycle constraints through relaxation prediction and search. Specifically, the constraint analysis module uses the critical path relaxation accuracy prediction results of LightSTA, employs the doubling method and the binary search method to perform timing constraint search to determine the upper and lower bounds, and uses the critical path relaxation accuracy prediction results to iteratively approximate the optimal clock cycle constraints between the upper and lower bounds, generating a set of timing constraints that meet the design margin. If the generated optimal clock cycle constraints are reasonable, they are integrated into the chip design flow of the placement stage and / or routing stage, and the subsequent chip design flow is executed. Otherwise, the iteration operation is repeated until the generated optimal clock cycle constraints are determined to be reasonable. In a specific implementation, the rationality judgment can be based on the relaxation value of the critical path. For example, if the relaxation value of the critical path is greater than the relaxation tolerance threshold, the path meets the timing constraints and is reasonable; otherwise, it is identified as a timing violation of the path, and the constraint is unreasonable.

[0054] This timing-driven, multi-stage acceleration system for chip design can analyze optimal timing constraints without performing complete placement and routing. Once the optimal clock cycle constraints are obtained, the entire design can be executed based on them, saving time required for repeated placement and routing. Compared to traditional design flows based on electronic design automation tools, this timing-driven, multi-stage acceleration system significantly shortens the feedback loop of unreasonable timing constraints.

[0055] In one embodiment, the integration optimization module 130 integrates the optimal clock cycle constraint into the chip design flow during the placement and / or routing stages, and interacts with electronic design automation tools (such as Synopsys tools, Cadence tools, etc.) to complete chip design iterations and evaluate the design acceleration effect. Compared with the chip design flow of the prior art, the present invention only requires one design execution after evaluation. In a specific implementation, the design acceleration effect is evaluated by the speedup ratio, which increases with the number of repeated designs. The specific speedup ratio depends on the number of repeated designs and the evaluation node in the actual project, and the calculation formula is:

[0056] . Formula (1)

[0057] Furthermore, in one embodiment, the chip design-related input data includes circuit design files, timing constraint files, process-related files, and configuration parameters. Specifically, the circuit design files include a netlist file after logic synthesis, and layout planning, placement, or clock tree synthesis information corresponding to the chip design stage; the timing constraint files include initial timing constraints, containing initial clock definitions, path constraints, and other timing constraint information; the process-related files include a standard cell library and parasitic parameter files for the target process node; and the configuration parameters include prediction modes (pre-placement / pre-routing), multi-mode multi-angle definitions, and relaxation tolerance thresholds.

[0058] Furthermore, in one embodiment, the final output data of the timing-driven chip design cross-stage acceleration system of the present invention includes: critical path relaxation accuracy prediction results, timing relaxation distribution, multi-mode multi-angle analysis results, etc. output by the timing prediction module, the optimal clock cycle constraint file output by the constraint analysis module, and the design acceleration effect evaluation results output by the integration optimization module.

[0059] Furthermore, it's worth noting that this timing-driven chip design cross-stage acceleration system is not limited to timing-driven optimization but can also be extended to optimization scenarios involving performance metrics such as area and power consumption. Through modular architecture design, appropriate predictive analytics methods can be selected for different optimization objectives, and combined with dynamically adjusted constraints to achieve comprehensive performance optimization. For example, in low-power design scenarios, timing prediction and constraint analysis driven by power consumption can generate design schemes that meet on-chip power consumption limits; in high-performance design scenarios, timing optimization can be prioritized while also considering area efficiency.

[0060] Furthermore, in one embodiment, the system supports advanced process nodes, is suitable for timing-sensitive high-performance circuit designs, covers small- to large-scale integrated circuits, and supports very large-scale integrated circuits through distributed computing.

[0061] The following section will utilize the aforementioned timing-driven chip design cross-stage acceleration system to conduct performance analysis and evaluation of the speed improvement of the pre-layout and pre-routing versions through specific experiments.

[0062] For the performance analysis and evaluation of the pre-layout version: From the above formula (1), the formula for calculating the speedup ratio of the pre-layout version is as follows:

[0063]

[0064] The pre-placement version experiment is based on 14 circuit designs from the ITC'99 benchmark and the OpenROAD project. Each design generates 40 circuit implementations based on different clock cycle constraints, for a total of 560 circuit implementations. The experiment uses TC process corners and 9m_cbest parasitic corner conditions, and predictions are based on the circuit netlist after logic synthesis. The clock cycle constraint range is [0.01, 3.00] nanoseconds, with 300 values ​​sampled at equal intervals. The pre-placement version integrates APPSTA and GM... 3 Static timing analysis methods STA and LightSTA are used, responsible for preliminary timing prediction, multi-mode and multi-angle adjustment and optimization, and critical path relaxation prediction accuracy improvement, respectively. The experimental procedure includes calling APPSTA to perform preliminary timing prediction before placement, and utilizing GM... 3 The STA method is used to adjust the results, and finally LightSTA is used to improve the accuracy of critical path relaxation prediction. The timing constraints are then analyzed based on the prediction results.

[0065] For performance analysis and evaluation of the pre-routing version: From the above formula (1), the formula for calculating the speedup ratio of the pre-routing version is as follows:

[0066]

[0067] The pre-routing version of the experiment was conducted under the same conditions as the pre-placement version, based on 14 circuit designs and 560 circuit implementations from the ITC'99 and OpenROAD projects. The experiment was performed under TC process corner and 9m_cbest parasitic corner conditions, with the input being the circuit netlist after placement and clock tree synthesis. The clock cycle constraint range was [0.01, 3.00] nanoseconds, with 300 values ​​sampled at equal intervals. The pre-routing version integrated GM... 3 STA and LightSTA are responsible for optimizing the accuracy of multi-modal, multi-angle temporal analysis and critical path relaxation prediction, respectively. The experimental procedure includes calling GM... 3 STA predicts timing results before routing, combines with LightSTA to improve the accuracy of critical path relaxation prediction, and analyzes timing constraints based on the prediction results.

[0068] Compared to the design flow of existing electronic design automation (EDA) tools, this invention achieves significant speedup. Experimental results show that the lower limit of speed improvement for the pre-placement version of this invention is an average of 63%, while the lower limit of speed improvement for the pre-routing version is an average of 33%. Furthermore, when the optimal clock cycle constraint does not exceed 3.00 nanoseconds, the speed improvement for the pre-placement version of this invention is typically between 141% and 261%, and the speed improvement for the pre-routing version is typically between 60% and 86%.

[0069] This embodiment is a method embodiment corresponding to the system embodiment described above, such as... Figure 3 As shown, Figure 3 This diagram illustrates a flowchart of a timing-driven chip design cross-stage acceleration method according to an embodiment of the present invention. This method implementation can be combined with the system implementation described above. The relevant technical details mentioned in the system implementation are still valid in this method implementation, and will not be repeated here to avoid repetition.

[0070] A timing-driven method for accelerating chip design across stages includes at least the following steps:

[0071] Step S1: Receive chip design-related input data and perform timing prediction and evaluation operations on the chip design-related input data;

[0072] Step S2: Based on the results of timing prediction and evaluation, use the constraint search method to analyze the rationality of timing constraints and generate the optimal clock cycle constraint;

[0073] Step S3: Integrate the optimal clock cycle constraint into the chip design flow of the placement and / or routing stages, and interact with electronic design automation tools to complete chip design iterations and evaluate the design acceleration effect.

[0074] In one embodiment, at least one static timing analysis method is integrated when performing timing prediction and evaluation operations. The static timing analysis method includes a machine learning-based pre-layout static timing analysis method (APPSTA) and a transfer learning-based multimodal multi-angle static timing analysis method (GMSTA). 3 This involves one or more of the following: STA (Static Time Analysis), Lightweight Static Time Analysis (LightSTA) based on time pessimism elimination. Specifically, APPSTA is called in the pre-layout stage for preliminary time series prediction, and GM (General Time Management) is used to perform the final prediction. 3 STA is fine-tuned, and then LightSTA is used to optimize the relaxation accuracy of the critical path; GM is called in the pre-routing stage. 3 A combination of STA and LightSTA is used for time series prediction.

[0075] In addition, it should be noted that, in combination Figure 1 As shown, the chip design cross-stage acceleration system and method of the present invention are for... Figure 1 The design flow for the period between specified timing constraints and the approval / verification process in existing technologies is improved. The design flow for the specified timing constraints and preceding them, as well as the design flow for approval / verification and subsequent processes, can be improved by... Figure 1 It is consistent with existing technical processes.

[0076] This method embodiment can be implemented in conjunction with the implementation methods of the above system embodiments. The relevant technical details mentioned in the implementation methods of the above embodiments remain valid in the implementation methods of this method embodiment, and will not be repeated here to avoid repetition. It should be noted that the scope of the methods and systems in the embodiments of the present invention is not limited to performing functions in the order shown or discussed, but may also include performing functions in a substantially simultaneous manner or in the reverse order according to the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be applied, omitted, or combined. Furthermore, features described with reference to certain examples may be combined in other examples.

[0077] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of the present invention.

Claims

1. A timing-driven chip design cross-stage acceleration system, characterized in that, Include: The timing prediction module is used to perform timing prediction and evaluation operations on the received chip design-related input data in the pre-placement and / or pre-routing stages of chip design. The constraint analysis module is used to analyze the rationality of timing constraints based on the timing prediction and evaluation results of the timing prediction module, and generate the optimal clock cycle constraint by using the constraint search method. An integrated optimization module is used to integrate the optimal clock cycle constraint into the chip design flow during the placement and / or routing stages, and interact with electronic design automation tools to complete chip design iterations and evaluate the design acceleration effect.

2. The system according to claim 1, characterized in that, The timing prediction module integrates at least one static timing analysis method, including a machine learning-based pre-layout static timing analysis method (APPSTA) and a transfer learning-based multi-modal multi-angle static timing analysis method (GM). 3 One or more combinations of STA, Lightweight Static Time Series Analysis Method Based on Time Series Pessimism Elimination (LightSTA).

3. The system according to claim 2, characterized in that, The timing prediction module invokes the pre-layout static timing analysis method (APPSTA) based on machine learning in the pre-layout stage to perform preliminary timing prediction, and then uses the multi-modal multi-angle static timing analysis method (GM) based on transfer learning. 3 Fine-tuning is performed using STA, and then the critical path relaxation accuracy is optimized using the Lightweight Static Temporal Analysis (LightSTA) method based on temporal pessimism elimination. In the pre-routing stage, a multi-modal, multi-angle static timing analysis method (GM) based on transfer learning is invoked. 3 A combination of Static Time Series Analysis (STA) and Lightweight Static Time Series Analysis (LightSTA) based on time series pessimism elimination is used for time series prediction.

4. The system according to claim 2, characterized in that, The constraint search method includes the doubling method and the binary method. The constraint analysis module uses the doubling method and the binary method to search for time series constraints based on the results of the time series prediction and evaluation. By iteratively approximating the optimal clock cycle constraint, a set of time series constraints that meet the design margin is generated.

5. The system according to claim 1, characterized in that, The design acceleration effect is evaluated using the speedup ratio, which is calculated using the following formula: 。 6. The system according to claim 1, characterized in that, The electronic design automation tools include at least one of the Synopsys suite of tools and the Cadence suite of tools.

7. The system according to claim 1, characterized in that, The chip design-related input data includes circuit design files, timing constraint files, process-related files, and configuration parameters. The circuit design file includes a netlist file after logic synthesis, as well as layout planning, placement, or clock tree synthesis information for the corresponding chip design stage; the timing constraint file includes timing constraint information such as initial clock definition and path constraints; the process-related file includes a standard cell library and parasitic parameter file for the target process node; and the configuration parameters include prediction mode, multi-mode multi-angle definition, and relaxation tolerance threshold.

8. The system according to claim 1, characterized in that, The system supports advanced process nodes and is suitable for timing-sensitive high-performance circuit designs; it covers small- to medium-scale integrated circuits and supports very large-scale integrated circuits through distributed computing.

9. A timing-driven method for accelerating chip design across stages, characterized in that, Include: Receive chip design-related input data and perform timing prediction and evaluation operations on the chip design-related input data; Based on the results of timing prediction and evaluation, a constraint search method is used to analyze the rationality of timing constraints and generate the optimal clock cycle constraint. The optimal clock cycle constraint is integrated into the chip design flow during the placement and / or routing phases, and interacts with electronic design automation tools to complete chip design iterations and evaluate the design acceleration effect.

10. The method according to claim 9, characterized in that, Integrating at least one static timing analysis method when performing timing prediction and evaluation operations, the static timing analysis method includes a machine learning-based pre-layout static timing analysis method (APPSTA) and a transfer learning-based multimodal multi-angle static timing analysis method (GM). 3 One or more of the following: STA, Lightweight Static Time Series Analysis Method Based on Time Series Pessimism Elimination (LightSTA); In the pre-layout stage, a machine learning-based pre-layout static timing analysis method (APPSTA) is invoked for preliminary timing prediction, followed by a transfer learning-based multi-modal multi-angle static timing analysis method (GM). 3 Fine-tuning is performed using STA, and then the critical path relaxation accuracy is optimized using the Lightweight Static Temporal Analysis (LightSTA) method based on temporal pessimism elimination. In the pre-routing stage, a multi-modal, multi-angle static timing analysis method (GM) based on transfer learning is invoked. 3 A combination of Static Time Series Analysis (STA) and Lightweight Static Time Series Analysis (LightSTA) based on time series pessimism elimination is used for time series prediction.

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