Analog method, device, equipment, storage medium and product of graphics processor
By using inter-process communication mechanisms to simulate the hardware connections and logic of graphics processors, the problem of poor scalability of existing simulation platforms is solved, enabling efficient graphics processor software development and problem localization.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- MOXIN ARTIFICIAL INTELLIGENCE TECH (SHENZHEN) CO LTD
- Filing Date
- 2026-02-25
- Publication Date
- 2026-06-19
AI Technical Summary
Existing graphics processor simulation platforms are difficult to expand and reuse, resulting in a large workload for development and maintenance and low development efficiency.
Inter-process communication mechanisms, such as shared memory, message queues, and socket communication, are used to simulate the hardware connections between different physical components within a graphics processor. The communication mechanisms and processing logic drive process groups to communicate and run, thereby simulating the execution process of a graphics processor.
It achieves high scalability and flexibility of the graphics processor simulation platform, greatly improving the development efficiency of related software and facilitating debugging and problem localization.
Smart Images
Figure CN121724825B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of computer technology, and in particular to a method, apparatus, device, storage medium, and product for simulating a graphics processor. Background Technology
[0002] Graphics Processing Units (GPUs) contain a large number of heterogeneous physical structures. To shorten development cycles, simulation platforms are needed for firmware and driver developers, runtime developers, compiler developers, and operator library developers. Current simulation platforms are typically designed specifically for GPUs, making them difficult to extend and reuse, resulting in a large workload for development and maintenance, and low development efficiency. Summary of the Invention
[0003] The purpose of this application is to provide a method, apparatus, device, storage medium, and product for simulating a graphics processor, in order to solve the problems of simulation platforms being difficult to expand and reuse, having a large workload for development and maintenance, and low development efficiency.
[0004] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:
[0005] In a first aspect, embodiments of this application provide a method for simulating a graphics processor, comprising:
[0006] Based on the physical components of the graphics processor, a process group corresponding to the graphics processor is created, and the process group includes the process corresponding to the physical component;
[0007] Configure the communication mechanism between different processes in the process group according to the communication mechanism between the physical components of the graphics processor;
[0008] Based on the communication mechanism and the processing logic of the physical components for the first task, the process group is driven to communicate and run in order to simulate the execution process of the graphics processor for the first task.
[0009] Secondly, embodiments of this application provide a graphics processor simulation device, comprising:
[0010] A creation module is used to create a process group corresponding to the graphics processor based on the physical components of the graphics processor, wherein the process group includes the process corresponding to the physical components;
[0011] A configuration module is used to configure the communication mechanism between different processes in the process group according to the communication mechanism between the physical components of the graphics processor.
[0012] The driver module is used to drive the process group to communicate and run according to the communication mechanism and the processing logic of the physical component for the first task, so as to simulate the execution process of the graphics processor for the first task.
[0013] Thirdly, embodiments of this application provide an electronic device, a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the computer program, when executed by the processor, implements the steps of the graphics processor simulation method as provided in the first aspect.
[0014] Fourthly, embodiments of this application provide a computer-readable storage medium that, when instructions in the storage medium are executed by a processor of an electronic device, enables the electronic device to perform the steps of the graphics processor emulation method provided in the first aspect.
[0015] Fifthly, embodiments of this application provide a computer program product, the computer program product including a non-transitory computer-readable storage medium storing a computer program operable to cause a computer to perform steps of the graphics processor simulation method provided in the first aspect.
[0016] The above-described technical solutions adopted in the embodiments of this application can achieve the following beneficial effects:
[0017] Different processes are used to simulate different physical components within a graphics processing unit (GPU). Inter-process communication (IPC) mechanisms, such as shared memory, message queues, and socket communication, are used to simulate the hardware connections between these physical components. Based on this, and according to the IPC mechanisms and the processing logic of each physical component for a specific task, the created processes are driven to communicate and run, simulating the GPU's execution of that task. Thus, the created processes, inter-process communication, and process execution constitute a GPU simulation platform. This platform can be flexibly adjusted according to the GPU's hardware architecture, exhibiting high scalability and flexibility, and significantly improving the development efficiency of GPU-related software. For mature hardware architectures, open-source simulation software or previously developed simulation software modules can be used directly. When it is necessary to enhance the GPU's physical components, this can be achieved simply by increasing the number of processes. By monitoring inter-process communication, the coordination and connections between physical components can be easily debugged, improving the efficiency of problem localization. Attached Figure Description
[0018] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:
[0019] Figure 1This is a schematic diagram of an example environment in which embodiments of this application can be implemented;
[0020] Figure 2 A schematic flowchart illustrating a graphics processor simulation method provided in an embodiment of this application;
[0021] Figure 3 This is a schematic diagram of the architecture of a graphics processor;
[0022] Figure 4 A schematic diagram of a process group corresponding to a graphics processor;
[0023] Figure 5 This is a schematic diagram of the architecture of a multi-graphics processor environment;
[0024] Figure 6 This is a schematic diagram of a process group corresponding to a multi-graphics processor environment.
[0025] Figure 7 A schematic diagram of the structure of a graphics processor simulation device provided in an embodiment of this application;
[0026] Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation
[0027] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0028] The term "comprising" and its variations as used in this document are open-ended, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the following description. The term "in response to" indicates that the performed operation depends on a condition or state. When the dependent condition or state is met, one or more operations may be performed in real time or with a set delay. Unless otherwise specified, there is no restriction on the order in which multiple operations are performed.
[0029] It should be noted that the concepts of "first" and "second" mentioned in this document are used only to distinguish different devices, modules or units, and are not used to restrict the order of functions performed by these devices, modules or units or their interdependencies.
[0030] It should be noted that the terms "one" and "more" used in this document are illustrative rather than restrictive, and those skilled in the art should understand that, unless explicitly stated otherwise in the context, they should be understood as "one or more".
[0031] The names of messages or information exchanged between multiple devices in this document are for illustrative purposes only and are not intended to limit the scope of such messages or information.
[0032] As mentioned earlier, current simulation platforms are typically designed specifically for GPUs, making them difficult to extend and reuse, resulting in a large workload for development and maintenance, and low development efficiency.
[0033] In view of this, embodiments of this application provide a method for simulating a graphics processing unit (GPU). Different processes are used to simulate different physical components within the GPU, and inter-process communication mechanisms, such as shared memory, message queues, and socket communication, are used to simulate the hardware connections between these different physical components. Based on this, according to the inter-process communication mechanisms and the processing logic of the physical components for a specific task, the created processes are driven to communicate and run, thereby simulating the GPU's execution process for that task. Thus, the created processes, inter-process communication, and process execution constitute a GPU simulation platform, which can be flexibly adjusted according to the GPU's hardware architecture, exhibiting high scalability and flexibility, and greatly improving the development efficiency of related GPU software (such as firmware, drivers, compilers, runtime, operator libraries, etc.).
[0034] The graphics processor simulation method provided in this application embodiment can be executed by an electronic device. The electronic device referred to herein may include terminals, such as, but not limited to, mobile phones, tablets, laptops, desktop computers, smart voice interaction devices, smart home appliances, smart wearable devices, vehicle terminals, aircraft, etc.; or, the electronic device may also include a server, such as a standalone physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing cloud computing services.
[0035] The technical solutions provided by the various embodiments of this application are described in detail below with reference to the accompanying drawings.
[0036] Figure 1 A schematic diagram of an example environment in which embodiments of this application can be implemented is shown. This example environment includes a terminal device 100 and a server 200.
[0037] The terminal device 100 and the server 200 establish a communication connection, which may include, but is not limited to, at least one of the following: wired connection and wireless connection.
[0038] Terminal device 100 includes, but is not limited to, smartphones, tablets, laptops, desktop computers, smart voice interaction devices, smart home appliances, smartwatches, vehicle terminals, and aircraft. Server 200 can be a standalone physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing cloud computing services.
[0039] Terminal device 100 can receive relevant parameters input by the user and send these parameters to server 200. Server 200 can obtain the processing result based on the received parameters and return the processing result to terminal device 100.
[0040] It should be understood that in some embodiments, the terminal device 100 may also obtain the processing result by itself based on relevant parameters input by the user (such as a certain task, the data required to execute the task, etc.) without interacting with the server 200. This application embodiment does not limit this.
[0041] Based on the example environment described above, this application provides a method for simulating a graphics processor. Please refer to... Figure 2 This is a flowchart illustrating a graphics processor simulation method provided in an embodiment of this application. The method includes the following steps:
[0042] S202, based on the physical components of the graphics processor, creates the process group corresponding to the graphics processor.
[0043] Physical components refer to the tangible, touchable, and physically existential basic units or parts that constitute a graphics processor. They are also the basic building blocks of a hardware system, possessing a definite physical form, size, material, and physical characteristics, and can achieve specific physical or functional effects independently or in conjunction with other components.
[0044] Process groups consist of processes corresponding to physical components. Process groups can simulate the physical components of a graphics processor. For example, Figure 3 A schematic diagram of a graphics processing unit (GPU) architecture is shown, which includes a memory controller, a command processor, and a computing unit. In this case, as... Figure 4 As shown, a process group can include a first process, a second process, and a third process. The first process corresponds to the video memory controller, the second process corresponds to the command controller, and the third process corresponds to the computing unit.
[0045] It is worth noting that a graphics processing unit (GPU) can include multiple computing units. Figure 3This illustration uses only one computational unit. Correspondingly, there are multiple third processes, with each computational unit having a corresponding third process. Figure 4 This is illustrated using only one third process.
[0046] Optionally, such as Figure 3 As shown, a graphics processing unit (GPU) is typically connected to a host computer, and there is usually frequent data interaction between them. The host computer can include a central processing unit (CPU), etc. To accurately simulate this process, the above-mentioned GPU simulation method can also include creating a fourth process corresponding to the host computer. For example, Figure 4 The process also includes a fourth process, which communicates with the first process to simulate data interaction between the graphics processor and the host.
[0047] Optionally, given the frequent data interaction between different graphics processors in a multi-GPU environment, to accurately simulate this process, the graphics processors may include a first graphics processor and a second graphics processor, each with a corresponding process group. For example, Figure 5 A schematic diagram of the architecture of a multi-graphics processor environment is shown, which includes graphics processor 1 and graphics processor 2, both of which are connected to the host. Figure 6 A schematic diagram of the process group corresponding to this environment is shown, such as... Figure 6 As shown, process group 1 corresponds to graphics processor 1, which includes first process 1, second process 1 and third process 1; process group 2 corresponds to graphics processor 2, which includes first process 2, second process 2 and third process 2. Both first process 1 and first process 2 can communicate with the fourth process.
[0048] S204, configures the communication mechanism between different processes in the process group according to the communication mechanism between the physical components of the graphics processor.
[0049] Inter-process communication mechanisms can simulate the communication mechanisms between the physical components corresponding to a process. Inter-process communication mechanisms can include, but are not limited to, at least one of the following: shared memory, message queues, socket communication, etc.
[0050] Specifically, S204 may include: in response to the communication mechanism between the first physical component and the second physical component being bus-based communication, configuring the communication mechanism between the process corresponding to the first physical component and the process corresponding to the second physical component as socket-based communication; and / or, in response to the communication mechanism between the first physical component and the second physical component being interrupt-based communication or mailbox-based communication, configuring the communication mechanism between the process corresponding to the first physical component and the process corresponding to the second physical component as message queue-based communication. Wherein, the first physical component and the second physical component are any two different physical components.
[0051] Understandably, communication between the physical components inside and outside a graphics processing unit (GPU) is typically based on a bus, or between the physical components of different GPUs. For example, the memory controller inside a GPU typically communicates with the host machine (such as the CPU) via the PCIe bus, and the command processor of one GPU typically communicates with the computing unit of another GPU via the NVLink bus. This is a cross-host communication method. Socket communication inherently possesses cross-process and cross-host characteristics. Furthermore, when using sockets, the system kernel's network protocol stack automatically handles packet encapsulation, addressing, routing, reliable transmission, or low-latency transmission. This is completely consistent with the protocol layer functionality required for bus communication. Therefore, socket communication can accurately simulate the bus-based communication mechanism between different physical components.
[0052] For example, with Figure 3 Taking the hardware architecture shown as an example, the memory controller communicates with the host via the PCIe bus, and the command controller also communicates with the host via the PCIe bus. Therefore, in Figure 4 In the process shown, the communication mechanism between the fourth process and the first process includes socket-based communication; the communication mechanism between the fourth process and the second process also includes socket-based communication.
[0053] In a multi-GPU environment, the communication mechanism between the third process in the first process group and the second process in the second process group includes socket-based communication; and / or, the communication mechanism between the second process in the first process group and the third process in the second process group also includes socket-based communication. Here, the first process group is the process group corresponding to the first GPU, and the second process group is the process group corresponding to the second GPU. Thus, the inter-process communication mechanism simulates chip-to-chip (C2C) communication between multiple GPUs.
[0054] For example, with Figure 5Taking the hardware architecture shown as an example, command processor 1 communicates with computing unit 2 via the NVLink bus, and command processor 2 communicates with computing unit 1 via the NVLink bus. Therefore, in Figure 6 In the process shown, the second process 1 and the third process 2 communicate with each other via sockets, and the second process 2 and the third process 1 communicate with each other via sockets.
[0055] Interrupt communication mechanisms are typically based on asynchronous event notifications, characterized by being asynchronous, immediate, and involving low data volumes. Message queues, on the other hand, can be configured in "notification mode," allowing a process to send a message to a message queue and another process to read the message from it, perfectly simulating the "asynchronous notification" characteristic of interrupts.
[0056] The mailbox mechanism typically involves one physical component writing data or commands to the mailbox, while another physical component reads data or commands from the mailbox, characterized by synchronous or semi-synchronous operation. A message queue can be viewed as a "mailbox," where the sending process writes messages (such as commands or data) to the message queue, and the receiving process reads messages from the message queue. This directly replicates the "write-read" model of a mailbox, thus simulating the mailbox communication mechanism between different physical components.
[0057] For example, with Figure 3 Taking the hardware architecture shown as an example, the command processor and the computing unit use an interrupt communication mechanism. Therefore, in Figure 4 In the process group shown, the communication mechanism between the second and third processes includes message queue-based communication.
[0058] S206, based on the communication mechanism and the processing logic of the physical components for the first task, drive the process group to communicate and run in order to simulate the execution process of the graphics processor for the first task.
[0059] The first task can be any task to be simulated. The data required to process the first task is called the first data. Both the first task and the first data can be set according to the simulation purpose (such as firmware development, driver development, runtime development, compiler development, operator library development, etc.), and this application embodiment does not limit this. For example, in the artificial intelligence (AI) scenario, the first task is a general matrix multiplication A×B, and the first data includes the input matrix A and the model's weight matrix B. As another example, the first task is a neural network forward propagation computation task, and the first data includes the training dataset, pre-trained model parameters, etc.
[0060] In one implementation, S206 may include: S2062, determining the interaction logic between different processes in the process group according to the processing logic; and S2064, driving the process group to communicate and run according to the interaction logic and communication mechanism.
[0061] Inter-process interaction logic reflects who sends messages first, who receives messages later, and who reads and writes memory, etc., which can replicate the processing pipeline and communication mechanism of the graphics processor. Based on the interaction logic and communication mechanism, the process group is driven to communicate and run, realizing the mechanism of "processing logic defines interaction and interaction drives communication". This achieves the precision and automation of process group communication, thereby accurately mapping the task execution behavior of the graphics processor to the process group, and realizing the accurate simulation of the graphics processor's execution process of the first task.
[0062] Combination Figure 4 The process group shown includes a first process, a second process, and a third process. Given that the first process corresponds to the video memory controller, the second process corresponds to the command processor, and the third process corresponds to the computing unit, the above-mentioned S2064 may include: driving the first process to create shared memory corresponding to the graphics processor; writing the first data required to execute the first task into the shared memory; driving the second process to allocate the first task to the third process; driving the third process to read the first data from the shared memory, execute the first task according to the first data, and write the execution result into the shared memory.
[0063] Specifically, after the first process creates shared memory, it can initialize a "memory allocation table" and place it at the beginning of the shared memory. Other processes can then map the shared memory into their own virtual address spaces, thus gaining access to it. Since, at the hardware level, the storage units of a graphics processor (such as video memory and multi-level cache) can be shared by multiple physical components, the created shared memory can effectively simulate these storage units, and process access to shared memory can simulate physical component access to these storage units. Processes can directly read and write to shared memory via pointers, without kernel intervention, which is fast, just as physical components access storage units via physical addresses, effectively simulating the "direct addressing" of storage units by physical components. Furthermore, when the first process that created the shared memory exits or the system restarts, the shared memory is released, and the data is lost, which effectively simulates the volatility of storage units.
[0064] After the first process creates shared memory, data can be written to the shared memory in various ways. In one scenario, the first process can write the first data to the sharing process.
[0065] In another scenario, if a fourth process corresponding to the host is also created, the fourth process is driven to write the first data into shared memory. Accordingly, before determining that the second process will assign the first task to the fourth process, the fourth process is also driven to send a first command to the second process, the first command including the first task.
[0066] For example, taking the first task as matrix multiplication C=A×B, the fourth process sends a message to the first process via a socket, requesting the first process to allocate three regions of shared memory to store the input matrix A, the weight matrix B, and the output matrix C. The first process marks these three regions as occupied in the shared memory allocation table and returns their addresses. The fourth process then copies the input matrix A and the weight matrix B into the corresponding addresses in the shared memory through memory copying.
[0067] The fourth process sends a first command to the second process based on the socket. The first command includes the first task, the storage address of the input matrix A, and the storage address of the weight matrix B.
[0068] As can be seen, this scenario can simulate the process of the host computer sending tasks and data to the graphics processor.
[0069] In S2064 above, the process of driving the second process to assign the first task to the third process can be achieved in various ways.
[0070] In one scenario, driving the second process to assign the first task to the third process may include: driving the second process to create a message queue and sending a first message to the message queue, wherein the first message contains the storage address of the first task and first data in shared memory. Correspondingly, driving the third process to read the first data from shared memory, execute the first task based on the first data, and write the execution result back to shared memory may include: driving the third process to retrieve the first message from the message queue, reading the first data from shared memory based on the storage address in the first message, and executing the first task in the first message based on the first data.
[0071] Understandably, the second process corresponds to the command processor, and the third process corresponds to the computing unit. In actual hardware architectures, the command processor and the computing unit typically use an interrupt communication mechanism, which is characterized by asynchronous, instantaneous, and low-data-volume communication. In the above approach, the second process sends messages to the message queue, and the third process reads messages from the message queue. This accurately simulates the "asynchronous notification" characteristic of interrupts, thereby better simulating the data interaction process between the command processor and the computing unit under the interrupt communication mechanism.
[0072] In another scenario, there are multiple computing units and multiple third processes, with each computing unit having a corresponding third process. Accordingly, driving the second process to assign the first task to the third process may include: driving the second process to split the first task into multiple subtasks, determining the third process corresponding to each subtask, and assigning the multiple subtasks to the corresponding third processes.
[0073] More specifically, when driving the second process to assign multiple subtasks to corresponding third processes, the second process can create multiple message queues, each corresponding to a subtask. The third process corresponding to a subtask reads messages from the message queue corresponding to that subtask and executes the subtask within the read message.
[0074] For example, the first task includes the matrix multiplication operation C = A × B, which can be achieved by splitting matrix A into four submatrices, denoted as . Matrix B is also split into 4 submatrices, denoted as . Therefore, the first task can be broken down into the following sub-tasks: , , as well as These are the four multiplication and addition operations.
[0075] For example, the first task is the forward propagation computation task of the neural network, which can be broken down into multiple sub-tasks such as the computation of different convolution kernels in the convolutional layer and the matrix block operation in the fully connected layer.
[0076] As can be seen, by driving the second process to split the first task into multiple subtasks and then assigning them to different third processes for execution, the parallel computing process of multiple computing units in a graphics processor can be simulated.
[0077] In S2064 above, when the graphics processor includes a first graphics processor and a second graphics processor, before driving the third process to execute the first task based on the first data and writing the execution result to shared memory, the method may further include: driving the third process in the first process group to send an acquisition request to the second process in the second process group, the acquisition request being used to request the acquisition of second data, the second data being stored in the shared memory corresponding to the second graphics processor; driving the second process in the second process group to read the second data from the shared memory corresponding to the second graphics processor; and returning the second data to the third process in the first process group. Here, the first process group is the process group corresponding to the first graphics processor, and the second process group is the process group corresponding to the second graphics processor.
[0078] Accordingly, the above-mentioned driving the third process to execute the first task based on the first data and write the execution result to the shared memory may include: driving the third process to execute the first task based on the first data and the second data, and writing the execution result to the shared memory corresponding to the first graphics processor.
[0079] For example, with Figure 5 Taking the multi-GPU environment shown as an example, GPU 1 and GPU 2 work together to complete a task. When executing the task, computing unit 1 usually needs to obtain corresponding data (i.e., second data) from GPU 2 in addition to the first data. The second data is usually stored in storage unit 2. Since the storage units of the GPUs are independent, computing unit 1 cannot directly access storage unit 2, but it can access task processor 2 through NVLink.
[0080] Based on this, Figure 6 In the process group shown, before executing the first task, the third process 1, in addition to reading the first data from shared memory 1, also sends a request to the second process 2 via a socket to request the second data. The second process 2 accesses shared memory 2, reads the second data from it, and returns it to the third process 1 via a socket. The third process 1 can then use the first and second data to execute the first task and write the processing result back to shared memory 1.
[0081] As can be seen, the above method can accurately simulate the C2C communication and collaborative task completion process between different graphics processors in a multi-graphics processor environment.
[0082] The foregoing illustrates a partial implementation of S206. It should be understood that S206 can also be implemented in other ways, and this application embodiment does not limit this.
[0083] The graphics processing unit (GPU) simulation method provided in this application uses different processes to simulate different physical components within the GPU. Inter-process communication (IPC) mechanisms, such as shared memory, message queues, and socket communication, are used to simulate the hardware connections between these physical components. Based on this, the created processes are driven to communicate and run according to the IPC mechanisms and the processing logic of the physical components for a specific task, thus simulating the GPU's execution process for that task. Therefore, the created processes, inter-process communication, and process execution constitute a GPU simulation platform. This platform can be flexibly adjusted according to the GPU's hardware architecture, exhibiting high scalability and flexibility, and significantly improving the development efficiency of GPU-related software (such as firmware, drivers, compilers, runtime, operator libraries, etc.). For mature hardware architectures, open-source simulation software or previously developed simulation software modules can be used directly. When it is necessary to enhance the GPU's physical components, this can be achieved simply by increasing the number of processes.
[0084] Furthermore, by monitoring inter-process communication, the coordination and connection between physical components can be easily debugged, improving the efficiency of problem localization. For example, by analyzing data stored in shared memory, the processing accuracy of physical components can be analyzed, pinpointing which physical component is experiencing accuracy issues at which stage. Alternatively, analyzing inter-process communication data can pinpoint problems with the communication mechanisms between physical components, and so on.
[0085] The foregoing has described specific embodiments of this specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are possible or may be advantageous.
[0086] Based on the same inventive concept, embodiments of this application also provide a graphics processor simulation device. Please refer to... Figure 7 This is a schematic diagram of the structure of a graphics processor simulation device 700 provided in an embodiment of this application. The device 700 includes:
[0087] The creation module 710 is used to create a process group corresponding to the graphics processor based on the physical components of the graphics processor, wherein the process group includes the process corresponding to the physical components.
[0088] The configuration module 720 is used to configure the communication mechanism between different processes in the process group according to the communication mechanism between the physical components of the graphics processor.
[0089] The driver module 730 is used to drive the process group to communicate and run according to the communication mechanism and the processing logic of the physical component for the first task, so as to simulate the execution process of the graphics processor for the first task.
[0090] In other embodiments, the configuration module is used to:
[0091] In response to the communication mechanism between the first physical component and the second physical component being bus-based, the communication mechanism between the process corresponding to the first physical component and the process corresponding to the second physical component is configured to be socket-based; and / or,
[0092] In response to the communication mechanism between the first physical component and the second physical component being an interrupt communication mechanism or a mailbox mechanism, the communication mechanism between the process corresponding to the first physical component and the process corresponding to the second physical component is configured to be message queue-based communication.
[0093] Wherein, the first physical component and the second physical component are any two different physical components.
[0094] In other embodiments, the driver module is used for:
[0095] Based on the processing logic, determine the interaction logic between different processes in the process group;
[0096] Based on the interaction logic and the communication mechanism, the process group is driven to communicate and run.
[0097] In other embodiments, the process group includes a first process, a second process, and a third process, wherein the first process corresponds to the video memory controller of the graphics processor, the second process corresponds to the command processor of the graphics processor, and the third process corresponds to the computing unit of the graphics processor.
[0098] The driver module drives the process group to communicate and run in the following manner:
[0099] The first process is driven to create shared memory corresponding to the graphics processor.
[0100] Write the first data required to perform the first task into the shared memory;
[0101] The second process is driven to assign the first task to the third process;
[0102] The third process is driven to read the first data from the shared memory, execute the first task based on the first data, and write the execution result into the shared memory.
[0103] In other embodiments, there are multiple computing units and multiple third processes, with each computing unit having a corresponding third process;
[0104] The process of driving the second process to assign the first task to the third process includes:
[0105] The second process is driven to split the first task into multiple sub-tasks, determine the third process corresponding to each sub-task, and assign the multiple sub-tasks to the corresponding third processes.
[0106] In other embodiments, the step of driving the second process to assign the first task to the third process includes:
[0107] The second process is driven to create a message queue and send a first message to the message queue. The first message contains the storage address of the first task and the first data in the shared memory.
[0108] The process of driving the third process to read the first data from the shared memory, executing the first task based on the first data, and writing the execution result back to the shared memory includes:
[0109] The third process is driven to retrieve the first message from the message queue, read the first data from the shared memory according to the storage address in the first message, and execute the first task in the first message according to the first data.
[0110] In other embodiments, the creation module is also used to create a fourth process corresponding to the host.
[0111] The driver module writes the first data required to execute the first task into the shared memory in the following manner: it drives the fourth process to write the first data into the shared memory.
[0112] The driver module is further configured to drive the fourth process to send a first command to the second process before the second process assigns the first task to the fourth process, the first command containing the first task.
[0113] In other embodiments, the communication mechanism between the fourth process and the first process includes socket-based communication; and / or,
[0114] The communication mechanism between the fourth process and the second process includes socket-based communication.
[0115] In other embodiments, the graphics processor includes a first graphics processor and a second graphics processor;
[0116] The driver module is further configured to, before driving the third process to execute the first task based on the first data and write the execution result to the shared memory, drive the third process in the first process group to send an acquisition request to the second process in the second process group. The acquisition request is used to request the acquisition of second data, which is stored in the shared memory corresponding to the second graphics processor. The first process group is the process group corresponding to the first graphics processor, and the second process group is the process group corresponding to the second graphics processor.
[0117] The second process in the second process group is driven to read the second data from the shared memory corresponding to the second graphics processor, and to return the second data to the third process in the first process group;
[0118] The driver module drives the third process to execute the first task based on the first data, and writes the execution result into the shared memory, including:
[0119] The third process is driven to execute the first task based on the first data and the second data, and the execution result is written to the shared memory corresponding to the first graphics processor.
[0120] In other embodiments, the communication mechanism between the third process in the first process group and the second process in the second process group includes socket-based communication; and / or,
[0121] The communication mechanism between the second process in the first process group and the third process in the second process group includes socket-based communication.
[0122] Obviously, the graphics processor simulation device 700 provided in this application embodiment can be used as the above-mentioned... Figure 2 The execution body of the graphics processor simulation method shown is therefore able to implement the above-mentioned graphics processor simulation method in... Figure 2 The functions implemented are the same, so they will not be explained again here.
[0123] Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Please refer to it. Figure 8 At the hardware level, the electronic device includes a processor, and optionally also includes an internal bus, a network interface, and memory. The memory may include main memory, such as high-speed random-access memory (RAM), or non-volatile memory, such as at least one disk drive. Of course, the electronic device may also include other hardware required for other business operations.
[0124] The processor, network interface, and memory can be interconnected via an internal bus, which can be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus, or an EISA (Extended Industry Standard Architecture) bus, etc. This bus can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 8 The symbol is represented by a single double-headed arrow, but this does not mean that there is only one bus or one type of bus.
[0125] Memory is used to store programs. Specifically, programs may include program code, which includes computer operation instructions. Memory may include main memory and non-volatile memory, and provides instructions and data to the processor.
[0126] The processor reads the corresponding computer program from non-volatile memory into main memory and then executes it, forming a graphics processing unit (GPU) emulation at the logical level. The processor executes the program stored in memory and specifically performs the following operations:
[0127] Based on the physical components of the graphics processor, a process group corresponding to the graphics processor is created, and the process group includes the process corresponding to the physical component;
[0128] Configure the communication mechanism between different processes in the process group according to the communication mechanism between the physical components of the graphics processor;
[0129] Based on the communication mechanism and the processing logic of the physical components for the first task, the process group is driven to communicate and run in order to simulate the execution process of the graphics processor for the first task.
[0130] The above is as stated in this application. Figure 2 The methods executed by the analog device of the graphics processor disclosed in the illustrated embodiments can be applied to a processor or implemented by a processor. The processor may be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method can be completed by integrated logic circuits in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The methods, steps, and logic block diagrams disclosed in the embodiments of this application can be implemented or executed. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software module can reside in a mature storage medium in the field, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or registers. This storage medium is located in memory, and the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method.
[0131] The electronic device can also perform Figure 2The method, and implement the emulation device of the graphics processor in Figure 2 The functions of the embodiments shown are not described in detail here.
[0132] Of course, in addition to software implementation, the electronic device of this application does not exclude other implementation methods, such as logic devices or a combination of hardware and software, etc. In other words, the execution subject of the following processing flow is not limited to each logic unit, but can also be hardware or logic devices.
[0133] This application also proposes a computer-readable storage medium that stores one or more programs, the programs including instructions that, when executed by an electronic device including multiple applications, enable the electronic device to perform... Figure 2 The method of the illustrated embodiment is specifically used to perform the following operations:
[0134] Based on the physical components of the graphics processor, a process group corresponding to the graphics processor is created, and the process group includes the process corresponding to the physical component;
[0135] Configure the communication mechanism between different processes in the process group according to the communication mechanism between the physical components of the graphics processor;
[0136] Based on the communication mechanism and the processing logic of the physical components for the first task, the process group is driven to communicate and run in order to simulate the execution process of the graphics processor for the first task.
[0137] This application also provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program operable to cause a computer to perform the steps of the graphics processor simulation method provided in this application.
[0138] In summary, the above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.
[0139] The systems, devices, modules, or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, a computer can be, for example, a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email device, game console, tablet computer, wearable device, or any combination of these devices.
[0140] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.
[0141] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0142] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.
Claims
1. A method of simulating a graphics processor, characterized by, include: Based on the physical components of the graphics processor, a process group corresponding to the graphics processor is created, and the process group includes the process corresponding to the physical component; Configure the communication mechanism between different processes in the process group according to the communication mechanism between the physical components of the graphics processor; Based on the processing logic of the physical component for the first task, the interaction logic between different processes in the process group is determined, and based on the interaction logic and the communication mechanism, the process group is driven to communicate and run in order to simulate the execution process of the graphics processor for the first task. The process group includes a first process, a second process, and a third process. The first process corresponds to the graphics memory controller of the graphics processor, the second process corresponds to the command processor of the graphics processor, and the third process corresponds to the computing unit of the graphics processor. The process group is driven to communicate and run in the following manner: The first process is driven to create shared memory corresponding to the graphics processor. Write the first data required to perform the first task into the shared memory; The second process is driven to assign the first task to the third process; The third process is driven to read the first data from the shared memory, execute the first task based on the first data, and write the execution result into the shared memory.
2. The method of claim 1, wherein, The step of configuring the communication mechanism between different processes in the process group according to the communication mechanism between the physical components of the graphics processor includes: In response to the communication mechanism between the first physical component and the second physical component being bus-based, the communication mechanism between the process corresponding to the first physical component and the process corresponding to the second physical component is configured to be socket-based; and / or, In response to the communication mechanism between the first physical component and the second physical component being an interrupt communication mechanism or a mailbox mechanism, the communication mechanism between the process corresponding to the first physical component and the process corresponding to the second physical component is configured to be message queue-based communication. Wherein, the first physical component and the second physical component are any two different physical components.
3. The method of claim 1, wherein, The number of computing units is multiple, the number of third processes is multiple, and each computing unit has a corresponding third process; The process of driving the second process to assign the first task to the third process includes: The second process is driven to split the first task into multiple sub-tasks, determine the third process corresponding to each sub-task, and assign the multiple sub-tasks to the corresponding third processes.
4. The method of claim 1, wherein, The process of driving the second process to assign the first task to the third process includes: The second process is driven to create a message queue and send a first message to the message queue. The first message contains the storage address of the first task and the first data in the shared memory. The process of driving the third process to read the first data from the shared memory, executing the first task based on the first data, and writing the execution result back to the shared memory includes: The third process is driven to retrieve the first message from the message queue, read the first data from the shared memory according to the storage address in the first message, and execute the first task in the first message according to the first data.
5. The method of claim 1, wherein, Before configuring the communication mechanism between different processes in the process group according to the communication mechanism between the physical components of the graphics processor, the method further includes: Create a fourth process corresponding to the host; The step of writing the first data required to perform the first task into the shared memory includes: The fourth process is driven to write the first data into the shared memory; Before the second process assigns the first task to the fourth process, the method further includes: The fourth process is driven to send a first command to the second process, the first command containing the first task.
6. The method of claim 5, wherein, The communication mechanism between the fourth process and the first process includes socket-based communication; and / or, The communication mechanism between the fourth process and the second process includes socket-based communication.
7. The method of claim 1, wherein, The graphics processor includes a first graphics processor and a second graphics processor; Before driving the third process to execute the first task based on the first data and writing the execution result to the shared memory, the method further includes: The third process in the first process group sends an acquisition request to the second process in the second process group. The acquisition request is used to request the acquisition of second data, which is stored in the shared memory corresponding to the second graphics processor. The first process group is the process group corresponding to the first graphics processor, and the second process group is the process group corresponding to the second graphics processor. The second process in the second process group is driven to read the second data from the shared memory corresponding to the second graphics processor, and to return the second data to the third process in the first process group; The step of driving the third process to execute the first task based on the first data and writing the execution result into the shared memory includes: The third process is driven to execute the first task based on the first data and the second data, and the execution result is written to the shared memory corresponding to the first graphics processor.
8. The method of claim 7, wherein, The communication mechanism between the third process in the first process group and the second process in the second process group includes socket-based communication; and / or, The communication mechanism between the second process in the first process group and the third process in the second process group includes socket-based communication.
9. An apparatus for simulating a graphics processor, the apparatus comprising: include: A creation module is used to create a process group corresponding to the graphics processor based on the physical components of the graphics processor, wherein the process group includes the process corresponding to the physical components; A configuration module is used to configure the communication mechanism between different processes in the process group according to the communication mechanism between the physical components of the graphics processor. The driving module is used to determine the interaction logic between different processes in the process group according to the processing logic of the physical component for the first task, and to drive the process group to communicate and run according to the interaction logic and the communication mechanism, so as to simulate the execution process of the graphics processor for the first task. The process group includes a first process, a second process, and a third process. The first process corresponds to the video memory controller of the graphics processor, the second process corresponds to the command processor of the graphics processor, and the third process corresponds to the computing unit of the graphics processor. The driver module drives the process group to communicate and run in the following ways: The first process is driven to create shared memory corresponding to the graphics processor. Write the first data required to perform the first task into the shared memory; The second process is driven to assign the first task to the third process; The third process is driven to read the first data from the shared memory, execute the first task based on the first data, and write the execution result into the shared memory.
10. An electronic device, comprising: It includes a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the computer program, when executed by the processor, implements the steps of the simulation method of the graphics processor as described in any one of claims 1 to 8.
11. A computer readable storage medium, characterized in that, When the instructions in the storage medium are executed by the processor of the electronic device, the electronic device is able to perform the steps of the graphics processor simulation method as described in any one of claims 1 to 8.
12. A computer program product, characterised in that, The computer program product includes a non-transitory computer-readable storage medium storing a computer program operable to cause a computer to perform the steps of the graphics processor simulation method as described in any one of claims 1 to 8.