Processing method and device of tensor data and related equipment

Abstract

The application discloses a Tensor data processing method and device and related equipment. The method comprises the following steps: acquiring prior information of Tensor data, wherein the prior information comprises a dimension parameter and a storage address mapping rule of the Tensor data; determining each target element based on the dimension parameter of the Tensor data; converting the virtual storage address of each target element into a physical storage address by using the storage address mapping rule, wherein the physical storage addresses are continuous; storing each target element into the corresponding physical storage address; and performing a preset operation on each target element stored in the physical storage address by using a preset algorithm to obtain a processing result. Thus, the cache hit rate is improved.

Description

Technical Field

[0001] This invention relates to the field of data processing technology, and in particular to methods, apparatus and related equipment for processing Tensor data. Background Technology

[0002] In modern processor design, the gap between memory access latency and processor computing power is becoming increasingly significant. To alleviate this contradiction, multi-level caches (e.g., L1, L2, and LLC) have become standard features in mainstream processors. Caches use cache lines as the basic unit of operation (e.g., the common 128-byte cache). Their working mechanism is as follows: when the processor accesses a memory address, the hardware automatically loads the entire cache line containing that address into the cache. If the processor supports hardware prefetching, it will also preload multiple adjacent or specifically related cache lines into the cache. Thanks to the temporal and spatial locality inherent in most programs—that is, recently accessed data is likely to be accessed again within a short period, and data at adjacent memory addresses will be accessed consecutively—caches can achieve a high hit rate, effectively hiding memory access latency and ensuring efficient processor operation.

[0003] With the rapid development of artificial intelligence technology, AI processors have evolved towards multi-core architectures. Their core objective is to fully unleash the parallel computing power of multiple cores to meet the demands of large-scale AI computing tasks. In the implementation of AI operators, to adapt to the parallel characteristics of multi-core architectures and fully leverage the processor's computing potential, a tiering strategy is widely adopted: a large-scale AI computing task is broken down into numerous fine-grained subtasks, and these subtasks are allocated to different computing cores through a scheduling mechanism to achieve parallel execution, thereby improving overall computing efficiency.

[0004] The input, intermediate, and output data of AI operators typically exist in the form of multidimensional tensors. These tensors are logically ordered in multiple dimensions, but in physical memory, they are often stored in a row-major or column-major linear storage format (e.g., M*K and K*N formats in matrix operations, and NCHW and NHWC formats in image data). When performing computations using a tile strategy, each tile corresponds to a small multidimensional sub-block within the tensor. This sub-block exhibits a continuous distribution in logical space, but in physical linear memory addresses, it may have excessively large strides, segmented discrete distributions, or even multiple nested strides. In other words, the tile sub-blocks have significant discontinuity in physical storage. This discontinuity in physical storage directly violates the principle of locality upon which caching relies, leading to a significant decrease in cache hit rate. Summary of the Invention

[0005] This invention provides a method, apparatus, and related equipment for processing Tensor data to improve cache hit rate.

[0006] According to a first aspect of the present invention, a method for processing Tensor data is provided, the method comprising: Obtain prior information of the Tensor data, wherein the prior information includes the dimension parameters and storage address mapping rules of the Tensor data; Based on the dimension parameters of the Tensor data, each target element is determined; Using the storage address mapping rule, the virtual storage address of each target element is converted into a physical storage address, wherein the physical storage addresses are consecutive physical storage addresses; For any given target element, store the target element in the physical storage address corresponding to the target element; The preset algorithm is used to perform preset operations on each target element stored in each physical storage address to obtain the processing result.

[0007] According to another aspect of the present invention, a processing apparatus for Tensor data is provided, the apparatus comprising: The acquisition module is used to acquire prior information of Tensor data, wherein the prior information includes the dimension parameters and storage address mapping rules of the Tensor data; The target element determination module is used to determine each target element based on the dimension parameters of the Tensor data; The address translation module is used to convert the virtual storage address of each target element into a physical storage address using the storage address mapping rules, wherein the physical storage addresses are consecutive physical storage addresses. The storage module is used to store any target element in the physical storage address corresponding to the target element. The processing module is used to perform preset operations on each target element stored in each physical storage address using a preset algorithm to obtain the processing result.

[0008] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, which enables the at least one processor to perform the Tensor data processing method according to any embodiment of the present invention.

[0009] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions, the computer instructions being configured to cause a processor to execute and implement the Tensor data processing method according to any embodiment of the present invention.

[0010] According to another aspect of the present invention, a computer program product is also provided, including a computer program that, when executed by a processor, implements the steps of the Tensor data processing method as described in any embodiment of the present invention.

[0011] The technical solution of this invention involves obtaining prior information about Tensor data; determining target elements based on the dimension parameters of the Tensor data; converting the virtual storage addresses of each target element into consecutive physical storage addresses using storage address mapping rules; storing any target element in the corresponding physical storage address; and performing preset operations on each target element stored in the physical storage addresses using a preset algorithm to obtain the processing result. Therefore, this embodiment converts the virtual storage addresses of each target element into consecutive physical storage addresses, improving the cache hit rate.

[0012] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This is a schematic diagram of the structure of an electronic device provided according to an embodiment of the present invention; Figure 2 This is one of the flowcharts illustrating a method for processing Tensor data according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the address translation process provided in an embodiment of the present invention; Figure 4 This is a flowchart illustrating the process of determining the physical storage address of a target element according to an embodiment of the present invention; Figure 5 This is a second flowchart illustrating a method for processing Tensor data according to an embodiment of the present invention; Figure 6 This is the structure of a Tensor data processing apparatus provided according to an embodiment of the present invention. Detailed Implementation

[0015] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0016] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0017] Before introducing the Tensor data processing method provided in the embodiments of this application, for ease of understanding, the embodiments of this application will be described in detail below.

[0018] Before introducing the method for processing Tensor data in this application, the structure of the electronic device in this application will be described first. Figure 1 This is a schematic diagram of the structure of an electronic device, from Figure 1As can be seen from the embodiments of this application, the electronic device is an ATU (Address Translation Unit). This ATU can be placed as an independent hardware IP between each memory access unit IP and the cache. Alternatively, it can be integrated as a functional module into each memory access unit or cache, placed at the exit of the memory access unit or the entry of the cache. The memory access unit includes, but is not limited to, DMA, LSU (Read / Write Unit) of the computing core, high-speed interconnect port, or any other on-chip controller with memory access function.

[0019] The electronic device 100 in this embodiment includes a register group 101, an inlet packet receiving and classification unit 102, a parameter selection unit 103, an address mapping unit 104, and an outlet packet sending unit 105.

[0020] The electronic device in this application embodiment also includes several bus interfaces, including at least one Master interface and one Slave interface. Figure 1 In this context, ATU-M is the Master interface, and ATU-S is the Slave interface. ATU-S (Slave interface) interfaces with the Master interface of the preceding memory access unit and is used to intercept memory access transactions triggered by operators. ATU-M (Master interface) interfaces with the Slave interface of the following cache and is used to forward transactions after address remapping.

[0021] It should be noted that this application implements bus protocols including, but not limited to, AMBA, AXI, or custom NOC (Network on Chip) protocols. These buses typically include the following channels: Session ID, Address Channel, Data Channel, and Response Channel B. The Address Channel can be further subdivided into Address Write Channel (AW) and Address Read Channel (AR), and similarly, the Data Channel can be subdivided into Data Write Channel (DW) and Data Read Channel (DR). The Address Channel typically contains Sideband signals with attributes such as Burst, Cache, and User.

[0022] The ATU mainly performs address channel rewriting on the virtual memory addresses corresponding to each target element entering the ATU-S on the bus to obtain continuous physical memory addresses, which are then sent out by the ATU-M.

[0023] In one possible embodiment, register group 101 can have multiple groups, each corresponding to prior information of a set of Tensor data. Each register group includes: a remapping index, a Tensor register, and a Tiling register. The remapping index is used for the data path index register group. The Tensor register stores the dimensional parameters of the Tensor data (number of dimensions, length of each dimension, etc.), element bytes, and base address. The Tiling register stores the tile dimension parameters, etc.

[0024] In this embodiment, the register group is connected to the external control bus via a separate Slave port, allowing the external controller to configure the ATU.

[0025] In one possible embodiment, the ingress packet receiving and classification unit 102 is used to receive address request signals sent through the AW (write address) / AR (read address) channel, then decode and analyze these signals to extract key information contained in the request. This key information may include the memory address to be accessed, the data transfer size, the burst transfer mode, user-defined information, etc.

[0026] In one possible embodiment, the parameter selection unit 103 first extracts an index value from the key information of the AXI bus AW / AR channel, and uses this index value to look up a pre-configured "parameter register set". If the corresponding register is found (indexing successful), address mapping is performed according to the rules in the register. If the corresponding register is not found (indexing fails), address mapping is not performed. The original request is directly passed down to downstream devices (such as memory / peripherals).

[0027] In one possible embodiment, the address mapping unit 104 is used to convert the virtual storage address of each target element into consecutive physical storage addresses using the storage address mapping rules.

[0028] In one possible embodiment, the outgoing packet unit 105 is used to replace consecutive physical memory addresses into AW / AR, and then send them out from ATU-M along with channels such as ID / DR / DW / B.

[0029] The processing method for Tensor data in the embodiments of this application will be described in detail below. Figure 2 This is a flowchart illustrating a method for processing Tensor data according to an embodiment of the present invention. Figure 2 As can be seen from this, it may specifically include the following steps: S210: Obtain prior information of the Tensor data, wherein the prior information includes the dimension parameters and storage address mapping rules of the Tensor data; The prior information in this application embodiment also includes tile dimension parameters and traversal order. The dimension parameters of the Tensor data in this application embodiment may include the number of dimensions and the dimension length.

[0030] S220: Determine each target element based on the dimension parameters of the Tensor data; In this embodiment, the target element can be obtained directly based on the number of dimensions and the length of the dimensions in the Tensor data. For example, if the dimension parameter is 2*2, then the elements in the 2*2 array are determined as the target elements.

[0031] S230: Using the storage address mapping rule, the virtual storage address of each target element is converted into a physical storage address, wherein the physical storage addresses are consecutive physical storage addresses; The virtual memory address in this application embodiment includes a base address and a logical offset. The method of converting the virtual memory address to the physical memory address in this application embodiment is described below. Figure 3 This is a flowchart illustrating the address translation process, which may include the following steps: S310: For any target element, convert the logical offset of the target element into logical coordinates according to the dimension parameters of the Tensor data; In one possible embodiment, S310 can be specifically implemented as follows: traversing the dimension parameters of the Tensor data according to a preset traversal order; for any traversed dimension parameter, dividing the logical offset of the target element by the traversed dimension parameter to obtain a first integer value and a first remainder value, and determining the first integer value as the logical offset of the target element, and continuing to execute the step of traversing the dimension parameters of the Tensor data according to the preset traversal order until the traversal is completed, then determining each first remainder value obtained in each traversal as the logical coordinate of the target element.

[0032] For example, given a dimension parameter of [2, 3, 4], a logical offset of 17 for the target element, and a traversal order from high dimension to low dimension, we can obtain... 17 % 4 = 1, offset = 17 / / 4 = 4; 4%3=1, offset=4 / / 3=1; 1%2=1, offset=1 / / 2=0. Therefore, the logical coordinates of the target element are ( , , ), which is (1,1,1).

[0033] S320: Using the tile dimension parameter and the logical coordinates of the target element, obtain the tile index coordinates of the target element and the tile coordinates of the target element, wherein the tile coordinates are used to characterize the offset of the target element within the tile; In one possible embodiment, S330 can be specifically implemented as follows: dividing the logical coordinates of the target element by each dimension parameter in the tile dimension parameters to obtain each second integer value and each second remainder value; determining each second integer value as the tile index coordinates of the target element, and determining each second remainder value as the tile in-tile coordinates of the target element. The tile index coordinates can be obtained using formula (1): ...(1); in, For tile index coordinates, The logical coordinates of the target element. represents the dimension length in each dimension parameter, and [ ] represents integer division.

[0034] The coordinates within the tile can be obtained using formula (2): ...(2); in, The coordinates are within the tile.

[0035] S330: Linearize the tile index coordinates according to a preset traversal order to obtain tile linear index coordinates, and linearize the tile internal coordinates according to the traversal order to obtain tile linear internal coordinates; The preset traversal order in this embodiment is from high dimension to low dimension. The tile linear index coordinates can be obtained using formula (3): ... (3); in, For tile linear index coordinates, ~ For tile index coordinates, ~ These represent the corresponding number of tiles. , k=1~D-1. The dimension length in the dimension parameter of the Tensor data.

[0036] The linear inner coordinates of the tile can be determined using formula (4): ... (4); Wherein, intra represents the linear interior coordinates of the tile. The coordinates are within the tile. This refers to the dimension length in each dimension parameter.

[0037] S340: Obtain the physical storage address of the target element based on the linear index coordinates of the tile and the linear internal coordinates of the tile.

[0038] The following describes how the physical storage address of the target element is determined in the embodiments of this application. Figure 4 A flowchart illustrating the process of determining the physical storage address of a target element may include the following steps: S410: Multiply the tile linear index coordinates and the target parameter to obtain the first intermediate address; wherein, the target parameter is obtained by multiplying the intermediate parameter by the byte length of the target element, and the target parameter is obtained by multiplying each dimension parameter in the tile dimension parameters respectively; wherein, the target parameter can be obtained by formula (5): ... (5); in, For the target parameter, The length in bytes of the target element.

[0039] S420: Multiply the linear inner coordinates of the tile by the byte length of the target element to obtain the second intermediate address; S430: Add the base address, the first intermediate address, and the second intermediate address to obtain the physical storage address of the target element. The physical storage address of the target element can be obtained using formula (6): ... (6); in, The physical storage address of the target element. This is the base address of the target element.

[0040] S240: For any target element, store the target element in the physical storage address corresponding to the target element; S250: Use a preset algorithm to perform preset operations on each target element stored in each physical storage address to obtain the processing result.

[0041] The embodiments of this application do not limit the preset algorithm. The preset algorithm in the embodiments of this application can be set according to the specific actual situation.

[0042] The following describes the method for processing Tensor data in the embodiments of this application. Figure 5 This is a flowchart illustrating a method for processing Tensor data, which may include the following steps: S510: Obtain prior information of the Tensor data, wherein the prior information includes the dimension parameters and storage address mapping rules of the Tensor data; The prior information also includes a tile dimension parameter, which is used to characterize the dimension of any tile in the Tensor; S520: Determine each target element based on the dimension parameters of the Tensor data; S530: For any target element, convert the logical offset in the virtual storage address of the target element into logical coordinates according to the dimension parameters of the Tensor data; S540: Using the tile dimension parameter and the logical coordinates of the target element, obtain the tile index coordinates and the tile coordinates of the target element, wherein the tile coordinates are used to characterize the offset of the target element within the tile; S550: Linearize the tile index coordinates according to a preset traversal order to obtain tile linear index coordinates, and linearize the tile internal coordinates according to the traversal order to obtain tile linear internal coordinates; S560: Obtain the physical storage address of the target element based on the tile's linear index coordinates and the tile's linear internal coordinates; S570: For any target element, store the target element in the physical storage address corresponding to the target element; S580: Utilize a preset algorithm to perform preset operations on each target element stored in each physical storage address to obtain the processing result.

[0043] Based on the same inventive concept, this application also provides a Tensor data processing apparatus. Figure 6 This is a schematic diagram of the structure of the device for processing this Tensor data. Figure 6 As shown, the device 600 includes: The acquisition module 610 is used to acquire prior information of Tensor data, wherein the prior information includes the dimension parameters and storage address mapping rules of the Tensor data; The target element determination module 620 is used to determine each target element based on the dimension parameters of the Tensor data; Address translation module 630 is used to convert the virtual storage address of each target element into a physical storage address using the storage address mapping rule, wherein the physical storage addresses are consecutive physical storage addresses. Storage module 640 is used to store any target element in a physical storage address corresponding to the target element. The processing module 650 is used to perform preset operations on each target element stored in each physical storage address using a preset algorithm to obtain the processing result.

[0044] In one possible embodiment, the virtual memory address includes a base address and a logical offset; the prior information also includes a tile dimension parameter, which is used to characterize the dimension of any tile in the Tensor; The address translation module 630 is specifically used for: For any target element, the logical offset of the target element is converted into logical coordinates based on the dimension parameters of the Tensor data; Using the tile dimension parameter and the logical coordinates of the target element, the tile index coordinates and the tile coordinates of the target element are obtained, wherein the tile coordinates are used to characterize the offset of the target element within the tile. The tile index coordinates are linearized according to a preset traversal order to obtain tile linear index coordinates, and the tile internal coordinates are linearized according to the traversal order to obtain tile linear internal coordinates. The physical storage address of the target element is obtained based on the linear index coordinates of the tile and the linear internal coordinates of the tile.

[0045] In one possible embodiment, the address translation module 630 is further configured to: The dimension parameters of the Tensor data are traversed according to a preset traversal order; For any traversed dimension parameter, the logical offset of the target element is divided by the traversed dimension parameter to obtain a first integer value and a first remainder value. The first integer value is then determined as the logical offset of the target element. The step of traversing the dimension parameters of the Tensor data according to a preset traversal order continues until the traversal ends. Then, each first remainder value obtained in each traversal is determined as the logical coordinate of the target element.

[0046] In one possible embodiment, the address translation module 630 is further configured to: Divide the logical coordinates of the target element by each of the dimension parameters in the tile dimension parameters to obtain each second integer value and each second remainder value; The second integer values ​​are determined as the tile index coordinates of the target element, and the second remainder values ​​are determined as the tile coordinates of the target element.

[0047] In one possible embodiment, the address translation module 630 is further configured to: The first intermediate address is obtained by multiplying the tile linear index coordinates and the target parameter; wherein the target parameter is obtained by multiplying the intermediate parameter by the byte length of the target element, and the target parameter is obtained by multiplying each dimension parameter in the tile dimension parameters respectively; The second intermediate address is obtained by multiplying the linear inner coordinates of the tile by the byte length of the target element; The physical storage address of the target element is obtained by adding the base address, the first intermediate address, and the second intermediate address together.

[0048] The Tensor data processing apparatus provided in the embodiments of the present invention can execute the Tensor data processing method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of executing the method.

[0049] The collection, storage, use, processing, transmission, provision, and disclosure of user personal information involved in the technical solution disclosed herein comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0050] In some embodiments, the method for processing tensor data can be implemented as a computer program tangibly contained in a computer-readable storage medium, such as a storage unit. In some embodiments, part or all of the computer program can be loaded and / or installed on an electronic device via ROM and / or a communication unit. When the computer program is loaded into RAM and executed by a processor, one or more steps of the method for processing tensor data described above can be performed. Alternatively, in other embodiments, the processor can be configured to perform the method for processing tensor data by any other suitable means (e.g., by means of firmware).

[0051] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0052] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0053] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0054] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0055] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0056] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0057] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0058] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method for processing Tensor data, characterized in that, The method includes: Obtain prior information of Tensor data, wherein the prior information includes the dimension parameters and storage address mapping rules of the Tensor data; Based on the dimension parameters of the Tensor data, each target element is determined; Using the storage address mapping rule, the virtual storage address of each target element is converted into a physical storage address, wherein the physical storage addresses are consecutive physical storage addresses; For any given target element, store the target element in the physical storage address corresponding to the target element; The preset algorithm is used to perform preset operations on each target element stored in each physical storage address to obtain the processing result.

2. The method according to claim 1, characterized in that, The virtual storage address includes a base address and a logical offset; the prior information also includes a tile dimension parameter, which is used to characterize the dimension of any tile in the Tensor; The step of using the storage address mapping rule to convert the virtual storage address of each target element into its respective physical storage address includes: For any target element, the logical offset of the target element is converted into logical coordinates based on the dimension parameters of the Tensor data; Using the tile dimension parameter and the logical coordinates of the target element, the tile index coordinates and the tile coordinates of the target element are obtained, wherein the tile coordinates are used to characterize the offset of the target element within the tile. The tile index coordinates are linearized according to a preset traversal order to obtain tile linear index coordinates, and the tile internal coordinates are linearized according to the traversal order to obtain tile linear internal coordinates. The physical storage address of the target element is obtained based on the linear index coordinates of the tile and the linear internal coordinates of the tile.

3. The method according to claim 2, characterized in that, For any target element, converting the logical offset of the target element into logical coordinates based on the dimension parameters of the Tensor data includes: The dimension parameters of the Tensor data are traversed according to a preset traversal order; For any traversed dimension parameter, the logical offset of the target element is divided by the traversed dimension parameter to obtain a first integer value and a first remainder value. The first integer value is then determined as the logical offset of the target element. The step of traversing the dimension parameters of the Tensor data according to a preset traversal order continues until the traversal ends. Then, each first remainder value obtained in each traversal is determined as the logical coordinate of the target element.

4. The method according to claim 2, characterized in that, The step of obtaining the tile index coordinates and the tile-in-tile coordinates of the target element using the tile dimension parameters and the logical coordinates of the target element includes: Divide the logical coordinates of the target element by each of the dimension parameters in the tile dimension parameters to obtain each second integer value and each second remainder value; The second integer values ​​are determined as the tile index coordinates of the target element, and the second remainder values ​​are determined as the tile coordinates of the target element.

5. The method according to claim 2, characterized in that, The step of obtaining the physical storage address of the target element based on the tile's linear index coordinates and the tile's linear interior coordinates includes: The first intermediate address is obtained by multiplying the tile linear index coordinates and the target parameter; wherein the target parameter is obtained by multiplying the intermediate parameter by the byte length of the target element, and the target parameter is obtained by multiplying each dimension parameter in the tile dimension parameters respectively; The second intermediate address is obtained by multiplying the linear inner coordinates of the tile by the byte length of the target element; The physical storage address of the target element is obtained by adding the base address, the first intermediate address, and the second intermediate address together.

6. A device for processing Tensor data, characterized in that, The device includes: The acquisition module is used to acquire prior information of Tensor data, wherein the prior information includes the dimension parameters and storage address mapping rules of the Tensor data; The target element determination module is used to determine each target element based on the dimension parameters of the Tensor data; The address translation module is used to convert the virtual storage address of each target element into a physical storage address using the storage address mapping rules, wherein the physical storage addresses are consecutive physical storage addresses. The storage module is used to store any target element in the physical storage address corresponding to the target element. The processing module is used to perform preset operations on each target element stored in each physical storage address using a preset algorithm to obtain the processing result.

7. The apparatus according to claim 6, characterized in that, The virtual storage address includes a base address and a logical offset; the prior information also includes a tile dimension parameter, which is used to characterize the dimension of any tile in the Tensor; The address translation module is specifically used for: For any target element, the logical offset of the target element is converted into logical coordinates based on the dimension parameters of the Tensor data; Using the tile dimension parameter and the logical coordinates of the target element, the tile index coordinates and the tile coordinates of the target element are obtained, wherein the tile coordinates are used to characterize the offset of the target element within the tile. The tile index coordinates are linearized according to a preset traversal order to obtain tile linear index coordinates, and the tile internal coordinates are linearized according to the traversal order to obtain tile linear internal coordinates. The physical storage address of the target element is obtained based on the linear index coordinates of the tile and the linear internal coordinates of the tile.

8. An electronic device, characterized in that, The electronic device includes: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the method for processing Tensor data according to any one of claims 1-5.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that cause a processor to execute the method for processing Tensor data as described in any one of claims 1-5.

10. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the method for processing Tensor data according to any one of claims 1-5.

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