Programming of high resistance state HRS for resistive memory elements

Abstract

Programming of a high resistance state (HRS) of a resistive memory element. A method (100) of programming a high resistance state of a memory element (Stck) portion of a resistive random access memory (MEM), the method (100) comprising: an initial step (S110) of writing a high resistance state of the memory element (Stck); and a retuning step (S140) after the initial step (S110) of writing the high resistance state (HRS), the retuning step (S140) comprising at least one operating cycle, the at least one operating cycle comprising, in order: a retuning set operation (SETrec) comprising flowing a retuning set current (Irec.set) through the memory element (Stck), the retuning setting current (Irec.set) has an absolute value lower than the nominal programming current (Ip.set); and a re-reset operation (RESET) that includes flowing a re-reset current (Ireset) through the memory element (Stck).

Description

Technical Field

[0001] The technical field of this invention is resistive random access memory (ReRAM) or resistive RAM, each of which includes memory elements whose resistance states define information bits. More specifically, this invention relates to a method for programming ReRAM. Background Technology

[0002] Non-volatile memory (NVM) is a type of computer memory that retains information even when its power is off. Examples of non-volatile memory include read-only memory (ROM), erasable ROM (EPROM), flash memory, ferroelectric random access memory (FRAM), magnetoresistive random access memory (MRAM), phase-change memory (PCM), and resistive random access memory (ReRAM).

[0003] The latter type of memory, ReRAM, is typically formed by an array of stacked stacks, each stack having a layer Diel made of a dielectric solid material and two electrodes E1 and E12, with the layer Diel interposed between the two electrodes, as shown below. Figure 1 As illustrated. This structure constitutes a memory bit element or memory element, and typically operates by altering the resistance of the layer Diel by forming and dissolving conductive filaments within a normally non-conductive dielectric layer. The dielectric layer can be formed from, for example, chalcogenides, perovskites, or oxides of transition metals (such as hafnium oxide (HfOx)).

[0004] The memory is formed by an array of such memory bit elements, each forming the core of a bit cell. This description will take ReRAM (i.e., OxRAM) as an example, which uses oxides of transition metals to form the dielectric solid-state material.

[0005] At the end of its manufacturing process, a ReRAM device typically undergoes an initialization phase, designed to activate each memory cell in its individual memory units. This phase may be part of the manufacturing process or performed immediately afterward and is typically performed only once, after which the device is used to store data via set or reset operations. The purpose of the initialization phase is to provide better control over the electrical characteristics of the memory cells and to improve device yield by enhancing the stability of key functional parameters such as current and resistance values. This process is sometimes performed using a so-called FORM algorithm. See US 2021 / 110870 A1 and US 2015 / 0287919 A1. Once initialization is complete, the memory device is ready for normal operation and data storage. Information can then be written by applying set and reset operations, which define the resistance state of the memory elements and thus the bit values, as described below. Figure 1 As shown, during the set operation (SET), a given voltage is applied between the two electrodes to generate a set current I. p.set And the associated electric field along the first direction d1 from electrode El2 to electrode El1. This is due to the presence of oxygen ions Oxy and oxygen vacancies V in the volume of dielectric layer Diel. Oxy The formation and diffusion of the current can cause the formation of conductive filaments (Fil) within the originally electrically insulating layer (Diel). The bit element is then placed in a low-resistance state, or LRS. The higher the setting current, the larger the filament and the lower the resistance of the bit element.

[0006] Conversely, during the RESET operation, a reverse voltage is applied to generate a reset current I flowing between the two electrodes El1 and El2 in a second direction d2, opposite to the first direction. p.res The reset current dissipates the conductive filament Fil generated during the Set operation, forming a dissipated filament DisFil and increasing the resistance of the bit element. The bit element is then placed in a high-resistance state, or HRS.

[0007] Each of the LRS and HRS states can be associated with a bit value in the digital memory. During a read operation, a read current flows between two electrodes to evaluate the resistance state of the bit element, and thus the associated bit value. The absolute value of the read current is lower than both the set and read currents, thus not altering the state of the dielectric layer.

[0008] The formation process of the filament and its final configuration (which determines the resistance of the memory element under LRS) are inherently random. Therefore, the characteristics of the bit cells are distributed within a certain range. In this context, Figure 2 The resistance of a set of bit cells in the same array is illustrated.

[0009] Figure 2(A) and Figure 2 (B) illustrates the probability Pr of each bit cell in the array taking a given resistance value R (Ω) in the ideal and more realistic scenarios, respectively. In the ideal case, only two values ​​are possible: a unique first value for the resistance of the low-resistance state LRS and a second unique value for the resistance of the high-resistance state HRS.

[0010] In the ideal model, a bit cell can only reach these two states, and each state has a unique and definite resistance value. However, in practice, the resistance values ​​are dispersed across ranges that can each be described as probability densities, which have a given value (for the two states LRS and HRS, R0 ... 0_LRS and R 0_HRS The peak is centered on the shape of the peak and exhibits a standard deviation σ (for simplicity, the distributions of LRS and HRS are similar in this example), as shown in the figure. Figure 2 exemplified by (B).

[0011] like Figure 2 As illustrated in (B), the two states, LRS and HRS, can actually be very close to each other. The distributions of these two states can even overlap. This can lead to confusion between the LRS and HRS states, and errors during data read operations stored in ReRAM.

[0012] The absolute value I of the programming current depends on the definition of the set current and reset current. prog The resistance values ​​of HRS and LRS change.

[0013] like Figure 3 As shown, for a given memory element, using the first programming current I... Prog Setting 1 will result in a first filament Fil1 of a given width, and thus a first resistance value R1. LRS The LRS. Using the same programming current I. Prog 1. The reset operation RESET will, to some extent, dissolve the filament and thus reduce it to the first given resistance value R1. HRS HRS. These results in Figure 3 The left side is shown.

[0014] Figure 3 The right side shows the results of the same set and reset operations as the left side, except that a stronger programming current IProg2 is used. The filament Fil2 formed by the set operation is thicker than the filament Fil1 and is more difficult to resolve by the reset operation, resulting in a resistance value lower than the first resistance value R1. LRS The second resistance value R2 LRS The LRS, and thus below the first resistance value R1. HRS The second resistance value R2HRS HRS.

[0015] Therefore, programming the LRS of a memory element with a stronger set current can help form a thicker filament. The advantage of this method is that it helps form an LRS with a lower resistance value. However, thicker filaments are more difficult to resolve, resulting in a relatively low resistance value in the HRS, which contradicts the overall goal of increasing the resistance margin between the LRS and HRS. Furthermore, the memory's HRS retention capability is reduced because thicker filaments are more likely to self-reform over time.

[0016] We see that the write methods used in OxRAM, and more generally in ReRAM, need to be improved.

[0017] Purpose of the invention

[0018] Against this backdrop, the inventors propose a programming method for ReRAM memory elements that allows setting a high resistance value for the HRS while maintaining a low resistance value for the LRS, thereby improving the resistance margin between the LRS and HRS. Summary of the Invention

[0019] Therefore, a first aspect of the present invention relates to a method for programming a high-resistance state of a memory element portion of a resistive random access memory, the random access memory being configured to program a low-resistance state of the memory element by causing a nominal programming current to flow through the memory element in a first direction, the method comprising: an initial step of writing a high-resistance state of the memory element, including causing a reset current to flow through the memory element in a second direction opposite to the first direction; and a readjustment step following the initial step of writing the high-resistance state, the readjustment step comprising at least one operating cycle comprising, in sequence: a readjustment set operation, the readjustment set operation including causing a readjustment set current to flow through the memory element in the first direction, the readjustment set current having an absolute value lower than the nominal programming current; and a readjustment reset operation, the readjustment reset operation including causing a readjustment reset current to flow through the memory element in the second direction, wherein the readjustment step increases the resistance value of the memory element obtained by the initial step of writing the high-resistance state.

[0020] By applying a readjustment operation that includes at least one set operation (which uses a programming current lower than the nominal current used in a normal write operation of the LRS) followed by a reset operation, the programming method according to the invention allows for achieving a higher resistance value of the HRS than that achievable by conventional HRS write methods.

[0021] Advantageously, the resistance margin between LRS and HRS is widened, which facilitates read operations and generally improves the reliability of ReRAM using this programming method.

[0022] Additional non-limiting features of the first aspect of the invention, either alone or in any technically feasible combination:

[0023] - The method may further include: a first readout operation measuring the resistance value of a resistive element after an initial step of performing a reset operation; and a test step in which the measured resistance value is compared with a threshold, wherein a readjustment step is performed when the measured resistance value is lower than the threshold.

[0024] - The method may further include: a second reading operation, after the readjustment step has been performed, measuring the readjustment resistance value of the resistive element; and a second test step, wherein the measured readjustment resistance value is compared with a threshold, wherein the readjustment step is performed again when the measured readjustment resistance value is lower than the threshold.

[0025] - The readjustment step may include exactly one occurrence of the operation loop;

[0026] - The readjustment step may include more than one occurrence of the operation loop;

[0027] - The readjustment step may include more than one but less than 20 occurrences of the operation cycle;

[0028] - The nominal programming current can have an absolute value between 175µA and 225µA, and the readjustment set current can have an absolute value between 75µA and 125µA.

[0029] - The initial step of writing to the high-resistance state of the memory element can dissolve the conductive filaments formed in the memory element; the reset set operation can reform the dissolved filaments; and the reset reset operation can dissolve the reformed filaments.

[0030] - This method can be performed during the normal operation of the resistive random access memory (MEM), rather than during the manufacturing and / or initialization phase of the resistive random access memory (MEM).

[0031] A second aspect of the invention relates to a ReRAM memory device comprising an array of bit cells controlled by column multiplexer circuitry and row driver circuitry, the row driver circuitry being configured to write high-resistance states of memory elements of the bit cells according to a method according to a first aspect of the invention. The ReRAM may be 0xRAM.

[0032] A third aspect of the invention relates to an embedded system comprising a microprocessor and a memory device according to a second aspect of the invention, the memory device being arranged to communicate with the microprocessor. Attached Figure Description

[0033] Many other features and advantages of the invention will become apparent when considered in conjunction with the accompanying drawings, and upon reading the following detailed description, in which the drawings are shown:

[0034] [ Figure 1 ] - Figure 1 This illustrates the operating principle of ReRAM;

[0035] [ Figure 2 ] - Figure 2 The resistivity distribution of a bit cell in a resistive memory is illustrated.

[0036] [ Figure 3 ] - Figure 3 The effect of programming current intensity on the resistance values ​​of LRS and HRS of memory elements is illustrated.

[0037] [ Figure 4 ] - Figure 4 The effects of the method according to the present invention are illustrated;

[0038] [ Figure 5 ] - Figure 5 This is a diagram illustrating the HRS writing method;

[0039] [ Figure 6 ] - Figure 6 Indicates according to Figure 5 The method of applying current to memory elements;

[0040] [ Figure 7 ] - Figure 7 This is illustrated by the phenomenon. Figure 5 and Figure 6 The method works;

[0041] [ Figure 8 ] - Figure 8 Explanation is shown Figure 5 A graph showing the operation of the method;

[0042] [ Figure 9 ] - Figure 9 It is proof Figure 5 A graph of specific values ​​of current intensity used in the method;

[0043] [ Figure 10 ] - Figure 10 Examples of combinations Figure 4 The illustrated memory element is a ReRAM memory; and

[0044] [ Figure 11 ] - Figure 11 Examples of combinations Figure 10 The illustrated memory is an embedded system. Detailed Implementation

[0045] The following will use... Figures 4 to 11 The general embodiments of the present invention will be described below.

[0046] Figure 4 The cumulative probability Cum.Pr represents the cumulative probability of a ReRAM memory element for a given resistance R, expressed in ohms, with respect to its corresponding low-resistance state LRS and high-resistance state HRS.

[0047] At (A), Figure 4 This indicates the difference between the resistance of LRS in the low-resistance state and the resistance of HRS in the conventional high-resistance state obtained using the conventional writing method. Conv There are instances where there is overlap indicated as Over. This overlap is a source of difficulty in using ReRAM.

[0048] At (B), Figure 4 This describes the goal and function of the programming method described below. The aim is to employ a programming approach that allows the HRS curve to be shifted towards higher R values, from a conventional high-resistivity HRS state. Conv The high resistance state HRS obtained by the method according to the invention Inv Then, a margin Marg is introduced between the low-resistance and high-resistance states of the ReRAM, or the margin Marg is widened if it already exists.

[0049] In other words, a higher resistance value is required than in conventional implementations for the HRS state of memory elements in ReRAM. The method designed by the inventors is based on the principle of better dissolving the filaments formed in the memory elements than in typical implementations. This principle is derived from... Figure 5 Method 100 is implemented, and this method is applied to, for example, Figure 1 The memory element Stck of the ReRAM shown.

[0050] In order to set the memory element to a state in which the method applies, the initial low-resistance state programming step LRS of the memory element is performed. prog This programming creates conductive filaments (Fil) within the originally electrically insulating dielectric layer (Diel).

[0051] In this implementation scheme, the programming step LRS prog This includes setting the bit via programming at step S90. progThe memory element is programmed using LRS. Operation SET is performed by applying voltage to the electrodes E1 and E12 of the memory element. prog So that it has an absolute current value I nom The nominal programming current I p.set The current circulates through the stack Stck along the first direction d1. The absolute current value and flow direction are selected to form the filament Fil.

[0052] Next, at step S105, a command to program the memory element Stck to HRS is received, and then the high-resistance state programming step HRS of the memory element is executed according to the following steps S110 to S140. prog .

[0053] In the first step S110 of programming the memory element using HRS, a programming reset operation RESET is performed by applying a constant voltage to the electrodes E1 and E12 of the memory element. prog In order to cyclically program the reset current I p.res The programming reset current I p.res Initially, it will have the same characteristics as I. p.set Roughly the same absolute value I nom However, along the second direction d2 in the stack body Stck, opposite to the first direction, the current decreases and converges subsequently towards the HRS state of the memory element. The initial reset current can have a different value than I. nom The absolute value of.

[0054] At step S120, a first read operation READ is performed on the resistive element Stck to measure its resistance value R after the first step S110 of programming the memory element with HRS.

[0055] After the first read operation in step S120, test step S130 is performed, wherein the read value R is compared with the threshold R. Th By comparison, this threshold is considered to be the lowest acceptable resistance value for the high-resistivity state (HRS) of a memory element.

[0056] If the read value R is greater than or equal to the threshold R Th If the resistance value is sufficient to ensure proper operation of the memory, the margin between LRS and HRS meets the predetermined specifications of the memory.

[0057] However, if the read value R is lower than the threshold R Th Then the method proceeds to the readjustment step S140, which involves increasing the resistance value R of the memory element to above a threshold R. Th The core of the method.

[0058] The readjustment step S140 includes n loops, each loop including a readjustment set operation SET. rec Then comes the reset operation RESET. rec The number n is an integer that can be between 1 and 30, preferably between 1 and 20.

[0059] RESET operation rec This is performed by applying voltages to the electrodes E1 and E12 of the memory element so that the readjustment reset current I... rec.res The memory element Stck is circulated along the second direction d2.

[0060] Reset current I rec.res Optionally, it can be used in conjunction with the programming reset operation RESET in step S110. prog Programmable reset current I p.res The characteristics of the current used to dissolve the filament Fil (direction, intensity, and duration of the applied voltage) are the same as those of the current I used for normal writing of the HRS at step S110. p.res They have the same characteristics.

[0061] Conversely, the set operation in step S140 is readjusted. rec Unlike the conventional LRS programming set operation of ReRAM, SET prog That is, the current I used to form the filament Fil in the readjustment step S140. rec.set Unlike the current I used for normal writing to the LRS at step S90. p.set Readjust the current I rec.set The intensity is lower in absolute value than the current I used in a regular set operation of ReRAM memory. p.set :|I rec.set |<|I p.set |

[0062] Figure 7 and Figure 8 This helps explain the principle behind the readjustment step S140.

[0063] Figure 7 The low-resistance state R of the memory element is shown at (A). LHS and high resistance state R HRS The plotted resistor value serves as the absolute value of the programming current I used to write these states using regular set and reset operations. prog The function.

[0064] If we take the relatively high value I from the programming current Start Write low resistance state START LRS To begin, use the same Iprog The reset operation will write the value to the high-resistance state START. HRS The high resistance state START HRS It still has a lower resistance state than the target TARG HRS The resistance value is much lower. This is because... Figure 3 The phenomena shown are the same as those discussed previously.

[0065] To write the high-resistance state TARG HRS We can consider starting from the high resistance state. HRS Begin by reducing the programming current to the high resistance state TARG on the curve. HRS The current corresponding to the current I Targ To write the corresponding low-resistance state TARG LRS Then a reset operation is applied to achieve the target state TARG. HRS However, this approach is not feasible because... Figure 7 In case (A), the initial high resistance state START HRS The resistance value is lower than the target low resistance state TARG LRS The resistance value.

[0066] To circumvent this impossibility, the method includes employing a series of loops, each loop including a set operation followed by a reset operation, which allows for a gradual approach to the target high-resistance state TARG, even starting from the low-resistance state STARTLRS. HRS ,like Figure 7 As shown in (B). Based on the following regarding... Figure 8 The reason for this is that the current used must be lower than that initially used to write the START state. LRS The current.

[0067] exist Figure 7 In the scenario shown in (B), starting from state START LRS Write status TARG HRS It requires 9 steps, and there is no situation where the transition from HRS to LRS would mean increasing the resistance value. Figure 7 The impossibility mentioned in scenario (A). These 9 steps are distributed across 5 pairs of LRS and HRS labeled (1) to (5).

[0068] In conventional write methods, the resistance of the memory element is essentially along... Figure 7 The Y-axis of the graph moves back and forth between the two resistance states in a one-dimensional manner. Conversely, Figure 4Programming method 100 advantageously allows the resistance value to be moved along both the X and Y axes of the graph, thus allowing greater flexibility in the programming of the ReRAM memory. In this example, we can see that the achievable resistance value has been obtained by obtaining resistance R. gain It represents state R. HRS With TARG HRS The difference between the resistance values.

[0069] Figure 8 This phenomenon explains the dielectric layer pair of the memory element Stick. Figure 7 The response to the series of steps shown in (B).

[0070] For in Figure 7 Each of the five pairs of LRS and HRS identified as (1) to (5) in (B) Figure 8 The left side represents the filament formed through a series of set operations, and Figure 8 The right side represents the dissociation filament DisFil obtained through a series of reset operations.

[0071] The principle is to start with a thick filament Fil that requires a low resistance value, and to reduce the thickness of the filament by repeatedly eliminating it and reforming it into a thinner form in a continuous cycle performed as in step S140. In this way, the filament obtained at the last pair of states (5) is thin and can be easily eliminated to obtain a state HRS with a high resistance value. Generally, the number of state pairs is equal to SET. rec / RESET rec The number of times the loop repeats, n. Figure 8 This indicates the corresponding current I. p.res The first reset operation of the programming reset operation in step S110, and the use of current I rec.res The subsequent reset operation. The set operation utilizes current I. rec.set To execute. In this example, four loops are executed, each loop including a SET. rec Operation and a RESET rec operate.

[0072] Step S140 changes the resistance value R of the memory element to the value R to be read during the new step S120. rec This value is considered the new R value and is compared with the threshold R at the new test step S130. Th Compare them.

[0073] If the threshold R Th If the resistance value is still greater than the read value R, then steps S140, S120, and S130 are executed again until the resistance value R becomes greater than or equal to the threshold R. ThIn this case, the method proceeds to step S150 and ends at step S150.

[0074] like Figure 6 As shown, Figure 5 The method can be implemented by any conventional ReRAM memory and programmed to perform the steps of method 100 detailed above. More specifically, the set, reset, and read operations may include applying a command voltage (applying voltage for a finite time period) to electrodes E1 and E12 in the form of pulses, which results in the generation of current-cycle pulses of strength entering the memory elements, as is well known. Figure 6 It is a graph representing the intensity of an applied current I as a function of time t. Figure 6 This is merely an illustrative diagram, and the intensity, length, and profile of the pulses shown are not intended to be limited thereto.

[0075] During a set operation, a voltage is applied, generating a circulating current in the memory element. This circulating current must be limited to prevent damage to the memory because the resistance forming the filament and thus reducing the current causes the current to rise, and the current must be limited to prevent damage to the memory.

[0076] During a reset operation, a voltage of the same order of magnitude but opposite sign as the voltage used during a set operation can be used to generate a current that is essentially the same as the initial current flowing in the memory element at the end of the set operation. This current decreases as the filament dissipates with increasing resistance.

[0077] The voltage required to generate the current suitable for set, reset, and read operations may vary depending on the ReRAM technology, the electronic setup of the memory cells, the array of memory elements, or more generally, the electronic circuitry used to control the ReRAM.

[0078] On the other hand, the current value is better defined. Figure 9 This illustrates a current value that can be used to determine the appropriate current value for implementing the programmed set operation. prog and reset bit operation SET rec The graph shows the holding requirements: the current needs to be strong enough to form a sufficiently thick filament, resulting in a sufficiently high holding capability. The current used for the readjustment operation needs to be weak enough so that the filament it forms can be effectively dissipated by the reset operation, resulting in a resistance value in the high-resistance state that is higher than a given threshold fixed by the ReRAM specifications.

[0079] For the set operation SET prog and reset operation SET recWrite tests for LRS and HRS have been performed at four programming current values ​​(408µA, 307µA, 208µA, and 119µA). In this example, it can be seen that the higher the current, the lower the resistance of LRS, and vice versa. Here, for the resistance value in the HRS state, the current needs to be as low as 119µA to reach the threshold R. Th And it is considered acceptable. As shown in the figure, this can be achieved by comparing two different programming currents ( Figure 9 The resistance values ​​at currents of 408µA and 119µA were used to estimate the gain of the resistance value in the high-resistance state.

[0080] In fact, the SET operation is performed as described above. prog A favorable value for the current can be defined as between 175µA and 225µA. Current of the same absolute value can be used for the reset operation. prog and RESET rec Conversely, the reset operation SET rec The current is lower than that of the set operation. prog The current value can be defined as being between 75µA and 125µA.

[0081] The number of cycles n required to achieve the HRS acceptable resistance value can be determined empirically.

[0082] Alternative locations, such as Figure 5 As shown in method 100, a re-adjustment may be performed only when necessary, after the read and test operations.

[0083] Read and test operations can be performed between each loop, which will correspond to Figure 5 In the diagram, n=1. The disadvantage of this particular variant is the speed loss when several cycles are required. On the other hand, it limits the number of set and reset operations, limits wear on memory elements, and thus enhances retention and reliability.

[0084] Alternatively, a fixed number of loops, n > 1, can be executed between two test operations. This is useful when a large number of loops are needed to reach a threshold R. Th At that time, this particular variant may be advantageous in terms of speed because it allows for limiting the number of reset and test operations.

[0085] The stacked body Stck described above can form the active element of a ReRAM memory MEM. Set, reset, and read operations can be applied to the bit cells integrated in the array ARR, each of which includes a stacked body Stck.

[0086] Figure 10 The basic conventional structure of a resistive memory (MEM) is illustrated. Such a memory is described, for example, in patent US11735260B2.

[0087] Usually, such as Figure 10 As illustrated in (C), each bit cell BC of the array ARR includes: (i) a stack body Stck that forms a variable resistor Var R (See) Figure 10 (b) and implements the function of the memory bit element for each bit cell; and (ii) a selection transistor Sel Tr It has a source and a drain connected in series with a variable resistor.

[0088] An array of bit cells (ARR) typically includes rows and columns of bit cells, such as... Figure 10 As illustrated in (A). Each column includes: (i) a bit line BL, which passes through a variable resistor Var for each bit cell in the column. R Connected to transistor Sel Tr (i) the source and drain of transistor SelTr; and (ii) the source line SL, which passes through the source and drain of transistor SelTr and the variable resistor Var. R Connected to bit line BL. Each row of bit cells includes a word line WL, which is connected to the select transistor Sel for each bit cell in that row. Tr The gate of the [unclear text - likely a typo]. The bit line BL and source line SL are each connected to the column multiplexer circuit SL / BL-Mux and controlled by it. The word line WL is each connected to the row driver circuit WL-Drv and controlled by it.

[0089] Figure 11 An example is the EmbSys embedded system, which integrates OxRAM for communication with a microprocessor CPU. Such systems can be used in portable semiconductor devices configured to process numerical data. Generally, any embedded device that conventionally uses flash memory can alternatively use resistive memory. OxRAM benefits from the enhanced retention capabilities of the stack described above and makes it particularly suitable for high-temperature applications, such as transportation applications.

[0090] By studying the accompanying drawings, the disclosure, and the appended claims, those skilled in the art can understand and implement other variations of the disclosed embodiments when practicing the claimed invention.

Claims

1. A method (100) for programming a high-resistance state (HRS) of a memory element (Stck) portion of a resistive random access memory (MEM), said random access memory being configured to program by causing a nominal programming current (I0) to be applied. p.set The method (100) involves programming the low-resistance state (LRS) of the memory element by flowing through the memory element (Stck) in a first direction (d1), the method comprising: - An initial step (S110) for writing the high-resistance state (HRS) of the memory element (Stck), the initial step including setting the reset current (I) reset The memory element flows along a second direction (d2) opposite to the first direction (d1); and - A readjustment step (S140) following the initial step (S110) of writing the high resistance state (HRS), the readjustment step (S140) comprising at least one operating cycle, the at least one operating cycle comprising in the following order: - Resetting the set bit (SET) rec The readjustment bit operation includes setting the readjustment bit current (I) rec.set The readjustment current (I) flows along the first direction (d1) through the memory element (Stck), and the readjustment current (I) rec.set It has a lower nominal programming current (I) p.set The absolute value of ) and - Reset operation (RESET), the reset operation including setting the reset current (I) reset The current flows through the memory element (Stck) along the second direction (d2). The readjustment step (S140) increases the resistance value (R) of the memory element obtained by writing the high resistance state (HRS) in the initial step (S110).

2. The method according to claim 1, further comprising: - After the initial step (S110) of performing the reset operation (RESET), a first read operation (S120) is performed to measure the resistance value (R) of the memory element. as well as - Test step (S130), in which the measured resistance value (R) is compared with the threshold (R0). Th ) for comparison, Wherein, when the measured resistance value (R) is lower than the threshold (R0), Th When ), the readjustment step (S140) is performed.

3. The method according to claim 1 or 2, further comprising: - After the readjustment step (S140) has been performed, the readjustment resistance value (R) of the memory element is measured. rec The second read operation (S120); as well as - Second test step (S130), in which the measured readjustment resistance value (R) is compared with the threshold value (R). Th ) for comparison, Among them, when the measured readjustment resistance value (R) rec ) below the threshold (R) Th When the readjustment step (S140) is executed again, the readjustment step is executed again.

4. The method according to any one of claims 1 to 3, wherein, The readjustment step (S140) includes exactly one occurrence of the operation cycle.

5. The method according to any one of claims 1 to 3, wherein, The readjustment step (S140) includes the occurrence of the operation cycle more than once.

6. The method according to claim 5, wherein, The readjustment step (S140) includes the occurrence of the operation cycle more than once and less than 20 times.

7. The method according to any one of claims 1 to 6, wherein: - The nominal programming current (I p.set It has an absolute value (I) between 175µA and 225µA. nom ),and - The readjustment current (I rec.set It has an absolute value between 75µA and 125µA.

8. The method according to any one of claims 1 to 7, wherein: - The initial step (S110) of writing the high resistance state (HRS) of the memory element (Stck) dissolves the conductive filament (Fil) formed in the memory element (Stck). - The reset bit operation (SET) rec This causes the dissolved filaments to reform; and - The reset operation (RESET) dissolves the reformed filament.

9. The method according to any one of claims 1 to 8, wherein, The method is performed during the normal operation of the resistive random access memory (MEM), rather than during the manufacturing and / or initialization phases of the resistive random access memory (MEM).

10. A ReRAM memory device (MEM) comprising an array (ARR) of bit cells (BCs) controlled by column multiplexer circuitry (SL / BL-Mux) and row driver circuitry (WL-Drv), the row driver circuitry being configured to write a high-resistance state (HRS) of a memory element (Stck) of the bit cells (BCs) by the method of any one of claims 1 to 9.

11. The ReRAM memory device of claim 10, wherein the ReRAM is 0xRAM.

12. An embedded system (EmbSys) comprising a microprocessor (CPU) and a memory device (MEM) according to claim 10 or 11, the memory device being arranged to communicate with the microprocessor (CPU).

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