Memory system, operating method thereof, and readable storage medium

Abstract

Embodiments of the present disclosure disclose a memory system, an operating method thereof, and a readable storage medium, the memory system including: a memory device including a plurality of memory blocks, each of the memory blocks including a plurality of word lines and a plurality of memory cells coupled to the plurality of word lines; the memory controller is coupled with the storage device and is configured to utilize the first type of reread meters and the second type of reread meters to jointly obtain reread voltage; the first type of rereading table comprises first voltage deviation values corresponding to different conditions when one storage block in the plurality of storage blocks is fully written; the second type of rereading table comprises a second voltage deviation value corresponding to the state of each word line based on the first type of rereading table when one storage block in the plurality of storage blocks is not fully written; the memory device is controlled to perform a reread operation using the reread voltage.

Description

[0001] Divisional Explanation This application is a divisional application of the Chinese Patent Application No. 202310837674.6, with the title of “Memory System and Operating Method Thereof, and Readable Storage Medium”, filed on July 7, 2023. TECHNICAL FIELD

[0002] Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a memory system and an operating method thereof, and a readable storage medium. BACKGROUND

[0003] A memory device is a storage apparatus used for saving information in modern information technology. As a typical non-volatile semiconductor memory, a NAND (Not-And) type memory gradually becomes a mainstream product in the storage market due to its high storage density, controllable production cost, suitable programming and erasing speed, and retention characteristics.

[0004] However, as people's requirements for storage devices continue to increase, there is much room for improvement in memory devices and systems. SUMMARY

[0005] According to a first aspect of embodiments of the present disclosure, a memory system is provided, comprising: a memory device, comprising a memory block, the memory block comprising a plurality of word lines and a plurality of memory cells coupled to the plurality of word lines; and a memory controller coupled to the memory device and configured to: obtain a read voltage based on a first voltage offset table and a second voltage offset table; the first voltage offset table comprising voltage offset values under different conditions when the memory block is in a full written state; the second voltage offset table comprising voltage offset values corresponding to the first table based on different positions of word lines in a non-full written state of the memory block; and control the memory device to perform a read operation based on the read voltage.

[0006] In some embodiments, the first voltage offset table and the second voltage offset table are both re-read tables, and the read operation performed based on the read voltage is a re-read operation.

[0007] In some embodiments, the memory block comprises a non-full written memory block, and to perform the read operation on the non-full written memory block, the memory controller is configured to: obtain a first voltage offset value related to a memory cell to be read in the non-full written memory block based on the first voltage offset table; obtaining a second voltage offset value corresponding to the to-be-read memory cell based on the second voltage offset table, a group to which a word line coupled to the to-be-read memory cell belongs, and a relationship between the word line coupled to the to-be-read memory cell and the first blank word line; obtaining a read voltage when the read operation is performed on the to-be-read memory cell based on the first voltage offset value and the second voltage offset value.

[0008] In some embodiments, the memory controller is configured to: obtaining a total offset voltage value by summing the first voltage offset value and the second voltage offset value; obtaining a read voltage when the read operation is performed on the to-be-read memory cell by summing a default read voltage and the total offset voltage value.

[0009] In some embodiments, the memory block includes a 0th word line to an Nth word line sequentially numbered according to physical positions; the memory block is programmed in an order from the 0th word line to the Nth word line; the N is an integer greater than 2; the 0th word line to the Nth word line are divided into a plurality of word line groups, and each word line group includes at least two adjacent word lines; in the not-full memory block, the 0th word line to the Nth word line include the first blank word line, an edge word line adjacent to the first blank word line, and an intermediate word line spaced from the first blank word line; wherein the edge word line falls into different groups, and corresponding voltage offset values in the second voltage offset table are different.

[0010] In some embodiments, the corresponding second voltage offset value when the word line coupled to the to-be-read memory cell is the edge word line is different from the corresponding second voltage offset value when the word line coupled to the to-be-read memory cell is the intermediate word line.

[0011] In some embodiments, the absolute value of the offset amount of the corresponding second voltage offset value when the word line coupled to the to-be-read memory cell is the edge word line from the first voltage offset value is greater than the absolute value of the offset amount of the corresponding second voltage offset value when the word line coupled to the to-be-read memory cell is the intermediate word line from the first voltage offset value.

[0012] In some embodiments, the closer the intermediate word line is to the 0th word line, the greater the absolute value of the offset amount of the corresponding second voltage offset value when the word line coupled to the to-be-read memory cell is the intermediate word line from the first voltage offset value.

[0013] In some embodiments, The closer the distance between the edge word line and the 0th word line, the greater the absolute value of the offset of the second voltage offset value from the first voltage offset value when the word line to which the storage unit to be read is coupled is the edge word line.

[0014] In some embodiments, each of the storage units is configured to store multi-bit data, and the multi-bit data is read by multi-step read voltages. The second voltage offset values corresponding to each of the multi-step read voltages are the same. Alternatively, The second voltage offset values corresponding to some of the multi-step read voltages are different.

[0015] In some embodiments, the second voltage offset values corresponding to at least two of the multi-step read voltages are different. The multi-step read voltages are divided into multiple intervals, and each interval contains one read voltage or at least two adjacent read voltages. The second voltage offset values corresponding to each of the read voltages in one interval are the same, and the second voltage offset values corresponding to the read voltages in different intervals are different.

[0016] In some embodiments, each of the groups corresponds to the multiple intervals; for different multiple intervals corresponding to the same group, the smaller the average number of steps of the read voltages contained in the corresponding interval, the greater the absolute value of the offset of the second voltage offset value corresponding to the corresponding interval from the first voltage offset value.

[0017] In some embodiments, the memory device includes multiple types of memory pages; and the different cases include at least one of the following: Different numbers of bits of data stored by the storage units; Different types of the memory pages; Different use scenarios of the memory device.

[0018] In some embodiments, the memory controller is configured to: After controlling the memory device to perform the read operation based on the read voltage, perform a hard decoding operation on the read data; In response to a failure of the hard decoding operation, perform a soft decoding operation; In response to a failure of the soft decoding operation, perform a redundant array data recovery operation.

[0019] According to a second aspect of the embodiments of the present disclosure, an operation method of a memory system is provided, including: obtaining a read voltage based on a first voltage offset table and a second voltage offset table; the first voltage offset table includes voltage offset values of a memory block of a memory device in different cases when the memory block is full; the second voltage offset table includes voltage offset values of word lines in different positions of the memory block when the memory block is not full based on corresponding voltage offset values of the first voltage offset table; performing a read operation based on the read voltage.

[0020] In some embodiments, the first voltage offset table and the second voltage offset table are both re-read tables, and the read operation performed based on the read voltage is a re-read operation.

[0021] In some embodiments, the memory block includes a not-full memory block, and obtaining the read voltage based on the first voltage offset table and the second voltage offset table includes: obtaining a first voltage offset value related to a memory cell to be read in the not-full memory block based on the first voltage offset table; obtaining a second voltage offset value corresponding to the memory cell to be read based on the second voltage offset table, a group to which a word line coupled to the memory cell to be read belongs, and a relationship between the word line coupled to the memory cell to be read and a first empty word line; obtaining a read voltage for performing the read operation on the memory cell to be read based on the first voltage offset value and the second voltage offset value.

[0022] In some embodiments, obtaining the read voltage for performing the read operation on the memory cell to be read based on the first voltage offset value and the second voltage offset value includes: summing the first voltage offset value and the second voltage offset value to obtain a total offset voltage value; summing a default read voltage and the total offset voltage value to obtain the read voltage for performing the read operation on the memory cell to be read.

[0023] In some embodiments, the memory block includes a 0th word line to an Nth word line sequentially numbered according to physical positions; the memory block is programmed in an order from the 0th word line to the Nth word line; and N is an integer greater than 2. The 0th word line to the Nth word line are divided into a plurality of word line groups, and each word line group includes at least two adjacent word lines. The first empty word line, an edge word line adjacent to the first empty word line, and an intermediate word line spaced from the first empty word line are included in the 0th word line to the Nth word line in the not-full memory block; the edge word line falls into different groups, and the corresponding voltage offset values in the second voltage offset table are different.

[0024] In some embodiments, the corresponding second voltage offset value when the word line to which the to-be-read memory cell is coupled is the edge word line is different from the corresponding second voltage offset value when the word line to which the to-be-read memory cell is coupled is the intermediate word line.

[0025] In some embodiments, The absolute value of the offset amount of the corresponding second voltage offset value when the word line to which the to-be-read memory cell is coupled is the edge word line from the first voltage offset value is greater than the absolute value of the offset amount of the corresponding second voltage offset value when the word line to which the to-be-read memory cell is coupled is the intermediate word line from the first voltage offset value.

[0026] In some embodiments, The closer the intermediate word line is to the 0th word line, the greater the absolute value of the offset amount of the corresponding second voltage offset value when the word line to which the to-be-read memory cell is coupled is the intermediate word line from the first voltage offset value.

[0027] In some embodiments, The closer the edge word line is to the 0th word line, the greater the absolute value of the offset amount of the corresponding second voltage offset value when the word line to which the to-be-read memory cell is coupled is the edge word line from the first voltage offset value.

[0028] In some embodiments, each of the memory cells is configured to store multi-bit data, and the multi-bit data is read by multi-step read voltages; The second voltage offset values corresponding to each of the multi-step read voltages are the same; Alternatively, The second voltage offset values corresponding to part of the multi-step read voltages are different.

[0029] In some embodiments, the second voltage offset values corresponding to at least two of the multi-step read voltages are different; The multi-step read voltages are divided into multiple intervals, each interval containing one read voltage or at least two adjacent read voltages; The second voltage offset values corresponding to each of the read voltages in one interval are the same, and the second voltage offset values corresponding to the read voltages in different intervals are different.

[0030] In some embodiments, each group corresponds to the plurality of intervals; for different intervals corresponding to the same group, the smaller the average order of the read voltage contained in the corresponding interval, the larger the absolute value of the offset of the second voltage offset value corresponding to the corresponding interval compared to the first voltage offset value.

[0031] In some embodiments, the memory device includes multiple types of memory pages, and the memory block includes multiple memory cells; the different cases include at least one of the following: The storage unit is configured to store different numbers of bits of data; The storage pages include different types; Different use cases of the memory device.

[0032] In some embodiments, the operating method further includes: After performing the read operation based on the read voltage, the read data is then subjected to hardware decoding. In response to the failure of the hardware decoding operation, a software decoding operation is performed; In response to the failure of the soft decoding operation, a redundant array data recovery operation is performed.

[0033] According to a third aspect of the present disclosure, a memory system is provided, comprising: A memory device, the memory device including a memory block, the memory block including a plurality of word lines and a plurality of memory cells coupled to the plurality of word lines; and A memory controller, coupled to the memory device, is configured to: Based on the first voltage offset value of a full memory block under a certain condition, and the second voltage offset value corresponding to the position of the word line coupled to the memory cell to be read in the unfulfilled memory block, the read voltage when reading the memory cell to be read in the unfulfilled memory block is obtained; and Based on the read voltage, the memory device is controlled to perform a read operation on the memory cell to be read in the unwritten memory block.

[0034] In some embodiments, the memory controller is configured to: The first voltage offset value and the second voltage offset value are summed to obtain the total offset voltage value; The default read voltage is summed with the total offset voltage value to obtain the read voltage when performing the read operation on the memory cell to be read.

[0035] In some embodiments, the memory block includes word lines 0 to N, numbered sequentially according to their physical location; the memory block is programmed in the order of the word lines 0 to N; where N is an integer greater than 2. The 0th to the Nth word lines are divided into multiple word line groups, and each word line group contains at least two adjacent word lines; In the unfilled memory block, the 0th word line to the Nth word line include: the first blank word line, the edge word line adjacent to the first blank word line, and the intermediate word line that is spaced apart from the first blank word line; wherein, the edge word lines fall into different groups and the second voltage offset value is different.

[0036] In some embodiments, the second voltage offset value corresponding to the word line coupled to the memory cell to be read is the edge word line and the second voltage offset value corresponding to the word line coupled to the memory cell to be read is the middle word line.

[0037] In some embodiments, The absolute value of the offset of the second voltage offset value relative to the first voltage offset value when the word line coupled to the memory cell to be read is the edge word line is greater than the absolute value of the offset of the second voltage offset value relative to the first voltage offset value when the word line coupled to the memory cell to be read is the middle word line.

[0038] In some embodiments, The closer the intermediate word line is to the 0th word line, the greater the absolute value of the second voltage offset value corresponding to the word line coupled to the memory cell to be read being the intermediate word line, compared to the first voltage offset value.

[0039] In some embodiments, The closer the edge word line is to the 0th word line, the greater the absolute value of the second voltage offset value corresponding to the word line coupled to the memory cell to be read being the edge word line, compared to the first voltage offset value.

[0040] In some embodiments, each of the memory cells is configured to store multiple bits of data, which are read via a multi-stage readout voltage. The second voltage offset value corresponding to each of the multi-stage reading voltages is the same; or, The second voltage offset value corresponding to some of the multi-stage read voltages is different.

[0041] In some embodiments, at least two of the multi-order read voltages correspond to different second voltage offset values; The multi-stage read voltage is divided into multiple intervals, each interval containing a first-stage read voltage or at least two adjacent read voltages. The second voltage offset value corresponding to each reading voltage in one interval is the same, while the second voltage offset value corresponding to multiple reading voltages in different intervals is different.

[0042] In some embodiments, each group corresponds to the plurality of intervals; for different intervals corresponding to the same group, the smaller the average order of the read voltage contained in the corresponding interval, the larger the absolute value of the offset of the second voltage offset value corresponding to the corresponding interval compared to the first voltage offset value.

[0043] In this embodiment, a first type of read-back table and a second type of read-back table are used to obtain the read-back voltage. The first type of read-back table includes first voltage offset values ​​for different conditions corresponding to a memory block when it is full. The second type of read-back table includes the state of each word line of a memory block when it is not full. Based on the different second voltage offset values ​​corresponding to the first type of read-back table, the first voltage offset value, the second voltage offset value, and the default read voltage are summed to obtain the read-back voltage for performing the read-back operation. This reduces the amount of data in the read-back table, facilitates faster lookup of the read-back table and increases the polling rate of the read-back operation, thereby increasing the read speed of the memory system. Attached Figure Description

[0044] Figure 1 This is a schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure; Figure 2a This is a schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present disclosure; Figure 2b This is a schematic diagram of an exemplary solid-state drive with a memory system according to an embodiment of the present disclosure; Figure 3a This is a schematic diagram showing the distribution of storage cells in a three-dimensional NAND type memory according to an embodiment of the present disclosure; Figure 3b This is a schematic diagram of an exemplary memory device including peripheral circuitry according to an embodiment of the present disclosure; Figure 4 This is a schematic cross-sectional view of a memory cell array including NAND memory strings according to an embodiment of the present disclosure; Figure 5 This is a schematic diagram of an exemplary memory device including a memory cell array and peripheral circuitry according to an embodiment of the present disclosure; Figure 6 This is a schematic diagram of a read operation process including a reread operation according to an embodiment of the present invention; Figure 7 This is a block diagram illustrating the application of a memory controller including an error correction module in a memory system according to an embodiment of the present disclosure. Figure 8 This is a schematic diagram of a reread table according to an embodiment of the present disclosure; Figure 9 This is a schematic diagram illustrating a threshold voltage offset of a filled memory block, an intermediate word line of an unfilled memory block, and an edge word line of an unfilled memory block, according to an embodiment of this disclosure. Figure 10 This is a first type of reread representation intent corresponding to a filled storage block in an embodiment of this disclosure; Figure 11 This is a schematic diagram of a threshold voltage after Gray code programming according to an embodiment of the present disclosure; Figure 12a This is a schematic diagram of a second type of reread table according to an embodiment of the present disclosure; Figure 12b This is another schematic diagram of the second type of reread table according to an embodiment of this disclosure; Figure 12c This is a schematic diagram of a second type of reread table with storage-state partitioned intervals according to an embodiment of this disclosure; Figure 13 This is a schematic flowchart illustrating an operation method of a memory system according to an embodiment of the present disclosure.

[0045] In the above figures (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The figures illustrate, by way of example and not limitation, the various embodiments discussed herein. Detailed Implementation

[0046] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0047] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0048] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0049] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0050] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0051] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0052] To gain a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of this disclosure.

[0053] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments of this disclosure are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0054] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0055] The memory devices in the embodiments of this disclosure include, but are not limited to, three-dimensional NAND type memory. For ease of understanding, three-dimensional NAND type memory will be used as an example for explanation.

[0056] Figure 1 A block diagram of an exemplary system 100 having a memory device according to some aspects of this disclosure is shown. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 1 As shown, system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 108 may be configured to send data to or receive data from the memory device 104.

[0057] According to some embodiments, memory controller 106 is coupled to memory device 104 and host 108 and is configured to control memory device 104. Memory controller 106 can manage data stored in memory device 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, memory controller 106 is designed to operate in high duty cycle environments, such as SSDs or embedded multimedia cards (eMMCs), which are used as data storage in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays.

[0058] The memory controller 106 can be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions relating to data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) relating to data read from or written to the memory device 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 can communicate with external devices (e.g., host 108) according to specific communication protocols. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Devices (IDE) protocol, Firewire protocol, etc.

[0059] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. Figure 2aIn one example shown, the memory controller 106 and a single memory device 104 can be integrated into a memory card 202. The memory card 202 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 can also include a connection between the memory card 202 and a host computer (e.g., Figure 1 The host 108) is coupled to the memory card connector 204. In such a... Figure 2b In another example shown, the memory controller 106 and multiple memory devices 104 may be integrated into the SSD 206. The SSD 206 may also include components for connecting the SSD 206 to a host computer (e.g., Figure 1 The SSD connector 208 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0060] Figure 3a An exemplary schematic diagram of a storage cell array for a three-dimensional NAND flash memory is provided, such as... Figure 3a As shown, the memory cell array of a three-dimensional NAND flash memory consists of several rows of parallel, staggered memory cell rows parallel to the gate isolation structure. Each two rows of memory cell rows are separated by a gate isolation structure and an up-select gate isolation structure. Each memory cell row includes multiple memory cells. The gate isolation structure may include a first gate isolation structure and a second gate isolation structure. The first gate isolation structure divides the memory cell array into multiple memory blocks. Multiple second gate isolation structures can divide the memory blocks into multiple finger memory regions. An up-select gate isolation structure located in the middle of each finger memory region can divide the finger memory region into two parts, thereby dividing the finger memory region into two memory chips. Figure 3a The memory block shown contains 6 memory chips; however, in practical applications, the number of memory chips in a memory block is not limited to this. A memory cell in a memory block coupled to a word line can be called a memory page.

[0061] It should be noted that, Figure 3a The number of cell rows between the gate isolation structure and the top-select gate isolation structure given is merely an exemplary example and is not intended to limit the number of cell rows contained in a single memory region of the three-dimensional NAND memory in this disclosure. In practical applications, the number of cell rows contained in a single memory region can be adjusted according to actual conditions, such as 2, 4, 8, 16, etc.

[0062] Figure 3b A schematic circuit diagram of an exemplary memory device 300, including peripheral circuitry, is shown according to some aspects of this disclosure. The memory device 300 may be... Figure 1 An example of memory device 104 is provided. Memory device 300 may include a memory cell array 301 and peripheral circuitry 302 coupled to the memory cell array 301. The memory cell array 301 is illustrated as a three-dimensional NAND-type memory cell array, wherein the memory cells 306 are provided in the form of an array of NAND memory strings 308, each NAND memory string 308 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0063] In some implementations, each memory cell 306 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 306 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC may store two bits per cell, three bits per cell (also known as a three-level cell (TLC)), or four bits per cell (also known as a four-level cell (QLC)). Each MLC can be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to write one of three possible nominal storage values ​​into the cell, while a fourth nominal storage value in addition to these three nominal storage values ​​can be used to indicate an erase state.

[0064] like Figure 3bAs shown, each NAND memory string 308 may include a lower select gate (BSG) 310 at its source end and an upper select gate (TSG) 312 at its drain end. BSG 310 and TSG 312 can be configured to activate the selected NAND memory string 308 during read and program operations. In some embodiments, the sources of the NAND memory strings 308 in the same memory block 304 are coupled via a common source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each NAND memory string 308 is coupled to a corresponding bit line (BL) 316, from which data can be read or written via an output bus (not shown). In some implementations, each NAND memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having TSG 312) or a deselection voltage (e.g., 0V) to the corresponding TSG 312 via one or more TSG lines 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having BSG 310) or a deselection voltage (e.g., 0V) to the corresponding BSG 310 via one or more BSG lines 315.

[0065] like Figure 3b As shown, NAND memory strings 308 can be organized into multiple memory blocks 304, each of which may have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is the basic data unit for an erase operation, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase memory cells 306 in a selected memory block 304a, an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)) can be used to bias and couple the source line 314 of the selected memory block 304a and the unselected memory block 304b on the same face as the selected memory block 304a. It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 306 of adjacent NAND memory strings 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some implementations, in conjunction with the preceding... Figure 3aMultiple memory cells are isolated from each other by an upselect gate isolation structure and a gate isolation structure. The multiple memory cells between the upselect gate isolation structure and the gate isolation structure are arranged into multiple memory cell rows, each of which is parallel to both the gate isolation structure and the upselect gate isolation structure. Memory cells in a memory chip sharing the same word line form a physical page 320. Each physical page 320 can be mapped to at least one logical page according to the memory mode of the corresponding memory cell 306 (e.g., SLC or MLC as described above). Logical pages can constitute the basic data unit for programming and reading operations.

[0066] Figure 4 A schematic cross-sectional view of an exemplary memory cell array 301 including NAND memory strings 308 is shown, according to some aspects of this disclosure. Figure 4 As shown, the NAND memory string 308 may include a stacked structure 410, which includes multiple gate layers 411 and multiple insulating layers 412 stacked alternately in sequence, and a memory string 308 perpendicularly penetrating the gate layers 411 and insulating layers 412. The gate layers 411 and insulating layers 412 may be stacked alternately, with adjacent gate layers 411 separated by an insulating layer 412. The number of pairs of gate layers 411 and insulating layers 412 in the stacked structure 410 determines the number of memory cells included in the memory cell array 301.

[0067] The constituent materials of the gate layer 411 may include conductive materials. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, such as a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stack 410 may extend laterally as an upper select gate line, the gate layer 411 at the bottom of the stack 410 may extend laterally as a lower select gate line, and the gate layer 411 extending laterally between the upper and lower select gate lines may serve as a word line layer.

[0068] In some embodiments, the stacked structure 410 may be disposed on the substrate 401. The substrate 401 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0069] In some embodiments, the NAND memory string 308 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes channel holes filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polycrystalline silicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0070] Return to reference Figure 3b The peripheral circuitry 302 can be coupled to the memory cell array 301 via bit line 316, word line 318, source line 314, BSG line 315, and TSG line 313. The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory cell array 301 by applying voltage and / or current signals to each target memory cell 306 via bit line 316, word line 318, source line 314, BSG line 315, and TSG line 313, and by sensing voltage and / or current signals from each target memory cell 306. The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuitry is shown. Peripheral circuitry 302 includes a page buffer / sensor amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 5 Additional peripheral circuitry not shown.

[0071] Page buffer / sensor amplifier 504 can be configured to read data from and program (write) data to memory cell array 301 according to control signals from control logic 512. In one example, page buffer / sensor amplifier 504 can store a page of programming data (write data) to be programmed into a memory page 320 of memory cell array 301. In another example, page buffer / sensor amplifier 504 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 306 coupled to selected word line 318. In yet another example, page buffer / sensor amplifier 504 can also sense a low-power signal from bit line 316 representing a data bit stored in memory cell 306 and amplify a small voltage swing to a recognizable logic level during read operations. Column decoder / bit line driver 506 can be configured to be controlled by control logic 512 and select one or more NAND memory strings 308 by applying a bit line voltage generated from voltage generator 510.

[0072] The row decoder / word line driver 508 can be configured to be controlled by control logic 512 and to select / deselect memory blocks 304 of the memory cell array 301 and to select / deselect word lines 318 of memory blocks 304. The row decoder / word line driver 508 can also be configured to drive word lines 318 using word line voltages generated from voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive BSG lines 315 and TSG lines 313. As described in detail below, the row decoder / word line driver 508 is configured to perform programming operations on memory cells 306 coupled to one or more selected word lines 318. The voltage generator 510 can be configured to be controlled by control logic 512 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, channel boost voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0073] In some specific embodiments, the programming operation may include multiple stages. For example, the programming operation may include a channel pre-charge stage, a channel boost stage, a programming pulse stage, and a recovery stage. In the channel pre-charge stage, a voltage generator can generate the voltage required for the next stage, such as the voltage applied to each gate, the channel boost voltage, etc.; in the channel boost stage, a channel boost voltage can be applied to the selected word line; in the programming pulse stage, the target voltage for each programming operation can be applied to the selected word line. In the recovery stage, the voltage can be reduced to the corresponding voltage, such as Vcc or Vdd, for both unselected and selected word lines. The recovery stage can achieve this by stepping down the voltage to the corresponding voltage once or multiple times, for example, by first reducing the voltage to an intermediate voltage, maintaining it at that intermediate voltage for a period of time, and then reducing it to the corresponding voltage.

[0074] Control logic 512 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 514 can be coupled to control logic 512 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 516 can be coupled to control logic 512 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic 512, as well as to buffer status information received from control logic 512 and relay it to the host. Interface 516 can also be coupled to column decoder / bit line driver 506 via data bus 518 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory cell array 301.

[0075] In some embodiments, the storage cells of a NAND type memory can be divided into single-level storage cells (one-bit storage cell), double-level storage cells (two-bit storage cells), triple-level storage cells (three-bit storage cells), quadruple-level storage cells (four-bit storage cells), and five-level storage cells (five-bit storage cells) according to storage density. However, regardless of whether it is a single-level or multi-level storage cell, its read operation can be performed on a page-by-page basis. Specifically, when performing a read operation, a read voltage is applied to the word line (i.e., the selected word line) coupled to the selected page in the memory device 104. When the read voltage reaches the threshold voltage of the multiple storage cells coupled to the selected word line, or when the number of storage cells that do not reach the threshold voltage is within an allowable range, the read operation of the entire page ends. The storage cell can be an M-bit storage cell, and the storage cell has 2 bits including an erase state. M One storage state, through 2 M-1 read voltage reads M bits of stored data. For example, the first read voltage is between the threshold voltages of the erase state and the first storage state. When the first read voltage is applied to the word line, the memory cell in the erase state is turned on, and the memory cell in the first storage state is not turned on. The erase state and the first storage state are distinguished and read.

[0076] It should be noted that during the read operation, memory cells that do not reach the target threshold voltage are marked as error bits. To prevent read errors, error correction codes (ECC) are introduced. When the number of error bits is less than or equal to the maximum number of failure bits that the error correction code can correct, all error bits in the read operation can be corrected, thus enabling correct data reading.

[0077] In some embodiments, the host 108 sends a read command (or read instruction, read request) to the memory controller 106 according to the current user command requirements. The memory controller 106 transmits the read control command, including information such as a logical address-physical address mapping table, to the memory device 104 through interface 516, controlling the memory device 104 to perform a read operation on the memory cell corresponding to the corresponding physical address. The memory device 104 then sends the read data back to the memory controller 106 through interface 516. The memory controller 106 then feeds the data back to the host 108 via an interface such as PCIe or SATA. Specifically, the memory controller 106 sends the read control command to the control logic of the memory device through interface 516. The control logic applies a relevant operating voltage to the selected word line or bit line according to the relevant physical address, thereby performing a read operation on the corresponding memory cell. The operating voltage can be generated by the control logic according to the relevant read voltage mapping table, controlled by a voltage generator, and then applied to the word line of the corresponding address after decoding by a row decoder, or applied to the bit line of the corresponding address after decoding by a column decoder.

[0078] In other embodiments, when the memory device 104 reads a corresponding memory cell under the control of the memory controller 106, a read error occurs. In this case, the memory controller 106 responds to the read operation failure by controlling the memory (or the error correction module in the memory controller 106). The error correction mode may include ECC error correction. According to some aspects of embodiments of this disclosure, Figure 6 A schematic diagram illustrating an exemplary read operation flow of a memory system 102 is shown. Combined with Figure 6As shown, when the memory controller 106 controls the memory device 104 to perform a read operation, it first performs a default read operation (FW default read) on the memory cell at the corresponding physical address. If the default read fails, a read retry operation is performed. If the read retry operation fails, a soft decode operation is performed. If the soft decode operation fails, a redundant array data recovery (RAID) operation is performed. If the RAID operation fails, the read operation stops and fails because it cannot correct errors. The memory controller 106 sends a read fail signal to the host 108. The read retry operation and the default read operation can be applied to hardware decoding.

[0079] Error correction operations such as rereading, software decoding, and RAID can be performed by the error correction module 1064 (e.g., an ECC module) in the memory controller 106, controlling the memory device 104. Control commands are sent from the memory controller 106 to the memory device 104 via interface 516, and the memory device 104 feeds back the read information to the memory controller 106 via interface 516. It should be noted that once any one of the rereading, software decoding, or RAID operations is successfully completed, subsequent operations can be stopped.

[0080] In some specific embodiments, a software decoding operation can be understood as performing data re-decoding via a decoding unit 1066 (e.g., a software decoder) in the memory controller 106, and then performing a read operation based on the re-decoded data. A RAID operation can be understood as mirroring the data through secondary encoding, reconstructing the stored data and its parity check data. Typically, the re-encoding of the stored data for the redundant array is performed in the data buffer 1067 of the memory controller 106.

[0081] According to some aspects of embodiments of this disclosure, Figure 7 A block diagram of a memory system 102 including a memory controller 106 and an error correction module 1064 is provided. (Refer to...) Figure 7 As shown, the memory system 102 includes a memory controller 106 and a memory. The memory controller 106 and the memory device 104 can be coupled in any suitable manner. In this embodiment, the memory controller 106 includes a host I / F 1061, a memory I / F 1062, a control unit 1063, an error correction (ECC) module 1064, a data buffer 1067, and an internal bus 1060. The error correction module 1064 includes an encoding unit 1065 and a decoding unit 1066. The host I / F 1061 outputs commands received from the host 108, user data (write data), etc., to the internal bus 1060, and sends user data read from the memory device 104 (read data), responses from the control unit 1063, etc., back to the host 108.

[0082] The memory I / F controls the processes of writing user data to and reading from the memory device 104 based on instructions from the control unit 1063. The control unit 1063, such as a central processing unit (CPU) or microprocessor (MPU), controls the memory system 102 as a whole. The control unit 1063 performs control according to commands received from the host 108 via the host I / F 1061. For example, the control unit 1063 instructs the memory I / F to write user data and perform parity checks on the memory device 104 based on commands from the host 108. Furthermore, the control unit 1063 instructs the memory I / F to read user data and perform parity checks from the memory device 104 based on commands from the host 108.

[0083] The error correction module 1064 includes an encoding unit 1065 and a decoding unit 1066. The encoding unit 1065 encodes user data of a predetermined size written on the same page to generate parity data. The parity data is written on the page containing the user data that forms the basis of the encoding, and the decoding unit 1066 uses the parity data to decode. The data buffer 1067 temporarily stores user data received from the host 108 before storing it in the memory device 104, and temporarily stores data read from the memory device 104 before sending it to the host 108.

[0084] In some embodiments, Figure 6 The process for determining the reread voltage in a reread operation may include: the error correction module 1064 in the memory controller 106 queries the corresponding reread table to obtain the corresponding voltage offset value. This voltage offset value can be a positive or negative offset value, and is summed with the default read voltage to obtain the reread voltage. The memory controller 106 controls the memory device 104 to perform a reread operation on the memory cell at the corresponding physical address using this reread voltage. It should be noted that the memory controller 106 may use a polling method when querying the reread table. A reread table may include multiple sub-tables, such as m sub-tables (or...). Figure 8 (Multiple rows of RR settings), where m is a natural number greater than 1. Each sub-table may include a voltage offset value for the corresponding storage state of the corresponding storage unit. The system sequentially queries from the first sub-table to the m-th sub-table, obtaining a voltage offset value for each query, and then sums them to obtain a reread voltage. The memory device 104 uses this reread voltage to perform the read operation. Therefore, a single reread operation can have a maximum of m sub-read operations, and this embodiment of the present disclosure does not impose any limitation on this.

[0085] In some embodiments, the memory cell array includes multiple memory blocks, each memory block including multiple word lines. Multiple memory cells coupled to a certain word line in each memory block can serve as one or more physical pages. In some embodiments, as the storage capacity requirements of the memory device 104 increase, the more memory blocks are divided, the higher the overall storage string integration density and the more word line layers (corresponding to the number of memory cell stacking layers) are. On the same word line, memory cells on a closed block and memory cells on an open block may have a threshold voltage offset due to differences in the total stored charge, parasitic capacitance, and charge coupling. This threshold voltage offset is an example for memory cells in the same storage state. An open block primarily reads its already written memory cells. Therefore, in some specific embodiments, the reread table will have separate reread tables for closed and open blocks. Specifically, in conjunction with... Figure 6 As shown, when a default read operation on a logical page in a full memory block fails, the memory controller 106 queries the reread table corresponding to the full memory block. When a default read operation on a logical page in a partially full memory block fails, the memory controller 106 queries the reread table corresponding to the partially full memory block. Even if the memory cells are on the same word line and in the same memory state, the voltage offset values ​​corresponding to the two reread tables may be different.

[0086] It should be noted that for a memory block that is not fully written, there are blank word lines and write word lines. A blank word line indicates that all memory cells coupled to it are in the erase state. A write word line indicates that some memory cells coupled to it are not in the erase state (at least partially in the programmable state). Furthermore, based on sequential programming, the first blank word line is the first blank word line that appears in the programming order among all blank word lines.

[0087] In some embodiments, for a full memory block, there are no blank word lines. A single reread table can be used for different memory pages within the block, regardless of word line positions, to reduce the size of the reread table. For a partially written memory block, there are blank word lines and write word lines. Because there is a charge difference between the physical page corresponding to the write word line and the physical page corresponding to its adjacent blank word line, the threshold voltage of the memory cells in a partially written memory block will have a more complex threshold voltage offset compared to a full memory block. The positional relationship between the write word line and the blank word line within the memory block also makes the threshold voltage offset more complex.

[0088] For example, during programming operations, either the top word line or the bottom word line can be used as the starting programming word line. The top word line is located at either end of a block (or memory string) with the top word line closer to the bit line, and the bottom word line is located at the end farther from the bit line. The starting word line can be word line 0, and the word lines can be numbered sequentially according to the programming order (the order in which programming voltages are applied), such as word lines 0-63, 0-95, 0-127, 0-230, 0-400, or more. During programming writes, writing can start from word line 0 to ensure that a single memory block can be filled, reducing addressing pressure. However, this only applies to physical addresses; logical addresses are not limited to their continuity. Write word lines for unfilled memory blocks can correspond to consecutive physical addresses. The word line adjacent to the first blank word line can be designated as the edge word line (edge ​​WL), and the remaining word lines are designated as inner word lines (inner WL). Specifically, taking word lines 0-230 as an example, when the write word line is word line 0-55, the middle word line is word line 0-54, and the edge word line is word line 55; when the write word line is word line 0-115, the middle word line is word line 0-114, and the edge word line is word line 115. The edge word line is closest to the first blank word line and is most affected by it. The offset value of the threshold voltage corresponding to the edge word line is greater than that corresponding to the middle word line. For a memory block that is not fully written, the reread table must include at least the contents for the edge word line and the middle word line respectively, or in other words, it must include sub-tables for the edge word line and the middle word line respectively, to meet the offset scenarios of different threshold voltages.

[0089] In some embodiments, for a partially written memory block, the offset values ​​of the threshold voltage corresponding to edge word lines and middle word lines at different positions are not the same when the word line number is larger (the more word line layers). Word lines can be grouped, with each group corresponding to different reread table contents or different reread sub-tables. The management of reread tables for filled and partially written memory blocks in this disclosure can include various scenarios: the various memory tables corresponding to filled and partially written memory blocks can be merged into a single reread master table for unified management; or, for different types of memory blocks, or even for reread tables corresponding to word line grouping in different memory blocks, they can be presented as reread sub-tables. This disclosure does not limit the unified or separate management of reread tables; subsequent firmware or programs will query based on the grouping information and word line positions attached to the reread table.

[0090] For example, refer to Figure 8 An exemplary total reread table is shown, including a table of associated rereads for filled storage blocks. Figure 8Taking a TLC memory cell storing 3 bits of data with 7 read voltage levels as an example, the table header shows the read voltage offset values ​​corresponding to the read voltages of the 7 memory states. The offset values ​​can be positive, negative, or 0. The offset value is summed with the corresponding default read voltage to obtain the new read voltage. The offset position includes word line address information, memory block type information, etc. The firmware can use this information to determine which row of the memory table to start polling for the current read operation or which row of the read table needs to be executed. The 7 read voltage levels are: Rd1LP, Rd2MP, Rd3UP, Rd4MP, Rd5LP, Rd6MP, and Rd7UP. When the memory cell to be read is located in a full memory block, the polled read table can include RR-1, RR-9 to RR-33, with a maximum of 26 queries and 26 voltage offset value operations to determine whether the read operation is successful. If any read operation is successful, the polling can be stopped; if it fails after 26 attempts, the read operation is considered to have failed, and the software decoding operation is initiated. Figure 8 The document also includes reread table sections (not shown) for RR-34 to RR-188, which correspond to the reread table sections for different word line groups of unwritten memory blocks. For example, taking RR-1, the voltage offset value obtained from a single query of the first memory state is a1 (in mV). a1 is summed with the default read voltage of the first memory state to obtain the reread voltage, which is used to determine whether a reread of the memory cell has been successful.

[0091] Taking a TLC memory cell with word lines 0-231 as an example, the first group includes word lines 0-56, the second group includes word lines 57-116, the third group includes word lines 117-172, and the fourth group includes word lines 173-230. This grouping includes write word lines, including middle and edge word lines. For example, when write word lines 0-57 fall into the second group, word lines 0-56 still belong to the second group, and their voltage offset values ​​are looked up according to the corresponding mode of the second group. This lookup is performed during a reread operation. Figure 8When the write word line falls into the first group, all intermediate word lines in the reread table iterate through RR-34 to RR-59, querying the voltage offset value up to 26 times. This 26 times can be a preset value written to the firmware. Edge word lines iterate through RR-112 to RR-137, querying the voltage offset value up to 26 times. When the write word line falls into the second group, all intermediate word lines in the reread table iterate through RR-60 to RR-85, querying the voltage offset value up to 26 times. Edge word lines iterate through RR-138 to RR-163, querying the voltage offset value up to 26 times. When the write word line falls into the third group, all intermediate word lines in the reread table iterate through RR-86 to RR-111, querying the voltage offset value up to 26 times. Edge word lines iterate through RR-164 to RR-189, querying the voltage offset value up to 26 times. When a write word line falls into the fourth group, the middle word lines poll the corresponding full memory block portion in the reread table, querying the voltage offset value at most 26 times; the edge word lines poll the portions RR-34 to RR-59, querying the voltage offset value at most 26 times. It should be noted that the fact that the middle and edge word lines have the same reread table as the other groups when a write word line falls into the fourth group is only a special case; other embodiments may differ.

[0092] In some actual reread operations, several specific reread operations are illustrated to explain the correspondence between word line groups and reread tables in the embodiments of this disclosure. When the write word lines are 0-10 and fall into the first group, the middle word lines are 0-9, and the polling is for RR-34 to RR-59; the edge word line is 10, and the polling is for RR-112 to RR-137. When the write word lines are 0-56 and fall into the first group, the middle word lines are 0-55, and the polling is for RR-34 to RR-59 in the reread table; the edge word line is 56, and the polling is for RR-112 to RR-137. When the write word lines are 0-57 and fall into the second group, the write word lines 0-56 are middle word lines, and the polling is not for RR-34 to RR-59, but for RR-60 to RR-85; the edge word lines are polled for RR-138 to RR-163. When the write word lines 0-117 fall into the third group, the middle word lines 0-116 are polled according to RR-86 to RR-111; the edge word lines are polled according to RR-164 to RR-189. Specifically, when the write word line is word line 0, and both the middle and edge word lines are word lines 0, there are more cases of initial programming threshold voltage deviation. In this case, partial polling according to RR-34 to RR-59 and RR-112 to RR-137 can be performed, with a maximum of 52 polls, reducing the Fail Bit Count (FBC) to improve reread accuracy. When word lines 0-231 are all written, the memory block is full, and polling is performed according to the full memory block.

[0093] Figure 8 The reread table also includes special cases such as RR-2, RR-3 to RR-7, and RR-8, which can include other test items, such as early-life and late-life detection of memory cells, and can be completed before the first polling. RR-2 corresponds to a fully written memory block, RR-3 to RR-7 correspond to the middle word lines of incomplete memory blocks, and RR-8 corresponds to the edge word lines of incomplete memory blocks. For Figure 8 The number of rows (or sub-tables) included in the reread table, and the preset maximum number of table lookups (e.g., 26 times) in a single polling process of a reread operation are just examples and are not limited. The more preset table lookups in a single reread operation, the fewer FBCs caused by the determined reread voltage, and the higher the reread accuracy.

[0094] Combination Figure 8 As shown, in order to better overcome the influence of middle word lines and edge word lines at different positions in the unfilled memory block on the threshold voltage offset, the write word lines are grouped and set up with independent polling reread tables. Polling items from RR-1 to RR-189 are set up, and the reread table data volume is large.

[0095] Furthermore, in some other use cases, there are also other corresponding reread tables, including but not limited to test items such as read interference, data retention, working life, and temperature. Different test items can also be set up separately. Figure 8 The reread table shown, or the addition of corresponding RR polling entries, further increases the size of the reread table, which further increases the storage space occupied. In particular, when the reread operation is started, the space occupied by the relevant registers in the memory controller 106 or the data buffer 1067 is further increased, which will increase the data transmission pressure to a certain extent, and will also squeeze the space occupied by other data, reducing data processing performance.

[0096] In view of the above, according to a first aspect of the present disclosure, a memory system 102 is provided, comprising: The memory device 104 includes a plurality of memory blocks, each memory block including a plurality of word lines and a plurality of memory cells coupled to the plurality of word lines; The memory controller 106 is coupled to the memory device and is configured to: The reread voltage is obtained by using a first type of reread table and a second type of reread table. The first type of reread table includes the first voltage offset value of a memory block under different conditions when it is full. The second type of reread table includes the second voltage offset value of each word line of a memory block when it is not full, based on the state of each word line of the memory block under the first type of reread table. The control memory device 104 performs a reread operation using a reread voltage.

[0097] In this embodiment of the disclosure, Figure 8 The portion of the reread table corresponding to the memory block that is filled with reread data is used as the base reread table to obtain... Figure 10 The first type of reread table shown can be: Figure 8 A sub-table of the middle reread table, based on Figure 10 The first type of reread table in the model uses voltage offset to construct the reread table corresponding to the incomplete memory block. The first type of reread table retains the RR-1, RR-9 to RR-33 portions of the completed memory block, and deletes the reread tables of the original incomplete memory blocks, as well as RR-2, RR-3 to RR-7 and RR-8, etc., which do not conform to the model. Figure 9 Additional test cases for the offset pattern. Figure 10 The offset voltage shown is denoted as the first voltage offset value. In some embodiments, this disclosure performs threshold voltage tests on the middle word lines and edge word lines of multiple filled memory blocks, various types of unfilled memory blocks.

[0098] Reference Figure 9As shown, for word lines with the same number or word lines coupled at the same layer, the threshold voltage of a fully written memory block (where the word line position has less impact on voltage offset) can be used as a reference. The threshold voltage of the middle word lines in a partially written memory block has a first offset value relative to the threshold voltage of a fully written memory block, and the threshold voltage of the edge word lines in a partially written memory block has a second offset value relative to the threshold voltage of a fully written memory block. The second offset value is greater than the first offset value. For memory cells with a small number of bits, such as TLC, the middle word lines corresponding to all memory states are offset by the same first offset value, and the edge word lines corresponding to all memory states are offset by the same second offset value. For memory cells with a large number of bits, such as QLC or some TLCs, the middle word lines corresponding to different memory states are offset by different first offset values, and the edge word lines corresponding to different memory states are offset by different second offset values. Therefore, a reread table corresponding to a partially written memory block can be constructed based on the reread table corresponding to a fully written memory block. The second voltage offset value in the second type of reread table is based on... Figure 9 The threshold voltage offset relationship between the middle word line of an incomplete memory block and a full memory block, as well as the threshold voltage offset relationship between the edge word line of an incomplete memory block and a full memory block, are set to reduce the total number of read repetition tables. For a full memory block, the first voltage offset value is summed with the default read voltage to obtain the read repetition voltage; for an incomplete memory block, the first voltage offset value, the second voltage offset value, and the default read voltage are summed to obtain the read repetition voltage.

[0099] In some embodiments, the memory device 104 includes multiple types of memory pages; the different cases include at least one of the following: The storage unit includes different storage bits; The storage pages include different types; Different use cases of the memory device 104.

[0100] In this embodiment of the present disclosure, the storage unit can store M bits of data, and the memory device 104 may include M types of pages. The M-bit storage unit reads its M-bit stored data through an N-level read voltage; M and N are both integers greater than 1, and N=2. M -1.

[0101] When M=2, the stored data in the memory cell consists of two bits. In this case, the memory includes two types of pages: the previous page and the next page. A two-bit memory cell requires a three-level (3=2) process. 2-1) Reading voltage reads the two-bit stored data; for example, the two-bit data stored in the memory cell corresponds to four states (one erase state and three store states), that is, four voltage ranges are assigned to four data values. During reading, the two-bit stored data in the memory cell is read by applying a third-order read voltage to distinguish the four voltage ranges. The previous page corresponds to a first-order read voltage, and the next page corresponds to a second-order read voltage.

[0102] When M=3, the data stored in the memory cell consists of three bits. In this case, the memory includes three types of pages: the previous page, the middle page, and the next page. A three-bit memory cell requires passing through a seven-level (7=2) sequence. 3 -1) Reading voltage reads the three-bit stored data; for example, the three-bit data stored in the memory cell corresponds to eight states (one erase state and seven store states), that is, eight voltage ranges are assigned to eight data values. During reading, a seventh-order read voltage, used to distinguish the eight voltage ranges, is applied to read the three-bit stored data in the memory cell. The previous page corresponds to a second-order read voltage, the middle page to a third-order read voltage, and the next page to a second-order read voltage. For example... Figure 9 as well as Figure 10 In the example read / reread table, the seven read voltages (Vrd1~7) for the seven memory states other than the erase state are: Rd1LP, Rd2MP, Rd3UP, Rd2MP, Rd5LP, Rd6MP, and Rd7UP. The previous page corresponds to Rd3UP and Rd7UP, the middle page corresponds to Rd2MP, Rd2MP, and Rd6MP, and the next page corresponds to Rd1LP and Rd5LP. The correspondence between the corresponding read voltage offset voltages and different types of memory pages in the read / reread table is the same as the correspondence between read voltages and memory pages, and will not be repeated here.

[0103] When M=4, the data stored in the memory cell consists of four bits. In this case, the memory includes four types of pages: top page, top-middle page, bottom-middle page, and bottom page. Four-bit memory cells correspond to fifteen levels (15=2). 4 -1) Reading voltage reads four bits of data; for example, the four bits of data stored in the memory cell correspond to sixteen states (one erase state and fifteen store states), that is, sixteen voltage ranges are assigned to sixteen data values. During reading, fifteen levels of read voltage are applied to distinguish the sixteen voltage ranges to read the three bits of stored data in the memory cell. Among them, the previous page corresponds to the fourth level of read voltage, the upper-middle page corresponds to the third level of read voltage, the lower-middle page corresponds to the fourth level of read voltage, and the next page corresponds to the fourth level of read voltage.

[0104] In some embodiments, the corresponding read voltage for each type of page, distinguishing the data stored in the corresponding bits, is determined according to encoding rules. For example, the encoding rules include, but are not limited to, Gray code encoding rules. It should be noted that typical binary Gray code is often simply referred to as Gray code. In the encoding of a set of numbers, if any two adjacent codes differ by only one binary digit, this encoding is called Gray code. Furthermore, since the largest and smallest numbers also differ by only one digit (i.e., "head and tail connected"), it is also called cyclic code or reflected code. Gray code has other encoding forms, such as decimal number encoding, four-bit natural binary encoding, etc. Gray code is generated by recursively producing code tables, for example, two-bit Gray code, three-bit Gray code, four-bit Gray code, etc. (See reference...) Figure 11 As shown, taking three-dimensional Gray code as an example, such as 111, 110, 100, 000, 101, 011, 001, and 101, these correspond to the erase state (ER) and seven storage states (P1-P7), respectively. As mentioned earlier, reading the eight voltage ranges corresponding to the eight storage states (one erase state and seven storage states) requires a seventh-order read voltage. In this embodiment, the three types of pages corresponding to the three-bit storage units are mapped to the seventh-order read voltage through the encoding rules of the three-bit Gray code. Specifically, the lower page corresponds to the first and fifth-order read voltages; the middle page corresponds to the second, fourth, and sixth-order read voltages; and the upper page corresponds to the third and seventh-order read voltages. It should be noted that the corresponding order is adjusted accordingly after the encoding rules are changed. Different usage scenarios include, but are not limited to: read interference; data retention; working life; temperature, etc. Different test items can correspond to multiple read tables for full storage blocks and multiple read tables for incomplete storage blocks.

[0105] In some embodiments, the storage block includes a first storage block, which is a storage block that is not fully written to, and the memory controller 106 is configured to: Using the first type of reread table, the first voltage offset value corresponding to the first storage block is obtained; Using the second type of reread table, and combining the group to which the word line coupled to the memory cell to be read in the first memory block belongs, and the relationship between the word line coupled to the memory cell to be read and the first blank word line, the corresponding second voltage offset value is obtained. Based on the first voltage offset value and the second voltage offset value, the reread voltage is obtained when performing a read operation on the memory cell to be read in the first memory block.

[0106] In some embodiments, the memory controller 106 is configured to: The first voltage offset value and the second voltage offset value are summed to obtain the total offset voltage value; The reread voltage is obtained by summing the default read voltage with the total offset voltage value. The default read voltage is the value used for execution. Figure 6 The reading voltage shown is for the default read operation.

[0107] For a full memory block, the first voltage offset value is summed with the default read voltage to obtain the reread voltage; for a partially written memory block, the first voltage offset value, the second voltage offset value, and the default read voltage are summed to obtain the reread voltage.

[0108] In some embodiments, the memory block includes word lines 0 to N, numbered sequentially according to their physical location; the memory block is programmed in the order of word lines 0 to N; where N is an integer greater than 2. All word lines of the memory block are divided into multiple groups, each group containing multiple adjacent word lines; All word lines in the first memory block include: the first blank word line, the edge word lines adjacent to the first blank word line, and the middle word lines that are spaced apart from the first blank word line; wherein the edge word lines falling into different groups have different second voltage offset values, and the middle word lines falling into different groups have different second voltage offset values.

[0109] In some embodiments, each group contains the same or similar number of word lines.

[0110] In some embodiments, the edge word lines and the middle word lines fall into the same group and have different second voltage offset values.

[0111] The first storage block is not full. When performing a reread operation, it utilizes... Figure 10 The first voltage offset value is obtained by setting the first type of reread table under different conditions for the filled memory block. As mentioned earlier, the word lines are numbered and grouped according to the programming order. The distance between the word line to be reread and the first blank word line can determine the middle word line and the edge word line of the written word line. The word line adjacent to the first blank word line among the written word lines is the edge word line, and the rest are middle word lines. In the same word line group, the second voltage offset value corresponding to the edge word line is greater than the second voltage offset value corresponding to the middle word line. The reread voltage is obtained by summing the first voltage offset value, the second voltage offset value, and the default read voltage for the corresponding word line.

[0112] Reference Figure 12a As shown, an example form of the second type of reread table is illustrated. Figure 12b The second type of reread table is shown. Figure 8The correspondence between the read / write tables is as follows: `close blk` represents a full memory block, which is closed for programming operations; `open block` represents a partially written memory block, which is active or open for programming operations; `openWL` represents the middle word line within a partially written memory block, `inner WL` represents the middle word line within that block, and `edge WL` represents the edge word line within that block. It should be noted that... Figure 12a and Figure 12b The second voltage offset value can be applied to the overall offset of the first voltage offset value for all storage states of the storage cell.

[0113] For example, taking a TLC memory cell with word lines 0-231 as an example, the first group includes word lines 0-56, the second group includes word lines 57-116, the third group includes word lines 117-172, and the fourth group includes word lines 173-230. These groups include write word lines, including middle and edge word lines. As the number of word lines increases further, more groups can be added, and each group may contain the same or different number of word lines. For example, when write word lines 0-57 fall into the second group, word lines 0-56 still belong to the second group, and the second voltage offset value in their second type of reread table is looked up according to the corresponding mode of the second group. Figure 12a In this configuration, each group of write word lines corresponds to two different second voltage offset values, with the absolute value of the second voltage offset value corresponding to the edge word line being greater than the absolute value of the second voltage offset value corresponding to the middle word line. Here, each memory cell in a memory state corresponds to the same second voltage offset value, and the four groups can correspond to eight second voltage offset values.

[0114] Specifically, in combination Figure 12b As shown, RR-1 and RR-9 to RR-33 in setting 1 are... Figure 8 and Figure 10 The first type of reread table content corresponding to the full memory block shown is the offset reference voltage of the second voltage offset value, with 26 RR settings. It should be noted that for the reference case corresponding to setting 1, the second voltage offset value relative to the first voltage offset value of the full memory block is 0.

[0115] Reference Figure 12a As shown, when the write word lines 0-10 fall into the first group, the middle word lines (0-9) have a corresponding second voltage offset value of -90mV, while the edge word line (10) has a corresponding second voltage offset value of -190mV. The rereading operation for the middle word lines can be found in [reference needed]. Figure 12b As shown in setting 2, a second voltage offset value of -90mV is added to the first voltage offset value corresponding to all storage states in each RR setting to replace... Figure 8The original reread table shows settings RR-34 to RR-59. At this point, the edge word line is word line 10, and the second voltage offset is -190mV, corresponding to... Figure 12b In setting 5, based on the first voltage offset value of a filled memory block, all memory states are offset by the second voltage offset value.

[0116] When the write word lines 0-57 fall into the second group, with the middle word lines being 0-56, the second voltage offset value of the first group is not followed; instead, the second voltage offset value of the second group is followed by -60mV. Figure 12b In setting 3, the first voltage offset value corresponding to the filled memory block is shifted by -60mV; the edge word line is number 57, and the second voltage offset value is -160mV, corresponding to... Figure 12b Setting 6 in the code shifts the first voltage offset value corresponding to the filled memory block by -160mV. Similarly, the second voltage offset value of the middle word line of the third group of write word lines is -30mV, and the second voltage offset value of the edge word lines is -120mV; the second voltage offset value of the middle word line of the fourth group of write word lines is 0mV, and the second voltage offset value of the edge word lines is -90mV.

[0117] Combination Figure 12b As shown in the embodiments of this disclosure, after setting the second reread table, the total RR settings of the reread table may include 26 settings for the filled memory block as the offset reference, 8 second voltage offset value settings, and 7 additional cases, compared to Figure 8 The 189 RR settings shown in this embodiment reduce the amount of data in the reread table, which facilitates faster firmware lookup and polling rate of reread operations, thereby increasing the read rate of the memory system.

[0118] In some embodiments, the closer the middle character line is to the 0th character line, the greater the absolute value of the second voltage offset value corresponding to the group into which the middle character line falls compared to the first voltage offset value. The closer the edge word line is to the 0th word line, the greater the absolute value of the second voltage offset value in the second type of reread table corresponding to the group into which the edge word line falls compared to the first voltage offset value. When the edge character line and the middle character line fall into the same group, the absolute value of the offset of the second voltage offset value corresponding to the edge character line relative to the first voltage offset value is greater than the absolute value of the offset of the second voltage offset value corresponding to the middle character line relative to the first voltage offset value.

[0119] Reference Figure 12aAs shown, considering the middle word lines in different groups, the closer the middle word line is to word line 0, the smaller its number, and the earlier its programming order, the larger the absolute value of its corresponding second voltage offset value. Similarly, considering the edge word lines in different groups, the closer the edge word line is to word line 0, the smaller its number, and the earlier its programming order, the larger the absolute value of its corresponding second voltage offset value. The absolute value of the second voltage offset value corresponding to the edge word line within the same group can be greater than the absolute value of the second voltage offset value corresponding to the middle word line.

[0120] In some embodiments, the storage unit includes a multi-bit storage unit, which reads multi-bit stored data through a multi-stage read voltage; The second voltage offset value corresponding to each of the multi-stage reading voltages is the same; or, The second voltage offset value corresponding to some of the multi-stage read voltages is different.

[0121] Reference Figure 12a and Figure 12b As shown, for all storage states on the same word line, the second voltage offset value is applied across the entire system.

[0122] In some embodiments, at least two of the multi-order read voltages correspond to different second voltage offset values; The multi-stage read voltage is divided into multiple intervals, each interval containing a first-stage read voltage or adjacent multi-stage read voltages. The second voltage offset value corresponding to each reading voltage in one interval is the same, while the second voltage offset value corresponding to multiple reading voltages in different intervals is different.

[0123] Reference Figure 12c As shown, the memory state is divided into multiple intervals, and the second voltage offset value corresponding to the memory cell on the same word line is different under different memory states. Taking the P1 to P7 memory states of TLC as an example, only the first group of word lines and the second group of word lines are shown for illustration. For example, the 7th level read voltage of the TLC memory cell is divided into 3 intervals, and the corresponding second voltage offset value applied to the reread operation is also divided into 3 intervals. The first interval may only include the P1 state, the second interval may include the P2 to P6 states, and the third interval may include the P7 state.

[0124] Taking the write word lines falling into numbers 0 to 56 as an example, the second voltage offset value corresponding to the P1 storage state of the memory cell corresponding to the middle word line is -100mV, the second voltage offset value corresponding to the P2 to P6 states is -90mV, and the second voltage offset value corresponding to the P7 state is -80mV; the second voltage offset value corresponding to the P1 storage state of the memory cell corresponding to the edge word line is -200mV, the second voltage offset value corresponding to the P2 to P6 states is -190mV, and the second voltage offset value corresponding to the P7 state is -180mV.

[0125] In other embodiments, when the number of storage states in the memory cell is further increased, for example, in a QLC with P1 to P15, the first interval contains state P1, the second interval contains states P2 to P14, and the third interval contains state P15. Alternatively, the first interval contains states P1 to P2, the second interval contains states P3 to P13, and the third interval contains states P14 to P15. More intervals can also be divided, each containing the same or a different number of storage states, to increase the accuracy of the second voltage offset value and improve the pass rate of reread operations.

[0126] In some embodiments, each group corresponds to the plurality of intervals; for different intervals corresponding to the same group, the smaller the average order of the read voltage contained in the corresponding interval, the larger the absolute value of the offset of the second voltage offset value corresponding to the corresponding interval compared to the first voltage offset value.

[0127] Reference Figure 12c As shown, considering the division of the memory states of the memory cells corresponding to the first group of write word lines, the average order of the first interval is smaller than that of the second interval, and the average order of the second interval is smaller than that of the third interval. The absolute value of the second voltage offset corresponding to the middle word line in the first interval is the largest, followed by the second interval, and the third interval has the smallest. The variation pattern of the second voltage value for the edge word lines is the same and will not be elaborated further. In some practical embodiments, the variation pattern of the second voltage offset corresponding to the memory state may be related to the amount of charge stored in the memory cell. When the storage amount is small, a larger threshold voltage offset will occur, requiring more voltage offset values ​​for correction.

[0128] In some embodiments, the memory controller 106 is configured to: After performing the reread operation, the reread data is hardware decoded. In response to the failure of the hardware decoding operation, a software decoding operation is performed; In response to the failure of the soft decoding operation, a redundant array data recovery operation is performed.

[0129] Reference Figure 6As shown, when the memory controller 106 controls the memory device 104 to perform a read operation, it first performs a default read operation (FW default read) on the memory cell at the corresponding physical address. If the default read fails, it performs a retry operation (Read retry). If the retry operation fails, it performs a soft decode operation (Softdecode). If the soft decode operation fails, it performs a redundant array data recovery (RAID) operation. If the RAID operation fails, the read operation stops and fails because it cannot correct errors. The memory controller 106 sends a read fail signal to the host 108.

[0130] According to some aspects of embodiments of the present disclosure, a method of operating a memory system 102 is provided, with reference to Figure 13 As shown, the operation method includes: The reread voltage is obtained by using a first type of reread table and a second type of reread table. The first type of reread table includes a first voltage offset value corresponding to different conditions when one of the multiple memory blocks of the memory device is full. The second type of reread table includes a second voltage offset value corresponding to the state of each word line of one of the multiple memory blocks when it is not full, based on the first type of reread table. The rereading operation is performed using the rereading voltage.

[0131] In some embodiments, the storage block includes a first storage block, which is a storage block that is not fully written to; the step of obtaining the reread voltage using a first type of reread table and a second type of reread table includes: Using the first type of reread table, the first voltage offset value corresponding to the first storage block is obtained; Using the second type of reread table, and combining the group to which the word line coupled to the memory cell to be read in the first memory block belongs, and the distance between the word line coupled to the memory cell to be read and the first blank word line, the corresponding second voltage offset value is obtained. Based on the first voltage offset value and the second voltage offset value, the reread voltage is obtained when performing a read operation on the memory cell to be read in the first memory block.

[0132] In some embodiments, obtaining the reread voltage corresponding to the memory cell to be read in the first memory block based on the first voltage offset value and the second voltage offset value includes: The first voltage offset value and the second voltage offset value are summed to obtain the total offset voltage value; The reread voltage is obtained by summing the default read voltage with the total offset voltage value.

[0133] In some embodiments, the memory block includes word lines 0 to N, numbered sequentially according to their physical location; the memory block is programmed in the order of word lines 0 to N; where N is an integer greater than 2. The memory block contains all word lines divided into multiple groups, each group containing multiple adjacent word lines; All word lines in the first memory block include: the first word line, edge word lines adjacent to the first blank word line, and intermediate word lines spaced apart from the first blank word line; wherein the edge word lines falling into different groups have different second voltage offset values, and the intermediate word lines falling into different groups have different second voltage offset values.

[0134] In some embodiments, each group contains the same or similar number of word lines.

[0135] In some embodiments, the edge word lines and the middle word lines fall into the same group and have different second voltage offset values.

[0136] In some embodiments, the closer the middle character line is to the 0th character line, the greater the absolute value of the second voltage offset value corresponding to the group into which the middle character line falls compared to the first voltage offset value. The closer the edge word line is to the 0th word line, the greater the absolute value of the second voltage offset value in the second type of reread table corresponding to the group into which the edge word line falls compared to the first voltage offset value. When the edge character line and the middle character line fall into the same group, the absolute value of the offset of the second voltage offset value corresponding to the edge character line relative to the first voltage offset value is greater than the absolute value of the offset of the second voltage offset value corresponding to the middle character line relative to the first voltage offset value.

[0137] In some embodiments, the storage unit includes a multi-bit storage unit, which reads multi-bit stored data through a multi-stage read voltage; The second voltage offset value corresponding to each of the multi-stage reading voltages is the same; or, The second voltage offset value corresponding to some of the multi-stage read voltages is different.

[0138] In some embodiments, at least two of the multi-order read voltages correspond to different second voltage offset values; The multi-stage read voltage is divided into multiple intervals, each interval containing a first-stage read voltage or adjacent multi-stage read voltages. The second voltage offset value corresponding to each reading voltage in one interval is the same, while the second voltage offset value corresponding to multiple reading voltages in different intervals is different.

[0139] In some embodiments, each group corresponds to the plurality of intervals; for different intervals corresponding to the same group, the smaller the average order of the read voltage contained in the corresponding interval, the larger the absolute value of the offset of the second voltage offset value corresponding to the corresponding interval compared to the first voltage offset value.

[0140] In some embodiments, the memory device 104 includes multiple types of memory pages; the different cases include at least one of the following: The storage unit includes different storage bits; The storage pages include different types; Different use cases of the memory device 104.

[0141] In some embodiments, the operating method further includes: After performing the reread operation, the reread data is hardware decoded. In response to the failure of the hardware decoding operation, a software decoding operation is performed; In response to the failure of the soft decoding operation, a redundant array data recovery operation is performed.

[0142] According to some aspects of embodiments of this disclosure, a readable storage medium is provided that stores a computer program, which, when executed, implements the operation methods described in the above embodiments. The readable storage medium may include NAND flash memory, and the storage cells of the NAND flash memory may include floating-gate type storage cells with floating-gate transistors, or charge-trapping type storage cells with charge-trapping transistors.

[0143] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A memory system, characterized in that, include: A memory device, the memory device including a memory block, the memory block including a plurality of word lines and a plurality of memory cells coupled to the plurality of word lines; and A memory controller, coupled to the memory device, is configured to: The read voltage is obtained based on a first voltage offset table and a second voltage offset table; the first voltage offset table includes voltage offset values ​​under different conditions when the memory block is in a full state; the second voltage offset table includes voltage offset values ​​of word lines at different positions based on the first table when the memory block is in a non-full state. and The memory device is controlled to perform a read operation based on the read voltage.

2. The memory system according to claim 1, characterized in that, Both the first voltage offset table and the second voltage offset table are reread tables, and the read operation performed based on the read voltage is a reread operation.

3. The memory system according to claim 1, characterized in that, The storage block includes a partially written storage block. To perform the read operation on the partially written storage block, the memory controller is configured to: Based on the first voltage offset table, obtain the first voltage offset value related to the memory cell to be read in the unwritten memory block; Based on the second voltage offset table, the group to which the word line coupled to the memory cell to be read belongs, and the relationship between the word line coupled to the memory cell to be read and the first blank word line, the second voltage offset value corresponding to reading the memory cell to be read is obtained. Based on the first voltage offset value and the second voltage offset value, the read voltage is obtained when the read operation is performed on the memory cell to be read.

4. The memory system according to claim 3, characterized in that, The memory controller is configured to: The first voltage offset value and the second voltage offset value are summed to obtain the total offset voltage value; The default read voltage is summed with the total offset voltage value to obtain the read voltage when performing the read operation on the memory cell to be read.

5. The memory system according to claim 3, characterized in that, The storage block includes word lines 0 to N, numbered sequentially according to their physical location; the storage block is programmed in the order of word lines 0 to N. N is an integer greater than 2; The 0th to the Nth word lines are divided into multiple word line groups, and each word line group contains at least two adjacent word lines; In the unfilled memory block, word lines 0 to N include: the first blank word line, the edge word line adjacent to the first blank word line, and the intermediate word line that is spaced apart from the first blank word line; wherein the edge word lines fall into different groups, and the corresponding voltage offset values ​​in the second voltage offset table are different.

6. The memory system according to claim 5, characterized in that, The second voltage offset value corresponding to the word line coupled to the memory cell to be read is the edge word line and the second voltage offset value corresponding to the word line coupled to the memory cell to be read is the middle word line.

7. The memory system according to claim 6, characterized in that, The absolute value of the offset of the second voltage offset value relative to the first voltage offset value when the word line coupled to the memory cell to be read is the edge word line is greater than the absolute value of the offset of the second voltage offset value relative to the first voltage offset value when the word line coupled to the memory cell to be read is the middle word line.

8. The memory system according to claim 5, characterized in that, The closer the intermediate word line is to the 0th word line, the greater the absolute value of the second voltage offset value corresponding to the word line coupled to the memory cell to be read being the intermediate word line, compared to the first voltage offset value.

9. The memory system according to claim 5, characterized in that, The closer the edge word line is to the 0th word line, the greater the absolute value of the second voltage offset value corresponding to the word line coupled to the memory cell to be read being the edge word line, compared to the first voltage offset value.

10. The memory system according to claim 5, characterized in that, Each of the storage cells is configured to store multiple bits of data, which are read through a multi-stage readout voltage. The second voltage offset value corresponding to each of the multi-stage reading voltages is the same; or, The second voltage offset value corresponding to some of the multi-stage read voltages is different.

11. The memory system according to claim 10, characterized in that, At least two of the multi-stage read voltages correspond to different second voltage offset values; The multi-stage read voltage is divided into multiple intervals, each interval containing a first-stage read voltage or at least two adjacent read voltages. The second voltage offset value corresponding to each reading voltage in one interval is the same, while the second voltage offset value corresponding to multiple reading voltages in different intervals is different.

12. The memory system according to claim 11, characterized in that, Each group corresponds to the plurality of intervals; for different intervals corresponding to the same group, the smaller the average order of the read voltage contained in the corresponding interval, the larger the absolute value of the offset of the second voltage offset value corresponding to the corresponding interval compared with the first voltage offset value.

13. The memory system according to claim 1, characterized in that, The memory device includes multiple types of memory pages; the different cases include at least one of the following: The storage unit is configured to store different numbers of bits of data; The storage pages include different types; Different use cases of the memory device.

14. The memory system according to claim 1, characterized in that, The memory controller is configured to: After controlling the memory device to perform the read operation based on the read voltage, the read data is then hard-decoded. In response to the failure of the hardware decoding operation, a software decoding operation is performed; In response to the failure of the soft decoding operation, a redundant array data recovery operation is performed.

15. A method for operating a memory system, characterized in that, include: The read voltage is obtained based on the first voltage offset table and the second voltage offset table; The first voltage offset table includes voltage offset values ​​under different conditions when the memory blocks of the memory device are in a full state; The second voltage offset table includes the voltage offset values ​​of word lines at different positions when the memory block is in a non-full state, based on the voltage offset values ​​corresponding to the first voltage offset table; The read operation is performed based on the read voltage.

16. The operating method according to claim 15, characterized in that, Both the first voltage offset table and the second voltage offset table are reread tables, and the read operation performed based on the read voltage is a reread operation.

17. The operating method according to claim 15, characterized in that, The storage block includes storage blocks that are not fully written to; obtaining the read voltage based on the first voltage offset table and the second voltage offset table includes: Based on the first voltage offset table, obtain the first voltage offset value related to the memory cell to be read in the unwritten memory block; Based on the second voltage offset table, the group to which the word line coupled to the memory cell to be read belongs, and the relationship between the word line coupled to the memory cell to be read and the first blank word line, the second voltage offset value corresponding to reading the memory cell to be read is obtained. Based on the first voltage offset value and the second voltage offset value, the read voltage is obtained when the read operation is performed on the memory cell to be read.

18. The operating method according to claim 17, characterized in that, The step of obtaining the read voltage when performing the read operation on the memory cell to be read based on the first voltage offset value and the second voltage offset value includes: The first voltage offset value and the second voltage offset value are summed to obtain the total offset voltage value; The default read voltage is summed with the total offset voltage value to obtain the read voltage when performing the read operation on the memory cell to be read.

19. The operating method according to claim 17, characterized in that, The storage block includes word lines 0 to N, numbered sequentially according to their physical location; the storage block is programmed in the order of word lines 0 to N. N is an integer greater than 2; The 0th to the Nth word lines are divided into multiple word line groups, and each word line group contains at least two adjacent word lines; In the unfilled memory block, word lines 0 to N include: the first blank word line, the edge word line adjacent to the first blank word line, and the intermediate word line that is spaced apart from the first blank word line; wherein the edge word lines fall into different groups, and the corresponding voltage offset values ​​in the second voltage offset table are different.

20. The operating method according to claim 19, characterized in that, The second voltage offset value corresponding to the word line coupled to the memory cell to be read is the edge word line and the second voltage offset value corresponding to the word line coupled to the memory cell to be read is the middle word line.

21. The operating method according to claim 20, characterized in that, The absolute value of the offset of the second voltage offset value relative to the first voltage offset value when the word line coupled to the memory cell to be read is the edge word line is greater than the absolute value of the offset of the second voltage offset value relative to the first voltage offset value when the word line coupled to the memory cell to be read is the middle word line.

22. The operating method according to claim 19, characterized in that, The closer the intermediate word line is to the 0th word line, the greater the absolute value of the second voltage offset value corresponding to the word line coupled to the memory cell to be read being the intermediate word line, compared to the first voltage offset value.

23. The operating method according to claim 19, characterized in that, The closer the edge word line is to the 0th word line, the greater the absolute value of the second voltage offset value corresponding to the word line coupled to the memory cell to be read being the edge word line, compared to the first voltage offset value.

24. The operating method according to claim 19, characterized in that, Each of the storage cells is configured to store multiple bits of data, which are read through a multi-stage readout voltage. The second voltage offset value corresponding to each of the multi-stage reading voltages is the same; or, The second voltage offset value corresponding to some of the multi-stage read voltages is different.

25. The operating method according to claim 24, characterized in that, At least two of the multi-stage read voltages correspond to different second voltage offset values; The multi-stage read voltage is divided into multiple intervals, each interval containing a first-stage read voltage or at least two adjacent read voltages. The second voltage offset value corresponding to each reading voltage in one interval is the same, while the second voltage offset value corresponding to multiple reading voltages in different intervals is different.

26. The operating method according to claim 25, characterized in that, Each group corresponds to the plurality of intervals; for different intervals corresponding to the same group, the smaller the average order of the read voltage contained in the corresponding interval, the larger the absolute value of the offset of the second voltage offset value corresponding to the corresponding interval compared with the first voltage offset value.

27. The operating method according to claim 15, characterized in that, The memory device includes multiple types of memory pages, and the memory block includes multiple memory cells; the different cases include at least one of the following: The storage unit is configured to store different numbers of bits of data; The storage pages include different types; Different use cases of the memory device.

28. The operating method according to claim 15, characterized in that, The operation method further includes: After performing the read operation based on the read voltage, the read data is then subjected to hardware decoding. In response to the failure of the hardware decoding operation, a software decoding operation is performed; In response to the failure of the soft decoding operation, a redundant array data recovery operation is performed.

29. A memory system, characterized in that, include: A memory device, the memory device including a memory block, the memory block including a plurality of word lines and a plurality of memory cells coupled to the plurality of word lines; and A memory controller, coupled to the memory device, is configured to: Based on the first voltage offset value of a full memory block under a certain condition, and the second voltage offset value corresponding to the position of the word line coupled to the memory cell to be read in the unfulfilled memory block, the read voltage when reading the memory cell to be read in the unfulfilled memory block is obtained. and Based on the read voltage, the memory device is controlled to perform a read operation on the memory cell to be read in the unwritten memory block.

30. The memory system according to claim 29, characterized in that, The memory controller is configured to: The first voltage offset value and the second voltage offset value are summed to obtain the total offset voltage value; The default read voltage is summed with the total offset voltage value to obtain the read voltage when performing the read operation on the memory cell to be read.

31. The memory system according to claim 29, characterized in that, The storage block includes word lines 0 to N, numbered sequentially according to their physical location; the storage block is programmed in the order of word lines 0 to N. N is an integer greater than 2; The 0th to the Nth word lines are divided into multiple word line groups, and each word line group contains at least two adjacent word lines; In the unfilled memory block, the 0th word line to the Nth word line include: the first blank word line, the edge word line adjacent to the first blank word line, and the intermediate word line that is spaced apart from the first blank word line; wherein, the edge word lines fall into different groups and the second voltage offset value is different.

32. The memory system according to claim 31, characterized in that, The second voltage offset value corresponding to the word line coupled to the memory cell to be read is the edge word line and the second voltage offset value corresponding to the word line coupled to the memory cell to be read is the middle word line.

33. The memory system according to claim 32, characterized in that, The absolute value of the offset of the second voltage offset value relative to the first voltage offset value when the word line coupled to the memory cell to be read is the edge word line is greater than the absolute value of the offset of the second voltage offset value relative to the first voltage offset value when the word line coupled to the memory cell to be read is the middle word line.

34. The memory system according to claim 31, characterized in that, The closer the intermediate word line is to the 0th word line, the greater the absolute value of the second voltage offset value corresponding to the word line coupled to the memory cell to be read being the intermediate word line, compared to the first voltage offset value.

35. The memory system according to claim 31, characterized in that, The closer the edge word line is to the 0th word line, the greater the absolute value of the second voltage offset value corresponding to the word line coupled to the memory cell to be read being the edge word line, compared to the first voltage offset value.

36. The memory system according to claim 31, characterized in that, Each of the storage cells is configured to store multiple bits of data, which are read through a multi-stage readout voltage. The second voltage offset value corresponding to each of the multi-stage reading voltages is the same; or, The second voltage offset value corresponding to some of the multi-stage read voltages is different.

37. The memory system according to claim 36, characterized in that, At least two of the multi-stage read voltages correspond to different second voltage offset values; The multi-stage read voltage is divided into multiple intervals, each interval containing a first-stage read voltage or at least two adjacent read voltages. The second voltage offset value corresponding to each reading voltage in one interval is the same, while the second voltage offset value corresponding to multiple reading voltages in different intervals is different.

38. The memory system according to claim 37, characterized in that, Each group corresponds to the plurality of intervals; for different intervals corresponding to the same group, the smaller the average order of the read voltage contained in the corresponding interval, the larger the absolute value of the offset of the second voltage offset value corresponding to the corresponding interval compared with the first voltage offset value.

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