A ring-shaped photonic crystal-based chip and a preparation method thereof

Abstract

This application relates to the field of chip fabrication technology and provides a chip based on a ring photonic crystal and its fabrication method. The fabrication method includes: growing a nucleation layer on a substrate; growing a superlattice structure; sequentially growing an n-type cladding layer, an n-type waveguide layer, a quantum well, a p-type electron blocking layer, and a p-type extended contact layer; in-situ annealing; etching patterned grooves on the p-type extended contact layer to form multiple columnar structures; sequentially and periodically growing Al2O3 and SiO2 layers on the bottom and sidewalls of the patterned grooves to form a ring photonic crystal; growing a patterned transparent conductive layer on the surface of the columnar structures; and growing patterned electrodes. This fabrication method can effectively adjust the directionality of the photonic bandgap, forming a uniform light wave from all sides, thereby suppressing laser leakage from non-emitting areas on the sides and improving light extraction efficiency. Furthermore, the periodic distribution of the ring photonic crystal ensures a high degree of matching with the laser mode emitted from the sides, effectively guaranteeing beam quality.

Description

Technical Field

[0001] This application relates to the field of chip fabrication technology, and in particular to a chip based on a ring photonic crystal and its fabrication method. Background Technology

[0002] Photonic crystals play a crucial role in chips, becoming one of the key enabling technologies for miniaturized, high-performance, and low-power optoelectronic devices and integrated systems through their unique photonic bandgap characteristics.

[0003] The photonic bandgap is a core characteristic of photonic crystals. By designing periodic dielectric structures, the propagation of light waves of specific wavelengths can be confined. Existing side-emitting lasers mostly use ordinary photonic crystals (such as strip or square lattice structures) for light confinement, attempting to reduce light escape through the photonic bandgap effect. However, these non-ring structures have inherent defects: their photonic bandgap has insufficient directional control, making it difficult to uniformly confine light waves from all sides, resulting in some laser leakage from the non-emitting areas on the side, reducing the effective extraction efficiency of the emitting surface; at the same time, the periodic distribution of the non-ring structure has a low matching degree with the laser mode of side-emitting lasers, which easily leads to mode disorder, further affecting the extraction efficiency and beam quality. Summary of the Invention

[0004] This application provides a chip based on a ring photonic crystal and its fabrication method, which effectively improves light extraction efficiency and ensures beam quality.

[0005] In a first aspect, the method for fabricating a chip based on a ring photonic crystal provided in this application includes: growing a nucleation layer on a substrate; the growth temperature of the nucleation layer is a first temperature; growing a superlattice structure on the nucleation layer; the growth temperature of the superlattice structure is a second temperature, wherein the first temperature is lower than the second temperature; sequentially growing an n-type cladding layer, an n-type waveguide layer, a quantum well, a p-type electron blocking layer, and a p-type extended contact layer on the superlattice structure; wherein the Al composition in the n-type cladding layer gradually decreases from the side closer to the superlattice structure to the side farther away from the superlattice structure; performing in-situ annealing; and using inductively coupled plasma technology to... Patterned grooves are etched on the p-type extended contact layer to form multiple columnar structures. These columnar structures are arranged in an array, with a height greater than zero and less than or equal to the sum of the thicknesses of the p-type extended contact layer, the p-type electron blocking layer, and the quantum well. Al₂O₃ and SiO₂ layers are periodically grown at the bottom and sidewalls of the patterned grooves to form a ring-shaped photonic crystal. The surfaces of the Al₂O₃ and SiO₂ layers facing away from the bottom of the patterned grooves are on the same horizontal plane as the surfaces of the columnar structures. A patterned transparent conductive layer is grown on the surface of the columnar structures. Patterned electrodes are then grown on the patterned transparent conductive layer.

[0006] In some feasible implementations, patterned grooves are etched on the p-type extended contact layer using inductively coupled plasma (ICP-P) technology to form multiple columnar structures. This includes: coating a first mask layer on the p-type extended contact layer; etching multiple first grooves on the first mask layer using photolithography to form a patterned first mask layer; arranging the multiple first grooves in an array, with the etching depth of the multiple first grooves being the same as the coating thickness of the first mask layer; etching the patterned first mask layer using ICP-P to form patterned grooves; the etching depth of the patterned grooves being less than or equal to the sum of the thicknesses of the p-type extended contact layer, the p-type electron blocking layer, and the quantum well; and forming multiple columnar structures inside the patterned grooves.

[0007] In some feasible implementations, a patterned transparent conductive layer is grown on the surface of the columnar structure, including: growing a transparent conductive layer on the surface of the p-type extended contact layer, the Al2O3 layer, and the SiO2 layer; coating a second mask layer on the transparent conductive layer; etching multiple second grooves on the second mask layer using photolithography to form a patterned second mask layer; arranging the multiple second grooves in an array, with each second groove corresponding to a columnar structure; etching the patterned second mask layer using inductively coupled plasma technology to form a patterned transparent conductive layer; the etching depth of the patterned second mask layer is the sum of the thicknesses of the second mask layer and the transparent conductive layer.

[0008] In some feasible implementations, the distance between any two adjacent columnar structures is 40μm-100μm.

[0009] In some feasible implementations, the Al composition in the p-type extended contact layer gradually decreases from the side closer to the p-type electron blocking layer to the side farther away from the p-type electron blocking layer.

[0010] In some feasible implementations, the number of periods of the quantum well is 2-10; the quantum well includes a well structure and a barrier structure grown sequentially; after the well structure is grown, the well structure is flushed with NH3 atmosphere for a first preset time, and the barrier structure is regrown, wherein the Al component in the barrier structure is greater than the Al component in the well structure.

[0011] In some feasible implementations, the fabrication method of the chip based on the ring photonic crystal further includes baking the substrate in an H2 atmosphere for a second preset time before growing the nucleation layer on the substrate.

[0012] The method for fabricating a chip based on a ring photonic crystal provided in the first aspect of this application can effectively adjust the directionality of the photonic bandgap, forming a uniform light wave in all directions from the side, thereby suppressing laser leakage from the non-light-emitting area on the side and improving the light-emitting efficiency. Moreover, the ring photonic crystal is periodically distributed and has a high degree of matching with the laser mode emitted from the side, effectively ensuring the beam quality.

[0013] Secondly, this application provides another method for fabricating a chip based on a ring photonic crystal, comprising: growing a nucleation layer on a substrate; the growth temperature of the nucleation layer being a first temperature; sequentially growing a superlattice structure, an n-type cladding layer, an n-type waveguide layer, and a quantum well on the nucleation layer; the growth temperature of the superlattice structure being a second temperature, wherein the first temperature is lower than the second temperature; etching patterned grooves on the quantum well using inductively coupled plasma technology to form multiple columnar structures; wherein the multiple columnar structures are arranged in an array, and the height of the columnar structures is greater than zero and less than or equal to the thickness of the quantum well; and at the bottom of the patterned grooves... Al2O3 and SiO2 layers are periodically grown on the sidewalls to form a ring-shaped photonic crystal. The surfaces of the Al2O3 and SiO2 layers facing away from the bottom of the patterned groove are on the same horizontal plane as the surface of the columnar structure. A p-type electron blocking layer and a p-type extended contact layer are sequentially grown on the quantum well. In-situ annealing is then performed. A patterned transparent conductive layer is grown on the p-type extended contact layer. The cross-sectional shape of the patterned transparent conductive layer is the same as that of the columnar structure, and the patterned transparent conductive layer and the columnar structure are arranged in a one-to-one correspondence. Patterned electrodes are grown on the patterned transparent conductive layer.

[0014] Thirdly, this application provides another chip based on a ring-shaped photonic crystal, comprising: a substrate; a nucleation layer grown on the substrate; the nucleation layer being grown at a first temperature; a superlattice structure grown on the side of the nucleation layer away from the substrate; the superlattice structure being grown at a second temperature, the first temperature being lower than the second temperature; an n-type cladding layer grown on the side of the superlattice structure away from the nucleation layer; the Al composition in the n-type cladding layer gradually decreasing from the side closer to the superlattice structure to the side farther away from the superlattice structure; an n-type waveguide layer grown on the side of the n-type cladding layer away from the superlattice structure; a quantum well grown on the side of the n-type waveguide layer away from the n-type cladding layer; and a p-type electron blocking layer. A p-type extended contact layer is grown on the side of the quantum well away from the n-type waveguide layer; a p-type extended contact layer is grown on the side of the p-type electron blocking layer away from the quantum well; a patterned groove is formed in the quantum well or at least in the p-type extended contact layer; multiple columnar structures are formed inside the patterned groove; the multiple columnar structures are arranged in an array; a ring-shaped photonic crystal is grown in the patterned groove; the ring-shaped photonic crystal includes periodically grown Al2O3 layers and SiO2 layers; a patterned transparent conductive layer is grown on the columnar structures; and the patterned transparent conductive layer is arranged in a one-to-one correspondence with the columnar structures; a patterned electrode is grown on the patterned transparent conductive layer; and the patterned electrode is arranged in a one-to-one correspondence with the patterned transparent conductive layer.

[0015] In some feasible implementations, a ring-shaped photonic crystal is disposed in a quantum well, with the height of the ring-shaped photonic crystal being greater than zero and less than or equal to the thickness of the quantum well; or, a ring-shaped photonic crystal is disposed in a p-type extended contact layer, with the height of the ring-shaped photonic crystal being greater than zero and less than or equal to the thickness of the p-type extended contact layer; or, a ring-shaped photonic crystal is disposed in a p-type extended contact layer, a p-type electron blocking layer, and a quantum well, with the height of the ring-shaped photonic crystal being greater than the thickness of the p-type extended contact layer and less than or equal to the sum of the thicknesses of the p-type extended contact layer, the p-type electron blocking layer, and the quantum well.

[0016] The beneficial technical effects of the second and third aspects can be found in the first aspect, and will not be repeated here. Attached Figure Description

[0017] To more clearly illustrate the technical solution of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic flowchart of the first method for fabricating a chip based on a ring photonic crystal provided in this application embodiment;

[0019] Figure 2 This is one of the process schematic diagrams of the first method for fabricating a chip based on a ring photonic crystal provided in the embodiments of this application;

[0020] Figure 3 This is a schematic diagram of the fabrication process of the first type of ring photonic crystal provided in the embodiments of this application;

[0021] Figure 4A This is the second schematic diagram of the process for fabricating a chip based on a ring photonic crystal, as provided in the embodiments of this application.

[0022] Figure 4B It is a kind of Figure 4A A schematic diagram of the columnar structure in the diagram;

[0023] Figure 4C It is another kind Figure 4A A schematic diagram of the columnar structure in the diagram;

[0024] Figure 5 This is a schematic diagram of the graphic groove provided in an embodiment of this application;

[0025] Figure 6AThis is the third schematic diagram of the process for fabricating a chip based on a ring photonic crystal, as provided in the embodiments of this application.

[0026] Figure 6B This is a schematic diagram of the structure of the first type of ring photonic crystal provided in the embodiments of this application;

[0027] Figure 7 This is the fourth schematic diagram of the process for fabricating a chip based on a ring photonic crystal, as provided in the embodiments of this application.

[0028] Figure 8 yes Figure 7 The top view shown in (d) is shown in the middle.

[0029] Figure 9 This is the fifth schematic diagram of the process for fabricating a chip based on a ring photonic crystal, as provided in the embodiments of this application.

[0030] Figure 10 This is a schematic flowchart of the second method for fabricating a chip based on a ring photonic crystal provided in the embodiments of this application;

[0031] Figure 11 This is one of the process schematic diagrams of the second method for fabricating a chip based on a ring photonic crystal provided in the embodiments of this application;

[0032] Figure 12 This is a schematic diagram of the structure of a chip based on a ring photonic crystal provided in an embodiment of this application.

[0033] Illustration markings:

[0034] 100. Chips based on ring photonic crystals;

[0035] 101. Substrate; 102. Nucleation layer; 103. Superlattice structure; 104. n-type cladding layer; 105. n-type waveguide layer; 106. Quantum well; 107. p-type electron blocking layer; 108. p-type extended contact layer; 10a. Patterned groove; 10b. Columnar structure; 10b-1. First columnar structure; 10b-2. Second columnar structure; 10b-3. Third columnar structure; 10c. Ring photonic crystal; 10c-1. First ring photonic crystal; 10c-2. Second ring photonic crystal; 10c-3. Third ring photonic crystal; c1. Al2O3 layer; c2. SiO2 layer; 109. Patterned transparent conductive layer; 110. Patterned electrode. Detailed Implementation

[0036] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are all within the protection scope of this application.

[0037] In the following description, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0038] Furthermore, in this application, directional terms such as "upper," "lower," "inner," and "outer" are defined relative to the indicated placement of the components in the accompanying drawings. It should be understood that these directional terms are relative concepts, used for relative description and clarification, and can change accordingly depending on the placement of the components in the accompanying drawings.

[0039] With the rise of 3D printing, the requirements for photopolymerization technology are gradually increasing, making the core requirement for stable product quality—deep ultraviolet (light emitting diode, LED)—more urgent. Compared with traditional ultraviolet mercury lamps, deep ultraviolet LEDs have outstanding advantages such as small size, energy saving and environmental protection (mercury-free), instant switching, ultra-long lifespan, and precisely customizable wavelength. This makes deep ultraviolet LEDs particularly crucial for addressing the issues of "surface curing" and "high-precision curing."

[0040] In deep ultraviolet (DUV) LEDs, light extraction in the transverse magnetic mode (TM) is a core technological challenge. As the emission wavelength of DUV LEDs shortens, their emission characteristics gradually shift from being dominated by the common transverse electric mode (TE) to being dominated by the TM mode. In the TM mode, photons are mainly emitted from the side of the chip, significantly reducing the light extraction efficiency at the emitting surface.

[0041] The essence of a photonic crystal lies in the periodic arrangement of its dielectric constant in space. When light propagates within it, it encounters countless interfaces with abrupt changes in refractive index, resulting in scattering at each interface. For light of a specific frequency (whose wavelength is comparable to the lattice constant), these wavelets scattered from different lattice planes satisfy the condition of coherent destructive interference in a specific propagation direction. When the optical path difference between adjacent scattering paths is an odd multiple of half the wavelength, these scattered waves are out of phase. In a perfectly periodic structure, this destructive interference effect works synergistically and superimposes throughout the entire space, ultimately preventing light waves of that frequency from forming a stable propagation mode. This suppression capability is directly determined by the lattice constant, structural symmetry, and the refractive index contrast of the medium; high contrast is key to generating a wide and strong photonic bandgap.

[0042] The photonic bandgap is a core characteristic of photonic crystals. By designing periodic dielectric structures, the propagation of light waves of specific wavelengths can be confined. Existing side-emitting lasers mostly use ordinary photonic crystals (such as strip or square lattice structures) for light confinement, attempting to reduce light escape through the photonic bandgap effect. However, these non-ring structures have inherent defects: their photonic bandgap has insufficient directional control, making it difficult to uniformly confine light waves from all sides, resulting in some laser leakage from the non-emitting areas on the side, reducing the effective extraction efficiency of the emitting surface; at the same time, the periodic distribution of the non-ring structure has a low matching degree with the laser mode of side-emitting lasers, which easily leads to mode disorder, further affecting the extraction efficiency and beam quality.

[0043] To address the aforementioned technical problems, this application provides a chip based on a ring photonic crystal and its fabrication method, which can effectively improve light extraction efficiency and ensure beam quality.

[0044] Figure 1 This is a schematic flowchart of the first method for fabricating a chip based on a ring photonic crystal provided in this application embodiment; Figure 2 This is one of the process schematic diagrams of the first method for fabricating a chip based on a ring photonic crystal provided in the embodiments of this application.

[0045] See Figure 1 and Figure 2 As shown, the first method for fabricating a chip based on a ring photonic crystal provided in this application embodiment may include the following steps S11 to S18.

[0046] Step S11: Growing a nucleation layer 102 on substrate 101.

[0047] In this step, metal-organic chemical vapor deposition (MOCVD) technology can be used to epitaxially grow a nucleation layer 102 on the substrate 101, which can form a high-density island nucleus to reduce subsequent high-temperature layer dislocations.

[0048] The nucleation layer 102 can be aluminum nitride (AlN). The growth environment of the nucleation layer 102 may include: a pressure of 100 mbar, a flow rate of trimethylaluminum (TMAl) of 25 standard milliliters per minute (sccm), and a flow rate of ammonia (NH3) of 3000 standard milliliters per minute (sccm).

[0049] In some feasible implementations, the growth temperature of the nucleation layer 102 is a first temperature, which can be set between 550℃ and 650℃.

[0050] For example, the first temperature can be one of 550°C, 575°C, 600°C, 625°C, or 650°C. Of course, the first temperature can also be any other value between 550°C and 650°C.

[0051] In some feasible implementations, the growth thickness of the nucleation layer 102 can be 20nm-50nm.

[0052] For example, the thickness of the nucleation layer 102 can be 20 nm, 30 nm, 40 nm, or 50 nm. Of course, the thickness of the nucleation layer 102 can also be other values ​​between 20 nm and 50 nm.

[0053] In one specific implementation, the nucleation layer 102 is grown at a temperature of 600℃ and has a thickness of 30nm.

[0054] Step S12: Grow a superlattice structure 103 on the nucleation layer 102; the growth temperature of the superlattice structure 103 is the second temperature, and the first temperature is lower than the second temperature.

[0055] In this step, periodic superlattice structures 103 are alternately grown on the nucleation layer 102 using MOCVD technology for stress relief and dislocation filtering.

[0056] The superlattice structure 103 includes an AlN layer and an AlGaN layer (not shown in the figure). The AlN layer and the AlGaN layer have the same growth thickness. The growth environment of the AlN layer and the AlGaN layer may include: a pressure of 50 mbar, a flow rate of trimethylaluminum™Al of 40 sccm, and a flow rate of ammonia (NH3) of 5000 sccm.

[0057] In some feasible implementations, the growth temperature of the superlattice structure 103 is a second temperature, which is higher than the first temperature. The second temperature can be set between 800℃ and 1400℃.

[0058] For example, the second temperature can be one of 800°C, 900°C, 1000°C, 1100°C, or 1400°C. Of course, the second temperature can also be any other value between 800°C and 1400°C.

[0059] In some feasible implementations, the AlN and AlGaN layers in each period of the superlattice structure 103 have the same thickness, ranging from 5 nm to 20 nm.

[0060] For example, the thickness of the AlN and AlGaN layers can be 5 nm, 10 nm, 15 nm, or 20 nm. Of course, the thickness of the AlN and AlGaN layers can also be other values ​​between 5 nm and 20 nm.

[0061] In some feasible implementations, the superlattice structure 103 has a period number of 2-10.

[0062] For example, the number of periods in the superlattice structure 103 can be 2, 3, 4, 5, 6, 7, 8, 9 or 10.

[0063] In one specific implementation, the growth temperature of the superlattice structure 103 is 1250℃, the thickness of the AlN layer and the AlGaN layer in each period is 10nm, the number of periods of the superlattice structure 103 is 5, and the growth thickness of the superlattice structure 103 is 5×(10nm+10nm)=1.0µm.

[0064] Step S13: An n-type cladding layer 104, an n-type waveguide layer 105, a quantum well 106, a p-type electron blocking layer 107, and a p-type extended contact layer 108 are sequentially grown on the superlattice structure 103.

[0065] Specifically, in step S13, the growth of each structural layer can be performed using MOCVD technology. Step S13 may include steps S131 to S137.

[0066] Step S131: An n-type cladding layer 104 is grown on the superlattice structure 103. The Al composition in the n-type cladding layer 104 gradually decreases from the side closer to the superlattice structure 103 to the side farther away. That is, the Al composition in the n-type cladding layer 104 gradually decreases along the growth direction to reduce the polarization field and lower the series resistance.

[0067] In this step, the n-type cladding layer 104 can be an n-type doped aluminum gallium nitride alloy (n-Al). 0.4 Ga 0.6In the n-type cladding layer 104, the Al composition gradually decreases from the side closer to the superlattice structure 103 to the side closer to the n-type waveguide layer 105. The initial molar fraction of Al is 40%, the initial molar fraction of Ga is 60%, the final molar fraction of Al is 30%, and the final molar fraction of Ga is 70%. Along the growth direction of the n-type cladding layer 104, the Al composition gradually decreases from 40% to 30%. The growth environment of the n-type cladding layer 104 may include: a pressure of 200 mbar and a SiH4 doping concentration of 5 × 10⁻⁶. 18 cm -3 .

[0068] In some feasible implementations, the growth temperature of the n-type coating 104 can be between 800℃ and 1200℃.

[0069] For example, the growth temperature of the n-type coating 104 can be one of 800℃, 900℃, 1000℃, 1100℃, or 1200℃. Of course, the growth temperature of the n-type coating 104 can also be other values ​​between 800℃ and 1200℃.

[0070] In some feasible implementations, the growth thickness of the n-type coating layer 104 can be between 0.5 μm and 1.5 μm.

[0071] For example, the growth thickness of the n-type coating 104 can be 0.5 μm, 1.0 μm, or 1.5 μm. Of course, the thickness of the n-type coating 104 can also be other values ​​between 0.5 μm and 1.5 μm.

[0072] In one specific implementation, the n-type coating layer 104 is grown at a temperature of 1020℃ and has a thickness of 1.0 μm.

[0073] Step S132: Grow an n-type waveguide layer 105 on the n-type cladding layer 104.

[0074] In this step, the n-type waveguide layer 105 is an n-type doped aluminum gallium nitride alloy (n-Al). 0.3 Ga 0.7 N, wherein the growth environment of the n-type waveguide layer 105 can be the same as that of the n-type cladding layer 104, and the growth thickness of the n-type waveguide layer 105 can be 80 nm.

[0075] Step S133: Grow a quantum well 106 on the n-type waveguide layer 105.

[0076] In this step, the quantum well 106 can be a periodic structure, with each period including a well structure and a barrier structure (not shown in the figure) grown sequentially. Step S133 may include steps S1331 to S1333.

[0077] Step S1331: Grow a well structure on the n-type waveguide layer 105.

[0078] In this step, the growth environment of the trap structure includes: growth pressure maintained at 150 mbar, source flow rate: 18 sccm for TMAl, 12 sccm for trimethylgallium TMGa, and 6000 sccm for NH3.

[0079] Step S1332: Use NH3 atmosphere to flush the trap structure for the first preset time.

[0080] In this step, the purpose of flushing the trap structure is to suppress AlGaN intermixing. The first preset time can be 1s-5s.

[0081] In one specific implementation, the first preset time can be 2 seconds.

[0082] Step S1333: Grow a barrier structure on the well structure.

[0083] In this step, the growth environment for the well structure and the barrier structure is the same, but the Al composition in the barrier structure is greater than that in the well structure to provide sufficient band-level confinement carriers. The well structure can be Al... 0.25 Ga 0.75 N, the barrier structure can be Al 0.45 Ga 0.55 N.

[0084] In some feasible implementations, the growth temperature of the quantum well 106 can be 600℃-1000℃.

[0085] For example, the growth temperature of quantum well 106 can be 600°C, 800°C, or 1000°C. Of course, the growth temperature of quantum well 106 can also be other values ​​between 600°C and 1000°C.

[0086] In one specific implementation, the growth temperature of the quantum well 106 is 880°C.

[0087] In some feasible implementations, the growth thickness of the well structure can be 1nm-4nm, the growth thickness of the barrier structure can be 10nm-15nm, and the number of periods of the quantum well 106 can be 2-10.

[0088] For example, the growth thickness of the well structure can be 2 nm, 3 nm or 4 nm, the growth thickness of the barrier structure can be 10 nm, 12 nm or 15 nm, and the number of periods of the quantum well 106 can be 3, 5 or 7.

[0089] In one specific implementation, the growth thickness of the well structure is 2.5 nm, the growth thickness of the barrier structure is 13 nm, the number of periods is 5, the total growth thickness of the quantum well 106 is 5 × (2.5 nm + 13 nm) = 77.5 nm, and the peak wavelength is 275 nm.

[0090] Step S134: Grow a p-type electron blocking layer 107 on the quantum well 106.

[0091] In this step, the purpose of growing the p-type electron blocking layer 107 is to block electron overflow and reduce Auger recombination. The p-type electron blocking layer 107 can be p-Al. 0.4 Ga 0.6 N:Mg. The growth environment for the p-type electron blocking layer 107 may include a pressure of 150 mbar and a flow rate of 0.15 sccm for magnesia-Cp2Mg.

[0092] In some feasible implementations, the growth temperature of the p-type electron blocking layer 107 is 800℃-1000℃, and the growth thickness of the p-type electron blocking layer 107 is 80nm-120nm.

[0093] For example, the growth temperature of the p-type electron blocking layer 107 can be 800°C, 900°C or 1000°C, and the growth thickness of the p-type electron blocking layer 107 can be 80nm, 100nm or 120nm.

[0094] In one specific implementation, the growth temperature of the p-type electron blocking layer 107 is 960℃, and the growth thickness of the p-type electron blocking layer 107 is 100nm.

[0095] Step S135: Grow a p-type extended contact layer 108 on the p-type electron blocking layer 107. The Al composition in the p-type extended contact layer 108 gradually decreases from the side closer to the p-type electron blocking layer 107 to the side farther away from the p-type electron blocking layer 107.

[0096] In this step, the p-type extended contact layer 108 serves both as a current spreader and an ohmic contact. The growth environment for the p-type extended contact layer 108 includes a growth temperature of 950°C and a pressure of 150 mbar.

[0097] In some feasible implementations, the p-type extended contact layer 108 is a graded structure from p-AlGaN+Mg doping to p-GaN. p-AlGaN+Mg doping can serve as a current spreading layer, and p-GaN can serve as an ohmic contact layer. Specifically, the Al composition in the p-type extended contact layer 108 changes from p-Al... 0.2 Ga 0.8N+Mg doping is gradually transitioned to p-GaN, with a gradient in Al composition to achieve a smooth band transition, reduce the hole injection barrier, and improve carrier injection efficiency. The p-GaN can be grown to a thickness of 150 nm for ohmic contacts.

[0098] After step S135 is completed, the following can be obtained: Figure 2 The structure shown.

[0099] Step S14: Perform in-situ annealing.

[0100] In-situ annealing is a technique that involves annealing the material directly in the same equipment or environment used for material preparation, without removing the material or cooling it to room temperature. In this step, in-situ annealing effectively activates dopant elements and improves crystal quality.

[0101] In one specific implementation, in-situ annealing can be performed under a nitrogen atmosphere at a temperature of 750°C for 20 minutes to activate the Mg-H complex and increase the hole concentration to >3 × 10⁻⁶. 17 cm -3 .

[0102] Figure 3 This is a schematic diagram of the fabrication process of the first type of ring photonic crystal provided in the embodiments of this application. Figure 3 (a) to (c) represent different steps in the process of preparing the patterned groove.

[0103] Combination Figure 1 and Figure 3 As shown, in step S15: patterned grooves 10a are etched on the p-type extended contact layer 108 using inductively coupled plasma technology to form multiple columnar structures 10b.

[0104] The columnar structures 10b are arranged in an array, and the height of the columnar structures 10b is greater than zero and less than or equal to the sum of the thicknesses of the p-type extended contact layer, the p-type electron blocking layer and the quantum well.

[0105] Step S15 may include steps S151 to S153.

[0106] Step S151: Coat the first mask layer b1 on the p-type extended contact layer 108.

[0107] In this step, the first mask layer b1 can be made of photoresist material and uniformly covered on the surface of the p-type extended contact layer 108 by spin coating.

[0108] After step S151 is completed, the following can be obtained: Figure 3 The structure shown in (a) is shown in the middle.

[0109] Step S152: Using photolithography, a plurality of first grooves are etched on the first mask layer b1 to form a patterned first mask layer.

[0110] In this step, the bottom of the etched first groove exposes the surface of the p-type extended contact layer 108. The first groove can be circular in shape, and etching the first groove provides precise pattern guidance for subsequent etching.

[0111] Specifically, the first grooves are arranged in an array, and the etching depth of the first grooves is the same as the coating thickness of the first mask layer b1.

[0112] After step S152 is completed, the following can be obtained: Figure 3 The structure shown in (b) is shown in the middle.

[0113] Step S153: The patterned first mask layer is etched using inductively coupled plasma technology to form a patterned groove 10a. The etching depth of the patterned groove 10a is less than or equal to the sum of the thicknesses of the p-type extended contact layer 108, the p-type electron blocking layer 107, and the quantum well 106; multiple columnar structures 10b are formed inside the patterned groove 10a.

[0114] In this step, the p-type extended contact layer 108 is reserved according to the position and shape of the first groove, and the etching direction is opposite to the growth direction of the p-type extended contact layer 108, and multiple arrayed columnar structures 10b are etched.

[0115] After step S153 is completed, the following can be obtained: Figure 3 The structure shown in (c) is as follows.

[0116] Figure 4A This is the second schematic diagram of the process for fabricating a chip based on a ring photonic crystal, as provided in the embodiments of this application. Figure 4B It is a kind of Figure 4A A schematic diagram of the columnar structure 10b in the diagram; Figure 4C It is another kind Figure 4A The structural diagram corresponding to columnar structure 10b in the diagram.

[0117] See Figure 4A , Figure 4B and Figure 4C As shown, after step S14 is completed, the result is as follows: Figure 4A , Figure 4B or Figure 4C The structure shown.

[0118] exist Figure 4A In this process, the etching depth of the patterned groove 10a is greater than zero and less than the growth thickness of the p-type extended contact layer 108. Figure 4B Image (a) shows a top view of columnar structure 10b. Figure 4B Figure (b) shows a three-dimensional schematic diagram of columnar structure 10b.

[0119] It is worth noting that the shape of the columnar structure 10b can be set by the shape of the first groove. That is, in the embodiments of this application, the first groove is not limited to a circle, but can also be [other shapes]. Figure 4C The square columnar structure 10b shown is, of course, a triangular prism or an elliptic in other implementations. This application does not specifically limit the shape of the columnar structure 10b.

[0120] It should be emphasized that the array arrangement of the columnar structures 10b obtained by etching in this embodiment is not limited to the following. Figure 4B and Figure 4C The arrangement shown can be implemented in other ways, with the multiple columnar structures 10b arranged in other array configurations.

[0121] Figure 5 This is a schematic diagram of the graphic groove provided in the embodiments of this application. Figure 5 In the middle (a) to (e), there are patterned grooves 10a with different etching depths.

[0122] See Figure 5 As shown in (a), the etching depth of the patterned groove 10a is the growth thickness of the p-type extended contact layer 108. In this implementation, the patterned groove 10a completely penetrates the p-type extended contact layer 108, and the bottom of the patterned groove 10a exposes the surface of the p-type electron blocking layer 107.

[0123] See Figure 5 As shown in (b), the etching depth of the patterned groove 10a is greater than the growth thickness of the p-type extended contact layer 108, and less than the sum of the growth thicknesses of the p-type extended contact layer 108 and the p-type electron blocking layer 107. In this implementation, the patterned groove 10a penetrates the p-type extended contact layer 108 and extends into the interior of the p-type electron blocking layer 107.

[0124] See Figure 5 As shown in (c), the etching depth of the patterned groove 10a is equal to the sum of the growth thicknesses of the p-type extended contact layer 108 and the p-type electron blocking layer 107. In this implementation, the patterned groove 10a penetrates the p-type extended contact layer 108 and the p-type electron blocking layer 107, and the bottom of the patterned groove 10a exposes the surface of the quantum well 106.

[0125] See Figure 5As shown in (d), the etching depth of the patterned groove 10a is greater than the sum of the growth thicknesses of the p-type extended contact layer 108 and the p-type electron blocking layer 107, and less than the sum of the growth thicknesses of the p-type extended contact layer 108, the p-type electron blocking layer 107, and the quantum well 106. In this implementation, the patterned groove 10a penetrates the p-type extended contact layer 108 and the p-type electron blocking layer 107 and extends into the interior of the quantum well 106, but does not completely penetrate the quantum well 106 layer.

[0126] See Figure 5 As shown in (e), the etching depth of the patterned groove 10a is equal to the sum of the growth thicknesses of the p-type extended contact layer 108, the p-type electron blocking layer 107, and the quantum well 106 layer. In this implementation, the patterned groove 10a completely penetrates the p-type extended contact layer 108, the p-type electron blocking layer 107, and the quantum well 106 layer, and the bottom of the patterned groove 10a exposes the surface of the n-type waveguide layer 105.

[0127] Step S16: Periodically grow Al2O3 layer c1 and SiO2 layer c2 at the bottom and sidewalls of the patterned groove 10a to form a ring photonic crystal 10c.

[0128] In this step, atomic layer deposition (ALD) technology can be used to simultaneously grow periodic Al2O3 layers c1 and SiO2 layers c2 on the bottom and sidewalls of the patterned groove 10a, as well as on the surface of the p-type extended contact layer 108. The Al2O3 layer c1 serves as a high-refractive-index dielectric layer, effectively enhancing the localization effect of photons within the ring photonic crystal 10c. The SiO2 layer c2 serves as a low-refractive-index dielectric layer, forming an optical resonant structure with the Al2O3 layer c1.

[0129] Figure 6A This is the third schematic diagram of the fabrication method for the first chip based on a ring photonic crystal provided in this application embodiment. Among them, Figure 6A Figures (a) to (c) show schematic diagrams of different processes for manufacturing ring-shaped photonic crystals.

[0130] Specifically, step S16 may include steps S161-S162, which are executed in multiple cycles.

[0131] Step S161: Deposit an Al2O3 layer c1.

[0132] After completing step S161, you will get the following result: Figure 6A In the structure shown in (a), an Al2O3 layer c1 is uniformly deposited on the bottom and sidewalls of the patterned groove 10a. That is, in this step, the Al2O3 layer c1 encapsulates multiple columnar structures 10b.

[0133] Step S162: Deposit SiO2 layer c2.

[0134] After step S162 is completed, the result will be as follows: Figure 6A In the structure shown in (b), the SiO2 layer c2 is uniformly deposited on the bottom and sidewalls of the Al2O3 layer c1. That is, in this step, the SiO2 layer c2 encapsulates the Al2O3 layer c1.

[0135] The above steps are performed periodically, so that multiple columnar structures 10b are sequentially encapsulated by Al2O3 layer c1 and SiO2 layer c2. After step S16 is completed, the following can be obtained: Figure 6A The structure shown in (c) is as follows.

[0136] It is important to emphasize that during the sequential deposition of Al2O3 layer c1 and SiO2 layer c2, the surface of columnar structure 10b is simultaneously deposited. After the annular photonic crystal 10c is fabricated, photolithography is used to etch the Al2O3 layer c1 and SiO2 layer c2 on the surface of the p-type extended contact layer 108 to expose the surface of the p-type extended contact layer 108, thereby... Figure 6A The structure shown in (c) has a flat surface, and the surfaces of the Al2O3 layer c1 and the SiO2 layer c2 on the side opposite to the bottom of the patterned groove 10a are on the same horizontal plane as the surface of the columnar structure 10b. Figure 6A The ring photonic crystal 10c shown in (c) has 3 periods. This is only an illustrative example for easy viewing and is not a specific limitation.

[0137] The multiple arrayed ring photonic crystals 10c formed through the above steps can effectively confine and control photons of specific wavelengths. The periodic refractive index distribution between adjacent ring photonic crystals 10c ensures that photons are limited to propagation within a specific frequency range due to the influence of the photonic bandgap, thus enabling precise control. The ring photonic crystals 10c can effectively adjust the directionality of the photonic bandgap, forming uniform light waves from all sides, thereby suppressing laser leakage from non-emitting areas on the sides, improving light extraction efficiency. Furthermore, the periodic distribution of the ring photonic crystals ensures high matching with the laser mode emitted from the sides, guaranteeing beam quality. The parameters of the ring photonic crystals 10c can be designed and adjusted according to actual application requirements to meet the control requirements of different wavelengths of photons, providing a flexible structural basis for chip applications in optical communication, optical sensing, and other fields.

[0138] In some feasible implementations, the growth thickness of Al2O3 layer c1 is 30nm-40nm; the growth thickness of SiO2 layer c2 is 45nm-55nm; and the growth cycle of Al2O3 layer c1 and SiO2 layer c2 is 8-18.

[0139] For example, the growth thickness of Al2O3 layer c1 can be 30nm, 35nm or 40nm, the growth thickness of SiO2 layer c2 can be 45nm, 50nm or 55nm, and the growth cycle of Al2O3 layer c1 and SiO2 layer c2 can be 8, 12 or 16.

[0140] In one specific implementation, the growth thickness of Al2O3 layer c1 is 35 nm; the growth thickness of SiO2 layer c2 is 48 nm; and the growth cycle of Al2O3 layer c1 and SiO2 layer c2 is 10.

[0141] Specifically, the thickness of Al2O3 layer c1 and SiO2 layer c2 and the growth cycle of Al2O3 layer c1 and SiO2 layer c2 can be adjusted according to the etching depth of the patterned groove 10a, so that the total thickness of the periodic Al2O3 layer c1 and SiO2 layer c2 is adapted to the height of the columnar structure 10b.

[0142] In some feasible implementations, the etching depth of different local locations of the patterned groove 10a is different, so that the height of the multiple columnar structures 10b is different. Therefore, after depositing the Al2O3 layer c1 and the SiO2 layer c2, the deposition depth of the multiple annular photonic crystals 10c is different.

[0143] Figure 6B This is a schematic diagram of the structure of the first type of ring photonic crystal provided in the embodiments of this application.

[0144] See Figure 6B As shown, in a specific implementation, the ring photonic crystal 10c may include a first ring photonic crystal 10c-1, a second ring photonic crystal 10c-2, and a third ring photonic crystal 10c-3. The first ring photonic crystal 10c-1 is located within the p-type extended contact layer 108, and its deposition height is less than the growth thickness of the p-type extended contact layer 108. The second ring photonic crystal 10c-2 penetrates the p-type extended contact layer 108 and extends into the p-type electron blocking layer 107, and its deposition height is less than the sum of the growth thicknesses of the p-type extended contact layer 108 and the p-type electron blocking layer 107. The third ring photonic crystal 10c-3 penetrates the p-type extended contact layer 108 and the p-type electron blocking layer 107 and extends into the quantum well 106, and its deposition height is equal to the sum of the thicknesses of the p-type extended contact layer 108, the p-type electron blocking layer 107, and the quantum well 106.

[0145] See also the following for some feasible implementation methods. Figure 5 As shown in (a), the width D between any two adjacent columnar structures 10b can be 40μm-100μm. The dimension L of the columnar structure 10b can be 230μm-280μm along the length, width, or diameter direction of the substrate 101.

[0146] Wherein, the width D between any two adjacent columnar structures 10b is the minimum dimension along the length, width, or diameter direction of the substrate 101. For example, when the columnar structure 10b is a cylinder, the width D is the minimum distance between the two cylinders, and the dimension L is the diameter of the cylinder.

[0147] For example, the width D between any two adjacent columnar structures 10b can be 40μm, 50μm or 80μm, and the size L of the columnar structure 10b can be 230μm, 260μm or 280μm.

[0148] See also Figure 6B As shown, taking the cylindrical columnar structure 10b as an example, the columnar structure 10b includes a first columnar structure 10b, a second columnar structure 10b, and a third columnar structure 10b. The diameter of the first columnar structure 10b is L1, the diameter of the second columnar structure 10b is L2, and the diameter of the third columnar structure 10b is L3. L1, L2, and L3 can be the same or different. The heights of the first columnar structure 10b, the second columnar structure 10b, and the third columnar structure 10b are different.

[0149] It is worth noting that the deposition height of the ring photonic crystal 10c and the height of the columnar structure 10b are both determined by the etching parameters of the patterned groove 10a. Ring photonic crystals 10c of different sizes can be obtained by adjusting the etching parameters of the patterned groove 10a.

[0150] The ring photonic crystal 10c provided in this application embodiment can be flexibly adjusted. The deposition height of multiple ring photonic crystals 10c can be the same or different, and the size of multiple columnar structures 10b can be the same or different.

[0151] Figure 7 This is the fourth schematic diagram of the process for fabricating a chip based on a ring photonic crystal, as provided in the embodiments of this application. Figure 8 yes Figure 7 The top view shown in (d). Figure 7 The different steps for preparing the patterned transparent conductive layer 109 are shown in (a) to (d).

[0152] Among some feasible implementation methods, see Figure 7 and Figure 8 As shown, step S17: A patterned transparent conductive layer 109 is grown on the columnar structure 10b; wherein, the patterned transparent conductive layer 109 can be circular, and the center of the patterned transparent conductive layer 109 coincides with the center of the columnar structure 10b.

[0153] In this step, a patterned transparent conductive layer 109 can be grown by sputtering.

[0154] Step S17 may include steps S171 to S174.

[0155] Step S171: Grow a transparent conductive layer on the surface of the p-type extended contact layer 108, the Al2O3 layer c1, and the SiO2 layer c2.

[0156] In this step, a transparent conductive layer can be grown using MOCVD technology.

[0157] After step S171 is completed, the following can be obtained: Figure 7 In the structure shown in (a), a transparent conductive layer is uniformly covered on the surface of the p-type extended contact layer 108.

[0158] Step S172: Coat the second mask layer b2 on the transparent conductive layer.

[0159] In this step, the second mask layer b2 can be a photoresist material, as described in step S151 above.

[0160] After step S172 is completed, the following can be obtained: Figure 7 As shown in (b), the second mask layer b2 uniformly covers the surface of the p-type extended contact layer 108.

[0161] Step S173: Use photolithography to etch a second groove on the second mask layer b2 to form a patterned second mask layer.

[0162] In this step, photolithography is used to etch the second mask layer b2 and etch multiple second grooves. This step can be referred to in the aforementioned step S152.

[0163] After etching is completed, the center of the second groove coincides with the center of the columnar structure 10b, and the projection of the second groove falls on the columnar structure 10b along the etching direction. That is to say, multiple second grooves are arranged in an array, and the second grooves are set in a one-to-one correspondence with the columnar structure 10b.

[0164] After step S173 is completed, the following can be obtained: Figure 7 The structure shown in (c) is as follows.

[0165] Step S174: The patterned second mask layer is etched using inductively coupled plasma technology to form a patterned transparent conductive layer 109.

[0166] In this step, the patterned second mask layer and the underlying transparent conductive layer are etched to a depth equal to the sum of the growth thicknesses of the patterned second mask layer and the transparent conductive layer.

[0167] After step S174 is completed, the following can be obtained: Figure 7 (d) and Figure 8 The structure shown.

[0168] Figure 9 This is the fifth schematic diagram of the fabrication method of the first chip based on a ring photonic crystal provided in this application embodiment; wherein, Figure 9 Image (a) shows a schematic diagram of the structure after the patterned electrode 110 has been grown. Figure 9 (b) is Figure 9 Top view of (a).

[0169] Step S18: Growing patterned electrodes 110 on the patterned transparent conductive layer 109.

[0170] In this step, see Figure 9 As shown in (a) and (b), electrodes are grown simultaneously on the surface of the patterned transparent conductive layer 109 and the Al2O3 layer c1 and SiO2 layer c2. The electrodes are uniformly deposited by vapor deposition process to form ohmic contacts and ensure efficient current injection.

[0171] After electrode growth is complete, the electrodes are stripped to form patterned electrodes 110 with the same shape as the patterned transparent conductive layer 109, so that the patterned electrodes 110 can perfectly cover the patterned transparent conductive layer 109. Then, annealing is performed to optimize ohmic contact performance and reduce contact resistance. After step S18 is completed, the chip 100 based on a ring photonic crystal is obtained.

[0172] In some feasible implementations, step S18 may be followed by step S19.

[0173] Step S19: Deposit a passivation layer SiN on the surface of the chip 100 based on the ring photonic crystal, thin or dic the substrate 101, and package it.

[0174] In some feasible implementations, the fabrication method of the chip based on the ring photonic crystal may also include step S10 before step S11.

[0175] Step S10: Bake substrate 101 in an H2 atmosphere for a second preset time.

[0176] In this step, pre-baking can effectively remove moisture and organic matter adsorbed on the surface of substrate 101. The pre-baking environment may include: a pre-baking temperature of 1050 °C, an H2 atmosphere, and a second preset time of 5 min.

[0177] The method for fabricating a chip based on a ring photonic crystal provided in this application embodiment is simple and flexible in fabricating the ring photonic crystal 10c, solving the technical problems of complex design and simulation, and also addressing the polarization sensitivity issue of related methods. The chip 100 based on the ring photonic crystal prepared by this method can effectively improve light extraction efficiency, effectively reduce process damage, facilitate large-scale development, achieve new functions and performance improvements, and effectively improve production yield.

[0178] Corresponding to the aforementioned embodiments of the chip fabrication method based on a ring photonic crystal, this application also provides another method for fabricating a chip based on a ring photonic crystal.

[0179] Figure 10 This is a schematic flowchart of the second method for fabricating a chip based on a ring photonic crystal provided in the embodiments of this application; Figure 11 This is one of the process schematic diagrams of the second method for fabricating a chip based on a ring photonic crystal provided in the embodiments of this application.

[0180] See Figure 10 and Figure 11 As shown, the second method for fabricating a chip based on a ring photonic crystal provided in this application includes the following steps S21 to S28.

[0181] Step S21: A nucleation layer 102 is grown on the substrate 101; the growth temperature of the nucleation layer 102 is the first temperature.

[0182] Step S21 can use the same preparation process as step S11 in the preparation method described in the previous embodiment.

[0183] Step S22: Grow a superlattice structure 103, an n-type cladding layer 104, an n-type waveguide layer 105, and a quantum well 106 on the nucleation layer 102; the growth temperature of the superlattice structure 103 is the second temperature, and the first temperature is lower than the second temperature.

[0184] Step S22 can use the same preparation process as steps S12 to S133 in the preparation method described in the foregoing embodiments.

[0185] After step S22 is completed, the following can be obtained: Figure 11 The structure shown in (a) is shown in the middle.

[0186] Step S23: Patterned grooves are etched on the quantum well 106 using inductively coupled plasma technology to form multiple columnar structures 10b; wherein the etching direction of the patterned grooves is opposite to the growth direction of the quantum well 106; the multiple columnar structures 10b are arranged in an array. The height of the columnar structures 10b is greater than zero and less than or equal to the thickness of the quantum well 106.

[0187] Step S23 can employ the same preparation process as S15 in the aforementioned embodiment. After step S23 is completed, the desired result can be obtained as shown below. Figure 11 The structure shown in (b) is shown in the middle.

[0188] Step S24: Periodically grow Al2O3 layer c1 and SiO2 layer c2 at the bottom and sidewalls of the patterned groove to form a ring-shaped photonic crystal. The surfaces of Al2O3 layer c1 and SiO2 layer c2 on the side away from the bottom of the patterned groove are at the same level as the surface of columnar structure 10b.

[0189] In particular, step S24 can use the same preparation process as S16 in the preparation method of the aforementioned embodiment.

[0190] After step S24 is completed, the result will be as follows: Figure 11 The structure shown in (c) is as follows.

[0191] Step S25: Grow a p-type electron blocking layer 107 and a p-type extended contact layer 108 sequentially on the quantum well 106.

[0192] In particular, step S25 can use the same preparation process as step S134 and step S135 in the preparation method of the foregoing embodiment.

[0193] Step S26: Perform in-situ annealing.

[0194] Step S26 can use the same preparation process as S14 in the preparation method described in the previous embodiment.

[0195] Step S27: A patterned transparent conductive layer 109 is grown on the p-type extended contact layer 108; the cross-sectional shape of the patterned transparent conductive layer 109 is the same as the cross-sectional shape of the columnar structure 10b, and the patterned transparent conductive layer 109 and the columnar structure 10b are arranged in a one-to-one correspondence.

[0196] The patterned transparent conductive layer 109 can be circular, and the center of the patterned transparent conductive layer 109 coincides with the center of the columnar structure 10b.

[0197] Step S27 can use the same preparation process as S17 in the preparation method described in the previous embodiment.

[0198] Step S28: Grow patterned electrodes 110 on the patterned transparent conductive layer 109.

[0199] Step S28 can employ the same preparation process as S18 in the aforementioned embodiment. After step S28 is completed, the desired result can be obtained as follows: Figure 11 The chip 100 based on a ring photonic crystal is shown in (d).

[0200] In some feasible implementations, step S28 may be followed by step S29.

[0201] Step S29: Deposit a passivation layer SiN on the surface of the chip 100 based on the ring photonic crystal, thin or dic the substrate 101, and package it.

[0202] Step S29 can use the same preparation process as S19 in the preparation method described in the previous embodiment.

[0203] In some feasible implementations, the chip fabrication method based on a ring photonic crystal provided in the embodiments of this application may include step S20 before step S21.

[0204] Step S20: Pre-bake the substrate 101.

[0205] In particular, step S20 can use the same preparation process as S10 in the preparation method in the aforementioned embodiments.

[0206] It should be emphasized that the chip fabrication method based on a ring photonic crystal provided in this embodiment differs from the aforementioned chip fabrication method based on a ring photonic crystal in the growth position of the ring photonic crystal 10c. In this implementation, the ring photonic crystal 10c is grown in the quantum well 106 structure, and the growth depth of the ring photonic crystal 10c is greater than zero and less than or equal to the thickness of the quantum well 106. The fabrication process and parameters used in the remaining steps can be the same as those provided in the aforementioned embodiment.

[0207] Corresponding to the aforementioned embodiments of the fabrication method of a chip based on a ring photonic crystal, this application also provides a chip 100 based on a ring photonic crystal.

[0208] Figure 12 This is a schematic diagram of the structure of a chip 100 based on a ring photonic crystal provided in an embodiment of this application. Figure 12 The diagrams (a) to (d) show different distributions of the ring-shaped photonic crystal.

[0209] See Figure 12 As shown in (a) to (d), the chip 100 based on a ring photonic crystal provided in this application embodiment includes a substrate 101, a nucleation layer 102, a superlattice structure 103, an n-type cladding layer 104, an n-type waveguide layer 105, a quantum well 106, a p-type electron blocking layer 107, a p-type extended contact layer 108, a patterned groove, a ring photonic crystal 10c, an Al2O3 layer c1, a SiO2 layer c2, a patterned transparent conductive layer 109, and a patterned electrode 110.

[0210] The nucleation layer 102 is grown on the substrate 101. The growth temperature of the nucleation layer 102 is the first temperature.

[0211] The nucleation layer 102 can be prepared by step S11 or step S21 in the embodiment of the above-described method for preparing a chip based on a ring photonic crystal.

[0212] The superlattice structure 103 is grown on the side of the nucleation layer 102 facing away from the substrate 101. The growth temperature of the superlattice structure 103 is a second temperature, where the first temperature is lower than the second temperature.

[0213] The superlattice structure 103 can be prepared by step S12 or step S22 in the embodiment of the above-described method for preparing a chip based on a ring photonic crystal.

[0214] The n-type cladding layer 104 grows on the side of the superlattice structure 103 away from the nucleation layer 102; the Al composition in the n-type cladding layer 104 gradually decreases from the side closer to the superlattice structure 103 to the side farther away from the superlattice structure 103.

[0215] The n-type cladding layer 104 can be prepared by step S131 or step S22 in the embodiment of the above-described method for fabricating a chip based on a ring photonic crystal.

[0216] The n-type waveguide layer 105 is grown on the side of the n-type cladding layer 104 away from the superlattice structure 103.

[0217] The n-type waveguide layer 105 can be prepared by step S132 or step S22 in the embodiment of the above-described method for preparing a chip based on a ring photonic crystal.

[0218] The quantum well 106 is grown on the side of the n-type waveguide layer 105 away from the n-type cladding layer 104.

[0219] The quantum well 106 can be prepared by step S133 or step S22 in the embodiment of the above-described method for preparing a chip based on a ring photonic crystal.

[0220] p-type electron blocking layer 107 is grown on the side of quantum well 106 away from n-type waveguide layer 105.

[0221] The p-type electron blocking layer 107 can be prepared by step S134 or step S25 in the embodiment of the above-described method for preparing a chip based on a ring photonic crystal.

[0222] p-type extended contact layer 108 is grown on the side of p-type electron blocking layer 107 away from quantum well 106.

[0223] The p-type extended contact layer 108 can be prepared by step S135 or step S25 in the embodiment of the above-described method for fabricating a chip based on a ring photonic crystal.

[0224] A patterned groove (not shown in the figure) is formed in the quantum well 106 or at least in the p-type extended contact layer 108; multiple columnar structures 10b are formed inside the patterned groove; the multiple columnar structures 10b are arranged in an array.

[0225] The patterned groove can be prepared by step S15 or step S23 in the embodiment of the above-described method for fabricating a chip based on a ring photonic crystal.

[0226] A ring-shaped photonic crystal 10c is grown in a patterned groove. The ring-shaped photonic crystal 10c includes a periodically grown Al2O3 layer c1 and a SiO2 layer c2.

[0227] The ring photonic crystal 10c can be prepared by step S16 or step S24 in the embodiment of the above-described method for preparing a chip based on a ring photonic crystal.

[0228] A patterned transparent conductive layer 109 is grown on the columnar structure 10b; and the patterned transparent conductive layer 109 and the columnar structure 10b are arranged in a one-to-one correspondence.

[0229] The patterned transparent conductive layer 109 can be prepared by step S17 or step S27 in the embodiment of the above-described method for preparing a chip based on a ring photonic crystal.

[0230] Patterned electrodes 110 are disposed on patterned transparent conductive layers 109. Each patterned electrode 110 corresponds to one patterned transparent conductive layer 109.

[0231] The patterned electrode 110 can be prepared by step S18 or step S28 in the embodiment of the above-described method for preparing a chip based on a ring photonic crystal.

[0232] See also Figure 12 As shown in (a), a ring-shaped photonic crystal 10c is disposed in a p-type extended contact layer 108, and the growth height of the ring-shaped photonic crystal 10c is greater than zero and less than or equal to the thickness of the p-type extended contact layer 108.

[0233] See also Figure 12 As shown in (b), a ring photonic crystal 10c is disposed in a p-type extended contact layer 108 and a p-type electron blocking layer 107. The growth height of the ring photonic crystal 10c is greater than the thickness of the p-type extended contact layer 108 and less than or equal to the sum of the thicknesses of the p-type extended contact layer 108 and the p-type electron blocking layer 107.

[0234] See also Figure 12In the middle (c), a ring photonic crystal 10c is disposed in the p-type extended contact layer 108, the p-type electron blocking layer 107 and the quantum well 106. The growth height of the ring photonic crystal 10c is greater than the sum of the thicknesses of the p-type extended contact layer 108 and the p-type electron blocking layer 107, and less than or equal to the sum of the thicknesses of the p-type extended contact layer 108, the p-type electron blocking layer 107 and the quantum well 106.

[0235] Specifically, in Figure 12 In the implementations shown in (a) to (c), the ring photonic crystal 10c can be prepared by step S15 in the embodiment of the above-described method for fabricating a chip based on the ring photonic crystal 10c.

[0236] See Figure 12 As shown in (d), a ring photonic crystal 10c is disposed in a quantum well 106, and the growth height of the ring photonic crystal 10c is greater than zero and less than or equal to the thickness of the quantum well 106.

[0237] Specifically, in Figure 12 In the implementation shown in (d), the ring photonic crystal 10c can be prepared by step S23 in the embodiment of the above-described method for preparing a chip based on a ring photonic crystal.

[0238] It should be noted that, upon considering the specification and practicing the application disclosed herein, those skilled in the art will readily conceive of other embodiments of this application. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein.

[0239] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The true scope is indicated by this application.

Claims

1. A method for fabricating a chip based on a ring photonic crystal, characterized in that, include: A nucleation layer is grown on a substrate; the growth temperature of the nucleation layer is a first temperature. A superlattice structure is grown on the nucleation layer; the growth temperature of the superlattice structure is a second temperature, and the first temperature is lower than the second temperature; An n-type cladding layer, an n-type waveguide layer, a quantum well, a p-type electron blocking layer, and a p-type extended contact layer are sequentially grown on the superlattice structure; wherein, the Al composition in the n-type cladding layer gradually decreases from the side closer to the superlattice structure to the side farther away from the superlattice structure; Perform in-situ annealing; Patterned grooves are etched on the p-type extended contact layer using inductively coupled plasma technology to form multiple columnar structures; wherein, the multiple columnar structures are arranged in an array, and the height of the columnar structures is greater than zero and less than or equal to the sum of the thicknesses of the p-type extended contact layer, the p-type electron blocking layer and the quantum well; Al2O3 and SiO2 layers are periodically grown at the bottom and sidewalls of the patterned groove to form a ring-shaped photonic crystal; wherein the surfaces of the Al2O3 and SiO2 layers on the side away from the bottom of the patterned groove are at the same level as the surface of the columnar structure. A patterned transparent conductive layer is grown on the surface of the columnar structure; Patterned electrodes are grown on the patterned transparent conductive layer.

2. The method for fabricating a chip based on a ring photonic crystal according to claim 1, characterized in that, Patterned grooves were etched on the p-type extended contact layer using inductively coupled plasma technology to form multiple columnar structures, including: A first mask layer is coated on the p-type extended contact layer; Multiple first grooves are etched on the first mask layer using photolithography to form a patterned first mask layer; the multiple first grooves are arranged in an array, and the etching depth of the multiple first grooves is the same as the coating thickness of the first mask layer; The patterned first mask layer is etched using inductively coupled plasma technology to form a patterned groove; the etching depth of the patterned groove is less than or equal to the sum of the thicknesses of the p-type extended contact layer, the p-type electron blocking layer, and the quantum well; multiple columnar structures are formed inside the patterned groove.

3. The method for fabricating a chip based on a ring photonic crystal according to claim 1, characterized in that, A patterned transparent conductive layer is grown on the surface of the columnar structure, including: A transparent conductive layer is grown on the surface of the p-type extended contact layer, the Al2O3 layer, and the SiO2 layer; A second mask layer is coated on the transparent conductive layer; Multiple second grooves are etched on the second mask layer using photolithography to form a patterned second mask layer; the multiple second grooves are arranged in an array, and the second grooves are configured to correspond one-to-one with the columnar structure; The patterned second mask layer is etched using inductively coupled plasma technology to form a patterned transparent conductive layer; the etching depth of the patterned second mask layer is the sum of the thicknesses of the second mask layer and the transparent conductive layer.

4. The method for fabricating a chip based on a ring photonic crystal according to claim 1, characterized in that, The distance between any two adjacent columnar structures is 40μm-100μm.

5. The method for fabricating a chip based on a ring photonic crystal according to claim 1, characterized in that, The Al composition in the p-type extended contact layer gradually decreases from the side closer to the p-type electron blocking layer to the side farther away from the p-type electron blocking layer.

6. The method for fabricating a chip based on a ring photonic crystal according to claim 1, characterized in that, The quantum well has a period number of 2-10; the quantum well comprises a well structure and a barrier structure grown sequentially. After the well structure is grown, it is flushed with NH3 atmosphere for a first preset time, and then the barrier structure is regrown. The Al content in the barrier structure is greater than that in the well structure.

7. The method for fabricating a chip based on a ring photonic crystal according to claim 1, characterized in that, Before growing the nucleation layer on the substrate, the fabrication method of the chip based on the ring photonic crystal further includes: The substrate is baked in an H2 atmosphere for a second preset time.

8. A method for fabricating a chip based on a ring photonic crystal, characterized in that, include: A nucleation layer is grown on a substrate; the growth temperature of the nucleation layer is a first temperature. A superlattice structure, an n-type cladding layer, an n-type waveguide layer, and a quantum well are sequentially grown on the nucleation layer; the growth temperature of the superlattice structure is a second temperature, and the first temperature is lower than the second temperature. Patterned grooves are etched on the quantum well using inductively coupled plasma technology to form multiple columnar structures; wherein, the multiple columnar structures are arranged in an array, and the height of the columnar structures is greater than zero and less than or equal to the thickness of the quantum well; Al2O3 and SiO2 layers are periodically grown at the bottom and sidewalls of the patterned groove to form a ring-shaped photonic crystal; wherein the surfaces of the Al2O3 and SiO2 layers on the side away from the bottom of the patterned groove are at the same level as the surface of the columnar structure. A p-type electron blocking layer and a p-type extended contact layer are sequentially grown on the quantum well; Perform in-situ annealing; A patterned transparent conductive layer is grown on the p-type extended contact layer; wherein the cross-sectional shape of the patterned transparent conductive layer is the same as the cross-sectional shape of the columnar structure, and the patterned transparent conductive layer and the columnar structure are arranged in a one-to-one correspondence. Patterned electrodes are grown on the patterned transparent conductive layer.

9. A chip based on a ring photonic crystal, characterized in that, The chip is fabricated using the method described in any one of claims 1 to 8, wherein the chip based on the ring photonic crystal comprises: Substrate; A nucleation layer is grown on the substrate; the growth temperature of the nucleation layer is a first temperature. A superlattice structure is grown on the side of the nucleation layer away from the substrate; the growth temperature of the superlattice structure is a second temperature, where the first temperature is lower than the second temperature; An n-type cladding layer is grown on the side of the superlattice structure away from the nucleation layer; the Al composition in the n-type cladding layer gradually decreases from the side closer to the superlattice structure to the side farther away from the superlattice structure. An n-type waveguide layer is grown on the side of the n-type cladding layer that is away from the superlattice structure. A quantum well is grown on the side of the n-type waveguide layer away from the n-type cladding layer. A p-type electron blocking layer is grown on the side of the quantum well away from the n-type waveguide layer; A p-type extended contact layer is grown on the side of the p-type electron blocking layer opposite to the quantum well; A patterned groove is formed in the quantum well or at least in the p-type extended contact layer; multiple columnar structures are formed inside the patterned groove; the multiple columnar structures are arranged in an array; A ring-shaped photonic crystal is grown in the patterned groove; the ring-shaped photonic crystal includes periodically grown Al2O3 and SiO2 layers; A patterned transparent conductive layer is grown on the columnar structure; and the patterned transparent conductive layer is provided in a one-to-one correspondence with the columnar structure. Patterned electrodes are grown on the patterned transparent conductive layer; and the patterned electrodes are arranged in a one-to-one correspondence with the patterned transparent conductive layer.

10. The chip based on a ring photonic crystal according to claim 9, characterized in that, The ring-shaped photonic crystal is disposed in the quantum well, and the height of the ring-shaped photonic crystal is greater than zero and less than or equal to the thickness of the quantum well; Alternatively, the annular photonic crystal is disposed in the p-type extended contact layer, and the height of the annular photonic crystal is greater than zero and less than or equal to the thickness of the p-type extended contact layer; Alternatively, the annular photonic crystal is disposed on the p-type extended contact layer and the p-type electron blocking layer, wherein the height of the annular photonic crystal is greater than the thickness of the p-type extended contact layer and less than or equal to the sum of the thicknesses of the p-type extended contact layer and the p-type electron blocking layer; Alternatively, the ring-shaped photonic crystal is disposed in the p-type extended contact layer, the p-type electron blocking layer, and the quantum well, wherein the height of the ring-shaped photonic crystal is greater than the sum of the thicknesses of the p-type extended contact layer and the p-type electron blocking layer, and less than or equal to the sum of the thicknesses of the p-type extended contact layer, the p-type electron blocking layer, and the quantum well.

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