Video signal conversion system, method and equipment based on FPGA (Field Programmable Gate Array) and medium

Abstract

The invention relates to a video signal conversion system, method and equipment based on an FPGA (Field Programmable Gate Array) and a medium. The system comprises a signal input module which is used for collecting externally input video source signals and transmitting the video source signals to an FPGA processing module through an IO port according to a corresponding circuit interface configured by a signal type. And the FPGA processing module is used for calling the DDR3 storage module to carry out video conversion operation on the video source signal according to the configuration information stored in the FLASH module and the EEPROM module, and outputting the converted video signal to the signal output module. And the signal output module is used for carrying out secondary processing on the video signal according to the adaptive interface protocol and format and then outputting the video signal through an output circuit interface configured by the IO port. The FLASH module and the EEPROM module serve as a first storage module and are connected in parallel with the DDR3 storage module. By adopting the method, efficient and high-quality video signal conversion can be realized, and the video conversion cost is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of video signal processing, in particular to a video signal conversion system, method, device and medium based on FPGA. BACKGROUND

[0002] With the continuous development of multimedia technology, more and more diversified display terminals have entered people's lives, such as computers, tablets, mobile phones, televisions, etc. The transmission and display requirements of video signals among various devices are increasing. However, there are great differences in the video signal formats supported by different devices, such as different parameters of resolution, frame rate, color space, etc. At the same time, the types of device interfaces are also diverse, from the traditional VGA interface, to the widely used HDMI interface, to the DP interface suitable for high-speed transmission, and to the LVDS interface commonly used for tablet display, their signal protocols and electrical characteristics are all different, which requires video signal conversion technology to realize signal compatibility.

[0003] At present, there are usually two ways to convert video signals, one is to design a conversion circuit with a special video conversion chip, and the other is to design a conversion circuit and corresponding software with an imported FPGA chip.

[0004] However, the above two methods each have defects, 1) special video conversion chip design: its function is usually fixed, usually only supporting a single video format and video interface, with poor flexibility, it is difficult to adjust according to the needs of different application scenarios; and once the market demand changes, the cost of updating and replacing the special chip is high and the cycle is long, which is not conducive to quickly responding to emerging video signal conversion needs. 2) using imported FPGA chip design: on the one hand, affected by international situation and trade policy, the stability of the supply chain is difficult to guarantee, there is a risk of supply interruption; on the other hand, its technical principle and design architecture are not transparent, it is difficult to carry out deep customization and optimization, and the development cost is high. At the same time, the existing video signal conversion scheme still needs to be improved in terms of conversion efficiency, signal quality, etc., and it is difficult to meet the needs of high-definition and ultra-high-definition video signal conversion. In summary, the existing video signal conversion technology is obviously inconvenient and defective in actual use, so it is necessary to improve it. SUMMARY

[0005] Therefore, it is necessary to provide a video signal conversion system, method, device and medium based on FPGA, which can improve the flexibility and quality of video conversion and reduce the conversion cost.

[0006] The application discloses an FPGA-based video signal conversion system, which comprises a signal input module, an FPGA processing module, a signal output module, a power module and a storage module.

[0007] The signal input module is used for collecting externally input video source signals and transmitting the video source signals to the FPGA processing module through IO ports according to corresponding circuit interfaces configured based on signal types.

[0008] The FPGA processing module is used for receiving video source signals transmitted through different circuit interfaces and performing video conversion operation on the video source signals by calling the DDR3 storage module according to configuration information stored in the FLASH module and the EEPROM module, and outputting the converted video signals to the signal output module.

[0009] The signal output module is used for receiving the converted video signals, performing secondary processing on the video signals according to adaptive interface protocols and formats, and outputting the processed video signals through output circuit interfaces configured by IO ports.

[0010] The FLASH module and the EEPROM module are connected in parallel with the DDR3 storage module as a first storage module.

[0011] The power module is connected in series with the first storage module, the DDR3 storage module and the FPGA processing module.

[0012] An FPGA-based video signal conversion method, which comprises the following steps: The signal input module is used for collecting externally input video source signals and transmitting the video source signals to the FPGA processing module through IO ports according to corresponding circuit interfaces configured based on signal types.

[0013] The FPGA processing module is used for receiving video source signals transmitted through different circuit interfaces and performing video conversion operation on the video source signals by calling the DDR3 storage module according to configuration information stored in the FLASH module and the EEPROM module, and outputting the converted video signals to the signal output module.

[0014] The signal output module is used for receiving the converted video signals, performing secondary processing on the video signals according to adaptive interface protocols and formats, and outputting the processed video signals through output circuit interfaces configured by IO ports.

[0015] A computer device comprises a memory and a processor, the memory stores a computer program, and the processor implements the following steps when executing the computer program: The signal input module collects the externally input video source signal, configures the corresponding circuit interface according to the type of the video source signal, and transmits the video source signal to the FPGA processing unit through the IO port.

[0016] The FPGA processing unit receives the video source signal transmitted through the different types of circuit interfaces, calls the configuration information stored in the FLASH storage unit and the EEPROM storage unit in advance, enables the DDR3 storage unit as an operation cache, performs video conversion operation on the video source signal, and generates the converted video signal.

[0017] The signal output unit receives the converted video signal, performs secondary processing on the converted video signal according to the adapted interface protocol and format, and outputs the processed video signal through the output circuit interface configured by the IO port.

[0018] A computer readable storage medium has a computer program stored thereon, and the computer program is executed by a processor to implement the following steps: The signal input module collects the externally input video source signal, configures the corresponding circuit interface according to the type of the video source signal, and transmits the video source signal to the FPGA processing unit through the IO port.

[0019] The FPGA processing unit receives the video source signal transmitted through the different types of circuit interfaces, calls the configuration information stored in the FLASH storage unit and the EEPROM storage unit in advance, enables the DDR3 storage unit as an operation cache, performs video conversion operation on the video source signal, and generates the converted video signal.

[0020] The signal output unit receives the converted video signal, performs secondary processing on the converted video signal according to the adapted interface protocol and format, and outputs the processed video signal through the output circuit interface configured by the IO port.

[0021] The FPGA-based video signal conversion system, method, device and medium described above take the FPGA processing module as the core to replace the special chip, flexibly adapt to the conversion requirements of multiple types of video signals (such as format conversion, resolution adjustment, etc.) by using the programmable characteristics of the FPGA, get rid of the dependence on single-function special chips, and improve the generality and scene adaptation capability of the system. First, the standardized FPGA hardware interface and modular configuration design are adopted, which can seamlessly compatible with domestic FPGA chips, reduces the technical lock-in risk through software and hardware decoupling, ensures the supply of core devices to be controllable, and strengthens the security of the supply chain. The storage architecture of the FLASH module and the EEPROM module is connected in parallel with the DDR3 module: the first storage module (FLASH+EEPROM) is connected in parallel with the DDR3 module, so that the configuration information reading and the operation data caching can be performed synchronously, the data interaction waiting time is reduced, and when the FPGA processing module calls the DDR3 module for high-speed operation, the configuration parameters can be obtained from the first storage module at the same time, the data processing throughput is significantly improved, and the conversion efficiency is optimized. Then, the signal input module dynamically configures the corresponding circuit interface through the IO port, ensures the lossless transmission of different types of video source signals (such as HDMI, VGA, etc.). In addition, the signal output module adds a secondary processing link of protocol adaptation and format optimization, reduces the distortion and loss in the signal conversion process, and improves the integrity of the output signal. Finally, the power module adopts a series connection mode to simplify the power supply link and reduce the hardware redundancy cost, and the programmable nature of the FPGA reduces the need for special circuit design, which can further compress the cost by replacing the domestic chip solution. In summary, through the architecture innovation and module cooperation, the system realizes efficient and high-quality video signal conversion based on FPGA, ensures the security of the supply chain, and reduces the comprehensive technical effects of cost. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 It is a structural block diagram of the FPGA-based video signal conversion system in one embodiment; Figure 2 It is a flowchart of the FPGA-based video signal conversion method in one embodiment; Figure 3 It is a work flowchart of the FPGA-based video signal conversion system in one embodiment; Figure 4 It is a system block diagram of the FPGA-based video signal conversion circuit in one embodiment; Figure 5 It is a power supply circuit diagram of the GW5AT series FPGA chip in one embodiment; Figure 6 It is a circuit diagram of the FLASH and EEPROM part in one embodiment; Figure 7This is a circuit diagram of the input circuit for the video signal of the GW5AT series FPGA chip in one embodiment; Figure 8 This is an example of the output circuit for the video signal of the GW5AT series FPGA chip. Figure 9 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0024] In one embodiment, such as Figure 1 As shown, an FPGA-based video signal conversion system is provided, including: a signal input module 102, an FPGA processing module 104, a signal output module 106, a power supply module 108, and a storage module 110. The storage module 110 includes a DDR3 storage module 1102, a FLASH module 1104, and an EEPROM module 1106.

[0025] The signal input module 102 is used to acquire externally input video source signals, and transmit the video source signals to the FPGA processing module through the IO port according to the corresponding circuit interface configured by the signal type.

[0026] The FPGA processing module 104 is used to receive video source signals transmitted from different circuit interfaces, and according to the configuration information stored in the FLASH module 1104 and the EEPROM module 1106, calls the DDR3 storage module to perform video conversion operations on the video source signals, and outputs the converted video signals to the signal output module.

[0027] The signal output module 106 is used to receive the converted video signal, perform secondary processing on the video signal according to the adapted interface protocol and format, and output it through the output circuit interface configured by the IO port.

[0028] The FLASH module 1104 and EEPROM module 1106 are connected in parallel with the DDR3 storage module 1102 as the first storage module.

[0029] The power module 108 is connected in series with the first storage module, the DDR3 storage module 1102 and the FPGA processing module 104 respectively.

[0030] The modules in the FPGA-based video signal conversion system can be implemented by software, hardware, or a combination thereof. The modules can be embedded in a processor in a computer device or independent of the processor, or stored in a memory in the computer device in a software form, so as to be called and executed by the processor.

[0031] In one embodiment, as shown in Figure 2 , a FPGA-based video signal conversion method is provided. The method is applied to a system as shown in Figure 1 , and includes the following steps. In step 202, a signal input module is used to collect an externally input video source signal, a corresponding circuit interface is configured according to the type of the video source signal, and the video source signal is transmitted to a FPGA processing unit through an IO port.

[0032] In step 204, the FPGA processing unit receives the video source signal transmitted through the different types of circuit interfaces, calls configuration information pre-stored in a FLASH storage unit and an EEPROM storage unit, enables a DDR3 storage unit as an operation cache, performs video conversion operation on the video source signal, and generates a converted video signal.

[0033] In step 206, the converted video signal received by a signal output unit is secondarily processed according to an adapted interface protocol and format, and the processed video signal is output through an output circuit interface configured by the IO port.

[0034] In the FPGA-based video signal conversion method, first, the programmable characteristics of the FPGA are flexibly adapted to the conversion requirements of multiple types of video signals (such as format conversion, resolution adjustment, etc.), without relying on a single function of a dedicated chip, improving the versatility and expansion capability of the conversion scene, and reducing the technical dependence on dedicated chips. Secondly, the operation process and configuration calling mechanism of the FPGA processing unit have a standardized interface, which can seamlessly compatible with domestic FPGA chips, avoiding technical lock-in through software and hardware decoupling, ensuring the supply independence of the core processing unit, and strengthening the supply chain security. Then, a configuration information pre-storage + cache coordination mechanism is adopted: the configuration information required for conversion is pre-stored in the FLASH module and the EEPROM module to realize fast reading during calling; at the same time, the DDR3 module is enabled as an operation cache to provide a large-capacity temporary data storage space for the FPGA processing module, so that the configuration information calling and video signal conversion operation can be promoted in parallel, reducing data interaction delay and significantly improving overall conversion efficiency. Finally, in the input stage, the corresponding circuit interface is dynamically configured according to the type of the video source signal to ensure that the original signal is transmitted to the FPGA module without loss; in the output stage, the converted signal is subjected to secondary processing of protocol adaptation and format optimization to reduce signal distortion and loss during conversion and ensure the quality of the output signal. In addition, the programmability of the FPGA module reduces the need for dedicated circuit design, which can reduce hardware costs by replacing domestic FPGA solutions and reduce redundant operations to further compress overall costs. The FPGA-based efficient and high-quality video signal conversion is realized, the supply chain security is ensured, and the hardware cost of video conversion requirements is reduced.

[0035] In one embodiment, the FPGA processing unit receives video source signals transmitted through different types of circuit interfaces, uses the FLASH storage unit and the EEPROM storage unit as the first storage unit, calls the configuration information in the first storage unit, and uses the DDR3 storage unit to realize the data interaction path in series to make the FPGA processing unit cooperatively complete the calling of the configuration information and the operation data cache.

[0036] In one embodiment, as shown in Figure 3 , a working process of a video signal conversion system based on a domestic FPGA is provided, and the specific content is as follows: 1) System startup: the power module supplies power, the FLASH and the EEPROM load the stored initialization program and configuration data to the domestic FPGA, and the DDR3 completes its initialization to prepare for receiving and storing data.

[0037] 2) Video signal input: The video conversion input module collects external video signals and transmits them to the domestic FPGA. Based on the powerful interface and logic functions of the domestic FPGA, it can support video signal conversion of various commonly used interface types such as DP, LVDS, MIPI, and HDMI according to the different external video signal input interfaces.

[0038] 3) Video processing conversion: The domestic FPGA calls the algorithm logic in FLASH and EEPROM, combines the data caching and operation assistance of DDR3, and performs format conversion, resolution adjustment, encoding and decoding, etc. on the input video signal.

[0039] 4) Video signal output: The domestic FPGA transmits the processed video signal to the video conversion output module, which outputs the video signal that meets the interface standards and application requirements. It supports various commonly used interfaces such as DP, LVDS, MIPI, and HDMI.

[0040] In one embodiment, as shown in Figure 4 , a system based on a domestic FPGA video signal conversion circuit is provided, which includes a power module, a domestic FPGA, a DDR module 3, a FLASH and EEPROM module, HDMI / LVDS / DP / MIPI signal input, and HDMI / LVDS / DP / MIPI signal output, six main modules.

[0041] Specifically, the power module: provides stable power support for each module (domestic FPGA, DDR3, FLASH EEPROM, etc.) of the system, ensuring the supply of electrical energy required for normal operation of the system. The domestic FPGA module: the invention uses GW5AT series FPGA chips from Gaoke Semiconductor as the core processor, receives video conversion input signals, combines the configuration programs and data stored in FLASH and EEPROM, uses DDR3 for data caching and operation, implements video conversion algorithm processing, and outputs the converted video signals to the video conversion output module.

[0042] It is worth noting that, Figure 5 The power supply circuit for the GW5AT series FPGA chip can be flexibly configured according to the required level of the video signal, meeting the requirements of commonly used video signal interfaces.

[0043] Further, the DDR3 module: is used to temporarily store a large amount of data generated during the video conversion process, such as video frame buffer and intermediate data during operation, to improve the smoothness and efficiency of video processing, and to cooperate with the domestic FPGA for high-speed data interaction. The FLASH and EEPROM modules: store system initialization programs, video conversion related configuration parameters, algorithm logic, etc. The system loads the necessary data to the domestic FPGA during startup to realize system function initialization and configuration.

[0044] It is worth mentioning that, Figure 6 For FLASH and EEPROM part circuit, domestic chip under the sky XT25F32FSOIGU flash chip is used for storing program, algorithm and other data, and domestic Zhongwei love chip AIP24C02ASA8 TR EEPROM chip is used for storing resolution, format, color and other configuration information. Different types of data are stored through FLASH and EEPROM, which ensures the flexibility and service life of the system.

[0045] Further, the video conversion input module is responsible for collecting external video source signals and transmitting them to the domestic FPGA as the original input of video conversion processing.

[0046] Figure 7 It is the input circuit of GW5AT series FPGA chip video signal, and its IO port can be flexibly configured as different interfaces according to the type of input signal.

[0047] Further, the video conversion output module receives the converted video signal output by the domestic FPGA after processing, and outputs the displayable or further processed video signal according to the adaptive interface protocol and format.

[0048] It is worth mentioning that, Figure 8 It is the output circuit of GW5AT series FPGA chip video signal, and its IO port can be flexibly configured as different interfaces according to the type of output signal. The use of domestic FPGA eliminates dependence on foreign chips, reduces supply chain risk, meets the technical needs of key fields such as security and autonomy, and improves the security of the system in defense, government and other scene applications. Secondly, with the help of the parallel processing capability of domestic FPGA, combined with DDR3 cache, complex video conversion operations can be quickly completed, ensuring the real-time and smoothness of video processing, and adapting to high-resolution and high-frame-rate video application scenarios. Compared with the single conversion interface type of special video conversion chips, the configuration information can be flexibly adjusted through FLASH and EEPROM, supporting multiple video format and interface conversion requirements, such as adapting to different display device video output, improving the system's versatility and expandability.

[0049] It should be understood that, although Figures 2-3 The steps in the flowchart of the method are displayed in sequence according to the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this article, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figures 2-3At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0050] In one embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 9 As shown, the computer device includes a processor, memory, network interface, display screen, and input system connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The network interface is used to communicate with external terminals via a network connection. When the computer program is executed by the processor, it implements an FPGA-based video signal conversion method. The display screen can be an LCD screen or an e-ink display screen. The input system can be a touch layer covering the display screen, buttons, a trackball, or a touchpad mounted on the computer device casing, or an external keyboard, touchpad, or mouse.

[0051] Those skilled in the art will understand that Figure 1 , Figures 4-9 The structure shown is merely a block diagram of a portion of the structure related to the present invention and does not constitute a limitation on the computer device to which the present invention is applied. A specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0052] In one embodiment, a computer device is provided, including a memory and a processor, the memory storing a computer program, the processor executing the computer program to perform the following steps: The signal input module acquires externally input video source signals, configures corresponding circuit interfaces according to the type of video source signals, and transmits the video source signals to the FPGA processing unit through the IO port.

[0053] The FPGA processing unit receives video source signals transmitted through different types of circuit interfaces, calls the configuration information pre-stored in the FLASH and EEPROM storage units, and simultaneously enables the DDR3 storage unit as a calculation cache to perform video conversion operations on the video source signals and generate the converted video signals.

[0054] The converted video signal received by the signal output unit is processed according to the adapted interface protocol and format, and the processed video signal is output through the output circuit interface configured by the IO port.

[0055] In one embodiment, when the processor executes the computer program, the following steps are also implemented: the FPGA processing unit receives the video source signal transmitted through different types of circuit interfaces, the FLASH storage unit and the EEPROM storage unit are used as the first storage unit, the configuration information in the first storage unit is called, and the DDR3 storage unit is used as a serial data interaction path to enable the FPGA processing unit to cooperatively complete the calling and operation data buffering of the configuration information.

[0056] In one embodiment, a computer readable storage medium is provided, and the computer readable storage medium stores a computer program. When the computer program is executed by a processor, the following steps are implemented: The video source signal input from the outside is collected through the signal input module, the corresponding circuit interface is configured according to the type of the video source signal, and the video source signal is transmitted to the FPGA processing unit through the IO port.

[0057] The FPGA processing unit receives the video source signal transmitted through different types of circuit interfaces, calls the configuration information pre-stored in the FLASH storage unit and the EEPROM storage unit, simultaneously enables the DDR3 storage unit as an operation cache, performs video conversion operation on the video source signal, and generates a converted video signal.

[0058] The converted video signal received by the signal output unit is processed according to the adapted interface protocol and format, and the processed video signal is output through the output circuit interface configured by the IO port.

[0059] In one embodiment, when the processor executes the computer program, the following steps are also implemented: the FPGA processing unit receives the video source signal transmitted through different types of circuit interfaces, the FLASH storage unit and the EEPROM storage unit are used as the first storage unit, the configuration information in the first storage unit is called, and the DDR3 storage unit is used as a serial data interaction path to enable the FPGA processing unit to cooperatively complete the calling and operation data buffering of the configuration information.

[0060] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer readable storage medium, and when the computer program is executed, the processes of the above-mentioned embodiment methods can be included. Any reference to memory, storage, database or other medium used in the embodiments provided by the present application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration but not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0061] Any combination of the technical features of the above embodiments can be made, and in order to make the description simple, all possible combinations of the technical features in the above embodiments are not described, however, as long as the combination of the technical features does not exist contradictory, it should be considered as the scope of the present application.

[0062] The above embodiments only express several embodiments of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are within the scope of the present application. Therefore, the scope of protection of the present application should be subject to the appended claims.

Claims

1. A video signal conversion system based on FPGA, characterized in that, The system includes: a signal input module, an FPGA processing module, a signal output module, a power supply module, and a storage module; the storage module includes a DDR3 storage module, a FLASH module, and an EEPROM module. The signal input module is used to acquire externally input video source signals, and transmit the video source signals to the FPGA processing module through the IO port according to the corresponding circuit interface configured by the signal type. The FPGA processing module is used to receive the video source signal transmitted from different circuit interfaces, and according to the configuration information stored in the FLASH module and the EEPROM module, call the DDR3 storage module to perform video conversion operation on the video source signal, and output the converted video signal to the signal output module. The signal output module is used to receive the converted video signal, perform secondary processing on the video signal according to the adapted interface protocol and format, and output it through the output circuit interface configured by the IO port. The FLASH module and the EEPROM module are connected in parallel with the DDR3 storage module as the first storage module; The power module is connected in series with the first storage module, the DDR3 storage module and the FPGA processing module.

2. The system according to claim 1, characterized in that, The power module is used to provide electrical energy to each module in the system; The FLASH module and the EEPROM module are used to load key data into the FPGA processing module when the system starts up, and then store different types of key data respectively to complete the system configuration.

3. The system according to claim 1, characterized in that, The FPGA processing module uses Gowin Semiconductor's GW5AT series FPGA chip as its core processor.

4. The system according to claim 1, characterized in that, The I / O port is used to configure the circuit interfaces corresponding to the input and output between modules according to the requirements of the externally input video source signal interface.

5. A video signal conversion method based on FPGA, characterized in that, Applied to the system according to any one of claims 1 to 4, the method comprises: The signal input module acquires externally input video source signals, configures corresponding circuit interfaces according to the type of the video source signals, and transmits the video source signals to the FPGA processing unit through the IO port; The FPGA processing unit receives video source signals transmitted through different types of circuit interfaces, calls configuration information pre-stored in FLASH and EEPROM storage units, and simultaneously enables DDR3 storage unit as a calculation cache to perform video conversion operations on the video source signals to generate converted video signals. The converted video signal received by the signal output unit is processed a second time according to the adapted interface protocol and format, and the processed video signal is output through the output circuit interface configured by the IO port.

6. The method according to claim 1, characterized in that, The FPGA processing unit receives video source signals transmitted via different types of circuit interfaces, calls configuration information pre-stored in the FLASH and EEPROM storage units, and simultaneously enables the DDR3 storage unit as a computation buffer to perform video conversion operations on the video source signals, generating converted video signals, including: The FPGA processing unit receives video source signals transmitted through different types of circuit interfaces, uses the FLASH storage unit and the EEPROM storage unit as the first storage unit, calls the configuration information in the first storage unit, and forms a serial data interaction path with the DDR3 storage unit, so that the FPGA processing unit can collaboratively complete the calling and processing of configuration information and data buffering.

7. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 5 to 6.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 5 to 6.

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