A GaN HEMT all-dielectric suspended field plate device and its fabrication method

Abstract

The application discloses a GaN HEMT full-dielectric suspended field plate device and a preparation method thereof. The device comprises a GaN buffer layer, a GaN channel layer and a nitride barrier layer which are epitaxially grown on a substrate in sequence; a source, a drain, a gate and a passivation layer which are formed above the nitride barrier layer; and a gradient-aperture metasurface which is formed above the passivation layer. The gradient-aperture metasurface constitutes a full-dielectric suspended field plate and is formed in an electrically suspended state between the gate and the drain. The gradient-aperture metasurface comprises periodically arranged dielectric microstructure units. The arrangement period of the units is 100-600 nm. The characteristic size monotonously changes in a gradient manner along a direction from the gate to the drain. The monotonous gradient change comprises linear, exponential and Gaussian gradient changes. The gradient-aperture metasurface is adopted as the full-dielectric suspended field plate. The spatial gradient design of the dielectric metasurface realizes electric field optimization, and can eliminate a parasitic capacitance, realize electromagnetic wave regulation and control and heat management.

Description

Technical Field

[0001] This invention belongs to the field of wide bandgap semiconductor power electronic device technology, specifically relating to a GaN HEMT all-dielectric suspended field plate device and its fabrication method. Background Technology

[0002] GaN HEMTs (Gallium Nitride High Electron Mobility Transistors) are widely used in 5G base stations, electric vehicles, radar, and satellite communications due to their high breakdown electric field (>3 MV / cm), high electron saturation velocity, and high power density. However, under high voltage bias, they suffer from electric field concentration in the gate-drain region, which can easily lead to premature breakdown, current collapse, and degradation of dynamic on-resistance.

[0003] Traditional solutions include metal field plates and dielectric field plates. While metal field plates can effectively modulate the electric field, they introduce significant gate-drain parasitic capacitance (Cgd), limiting high-frequency performance. Dielectric field plates, while reducing parasitic effects, lack the ability to actively control the electric field distribution. In recent years, metasurface technology has made breakthroughs in electromagnetic wave modulation, and its subwavelength artificial micro / nano structures can achieve localized field modulation. However, the application of the metasurface concept to RF power semiconductor devices, especially the construction of gradient aperture, all-dielectric, electrically levitated field plate structures, has not yet been reported. Furthermore, existing field plates often neglect thermal management requirements, making it difficult to address localized hotspots at high power densities. Summary of the Invention

[0004] The purpose of this invention is to provide a GaN HEMT all-dielectric suspended field plate device and its fabrication method. It uses a gradient aperture metasurface as the all-dielectric suspended field plate, and achieves electric field optimization through the spatial gradient design of the dielectric metasurface. It can also eliminate parasitic capacitance and realize electromagnetic wave modulation and thermal management.

[0005] To achieve the above objectives, one aspect of the present invention provides a GaN HEMT all-dielectric floating field plate device, comprising: a GaN buffer layer, a GaN channel layer and a nitride barrier layer epitaxially grown sequentially on a substrate; a source, a drain, a gate and a passivation layer formed above the nitride barrier layer; and a gradient aperture metasurface formed above the passivation layer.

[0006] The gradient aperture metasurface forms a fully dielectric levitation field plate, which is electrically levitation between the gate and the drain. It includes periodically arranged dielectric microstructure units with an arrangement period of 100~600 nm and a feature size of 50~500 nm. The microstructure units exhibit a monotonically varying gradient along the direction from the gate to the drain. The monotonically varying gradient includes linear, exponential, and Gaussian gradients.

[0007] Another aspect of the present invention provides a method for fabricating the above-described GaN HEMT all-dielectric suspended field plate device, comprising:

[0008] Step S1: Epitaxially grow a GaN buffer layer, a GaN channel layer, and a nitride barrier layer sequentially on the substrate;

[0009] Step S2: Fabricate the source and drain ohmic contacts and the gate Schottky contact of the device on the nitride barrier layer;

[0010] Step S3: Deposit a passivation layer on the entire device surface by chemical vapor deposition;

[0011] Step S4: Deposit a dielectric layer above the passivation layer, and form a gradient aperture metasurface structure in the dielectric layer as an all-dielectric suspended field plate through a nanopatterning process. The nanopatterning process includes electron beam lithography, nanoimprinting and self-assembly.

[0012] According to the GaN HEMT all-dielectric suspended field plate device and its fabrication method described above, a gradient aperture metasurface is used as the all-dielectric suspended field plate. The electric field is optimized through the spatial gradient design of the dielectric metasurface, and parasitic capacitance can be eliminated, thereby achieving electromagnetic wave modulation and thermal management. Attached Figure Description

[0013] To more clearly illustrate the technical solutions of the present invention, the accompanying drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort:

[0014] Figure 1 This is a schematic diagram of the cross-sectional structure of the GaN HEMT all-dielectric suspended field plate device according to Embodiment 1 of the present invention;

[0015] Figure 2 This is a top view of the GaN HEMT all-dielectric suspended field plate device according to Embodiment 1 of the present invention;

[0016] Figure 3 This is a schematic diagram of the cross-sectional structure of the GaN HEMT all-dielectric suspended field plate device according to Embodiment 2 of the present invention;

[0017] Figure 4 This is a top view of the GaN HEMT all-dielectric suspended field plate device according to Embodiment 2 of the present invention;

[0018] Figure 5 This is a schematic diagram of the cross-sectional structure of the GaN HEMT all-dielectric suspended field plate device according to Embodiment 3 of the present invention;

[0019] Figure 6 This is a top view of the GaN HEMT all-dielectric suspended field plate device of Embodiment 3 of the present invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0021] Embodiments of the present invention provide a GaN HEMT all-dielectric floating field plate device, comprising: a GaN buffer layer, a GaN channel layer, an AlGaN (or a nitride barrier layer such as AlN, InAlN, ScAlN, etc., with a typical thickness of 5–25 nm); source and drain ohmic contacts; a gate Schottky contact; and a passivation layer (SiN). x The device comprises a fully dielectric suspended field plate, consisting of a gradient-aperture metasurface. The material is a dielectric with a dielectric constant ≥4 or a thermal conductivity ≥50 W / m·K. The microstructure unit period is 100~600 nm, and the characteristic dimensions (aperture, column diameter, or width) exhibit a monotonically varying gradient (linear / exponential / Gaussian) along the gate-to-drain direction. The suspended field plate is not connected to any electrode and is electrically levitated. The device may also include a GaN or in-situ SiNx cap layer located above the nitride barrier layer.

[0022] The dielectric material of the all-dielectric suspended field plate can be a composite of dielectric materials with different dielectric constants or thermal conductivityes, and the composite method includes filling, coating, or embedding. The resulting microstructure unit is a nanopore or nanopillar, and the material is a high dielectric constant dielectric material with a dielectric constant ≥4, a high thermal conductivity dielectric material with a thermal conductivity ≥100, or a composite material of both. High dielectric constant dielectric materials include SiN. x High thermal conductivity dielectric materials include AlN, BN, SiC, and diamond, such as HfO2, Al2O3, HfSiON, and ZrO2. The gradient aperture variation function is a linear, exponential, or Gaussian function with a period of 100–600 nm and an aperture of 50–500 nm. This gradient-characteristic-size metasurface possesses functions such as electric field manipulation, parasitic capacitance manipulation, metasurface electromagnetic wave manipulation, enhanced thermal diffusion, and stress manipulation.

[0023] The present invention also provides a method for fabricating a GaN HEMT all-dielectric suspended field plate device, comprising:

[0024] Step S1: Epitaxially grow a GaN buffer layer, a GaN channel layer, and a nitride barrier layer sequentially on the substrate;

[0025] Step S2: Fabricate the source and drain ohmic contacts and the gate Schottky contact of the device on the nitride barrier layer;

[0026] Step S3: A passivation layer is deposited on the entire device surface using plasma-enhanced chemical vapor deposition.

[0027] Step S4: Deposit a dielectric layer above the passivation layer, and form a gradient aperture metasurface structure in the dielectric layer as an all-dielectric suspended field plate through a nanopatterning process. The nanopatterning process includes electron beam lithography, nanoimprinting, self-assembly and other processes.

[0028] The following three embodiments detail the GaN HEMT all-dielectric suspended field plate device and its fabrication method according to the present invention.

[0029] Example 1: GaN HEMT device based on gradient aperture metasurface all-dielectric suspended field plate

[0030] Step S1: Substrate and Epitaxial Structure Fabrication

[0031] like Figure 1 and Figure 2 As shown, SiC single-crystal substrate 101 was selected due to its combination of high thermal conductivity (~370 W / m·K) and good lattice matching. The following layers were epitaxially grown sequentially using a metal-organic chemical vapor deposition (MOCVD) system: GaN buffer layer 102: 1.5 μm thick, Fe-doped for high resistivity; GaN channel layer 103: 200 nm thick, unintentionally doped; Al₂O₃... 25 Ga0. 75 N barrier layer 104: 20 nm thick, undoped; GaN cap layer 105: 1-2 nm thick, surface passivated with NH3 to reduce interface defects.

[0032] Step S2: Preparation of Ohmic and Schottky Contacts

[0033] Source 201 / Drain 202 Ohmic Contact: A multilayer metal of Ti (20 nm) / Al (100 nm) / Ni (40 nm) / Au (60 nm) was sequentially deposited by electron beam evaporation, followed by rapid thermal annealing (RTA) at 850°C for 30 seconds in a N2 atmosphere to form a low-resistance ohmic contact (specific contact resistance <0.5 Ω·mm) for source 201 / drain 202.

[0034] Gate 203 Schottky contact: Ni (30 nm) / Au (200 nm) T-type or Y-type gate structure is prepared by stripping process, with gate length Lg = 0.2 μm and gate-drain spacing Lgd = 3 μm.

[0035] Device isolation: Photolithography defines the active region, and dry etching or ion implantation defines the mesa region, preferably using multiple multi-energy ion implantation methods, with N-type ions selected for implantation. + (Nitrogen ions), energy 50~250 keV, resistivity of the injected region increased to >10 9 Ω·cm, to achieve electrical isolation.

[0036] Step S3: Passivation layer deposition

[0037] A SiN layer was deposited on the entire device surface using plasma-enhanced chemical vapor deposition (PECVD). x The passivation layer 106, with a thickness of 20nm~150nm, is used to suppress surface states and provide a support platform for subsequent field plates.

[0038] Step S4: Construction of the all-dielectric suspended field plate with gradient aperture:

[0039] The plate is located in SiN x Above the passivation layer 106, a high electric field region is covered between the gate 203 and the drain 202.

[0040] First, a dielectric layer 301 of high k (dielectric constant) dielectric material (such as SiNx, HfO2, Al2O3, HfSiON, ZrO2) or high thermal conductivity dielectric material (such as AlN, BN, SiC, diamond) with a thickness of about 100 nm is deposited on top of the passivation layer using techniques such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).

[0041] Next, ZEP520A electron beam lithography (EBL) is spin-coated onto dielectric layer 301. Electron beam lithography is then used to define a gradient aperture metasurface pattern with a linear gradient distribution along the gate-drain direction. The feature size gradually increases from 50 nm near the gate to 300 nm near the drain, with a period of 400 nm. The shape can be either circular or columnar. The feature size (aperture or column diameter) exhibits a linear, exponential, or Gaussian gradient along the gate-drain direction.

[0042] Finally, the designed gradient aperture metasurface structure 302 was precisely etched using reactive ion etching (RIE), inductively coupled plasma etching (ICP), or atomic layer etching (ALE). After etching, surface dangling bonds on the dielectric layer were repaired using methods such as N2 plasma surface treatment or wet etching to improve dielectric stability.

[0043] In this embodiment, for the dielectric microstructure unit, dielectric materials 301 with high dielectric constant (≥4) or high thermal conductivity (≥100 W / m·K), such as AlN, BN, and diamond, are preferentially selected to simultaneously meet the requirements of electric field optimization and thermal management. Dielectric materials with thermal conductivity ≥100 W / m·K are used to construct the electro-thermal synergistic management channel.

[0044] The gradient aperture metasurface structure 302 allows for flexible adjustment of the electric field distribution according to actual needs, and also supports the integration of other functions, such as electromagnetic wave modulation and stress management. The entire structure requires no additional metal connections, maintaining its all-dielectric, electrically levitated characteristics.

[0045] Example 2: All-dielectric suspended field plate GaNHEMT device based on HfSiON-diamond inlaid composite gradient aperture metasurface

[0046] Step S1: Substrate and Epitaxial Structure Fabrication

[0047] like Figure 3 and Figure 4 As shown, SiC single-crystal substrate 101 was selected due to its combination of high thermal conductivity (~370 W / m·K) and good lattice matching. The following layers were epitaxially grown sequentially using a metal-organic chemical vapor deposition (MOCVD) system: GaN buffer layer 102: 1.5 μm thick, Fe-doped for high resistivity, resistivity > 1 × 10⁻⁶. 5 Ω·cm; GaN channel layer 103: 200nm thick, unintentionally doped; Al0. 25 Ga0. 75 N barrier layer 104: 20 nm thick, undoped; GaN cap layer 105: 1-2 nm thick, surface passivated with NH3 to reduce interface defects.

[0048] Step S2: Preparation of Ohmic and Schottky Contacts

[0049] Source 201 / Drain 202 Ohmic Contact: A multilayer metal of Ti (20 nm) / Al (100 nm) / Ni (40 nm) / Au (60 nm) was sequentially deposited by electron beam evaporation, followed by rapid thermal annealing (RTA) at 850°C for 30 seconds in a N2 atmosphere to form a low-resistance ohmic contact (specific contact resistance <0.5 Ω·mm) for source 201 / drain 202.

[0050] Gate 203 Schottky contact: After photolithography and etching to form gate trenches, Ni (30 nm) / Au (200 nm) T-type or Y-type gate structures are prepared by lift-off process, with gate length Lg = 0.2 μm and gate-drain spacing Lgd = 3 μm.

[0051] Device isolation: Photolithography defines the active region, and dry etching or ion implantation defines the mesa region, preferably using multiple multi-energy ion implantation methods, with N-type ions selected for implantation. + (Nitrogen ions), energy 50~250 keV, resistivity of the injected region increased to >10 9 Ω·cm, to achieve electrical isolation.

[0052] Step S3: Passivation layer deposition

[0053] A SiN layer was deposited on the entire device surface using plasma-enhanced chemical vapor deposition (PECVD). x The passivation layer 106, with a thickness of 20nm~150nm, is used to suppress surface states and provide a support platform for subsequent field plates.

[0054] Step S4: Construction of Hafnium Oxide Silicon (HfSiON)-Diamond Inlaid Composite All-Dielectric Suspended Field Plate

[0055] The plate is located in SiN x Above the passivation layer 106, a critical high electric field region is covered between the gate 203 and the drain 202.

[0056] A dense HfSiON dielectric layer 401 with a thickness of 100 nm was deposited on the device surface above the passivation layer using plasma-enhanced atomic layer deposition (PE-ALD).

[0057] ZEP520A electron beam lithography (EBL) was used to spin-coat a ZfSiON dielectric layer 401 to define a circular window array with a linear gradient distribution along the gate-drain direction. The period P = 400 nm, and the aperture increases linearly from 80 nm near the gate to 280 nm on the drain side, forming a total of 8 gradient unit regions. Reactive ion etching (RIE) was used to etch the windows into the interior of the ZfSiON dielectric layer or to the next SiN layer. x The interface of the passivation layer forms anchor points. After etching, N2 plasma surface treatment is performed to repair the dangling bonds on the HfSiON surface and improve dielectric stability.

[0058] The above-mentioned etching window was filled with nanocrystalline diamond 402 using microwave plasma chemical vapor deposition (MPCVD), and a nanocrystalline diamond film 403 was formed on the surface of the HfSiON dielectric layer. The diamond particle size was controlled between 50 and 250 nm to match the pore size.

[0059] Optionally, the surface of the nanocrystalline diamond film 403 is planarized using chemical mechanical polishing (CMP); the final structure is SiN. x Diamond nanopillars with a gradient distribution are embedded in the matrix to form a composite dielectric metasurface SiN.x Encapsulation and planarization; optionally, another layer of SiN is deposited via PECVD. x A thin film (200 nm thick) completely covers the diamond islands and fills the gaps to form a continuous dielectric layer.

[0060] Example 3: GaN HEMT device based on HfO2 / AlN stacked exponential gradient high-k metasurface

[0061] Step S1: Substrate and Epitaxial Structure Fabrication

[0062] like Figure 5 and Figure 6 As shown, SiC single-crystal substrate 101 was selected due to its combination of high thermal conductivity (~370 W / m·K) and good lattice matching. The following layers were epitaxially grown sequentially using a metal-organic chemical vapor deposition (MOCVD) system: GaN buffer layer 102: 1.5 μm thick, Fe-doped for high resistivity, resistivity > 1 × 10⁻⁶. 5 Ω·cm; GaN channel layer 103: 200nm thick, unintentionally doped; Al0. 25 Ga0. 75 N barrier layer 104: 20 nm thick, undoped; GaN cap layer 105: 1-2 nm thick, surface passivated with NH3 to reduce interface defects.

[0063] Step S2: Preparation of Ohmic and Schottky Contacts

[0064] Source 201 / Drain 202 Ohmic Contact: A multilayer metal of Ti (20 nm) / Al (100 nm) / Ni (40 nm) / Au (60 nm) was sequentially deposited by electron beam evaporation, followed by rapid thermal annealing (RTA) at 850°C for 30 seconds in a N2 atmosphere to form a low-resistance ohmic contact (specific contact resistance <0.5 Ω·mm) for source 201 / drain 202.

[0065] Gate Schottky contact: After photolithography and etching to form gate trenches, Ni (30nm) / Au (200nm) T-type or Y-type gate structures are prepared using a lift-off process, with gate length Lg = 0.2μm and gate-drain spacing Lgd = 3μm.

[0066] Device isolation: Photolithography defines the active region, and dry etching or ion implantation defines the mesa region, preferably using multiple multi-energy ion implantation methods, with N-type ions selected for implantation. + (Nitrogen ions), energy 50~250 keV, resistivity of the injected region increased to >10 9 Ω·cm, to achieve electrical isolation.

[0067] Step S3: Passivation layer deposition

[0068] A SiN layer was deposited on the entire device surface using plasma-enhanced chemical vapor deposition (PECVD). x The passivation layer 106, with a thickness of 20nm~150nm, is used to suppress surface states and provide a support platform for subsequent field plates.

[0069] Step S4: Construction of an all-dielectric suspended field plate of HfO2 / AlN stacked exponential gradient high-k metasurface

[0070] The suspended field plate, located above the passivation layer 106, covers the high-voltage region between the gate 203 and the drain 202. It consists of a periodic stacked structure 502 array composed of HfO2 5021 and AlN 5022, whose feature size monotonically increases exponentially along the gate-drain direction, achieving synergistic optimization of high dielectric constant (high k) gradient control and efficient thermal conduction. AlN combines high thermal conductivity, high breakdown strength (>10 MV / cm), and good interface passivation capability, providing a thermal-electric synergy foundation for subsequent high-k field plates.

[0071] Atomic layer deposition (ALD) was used to alternately deposit HfO2 and AlN films, forming a multilayer stacked structure of [HfO2 (5 nm) / AlN (10 nm)] × 6, with a total thickness of 90 nm. HfO2: dielectric constant ε ≈ 22~25, used to enhance local capacitive coupling to modulate the electric field; AlN: thermal conductivity 100~260 W / (m·K), serving as a thermal diffusion channel and improving the mechanical stability of the structure; all depositions are performed at 400°C to ensure compatibility with GaN processes and to prevent thermal damage.

[0072] ZEP520A electron beam lithography was spin-coated onto the surface of the stacked thin film, and a circular nanopillar pattern was defined using high-precision electron beam lithography (EBL). The feature size of the nanopillar pattern varied exponentially from the gate to the drain: the array period P = 500 nm, which met the subwavelength condition (<λ / 3 @ 10 GHz).

[0073] Anisotropic dry etching was used to etch HfO2 / AlN stacks to form a 90nm high stacked nanostructure 502 array with steep sidewalls (tilt angle >85°) and no obvious interlayer peeling or undercutting.

[0074] After etching, a N2 / O2 mixed plasma surface treatment (50 W, 60 s) is performed to repair surface defects and improve dielectric stability. The entire metasurface structure is not connected to any electrodes and is in a completely electrically floating state, ensuring that no additional parasitic capacitance is introduced.

[0075] A SiN layer was deposited on the entire device surface using plasma-enhanced chemical vapor deposition (PECVD). x Passivation layer 501, with a thickness of 50nm~250nm, is used for surface passivation and protection.

[0076] The device performance and electro-thermal synergistic mechanism in this embodiment include:

[0077] High-k electric field modulation: The high dielectric constant of HfO2 significantly enhances local capacitive coupling, reduces the peak electric field of the gate-drain region, increases the breakdown voltage, and suppresses the current collapse effect.

[0078] Synergistic thermal management: The AlN layer forms a vertical heat conduction path, reducing hotspot temperatures;

[0079] High-frequency characteristics are maintained: Due to the all-dielectric design, the gate-drain parasitic capacitance C gd The increase is relatively small, but compared to traditional metal field plates, it significantly improves the f of the device. T / f max .

[0080] Functional expansion potential: Introducing oxygen vacancies or doping Zr into HfO2 (forming HfZrO2) can endow the field plate with ferropolar polarization control capability and realize dynamic electric field reconstruction; the stacked structure can also be used for multi-band electromagnetic response design, supporting sensing or communication integration in future smart power chips.

[0081] In summary, the GaN HEMT all-dielectric levitation field plate device and its fabrication method based on gradient aperture metasurfaces of this invention achieve the following by constructing a gradient aperture metasurface composed of high k (dielectric constant) or high thermal conductivity dielectric material above the passivation layer as an electrical levitation field plate: uniform surface electric field along the channel direction, improving breakdown voltage; zero metal introduction, eliminating parasitic capacitance and maintaining high-frequency characteristics; selection of high thermal conductivity materials (such as AlN, BN, diamond, etc.) to achieve electro-thermal synergistic management; process compatibility with GaN processes, possessing mass production potential; and suitability for high-frequency, high-voltage, high-power, and intelligent power chip applications.

[0082] The all-dielectric gradient aperture metasurface field plate of this invention is fundamentally different from traditional metal field plates or floating metal field plates:

[0083] Traditional metal field plates or floating metal field plates: By introducing metal plates, the electric field lines at the gate edge are redistributed, "smoothing" the peak electric field and pushing it towards the drain, thereby improving the breakdown voltage. Multiple floating metal field plates are equivalent to introducing multiple "buffer steps," further smoothing the electric field distribution and suppressing electric field peaks more effectively than a single field plate, especially at high voltages. The all-dielectric gradient aperture metasurface field plate of this invention: Structurally, the metal field plate is completely removed, and a two-dimensional structure composed of nanoscale dielectric units (such as pores or columnar structures) is constructed in the passivation layer. The size (aperture) of these units varies gradient along the source-drain direction. It is essentially a local electric field modulator. The gradient aperture structure is equivalent to creating an equivalent refractive index gradient, which can "guide" and "reconstruct" the electric field lines in a very precise way, like an "optical lens" manipulating light waves, achieving unprecedented control over the electric field distribution.

[0084] Compared with floating metal field plates (whether single or multiple), the all-dielectric gradient aperture metasurface field plate of this invention has comprehensive advantages in a systematic and multi-dimensional way:

[0085] (1) Eliminate parasitic capacitance from the root and improve frequency performance.

[0086] Because it completely eliminates the use of metal, the parasitic capacitance introduced by the metal field plate is eliminated at its source. This allows the device to maintain higher intrinsic frequency characteristics, which is crucial for RF applications that require higher operating frequencies. However, regardless of the number of floating metal field plates, additional gate-drain parasitic capacitance (Cgd) is inevitably introduced. This is because a strong capacitive coupling, similar to a MOS structure, is formed between the metal and the underlying two-dimensional electron gas channel. When multiple metal field plates are used, the parasitic capacitance can even superimpose, severely dragging down the device's cutoff frequency (fT) and maximum oscillation frequency (fmax). This is an inherent drawback that metal field plate technology cannot avoid.

[0087] (2) More refined and proactive electric field shaping capabilities

[0088] Each subwavelength unit of a metasurface can be designed to fine-tune the local electric field. By designing gradient-variable apertures, a smooth, continuous, and nearly ideal linear distribution of the electric field from the gate edge to the drain can be achieved. This "engineered" electric field distribution can more efficiently improve the breakdown voltage while avoiding local electric field concentration. In contrast, the control of the electric field by a metal field plate is "passive" and "macroscopic." It can only push the electric field peak further away as a whole, but the shape of the electric field distribution is relatively fixed, and new, smaller electric field peaks may still appear at the edges of multiple field plates.

[0089] (3) Better thermal stability and reliability

[0090] Thanks to the optimized electric field distribution mentioned above, it can reduce the peak electric field at the gate edge to a lower level, thereby significantly improving the breakdown voltage of the device; the all-dielectric structure naturally has better thermal and chemical stability, and since there are no free electrons in the all-dielectric structure, there is no electromigration problem. The materials used (such as AlN, SiN) x It exhibits stable chemical properties, high temperature resistance, and radiation resistance, along with a low interface state density, effectively suppressing dynamic on-resistance degradation. It can be tightly integrated with standard dielectric deposition processes and nanopatterning processes (such as electron beam lithography), simplifying the process flow and avoiding potential problems at the metal-dielectric interface. In contrast, metal field plates face inherent risks such as electromigration, high-temperature diffusion, and interface degradation. Especially under high electric field and high-temperature operating conditions, metal atoms may migrate into GaN, leading to threshold voltage drift or increased leakage current.

[0091] The foregoing has only described certain exemplary embodiments of the present invention by way of illustration. Undoubtedly, those skilled in the art can modify the described embodiments in various ways without departing from the spirit and scope of the present invention. Therefore, the foregoing drawings and descriptions are illustrative in nature and should not be construed as limiting the scope of protection of the claims of the present invention.

Claims

1. A GaN HEMT all-dielectric suspended field plate device, characterized in that, include: A GaN buffer layer, a GaN channel layer, and a nitride barrier layer are epitaxially grown sequentially on the substrate; a source, drain, gate, and passivation layer are formed above the nitride barrier layer. And a gradient aperture metasurface formed above the passivation layer; The gradient aperture metasurface forms a fully dielectric levitation field plate, which is electrically levitation between the gate and the drain. It includes periodically arranged dielectric microstructure units with an arrangement period of 100~600 nm and a feature size of 50~500 nm. The microstructure units exhibit a monotonically varying gradient along the direction from the gate to the drain. The monotonically varying gradient includes linear, exponential, and Gaussian gradients. The dielectric microstructure unit is a nanopore or a nanopillar, with the characteristic size being the pore diameter or the pillar diameter. The material is a high dielectric constant dielectric material with a dielectric constant ≥4, a high thermal conductivity dielectric material with a thermal conductivity ≥50 W / m·K, or a composite material of both.

2. The device as described in claim 1, characterized in that, The high dielectric constant dielectric material includes SiN. x High thermal conductivity dielectric materials include AlN, BN, SiC, and diamond, such as HfO2, Al2O3, HfSiON, and ZrO2.

3. The device as described in claim 1 or 2, characterized in that, The thickness of the nitride barrier layer is 5–25 nm, and the materials include AlGaN, AlN, InAlN, and ScAlN; the thickness of the passivation layer is 20 nm–150 nm, and the materials include SiN. x And SiO2.

4. A method for fabricating the device according to claim 1 or 2, characterized in that, include: Step S1: Epitaxially grow a GaN buffer layer, a GaN channel layer, and a nitride barrier layer sequentially on the substrate; Step S2: Fabricate the source and drain ohmic contacts and the gate Schottky contact of the device on the nitride barrier layer; Step S3: Deposit a passivation layer on the entire device surface by chemical vapor deposition; Step S4: Deposit a dielectric layer above the passivation layer, and form a gradient aperture metasurface structure in the dielectric layer as an all-dielectric suspended field plate through a nanopatterning process. The nanopatterning process includes electron beam lithography, nanoimprinting and self-assembly.

5. The method as described in claim 4, characterized in that, In step S4, a dielectric material with high dielectric constant or high thermal conductivity is deposited above the passivation layer to form a dielectric layer; a gradient aperture metasurface pattern with a linear gradient distribution along the gate to drain direction is defined using a nanopatterning process; and the gradient aperture metasurface structure is etched using an etching process.

6. The method as described in claim 4, characterized in that, In step S4, a high dielectric constant dielectric material is deposited above the passivation layer as a dielectric layer; A circular window array with a linear gradient distribution along the gate-to-drain direction is defined using a nanopatterning process; An etching process is used to etch a window into the interior of the dielectric layer or the interface with the passivation layer. The etched window is filled with a high thermal conductivity dielectric material, and a high thermal conductivity dielectric material film is formed on the surface of the dielectric layer.

7. The method as described in claim 6, characterized in that, The high dielectric constant dielectric material is HfSiON, and the high thermal conductivity dielectric material is nanocrystalline diamond. The surface of the nanocrystalline diamond film is planarized by chemical mechanical polishing.

8. The method as described in claim 4, characterized in that, In step S4, high dielectric constant dielectric material and high thermal conductivity dielectric material are alternately deposited to form a multilayer stacked structure as a dielectric layer; Electron beam photoresist is spin-coated onto the surface of the dielectric layer, and a circular nanopillar pattern is defined by high-precision electron beam lithography. The feature size of the nanopillar pattern varies exponentially along the direction from the gate to the drain. Anisotropic dry etching is used to etch the multilayer stacked structure to form a stacked nanostructure array; Plasma-enhanced chemical vapor deposition is used to deposit a passivation layer on the entire device surface.

9. The method according to any one of claims 5-8, characterized in that, After etching, N2 plasma surface treatment is performed to repair surface defects on the etched surface of the dielectric layer and improve dielectric stability.

Images