Solar cell, preparation method thereof and photovoltaic module

Abstract

The invention relates to a solar cell, a preparation method thereof and a photovoltaic module. The solar cell includes: a semiconductor substrate; the P-type doped layer is arranged on the first surface and is positioned in the first conductive region; the N-type doped layer is arranged on the first surface and is positioned in the second conductive region; the isolation groove is concavely formed in the first surface of the isolation region; the isolation groove comprises a first side wall and a second side wall which are oppositely arranged along the arrangement direction of the first conductive region and the second conductive region, the first side wall is arranged adjacent to the P-type doped layer, and the second side wall is arranged adjacent to the N-type doped layer; wherein the orthographic projection of the first side wall on the semiconductor substrate is tangent to the orthographic projection of the P-type doping layer on the semiconductor substrate, and the orthographic projection of the second side wall on the semiconductor substrate is spaced from the orthographic projection of the N-type doping layer on the semiconductor substrate. The battery efficiency can be improved.

Description

Technical Field

[0001] This application relates to the field of solar cell technology, and in particular to a solar cell and its preparation method, and a photovoltaic module. Background Technology

[0002] A solar cell is a device that converts sunlight into electrical energy. Specifically, when a solar cell is in operation, sunlight shines on the semiconductor pn junction, forming new electron-hole pairs. Under the influence of the built-in electric field of the pn junction, photogenerated holes flow to the p-region, and photogenerated electrons flow to the n-region. When the circuit is connected, an electric current is generated. Solar cells where both the positive and negative electrodes are located on the back side are called back-contact solar cells. Compared to double-sided contact solar cells, back-contact solar cells have no metal grid lines on the front side. The emitter, back field, and corresponding positive and negative metal electrodes are integrated on the back side of the cell. This structure minimizes optical losses and can achieve higher conversion efficiency within the same area, making it one of the current technological directions for achieving high-efficiency crystalline silicon solar cells. However, the efficiency of current back-contact solar cells needs further improvement. Summary of the Invention

[0003] Therefore, it is necessary to provide a solar cell and its preparation method, as well as a photovoltaic module, to address the above-mentioned problems.

[0004] In a first aspect, embodiments of this application provide a solar cell, comprising:

[0005] A semiconductor substrate includes a first surface and a second surface disposed opposite to each other along the thickness direction of the semiconductor substrate; the first surface includes a first conductive region, a second conductive region and an isolation region, the isolation region being located between the first conductive region and the second conductive region;

[0006] A P-type doped layer is disposed on the first surface and located in the first conductive region;

[0007] An N-type doped layer is disposed on the first surface and located in the second conductive region;

[0008] An isolation trench is recessed on the first surface of the isolation region; along the arrangement direction of the first conductive region and the second conductive region, the isolation trench includes a first sidewall and a second sidewall disposed opposite to each other, the first sidewall being disposed adjacent to the P-type doped layer, and the second sidewall being disposed adjacent to the N-type doped layer;

[0009] Wherein, the orthographic projection of the first sidewall on the semiconductor substrate is tangent to the orthographic projection of the P-type doped layer on the semiconductor substrate, and the orthographic projection of the second sidewall on the semiconductor substrate is spaced apart from the orthographic projection of the N-type doped layer on the semiconductor substrate.

[0010] In one embodiment, the doping concentration of the P-type doped layer is between 3 × 10⁻⁶. 19 cm -3 -1×10 21 cm -3 ;

[0011] And / or, the doping concentration of the N-type doped layer is between 9 × 10⁻⁶. 19 cm -3 -1×10 21 cm -3 .

[0012] In one embodiment, the solar cell further includes a first tunneling layer located between the P-type doped layer and the first surface of the first conductive region;

[0013] The orthographic projection of the first tunneling layer on the semiconductor substrate is tangent to the orthographic projection of the first sidewall on the semiconductor substrate.

[0014] In one embodiment, the solar cell further includes a second tunneling layer located between the N-type doped layer and the first surface of the second conductive region;

[0015] The orthographic projection of the second tunneling layer on the semiconductor substrate is tangent to the orthographic projection of the second sidewall on the semiconductor substrate.

[0016] In one embodiment, the isolation groove includes a bottom wall connecting the first sidewall and the second sidewall;

[0017] The bottom wall is either polished or has a velvety surface.

[0018] In one embodiment, the first sidewall includes a first subwall and a second subwall, the first subwall being connected to the first surface located in the first conductive region, and the second subwall being connected to the first subwall and the bottom wall;

[0019] The angle between the second sub-wall and the plane containing the semiconductor substrate is greater than the angle between the first sub-wall and the plane containing the semiconductor substrate.

[0020] In one embodiment, the angle between the second sub-wall and the plane containing the semiconductor substrate is less than 90°.

[0021] In one embodiment, the angle between the first sub-wall and the plane containing the semiconductor substrate is between 20° and 80°.

[0022] In one embodiment, the first sub-wall, the second sub-wall, and the second sidewall are all polished surfaces.

[0023] In one embodiment, the base size of the smallest base structure on the second sub-wall is greater than the base size of the largest base structure on the first sub-wall.

[0024] In one embodiment, the average base size of all base structures on the first sub-wall is smaller than the average base size of all base structures on the second sidewall per unit area.

[0025] In one embodiment, the base size of the smallest base structure on the bottom wall is greater than the base size of the largest base structure on the second sub-wall; and the base size of the smallest base structure on the bottom wall is greater than the base size of the largest base structure on the second side wall.

[0026] In one embodiment, the distance between the orthographic projection of the second sidewall onto the semiconductor substrate and the orthographic projection of the N-type doped layer onto the semiconductor substrate is between 1 μm and 30 μm;

[0027] And / or, the N-type doped layer includes a main body and a ramp portion, the ramp portion being connected to the side of the main body near the isolation trench; the thickness of the ramp portion gradually increases from the isolation trench toward the main body.

[0028] In one embodiment, the distance between the first surface and the second surface of the first conductive region is greater than the distance between the first surface and the second surface of the second conductive region.

[0029] Secondly, this application provides a method for fabricating a solar cell, comprising:

[0030] A semiconductor substrate is provided; the semiconductor substrate includes a first surface and a second surface disposed opposite to each other along the thickness direction of the semiconductor substrate; the first surface includes a first conductive region, a second conductive region and an isolation region, the isolation region being located between the first conductive region and the second conductive region;

[0031] A P-type doped layer is formed in the first conductive region of the first surface;

[0032] An N-type doped layer is formed in the second conductive region of the first surface, and an isolation trench is formed in the first surface of the isolation region. Along the arrangement direction of the first conductive region and the second conductive region, the isolation trench includes a first sidewall and a second sidewall disposed opposite to each other. The first sidewall is disposed adjacent to the P-type doped layer, and the second sidewall is disposed adjacent to the N-type doped layer. The orthographic projection of the first sidewall on the semiconductor substrate is tangent to the orthographic projection of the P-type doped layer on the semiconductor substrate, and the orthographic projection of the second sidewall on the semiconductor substrate is spaced apart from the orthographic projection of the N-type doped layer on the semiconductor substrate.

[0033] In one embodiment, the step of forming a P-type doped layer in the first conductive region of the first surface includes:

[0034] A P-type doped material layer and a first protective layer are formed sequentially on the first surface;

[0035] A first patterned mask layer is printed on the first protective layer; the first patterned mask layer covers the first protective layer of the first conductive region, and exposes the first protective layer of the second conductive region and the isolation region;

[0036] The first protective layer of the second conductive region and the isolation region is etched.

[0037] Remove the first patterned mask layer;

[0038] The P-type doped material layer of the second conductive region and the isolation region is etched to obtain the P-type doped layer;

[0039] The semiconductor substrate of the second conductive region and the isolation region is etched.

[0040] In one embodiment, prior to the step of forming a sequentially stacked P-type doped material layer and a first protective layer on the first surface, the method includes:

[0041] A first tunneling material layer is formed on the first surface;

[0042] After the step of etching the P-type doped material layer of the second conductive region and the isolation region to obtain the P-type doped layer, and before the step of etching the semiconductor substrate of the second conductive region and the isolation region, the process includes:

[0043] The first tunneling material layer of the second conductive region and the isolation region is etched to obtain the first tunneling layer.

[0044] In one embodiment, the step of forming an N-type doped layer in the second conductive region on the first surface and forming an isolation trench on the first surface of the isolation region includes:

[0045] An N-type doped material layer and a second protective layer are formed sequentially on the first surface;

[0046] A second patterned mask layer is printed on the second protective layer; the second patterned mask layer covers the second protective layer of the second conductive region, exposing the second protective layer of the first conductive region and the isolation region;

[0047] The second protective layer of the first conductive region and the isolation region is etched.

[0048] Remove the second patterned mask layer;

[0049] The N-type doped material layer of the first conductive region and the isolation region is etched to obtain the N-type doped layer;

[0050] The semiconductor substrate of the first conductive region and the isolation region is etched.

[0051] In one embodiment, prior to the step of forming sequentially stacked N-type doped material layers and a second protective layer on the first surface, the method includes:

[0052] A second tunneling material layer is formed on the first surface;

[0053] After the step of etching the N-type doped material layer of the first conductive region and the isolation region to obtain the N-type doped layer, and before the step of etching the semiconductor substrate of the first conductive region and the isolation region, the process includes:

[0054] The second tunneling material layer of the first conductive region and the isolation region is etched to obtain the second tunneling layer.

[0055] Thirdly, this application provides a photovoltaic module, including the solar cell in any embodiment of the first aspect, or including a solar cell prepared using the preparation method of the solar cell in any embodiment of the second aspect.

[0056] The aforementioned solar cells, their fabrication methods, and photovoltaic modules, by setting an isolation trench between the first and second conductive regions, can prevent leakage current caused by contact between the P-type and N-type doped layers. By making the orthographic projection of the first sidewall on the semiconductor substrate tangent to the orthographic projection of the P-type doped layer on the semiconductor substrate, the coverage area of ​​the P-type doped layer in the first conductive region can be larger, which is beneficial for achieving a higher doping concentration, lower lateral resistance, and lower contact resistance of the P-type doped layer, thereby improving the fill factor and thus the cell efficiency. By making the orthographic projection of the second sidewall on the semiconductor substrate alternate with the orthographic projection of the N-type doped layer on the semiconductor substrate, it is equivalent to making the N-type doped layer "retreat" in the second conductive region, which is beneficial for depositing a passivation film layer in the retreated region, reducing photoparasitic absorption, and simultaneously improving short-circuit current and open-circuit voltage. Attached Figure Description

[0057] To more clearly illustrate the technical solutions in the embodiments or exemplary embodiments of this application, the drawings used in the description of the embodiments or exemplary embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0058] Figure 1 This is a schematic diagram of a partial cross-sectional structure of a solar cell provided in an embodiment of this application.

[0059] Figure 2 for Figure 1 The diagram shows a top view of the N-type doped layer, the isolation trench, and the P-type doped layer of the solar cell.

[0060] Figure 3 This is a schematic diagram of a partial cross-sectional structure of another solar cell provided in an embodiment of this application.

[0061] Figure 4 This is a partial cross-sectional structural diagram of another solar cell provided in an embodiment of this application.

[0062] Figure 5 for Figure 1 A schematic diagram of the tower base structure on the first sub-wall, second sub-wall, second sidewall, and bottom wall of the isolation tank in the solar cell shown.

[0063] Figure 6 This is a schematic flowchart of a method for fabricating a solar cell according to an embodiment of this application.

[0064] Figure 7 for Figure 6 A schematic diagram of the cross-sectional structure after the formation of the first patterned mask layer during the fabrication process shown.

[0065] Figure 8 for Figure 6 The diagram shows the cross-sectional structure of the first protective layer after patterning during the preparation process.

[0066] Figure 9 for Figure 6 The diagram shows a cross-sectional structure of the P-type doped layer and the first doped layer after their formation during the fabrication process.

[0067] Figure 10 for Figure 6 A schematic diagram of the cross-sectional structure after the formation of the second patterned mask layer during the fabrication process shown.

[0068] Figure label:

[0069] 1. Solar cell; 10. Semiconductor substrate; 10a. First surface; 10a1. First conductive region; 10a2. Second conductive region; 10a3. Isolation region; 10b. Second surface; 10c. Tower base structure; 20. P-type doped layer; 30. N-type doped layer; 31. Main body; 32. Sloping section; 40. Isolation trench; 41. First sidewall; 411. First sub-wall; 412. Second sub-wall; 42. Second sidewall; 43. Bottom wall 50. First tunneling layer; 60. Second tunneling layer; 71. First passivation layer; 72. First antireflection layer; 81. Second passivation layer; 82. Second antireflection layer; 91. First electrode; 92. Second electrode; 2. First tunneling material layer; 3. P-type doped material layer; 4. First protective layer; 5. First patterned mask layer; 6. Second tunneling material layer; 7. N-type doped material layer; 8. Second protective layer; 9. Second patterned mask layer. Detailed Implementation

[0070] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application are described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0071] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0072] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, part, region, layer, doping type, or portion discussed below may be referred to as a second element, part, region, layer, or portion.

[0073] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0074] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0075] Embodiments of the application are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures), thus allowing for the expectation of variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the application.

[0076] In one related technology, an isolation trench is provided between P-type doped polysilicon and N-type doped polysilicon, with a portion of the P-type doped polysilicon suspended above the isolation trench. However, this structure has poor passivation, increases carrier recombination, resulting in low battery efficiency and poor performance under low light intensity (weak light) conditions.

[0077] In related technology two, an isolation trench is provided between P-type doped polycrystalline silicon and N-type doped polycrystalline silicon. In a top-view orientation, there is a gap between the end of the P-type doped polycrystalline silicon closest to the isolation trench and the trench itself; that is, the P-type doped polycrystalline silicon "recedes." During fabrication, a laser is used to create an etching layer on the borosilicate glass, resulting in a suspended end on the P-type doped polycrystalline silicon, located above the isolation trench. Before forming the surface passivation layer, the suspended end is removed, causing the P-type doped polycrystalline silicon to "recede" during this process. However, on the one hand, this structure easily increases contact resistance and reduces battery efficiency; on the other hand, this fabrication process is relatively cumbersome.

[0078] In view of at least one of the above-mentioned problems, embodiments of this application provide a solar cell and its fabrication method, as well as a photovoltaic module. By setting an isolation trench between the first conductive region and the second conductive region, leakage current can be prevented from forming due to contact between the P-type doped layer and the N-type doped layer. By making the orthographic projection of the first sidewall on the semiconductor substrate tangent to the orthographic projection of the P-type doped layer on the semiconductor substrate, the coverage area of ​​the P-type doped layer in the first conductive region can be larger, which is beneficial to a higher doping concentration of the P-type doped layer, a lower lateral resistance, and a lower contact resistance, thereby improving the fill factor and thus improving the cell efficiency. By making the orthographic projection of the second sidewall on the semiconductor substrate alternate with the orthographic projection of the N-type doped layer on the semiconductor substrate, it is equivalent to making the N-type doped layer "retreat" in the second conductive region, which is beneficial to deposit a passivation film layer in the retreated region, reduce photoparasitic absorption, and simultaneously improve the short-circuit current and open-circuit voltage.

[0079] Firstly, referring to Figure 1 , Figure 2 and Figure 3 As shown, this application embodiment provides a solar cell 1, which includes a semiconductor substrate 10, a P-type doped layer 20, an N-type doped layer 30, and an isolation trench 40.

[0080] The semiconductor substrate 10 includes a first surface 10a and a second surface 10b disposed opposite to each other along the thickness direction of the semiconductor substrate 10; the first surface 10a is the side facing away from the sun when the solar cell 1 is operating, and the second surface 10b is the side facing the sun when the solar cell 1 is operating. The first surface 10a includes a first conductive region 10a1, a second conductive region 10a2, and an isolation region 10a3, with the isolation region 10a3 located between the first conductive region 10a1 and the second conductive region 10a2. A P-type doped layer 20 is disposed on the first surface 10a and located in the first conductive region 10a1. An N-type doped layer 30 is disposed on the first surface 10a and located in the second conductive region 10a2. An isolation trench 40 is recessed on the first surface 10a of the isolation region 10a3. Along the arrangement direction of the first conductive region 10a1 and the second conductive region 10a2, the isolation trench 40 includes a first sidewall 41 and a second sidewall 42 disposed opposite to each other. The first sidewall 41 is adjacent to the P-type doped layer 20, and the second sidewall 42 is adjacent to the N-type doped layer 30. Here, the first sidewall 41 can be understood as the sidewall of the isolation trench 40 that is closest to the P-type doped layer 20. The second sidewall 42 can be understood as the sidewall of the isolation trench 40 that is closest to the N-type doped layer 30.

[0081] Among them, such as Figure 2 As shown, the orthographic projection of the first sidewall 41 on the semiconductor substrate 10 is tangent to the orthographic projection of the P-type doped layer 20 on the semiconductor substrate 10, and the orthographic projection of the second sidewall 42 on the semiconductor substrate 10 is spaced apart from the orthographic projection of the N-type doped layer 30 on the semiconductor substrate 10. It should be noted that "the orthographic projection of the first sidewall 41 on the semiconductor substrate 10 is tangent to the orthographic projection of the P-type doped layer 20 on the semiconductor substrate 10" means that the orthographic projection of the first sidewall 41 and the orthographic projection of the P-type doped layer 20 do not overlap, and the orthographic projection of the first sidewall 41 and the orthographic projection of the P-type doped layer 20 are connected.

[0082] By providing an isolation trench 40 between the first conductive region 10a1 and the second conductive region 10a2, leakage current can be prevented from forming due to contact between the P-type doped layer 20 and the N-type doped layer 30. By making the orthographic projection of the first sidewall 41 on the semiconductor substrate 10 tangent to the orthographic projection of the P-type doped layer 20 on the semiconductor substrate 10, the coverage area of ​​the P-type doped layer 20 in the first conductive region 10a1 can be larger, which is beneficial for achieving a higher doping concentration, lower lateral resistance, and lower contact resistance of the P-type doped layer 20, thereby improving the fill factor and thus improving the battery efficiency. By making the orthographic projection of the second sidewall 42 on the semiconductor substrate 10 spaced apart from the orthographic projection of the N-type doped layer 30 on the semiconductor substrate 10, it is equivalent to making the N-type doped layer 30 "retreat" in the second conductive region 10a2, which is beneficial for depositing a passivation film layer in the retreated region, reducing photoparasitic absorption, and simultaneously improving the short-circuit current and open-circuit voltage.

[0083] In one embodiment, the semiconductor substrate 10 is N-type doped.

[0084] By making the orthographic projection of the first sidewall 41 on the semiconductor substrate 10 tangent to the orthographic projection of the P-type doped layer 20 on the semiconductor substrate 10, the coverage area of ​​the P-type doped layer 20 in the first conductive region 10a1 can be made larger. In this way, the effective area of ​​the PN junction is larger, which improves the battery efficiency.

[0085] It should be noted that the solar cell 1 provided in this application embodiment can adopt an inkjet printing route, abandoning the laser route. For example, in related technology two, when laser film opening is used, the instantaneous high temperature of the laser will cause the doping concentration of P-type doped polysilicon in the film opening area to rise rapidly. Furthermore, since P-type doped polysilicon is difficult to etch, it is difficult to etch the P-type doped polysilicon in the film opening area. However, this application adopts an inkjet printing route, eliminating the need for laser film opening. This not only avoids damage to the semiconductor substrate 10 caused by the laser but also avoids increasing the doping concentration of P-type doped polysilicon in the film opening area. Thus, under the same etching difficulty, this application embodiment can achieve a higher doping concentration of the P-type doped layer 20, resulting in lower lateral resistance and lower contact resistance, further improving cell efficiency.

[0086] In one embodiment, the material of the semiconductor substrate 10 may be a silicon substrate, a compound semiconductor substrate 10, etc. The silicon substrate includes a monocrystalline silicon substrate, a polycrystalline silicon substrate, an amorphous silicon substrate, etc., and the compound semiconductor substrate 10 includes a gallium arsenide substrate, a copper indium gallium selenide substrate, etc.

[0087] In one embodiment, the doping concentration of the p-type doped layer 20 is between 3 × 10⁻⁶. 19 cm -3 -1×10 21 cm -3 As described above, the embodiments of this application can achieve a higher doping concentration in the P-type doped layer 20, thereby reducing the lateral resistance and contact resistance, and further improving battery efficiency.

[0088] In one embodiment, the doping concentration of the N-type doped layer 30 is between 9 × 10⁻⁶. 19 cm -3 -1×10 21 cm -3 Thus, on the one hand, it is beneficial to achieve a higher doping concentration of the N-type doped layer 30, thereby reducing the lateral resistance and contact resistance, and further improving the battery efficiency; on the other hand, a higher N-type doping concentration is more conducive to etching.

[0089] In one embodiment, reference Figure 1As shown, the solar cell 1 also includes a first tunneling layer 50, which is located between the p-type doped layer 20 and the first surface 10a of the first conductive region 10a1. The orthographic projection of the first tunneling layer 50 on the semiconductor substrate 10 is tangent to the orthographic projection of the first sidewall 41 on the semiconductor substrate 10. It should be noted that "the orthographic projection of the first tunneling layer 50 on the semiconductor substrate 10 is tangent to the orthographic projection of the first sidewall 41 on the semiconductor substrate 10" means that the orthographic projection of the first tunneling layer 50 and the orthographic projection of the first sidewall 41 do not overlap, and the orthographic projection of the first tunneling layer 50 and the orthographic projection of the first sidewall 41 are connected.

[0090] In this way, the first tunneling layer 50 can completely cover the first surface 10a of the first conductive region 10a1, which is beneficial to improving the passivation effect.

[0091] In one embodiment, the solar cell 1 may further include a first intrinsic amorphous silicon layer (not shown), which is located between the p-type doped layer 20 and the first surface 10a of the first conductive region 10a1. The orthographic projection of the first intrinsic amorphous silicon layer on the semiconductor substrate 10 is tangent to the orthographic projection of the first sidewall 41 on the semiconductor substrate 10.

[0092] In one embodiment, the solar cell 1 further includes a second tunneling layer 60, which is located between the N-type doped layer 30 and the first surface 10a of the second conductive region 10a2. The orthographic projection of the second tunneling layer 60 onto the semiconductor substrate 10 is tangent to the orthographic projection of the second sidewall 42 onto the semiconductor substrate 10. It should be noted that "the orthographic projection of the second tunneling layer 60 onto the semiconductor substrate 10 is tangent to the orthographic projection of the second sidewall 42 onto the semiconductor substrate 10" means that the orthographic projection of the second tunneling layer 60 and the orthographic projection of the second sidewall 42 do not overlap, and the orthographic projection of the second tunneling layer 60 and the orthographic projection of the second sidewall 42 are connected.

[0093] In this way, the second tunneling layer 60 can completely cover the first surface 10a of the second conductive region 10a2, which is beneficial to improving the passivation effect.

[0094] In one embodiment, the isolation groove 40 includes a bottom wall 43 connecting the first sidewall 41 and the second sidewall 42. The bottom wall 43 has a polished surface, or a velvety surface. Figure 1 The bottom wall 43 is a polished surface. Figure 4 The bottom wall 43 is velvety.

[0095] It should be noted that the bottom wall 43 is a polished surface, which can make the bottom wall 43 reflect light better, thereby reflecting the light that will be emitted from the semiconductor substrate 10 back into the semiconductor substrate 10, thus improving the battery efficiency.

[0096] In one embodiment, the first sidewall 41 includes a first sub-wall 411 and a second sub-wall 412. The first sub-wall 411 is connected to the first surface 10a located in the first conductive region 10a1, and the second sub-wall 412 connects the first sub-wall 411 and the bottom wall 43. The angle between the second sub-wall 412 and the plane containing the semiconductor substrate 10 is greater than the angle between the first sub-wall 411 and the plane containing the semiconductor substrate 10. In other words, the slope of the first sub-wall 411 is relatively gentle, while the slope of the second sub-wall 412 is relatively steep. Here, the plane containing the semiconductor substrate 10 is a plane perpendicular to the thickness direction of the semiconductor substrate 10. (Reference) Figure 1 As shown, the angle between the second sub-wall 412 and the plane where the semiconductor substrate 10 is located is β, and the angle between the first sub-wall 411 and the plane where the semiconductor substrate 10 is located is α.

[0097] The above configuration can avoid the formation of right-angle or near-right-angle corners on the wall of the isolation tank 40, thereby facilitating the deposition of a first passivation layer 71 with a relatively uniform film thickness in the subsequent process within the isolation tank 40, and thus improving the passivation performance.

[0098] It is important to emphasize that when the first sub-wall 411 is planar, the angle between the plane containing the first sub-wall 411 and the plane containing the semiconductor substrate 10 is α. When the first sub-wall 411 is approximately planar or "non-planar," the angle α can be defined as follows: Figure 1 In the cross-section shown, the angle between the line connecting the two opposite endpoints of the first sub-wall 411 and the plane containing the semiconductor substrate 10 is α. When the second sub-wall 412 is planar, the angle between the plane containing the second sub-wall 412 and the plane containing the semiconductor substrate 10 is β. When the second sub-wall 412 is approximately planar or "non-planar," the angle β can be defined as follows: Figure 1 In the cross section shown, the angle between the line connecting the endpoints of the opposite ends of the second sub-wall 412 and the plane containing the semiconductor substrate 10 is β.

[0099] In one embodiment, the angle between the second sub-wall 412 and the plane containing the semiconductor substrate 10 is less than 90°. That is: Figure 1 β is less than 90°. This avoids the formation of right-angle or near-right-angle corners at the connection between the first sub-wall 411 and the second sub-wall 412, thus facilitating the subsequent process to deposit a first passivation layer 71 with a relatively uniform film thickness in the isolation tank 40, thereby improving passivation performance.

[0100] In one embodiment, the angle between the first sub-wall 411 and the plane containing the semiconductor substrate 10 is between 20° and 80°, i.e., 20° ≤ α ≤ 80°. Exemplarily, α can be 20°, 30°, 40°, 60°, 70°, 80°, or any two of the above values.

[0101] Understandably, if α is less than 20°, the connection between the first sub-wall 411 and the sidewall of the first tunneling layer 50 is prone to forming a near-right angle, which is not conducive to the formation of a first passivation layer 71 with a relatively uniform film thickness. If α is greater than 80°, the connection between the first sub-wall 411 and the second sub-wall 412 is prone to forming a near-right angle, which is also not conducive to the formation of a first passivation layer 71 with a relatively uniform film thickness. By keeping the angle α within the above range, it is easier for subsequent processes to deposit a first passivation layer 71 with a relatively uniform film thickness in the isolation tank 40, thereby improving the passivation performance.

[0102] In one embodiment, the first sub-wall 411, the second sub-wall 412, and the second sidewall 42 are all polished surfaces. This makes the first sub-wall 411, the second sub-wall 412, and the second sidewall 42 relatively flat, which is beneficial for depositing a first passivation layer 71 with a relatively uniform film thickness, thereby improving passivation performance.

[0103] In one embodiment, such as Figure 3 As shown, the solar cell 1 further includes a first passivation layer 71, which covers the P-type doped layer 20, the N-type doped layer 30, and the sidewalls of the isolation trench 40. For example, the material of the first passivation layer 71 may include aluminum oxide.

[0104] In one embodiment, such as Figure 3 As shown, the solar cell 1 also includes a first antireflection layer 72, which covers the first passivation layer 71. For example, the material of the first antireflection layer 72 may include silicon nitride, silicon oxynitride, etc.

[0105] In one embodiment, such as Figure 3 As shown, the solar cell 1 also includes a first electrode 91 and a second electrode 92. The first electrode 91 penetrates the first passivation layer 71 and the first antireflection layer 72 and is electrically connected to the P-type doped layer 20. The second electrode 92 penetrates the first passivation layer 71 and the first antireflection layer 72 and is electrically connected to the N-type doped layer 30.

[0106] In one embodiment, such as Figure 3 As shown, the solar cell 1 further includes a second passivation layer 81, which is disposed on the second surface 10b. For example, the material of the second passivation layer 81 may include aluminum oxide.

[0107] In one embodiment, such as Figure 3 As shown, the solar cell 1 further includes a second antireflection layer 82, which is disposed on the side of the second passivation layer 81 away from the semiconductor substrate 10. For example, the material of the second antireflection layer 82 may include silicon nitride, silicon oxynitride, etc.

[0108] In one embodiment, the base size of the smallest base structure 10c on the second sub-wall 412 is larger than the base size of the largest base structure 10c on the first sub-wall 411.

[0109] It should be noted here that the first sub-wall 411, the second sub-wall 412, and the second sidewall 42 are polished surfaces. Therefore, as... Figure 5 As shown, the first sub-wall 411, the second sub-wall 412, and the second sidewall 42 all have tower base structures 10c. In this embodiment, the tower base dimension refers to the side length of the bottom surface of the tower base structure 10c. The smallest tower base structure 10c on the second sub-wall 412 refers to the tower base structure 10c with the smallest tower base dimension among all the tower base structures 10c on the second sub-wall 412. The largest tower base structure 10c on the first sub-wall 411 refers to the tower base structure 10c with the largest tower base dimension among all the tower base structures 10c on the first sub-wall 411. For ease of measurement, it can also be defined as follows: within a unit area, the tower base structure 10c with the smallest tower base dimension among all the tower base structures 10c on the second sub-wall 412 is the smallest tower base structure 10c on the second sub-wall 412 as described above. Within a unit area, among all the tower base structures 10c on the first sub-wall 411, the tower base structure 10c with the largest tower base size is the largest tower base structure 10c on the first sub-wall 411 mentioned above. The unit area can be determined according to actual conditions, and the embodiments of this application do not particularly limit the magnitude of the unit area.

[0110] Reference Figure 5 As shown, the base size of the smallest base structure 10c on the second sub-wall 412 is L2, and the base size of the largest base structure 10c on the first sub-wall 411 is L4. It should be noted that the second sub-wall 412 is closer to the center of the semiconductor substrate 10 and has a greater need for reflection. By making L2 > L4, the reflectivity of the second sub-wall 412 can be strengthened, thereby matching the light emission requirement with the reflectivity, effectively reducing back surface light escape, and improving the battery short-circuit current.

[0111] In one embodiment, within a unit area, the average base size of all the base structures 10c on the first sub-wall 411 is smaller than the average base size of all the base structures 10c on the second sidewall 42. Exemplarily, the average base size on the first sub-wall 411 can be obtained by adding and averaging the base sizes of all the base structures 10c on the first sub-wall 411 within a unit area. Similarly, the average base size on the second sidewall 42 can be obtained by adding and averaging the base sizes of all the base structures 10c on the second sidewall 42 within a unit area.

[0112] The second sidewall 42 is closer to the center of the semiconductor substrate 10, and has a greater need for reflection. The above arrangement can make the reflection effect of the second sidewall 42 stronger, so that the light emission demand matches the reflection capability, effectively reducing back surface light escape and improving the battery short-circuit current.

[0113] In one embodiment, the average base size of all base structures 10c on the second sub-wall 412 within a unit area is equal to the average base size of all base structures 10c on the second sidewall 42. Exemplarily, the average base size on the second sub-wall 412 can be obtained by adding and averaging the base sizes of all base structures 10c on the second sub-wall 412 within a unit area. Here, "equal to" includes both absolute and approximate equality.

[0114] In one embodiment, the bottom wall 43 is a polished surface. The base size of the smallest base structure 10c on the bottom wall 43 is larger than the base size of the largest base structure 10c on the second sub-wall 412. Furthermore, the base size of the smallest base structure 10c on the bottom wall 43 is larger than the base size of the largest base structure 10c on the second side wall 42. The smallest base structure 10c on the bottom wall 43 refers to the base structure 10c with the smallest base size among all base structures 10c on the bottom wall 43. The largest base structure 10c on the second sub-wall 412 refers to the base structure 10c with the largest base size among all base structures 10c on the second sub-wall 412. The largest base structure 10c on the second side wall 42 refers to the base structure 10c with the largest base size among all base structures 10c on the second side wall 42. For ease of measurement, the following definition can also be used: Within a unit area, among all the base structures 10c on the bottom wall 43, the base structure 10c with the smallest base size is the smallest base structure 10c on the bottom wall 43 as described above. Within a unit area, among all the base structures 10c on the second sub-wall 412, the base structure 10c with the largest base size is the largest base structure 10c on the second sub-wall 412 as described above. Within a unit area, among all the base structures 10c on the second side wall 42, the base structure 10c with the largest base size is the largest base structure 10c on the second side wall 42 as described above.

[0115] Reference Figure 5 As shown, the base size of the smallest base structure 10c on the bottom wall 43 is L1, the base size of the largest base structure 10c on the second sub-wall 412 is L3, and the base size of the largest base structure 10c on the second side wall 42 is L5. It should be noted that the bottom wall 43 is closer to the center of the semiconductor substrate 10 and has a greater need for reflection. By making L1 > L3 and L1 > L5, the reflectivity of the bottom wall 43 can be strengthened, thereby matching the light emission requirement with the reflectivity, effectively reducing back surface light escape, and improving the battery short-circuit current.

[0116] In one embodiment, such as Figure 2 As shown, the distance S between the orthographic projection of the second sidewall 42 on the semiconductor substrate 10 and the orthographic projection of the N-type doped layer 30 on the semiconductor substrate 10 is between 1 μm and 30 μm. For example, the distance S can be 1 μm, 3 μm, 6 μm, 9 μm, 15 μm, 20 μm, 26 μm, 28 μm, 30 μm, or between any two of the above values.

[0117] The above settings allow for a moderate degree of "retreat" of the N-type doped layer 30, achieving a balance between improving passivation performance and reducing contact resistance.

[0118] In one embodiment, such as Figure 1 As shown, the N-type doped layer 30 includes a main body 31 and a slope portion 32, with the slope portion 32 connected to the side of the main body 31 near the isolation trench 40. The thickness of the slope portion 32 gradually increases from the isolation trench 40 towards the main body 31. It can be understood that the slope surface of the slope portion 32 can be a plane, an arc surface, or a rough surface. The present invention does not particularly limit the inclination angle and structural type of the slope surface of the slope portion 32.

[0119] Optionally, the thickness of the slope portion 32 is between 0.5 nm and 2 nm, and the thickness of the main body portion 31 is not less than 2 nm.

[0120] In one embodiment, the distance between the first surface 10a and the second surface 10b of the first conductive region 10a1 is greater than the distance between the first surface 10a and the second surface 10b of the second conductive region 10a2. In other words, the depth of the first surface 10a of the second conductive region 10a2 is greater than the depth of the first surface 10a of the first conductive region 10a1. That is, the height of the first conductive region 10a1 is relatively high. Since the first conductive region 10a1 contains a PN junction, the above arrangement helps to make the effective area of ​​the PN junction larger, thereby improving battery efficiency.

[0121] In addition, it should be emphasized that the above settings are conducive to the formation of Figure 1 or Figure 4 The isolation trench 40 with this special morphology, combined with the characteristic that the N-type doped layer 30 "recedes" and the P-type doped layer 20 "does not recede", enables the overall scheme to achieve the goal of improving passivation performance and reducing contact resistance.

[0122] In another embodiment, the distance between the first surface 10a and the second surface 10b of the first conductive region 10a1 is less than the distance between the first surface 10a and the second surface 10b of the second conductive region 10a2. Alternatively, the distance between the first surface 10a and the second surface 10b of the first conductive region 10a1 is equal to the distance between the first surface 10a and the second surface 10b of the second conductive region 10a2.

[0123] In one embodiment, such as Figure 1 As shown, the angle θ between the second sidewall 42 and the plane containing the semiconductor substrate 10 is between 15° and 75°. For example, θ can be 15°, 30°, 45°, 55°, 60°, 75°, or any two of the above values.

[0124] If θ is less than 15°, a near-right angle is easily formed at the connection between the second sidewall 42 and the sidewall of the second tunneling layer 60, which is not conducive to the formation of a first passivation layer 71 with a relatively uniform film thickness. If θ is greater than 75°, a near-right angle is easily formed at the connection between the second sidewall 42 and the bottom wall 43, which is also not conducive to the formation of a first passivation layer 71 with a relatively uniform film thickness. By keeping the angle θ within the above range, it is easier for subsequent processes to deposit a first passivation layer 71 with a relatively uniform film thickness in the isolation tank 40, thereby improving the passivation performance.

[0125] In one embodiment, a first inner expansion layer (not shown) is further provided within the semiconductor substrate 10, the depth of which is between 1 nm and 50 nm. The first inner expansion layer is located below the first tunneling layer 50.

[0126] In one embodiment, a second inner expansion layer (not shown) is further provided within the semiconductor substrate 10, the depth of which is between 1 nm and 50 nm. The second inner expansion layer is located below the second tunneling layer 60.

[0127] This application conducted efficiency tests on the battery in related technology 1 and the battery in the embodiments of this application. The test data is shown in the table below. It can be seen from the data in the table below that the battery provided in the embodiments of this application has better passivation, higher open-circuit voltage, higher fill factor, and higher battery efficiency.

[0128]

[0129] This application also applied a reverse bias voltage of 18V to the battery in related technology 1 and the battery in the embodiment of this application, and conducted leakage current tests. The test data are shown in the table below. It can be seen from the data in the table below that the battery in related technology 1 is more prone to leakage current, which leads to a decrease in open circuit voltage and fill factor. The leakage current prevention effect of the embodiment of this application is better and the battery efficiency is more stable.

[0130]

[0131] Secondly, refer to Figure 6 As shown in the figure, this application provides a method for fabricating a solar cell 1, which specifically includes the following steps:

[0132] S100: A semiconductor substrate 10 is provided. The semiconductor substrate 10 includes a first surface 10a and a second surface 10b disposed opposite to each other along the thickness direction of the semiconductor substrate 10; the first surface 10a includes a first conductive region 10a1, a second conductive region 10a2, and an isolation region 10a3, the isolation region 10a3 being located between the first conductive region 10a1 and the second conductive region 10a2. In this step, the semiconductor substrate 10 can be polished. In one example, the semiconductor substrate 10 is immersed in a polishing solution. The processing temperature is between 65℃ and 80℃, the polishing solution includes 1%-10% KOH or NaOH by mass fraction, and 1%-10% surfactant by mass fraction, the surfactant may include polyethylene glycol, ethylenediaminetetraacetic acid, sodium benzoate, complexing agent, defoamer, etc., and the process time is 2 min-15 min. After polishing, the tower base structure 10c has a tower base size of 12μm-45μm.

[0133] S200: A P-type doped layer 20 is formed in the first conductive region 10a1 of the first surface 10a.

[0134] S300: An N-type doped layer 30 is formed in the second conductive region 10a2 of the first surface 10a, and an isolation trench 40 is formed in the first surface 10a of the isolation region 10a3. Along the arrangement direction of the first conductive region 10a1 and the second conductive region 10a2, the isolation trench 40 includes a first sidewall 41 and a second sidewall 42 disposed opposite to each other. The first sidewall 41 is disposed adjacent to the P-type doped layer 20, and the second sidewall 42 is disposed adjacent to the N-type doped layer 30. The orthogonal projection of the first sidewall 41 on the semiconductor substrate 10 is tangent to the orthogonal projection of the P-type doped layer 20 on the semiconductor substrate 10, and the orthogonal projection of the second sidewall 42 on the semiconductor substrate 10 is spaced apart from the orthogonal projection of the N-type doped layer 30 on the semiconductor substrate 10.

[0135] In this embodiment, by providing an isolation trench 40 between the first conductive region 10a1 and the second conductive region 10a2, leakage current can be prevented from forming due to contact between the P-type doped layer 20 and the N-type doped layer 30. By making the orthographic projection of the first sidewall 41 on the semiconductor substrate 10 tangent to the orthographic projection of the P-type doped layer 20 on the semiconductor substrate 10, the coverage area of ​​the P-type doped layer 20 in the first conductive region 10a1 can be larger, which is beneficial for achieving a higher doping concentration, lower lateral resistance, and lower contact resistance of the P-type doped layer 20, thereby improving the fill factor and thus improving the battery efficiency. By making the orthographic projection of the second sidewall 42 on the semiconductor substrate 10 spaced apart from the orthographic projection of the N-type doped layer 30 on the semiconductor substrate 10, it is equivalent to making the N-type doped layer 30 "retreat" on the second conductive region 10a2, which is beneficial for depositing a passivation film layer in the retreated region, reducing photoparasitic absorption, and simultaneously improving the short-circuit current and open-circuit voltage.

[0136] In one embodiment, reference Figure 7 , Figure 8 and Figure 9 As shown, S200: A P-type doped layer 20 is formed in the first conductive region 10a1 of the first surface 10a, including the following steps:

[0137] S220: A P-type doped material layer 3 and a first protective layer 4 are sequentially stacked on the first surface 10a. In one example, a first intrinsic amorphous silicon layer of 100nm-400nm is deposited using an LPCVD process, followed by boron diffusion treatment of the first intrinsic amorphous silicon layer at a doping temperature between 850℃ and 1000℃. Then, the first protective layer 4 (e.g., a borosilicate glass layer) is fabricated, with a thickness between 30nm and 100nm. During this process, a first inner extension layer is formed.

[0138] S230: A first patterned mask layer 5 is printed on the first protective layer 4. The first patterned mask layer 5 covers the first protective layer 4 of the first conductive region 10a1, and exposes the first protective layer 4 of the second conductive region 10a2 and the isolation region 10a3. Specifically, a corrosion-resistant ink is inkjet printed on the first protective layer 4. The corrosion-resistant ink has HF corrosion resistance and is readily soluble in alkalis (such as NaOH, KOH, ammonia, etc.). The components of the corrosion-resistant ink may include fluorocarbon resin, surfactant, rheology modifier, organic solvents such as ethylene glycol, diethylene glycol, etc.

[0139] S240: The first protective layer 4 of the second conductive region 10a2 and the isolation region 10a3 is etched. Specifically, an HF solution with a mass fraction of 1%-10% can be used for etching.

[0140] S250: Remove the first patterned mask layer 5. Specifically, the corrosion-resistant ink can be dissolved and removed using a solution consisting of 1%-10% KOH or NaOH and 1%-5% diethylene glycol butyl ether.

[0141] S260: The P-type doped material layer 3 of the second conductive region 10a2 and the isolation region 10a3 is etched to obtain the P-type doped layer 20. Specifically, the etching process can be performed using a solution composed of 1%-10% KOH or NaOH and 1%-10% surfactant. The surfactant may include polyethylene glycol, ethylenediaminetetraacetic acid, sodium benzoate, complexing agent, defoamer, etc., and the process time is 2 min-15 min.

[0142] S280: Etching is performed on the semiconductor substrate 10 of the second conductive region 10a2 and the isolation region 10a3. Specifically, an etching solution consisting of 1%-10% KOH or NaOH and 1%-10% surfactant can be used for etching.

[0143] In one embodiment, reference Figure 10 As shown, S220: Before forming a P-type doped material layer 3 and a first protective layer 4 stacked sequentially on the first surface 10a, the following steps are also included:

[0144] S210: A first tunneling material layer 2 is formed on the first surface 10a. Specifically, the first tunneling material layer 2 can be deposited using an LPCVD process. The thickness of the first tunneling material layer 2 is between 1 nm and 3 nm.

[0145] S260: The P-type doped material layer 3 of the second conductive region 10a2 and the isolation region 10a3 is etched to obtain the P-type doped layer 20. Then, S280: The semiconductor substrate 10 of the second conductive region 10a2 and the isolation region 10a3 is etched. Before that, the following steps are included:

[0146] S270: The first tunneling material layer 2 of the second conductive region 10a2 and the isolation region 10a3 is etched to obtain the first tunneling layer 50. Specifically, the etching can be performed using a solution composed of 1%-10% KOH or NaOH and 1%-10% surfactant by mass fraction.

[0147] In one embodiment, S300: An N-type doped layer 30 is formed on the second conductive region 10a2 of the first surface 10a, and an isolation trench 40 is formed on the first surface 10a of the isolation region 10a3, specifically including the following steps:

[0148] S320: An N-type doped material layer 7 and a second protective layer 8 are sequentially stacked on the first surface 10a. Specifically, a second intrinsic amorphous silicon layer of 50nm-300nm can be deposited using an LPCVD process, followed by phosphorus diffusion on the second intrinsic amorphous silicon layer at a doping temperature between 800℃ and 980℃. Then, a second protective layer 8 (e.g., a phosphosilicate glass layer) is fabricated, with a thickness between 30nm and 100nm. During this process, a second inner extension layer is formed.

[0149] S330: A second patterned mask layer 9 is printed on the second protective layer 8. The second patterned mask layer 9 covers the second protective layer 8 of the second conductive region 10a2, exposing the second protective layer 8 of the first conductive region 10a1 and the isolation region 10a3. Specifically, a corrosion-resistant ink is printed on the second protective layer 8. The corrosion-resistant ink has HF corrosion resistance and is highly soluble in alkalis (e.g., NaOH, KOH, ammonia, etc.). The components of the corrosion-resistant ink may include fluorocarbon resin, surfactant, rheology modifier, and organic solvents such as ethylene glycol, diethylene glycol, etc. Each second conductive region 10a2 corresponds to one printing area, and the width between two adjacent printing areas is 20-150 μm.

[0150] S340: The second protective layer 8 of the first conductive region 10a1 and the isolation region 10a3 is etched. Specifically, an HF solution with a mass fraction of 1%-10% can be used for etching.

[0151] S350: Remove the second patterned mask layer 9. Specifically, the corrosion-resistant ink can be dissolved and removed using a solution consisting of 1%-10% KOH or NaOH and 1%-5% diethylene glycol butyl ether.

[0152] S360: The N-type doped material layer 7 of the first conductive region 10a1 and the isolation region 10a3 is etched to obtain the N-type doped layer 30. Specifically, an etching solution consisting of 1%-10% KOH or NaOH and 1%-10% surfactant can be used for etching. The surfactant may include polyethylene glycol, ethylenediaminetetraacetic acid, sodium benzoate, complexing agents, nucleating agents, etc., and the process time is 3 min-10 min. During this process, the N-type doped layer 30 on the second conductive region 10a2 will recede.

[0153] S380: Etching is performed on the semiconductor substrate 10 of the first conductive region 10a1 and the isolation region 10a3. Specifically, an etching solution consisting of 1%-10% KOH or NaOH and 1%-10% surfactant can be used for etching.

[0154] In one embodiment, S320: Before forming an N-type doped material layer 7 and a second protective layer 8 sequentially stacked on the first surface 10a, the following steps are also included:

[0155] S310: A second tunneling material layer 6 is formed on the first surface 10a. Specifically, the second tunneling material layer 6 can be deposited using an LPCVD process. The thickness of the second tunneling material layer 6 is between 1 nm and 3 nm.

[0156] S360: The N-type doped material layer 7 of the first conductive region 10a1 and the isolation region 10a3 is etched to obtain the N-type doped layer 30. Then, S380: The semiconductor substrate 10 of the first conductive region 10a1 and the isolation region 10a3 is etched. Before that, the following steps are also included:

[0157] S370: The second tunneling material layer 6 of the first conductive region 10a1 and the isolation region 10a3 is etched to obtain the second tunneling layer 60. Specifically, the etching can be performed using a solution composed of 1%-10% KOH or NaOH and 1%-10% surfactant by mass fraction.

[0158] It should be noted that the solar cell fabrication method provided in this application uses an inkjet printing route, abandoning the laser route. For example, in related technology two, when laser film opening is used, the instantaneous high temperature of the laser causes the doping concentration of P-type doped polysilicon in the opened area to rise rapidly. Furthermore, because P-type doped polysilicon is difficult to etch, it is difficult to etch the P-type doped polysilicon in the opened area. However, this application uses an inkjet printing route, eliminating the need for laser film opening. This not only avoids damage to the semiconductor substrate 10 caused by the laser but also prevents the doping concentration of P-type doped polysilicon in the opened area from increasing. Thus, under the same etching difficulty, this application embodiment can achieve a higher doping concentration of the P-type doped layer 20, resulting in lower lateral resistance and contact resistance, further improving cell efficiency.

[0159] Thirdly, embodiments of this application provide a photovoltaic module, including the solar cell in any embodiment of the first aspect, or including a solar cell prepared using the preparation method of the solar cell in any embodiment of the second aspect.

[0160] For example, the photovoltaic module includes multiple solar cells that can be wired together in series via solder strips, thereby collecting the electrical energy generated by each individual solar cell for subsequent power transmission. Of course, the solar cells can be arranged at intervals or stacked together in a shingled configuration.

[0161] Furthermore, the photovoltaic module also includes an encapsulation layer and a cover plate (not shown). The encapsulation layer covers the surface of the cell string, and the cover plate covers the surface of the encapsulation layer away from the cell string. Solar cells are electrically connected in a single piece or in multiple segments to form multiple cell strings, which are electrically connected in series and / or parallel. Specifically, in some embodiments, multiple cell strings can be electrically connected through conductive links. The encapsulation layer covers the surface of the solar cells. Exemplarily, the encapsulation layer can be an organic encapsulation film such as an ethylene-vinyl acetate copolymer film, a polyethylene octene co-elastomer film, or a polyethylene terephthalate film. The cover plate can be a glass cover plate, a plastic cover plate, or other cover plate with light-transmitting function.

[0162] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0163] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A solar cell, characterized by, The solar cell comprises: a semiconductor substrate comprising a first surface and a second surface oppositely arranged along a thickness direction of the semiconductor substrate; the first surface comprises a first conductive region, a second conductive region, and an isolation region between the first conductive region and the second conductive region; a P-type doped layer arranged on the first surface and located in the first conductive region; an N-type doped layer arranged on the first surface and located in the second conductive region; an isolation groove recessed in the first surface of the isolation region; along an arrangement direction of the first conductive region and the second conductive region, the isolation groove comprises a first sidewall and a second sidewall oppositely arranged, the first sidewall is arranged adjacent to the P-type doped layer, and the second sidewall is arranged adjacent to the N-type doped layer; wherein the orthogonal projection of the first sidewall on the semiconductor substrate is tangent to the orthogonal projection of the P-type doped layer on the semiconductor substrate, and the orthogonal projection of the second sidewall on the semiconductor substrate is spaced apart from the orthogonal projection of the N-type doped layer on the semiconductor substrate.

2. The solar cell according to claim 1, characterized in that, The P-type doped layer has a doping concentration of 3 x 1018 19 cm -3 -1 x 1018 21 cm -3 ; and / or the N-type doped layer has a doping concentration between 9 x 1018cm-3and 1 x 1020cm-3. 19 cm -3 -1 x 1018cm-3 21 cm -3 ; And / or, the doping type of the semiconductor substrate is N-type.

3. The solar cell according to claim 1, characterized in that, The solar cell further comprises a first tunneling layer between the P-type doped layer and the first surface of the first conductive region; the orthogonal projection of the first tunneling layer on the semiconductor substrate is tangent to the orthogonal projection of the first sidewall on the semiconductor substrate.

4. The solar cell according to claim 1, characterized in that, The solar cell further comprises a second tunneling layer between the N-type doped layer and the first surface of the second conductive region; the orthogonal projection of the second tunneling layer on the semiconductor substrate is tangent to the orthogonal projection of the second sidewall on the semiconductor substrate.

5. The solar cell according to claim 1, characterized in that, The isolation groove comprises a bottom wall connecting the first sidewall and the second sidewall; the bottom wall is a polished surface, or the bottom wall is a textured surface.

6. The solar cell according to claim 5, characterized in that, The first sidewall comprises a first sub-wall and a second sub-wall, the first sub-wall is connected to the first surface of the first conductive region, and the second sub-wall connects the first sub-wall and the bottom wall; the angle between the second sub-wall and the plane of the semiconductor substrate is greater than the angle between the first sub-wall and the plane of the semiconductor substrate.

7. The solar cell according to claim 6, characterized in that The angle between the second sub-wall and the plane of the semiconductor substrate is less than 90°.

8. The solar cell according to claim 6, characterized in that, The angle between the first sub-wall and the plane of the semiconductor substrate is between 20° and 80°.

9. The solar cell according to claim 6, characterized in that, The first sub-wall, the second sub-wall, and the second sidewall are all polished surfaces.

10. The solar cell according to claim 9, characterized in that, The tower base size of the smallest tower base structure on the second sub-wall is greater than the tower base size of the largest tower base structure on the first sub-wall.

11. The solar cell according to claim 9, characterized in that, The average tower base size of all tower base structures on the first sub-wall is less than the average tower base size of all tower base structures on the second sidewall per unit area.

12. The solar cell according to claim 6, characterized in that, The tower base size of the smallest tower base structure on the bottom wall is greater than the tower base size of the largest tower base structure on the second sub-wall, and the tower base size of the smallest tower base structure on the bottom wall is greater than the tower base size of the largest tower base structure on the second sidewall.

13. The solar cell of claim 1, wherein The distance between the orthogonal projection of the second sidewall on the semiconductor substrate and the orthogonal projection of the N-type doped layer on the semiconductor substrate is between 1 μm and 30 μm. And / or, the N-type doped layer includes a main body part and a slope part, the slope part is connected to the main body part near one side of the isolation groove; the thickness of the slope part gradually increases in the direction from the isolation groove to the main body part.

14. The solar cell of claim 1, wherein The distance between the first face and the second face of the first conductive region is greater than the distance between the first face and the second face of the second conductive region.

15. The solar cell of claim 1, wherein The included angle between the second side wall and the plane where the semiconductor substrate is located is between 15°-75°.

16. A method of fabricating a solar cell, characterized by, Comprise: Providing a semiconductor substrate; The semiconductor substrate comprises a first face and a second face arranged opposite along the thickness direction of the semiconductor substrate; the first face comprises a first conductive region, a second conductive region and an isolation region, the isolation region is located between the first conductive region and the second conductive region; Forming a P-type doped layer on the first conductive region of the first face; Forming an N-type doped layer on the second conductive region of the first face, and forming an isolation groove on the first face of the isolation region; along the arrangement direction of the first conductive region and the second conductive region, the isolation groove comprises a first side wall and a second side wall arranged opposite, the first side wall is arranged adjacent to the P-type doped layer, and the second side wall is arranged adjacent to the N-type doped layer; wherein the orthogonal projection of the first side wall on the semiconductor substrate is tangent to the orthogonal projection of the P-type doped layer on the semiconductor substrate, and the orthogonal projection of the second side wall on the semiconductor substrate is spaced from the orthogonal projection of the N-type doped layer on the semiconductor substrate.

17. The method of producing a solar cell according to claim 16, wherein The step of forming a P-type doped layer on the first conductive region of the first face comprises: Forming a P-type doped material layer and a first protective layer which are stacked in sequence on the first face; Printing a first patterned mask layer on the first protective layer; the first patterned mask layer covers the first protective layer of the first conductive region, and exposes the first protective layer of the second conductive region and the isolation region; Etching the first protective layer of the second conductive region and the isolation region; Removing the first patterned mask layer; Etching the P-type doped material layer of the second conductive region and the isolation region to obtain the P-type doped layer; Etching the semiconductor substrate of the second conductive region and the isolation region.

18. The method of producing a solar cell according to claim 17, wherein Before the step of forming a P-type doped material layer and a first protective layer which are stacked in sequence on the first face, it comprises: Forming a first tunneling material layer on the first face; After the step of etching the P-type doped material layer of the second conductive region and the isolation region to obtain the P-type doped layer, and before the step of etching the semiconductor substrate of the second conductive region and the isolation region, it comprises: Etching the first tunneling material layer of the second conductive region and the isolation region to obtain a first tunneling layer.

19. The method of producing a solar cell according to claim 16, wherein The step of forming an N-type doped layer on the second conductive region of the first face, and forming an isolation groove on the first face of the isolation region comprises: Forming an N-type doped material layer and a second protective layer which are stacked in sequence on the first face; printing a second patterned mask layer on the second protective layer; the second patterned mask layer covers the second protective layer of the second conductive region, exposing the second protective layer of the first conductive region and the isolation region; performing etching treatment on the second protective layer of the first conductive region and the isolation region; removing the second patterned mask layer; performing etching treatment on the N-type doped material layer of the first conductive region and the isolation region, to obtain the N-type doped layer; performing etching treatment on the semiconductor substrate of the first conductive region and the isolation region.

20. The method of producing a solar cell according to claim 19, wherein Before the step of forming an N-type doped material layer and a second protective layer in sequence on the first surface, the method comprises: forming a second tunneling material layer on the first surface; After the step of performing etching treatment on the N-type doped material layer of the first conductive region and the isolation region, to obtain the N-type doped layer, and before the step of performing etching treatment on the semiconductor substrate of the first conductive region and the isolation region, the method comprises: performing etching treatment on the second tunneling material layer of the first conductive region and the isolation region, to obtain a second tunneling layer.

21. A photovoltaic module, characterized by, The solar cell comprises any one of the solar cells according to claims 1-15, or the solar cell prepared by the preparation method of any one of claims 16-20.

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