Monocrystalline silicon stack formation and bonding to complementary metal oxide semiconductor wafer

Abstract

Systems, methods, and apparatus are provided for monocrystalline silicon stack formation and bonding to complementary metal oxide semiconductor (CMOS) wafers for forming vertical three-dimensional (3D) memories. An example method for forming an array of vertically stacked layers for formation of memory cells includes providing a silicon substrate; forming a monocrystalline silicon germanium layer on the surface of the substrate; epitaxially growing the silicon germanium to form a thicker silicon germanium layer; forming a monocrystalline silicon layer on the surface of the silicon germanium; epitaxially growing the silicon germanium to form a thicker silicon layer; and in the repeating stack-up, forming silicon germanium layers and silicon layers to form a vertical stack of alternating silicon layers and silicon germanium layers.

Description

[0001] Related application information of divisional application

[0002] This application is a divisional application of the invention patent application with the application date of November 01, 2021, the application number of 202111284481.X, and the invention name of “Single Crystal Silicon Stack Formation and Bonding to Complementary Metal Oxide Semiconductor Wafer”. TECHNICAL FIELD

[0003] The present disclosure relates generally to memory devices, and more specifically to single crystal silicon stack formation and bonding to complementary metal oxide semiconductor (CMOS) wafers for forming vertical three-dimensional (3D) memory. BACKGROUND

[0004] Memory is typically implemented in electronic systems such as computers, cellular phones, handheld devices, and the like. There are many different types of memory, including volatile and non-volatile memory. Volatile memory can require power to maintain its data, and can include random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), and synchronous dynamic random access memory (SDRAM). Non-volatile memory can provide persistent data by retaining stored data when unpowered, and can include NAND flash memory, NOR flash memory, nitride read-only memory (NROM), phase change memory (e.g., phase change random access memory), resistive memory (e.g., resistive random access memory), cross point memory, ferroelectric random access memory (FeRAM), and the like.

[0005] As design rules shrink, less semiconductor space is available for fabricating memory including DRAM arrays. A respective memory cell for a DRAM can include an access device (e.g., a transistor) having first and second source / drain regions separated by a channel region. A gate can be opposite the channel region and separated from the channel region by a gate dielectric. An access line, such as a word line, is electrically connected to the gate of a DRAM cell. The DRAM cell can include a storage node, such as a capacitor cell, coupled to a digit line by the access device. The access device can be activated (e.g., to select the cell) by the access line coupled to the access transistor. The capacitor can store a charge corresponding to a data value (e.g., a logical “1” or “0”) of the respective cell. SUMMARY

[0006] This disclosure provides a method for forming an array of vertically stacked layers for forming memory cells, the method comprising: providing a silicon substrate; forming a single-crystal silicon-germanium layer on a surface of the substrate; epitaxially growing silicon-germanium to form a thicker silicon-germanium layer; forming a single-crystal silicon layer on the surface of the silicon-germanium; epitaxially growing silicon formed on the surface of the silicon-germanium to form a thicker single-crystal silicon layer; and forming silicon-germanium layers and silicon layers in repeated stacking to form an alternating vertical stack of silicon and silicon-germanium layers.

[0007] Another aspect of this disclosure provides an apparatus formed by stacking materials onto a CMOS wafer, wherein the apparatus includes: a CMOS wafer; a first single-crystal silicon-germanium layer attached to a surface of the CMOS wafer; a first single-crystal silicon layer positioned on the surface of the silicon-germanium layer; and, in repeated stacking, silicon-germanium layers and silicon layers forming an alternating vertical stack of silicon and silicon-germanium layers.

[0008] Another aspect of this disclosure provides a method for forming a memory cell array with vertically stacked layers, the method comprising: providing a silicon substrate; forming a single-crystal silicon-germanium layer on a surface of the substrate; forming a single-crystal silicon layer on the surface of the silicon-germanium layer; forming silicon-germanium layers and silicon layers in repeated stacking to form an alternating vertical stack of silicon and silicon-germanium layers; and bonding the vertically stacked surfaces to a CMOS wafer. Attached Figure Description

[0009] Figure 1A This is a schematic illustration of a vertical three-dimensional (3D) memory according to several embodiments of the present disclosure.

[0010] Figure 1B A perspective view illustrating a portion of a digital line and a body contact area for a semiconductor device according to several embodiments of the present disclosure.

[0011] Figure 2A This is a schematic illustration of a vertical three-dimensional (3D) memory according to several embodiments of the present disclosure.

[0012] Figure 2B A perspective view illustrating a portion of a three-node access device in a vertical three-dimensional (3D) memory array according to several embodiments of the present disclosure.

[0013] Figure 3 A perspective view illustrating a portion of a three-node access device in a vertical three-dimensional (3D) memory cell according to several embodiments of the present disclosure.

[0014] Figure 4 This document describes example processes for generating a single-crystal silicon stack for a vertical three-dimensional (3D) memory according to several embodiments of the present disclosure.

[0015] Figure 5This document describes example processes for stacking and bonding single-crystal silicon to a CMOS wafer according to several embodiments of the present disclosure.

[0016] Figure 6 This describes another example of a process for stacking and bonding single-crystal silicon to a CMOS wafer according to several embodiments of the present disclosure.

[0017] Figure 7 This invention describes an example of a patterned vertical memory array formed from a stack of single-crystal silicon bonded to a CMOS wafer, according to several embodiments of the present disclosure.

[0018] Figure 8 This is a block diagram of a device in the form of a computing system including a memory device, according to several embodiments of the present disclosure. Detailed Implementation

[0019] Embodiments of this disclosure describe systems, apparatus, and methods for forming a stack of single-crystal silicon and bonding it to a CMOS wafer.

[0020] In vertically stacked memory array structures (e.g., transistor structures), polysilicon (also known as polycrystalline silicon) can leak, allowing current to leak through the polycrystalline structure, making the transistors less efficient. Monocrystalline silicon is not prone to leakage; however, it cannot be grown on amorphous dielectric materials (e.g., oxides or nitrides), which are common materials for forming transistors. Furthermore, the temperatures required to grow monocrystalline silicon are too high for CMOS components, on which vertically stacked memory array structures can be formed, thus prohibiting the use of monocrystalline silicon in such implementations.

[0021] However, as disclosed in the embodiments of this disclosure, it is possible to use a silicon wafer that can serve as a substrate for transistors during the high-temperature processes required for the formation of single-crystal silicon. In such embodiments, a silicon-germanium layer can be grown on a silicon substrate. Single-crystal silicon can then be grown on the silicon-germanium layer.

[0022] This can be achieved, for example, by providing a thin monocrystalline silicon-germanium layer as a seed layer, and then heating the layer to grow the monocrystalline silicon-germanium layer to a thicker thickness through epitaxial growth. Once the desired layer thickness is formed, a silicon layer can be formed on the surface of the silicon-germanium layer. Similarly, this can be achieved, for example, by providing a thin monocrystalline silicon layer as a seed layer, and then heating the layer to grow the thin monocrystalline silicon layer to a thicker monocrystalline silicon layer through epitaxial growth.

[0023] Depending on the silicon-germanium concentration, if silicon is amount x and germanium is amount y, and if y is less than x, then silicon / silicon-germanium has a smaller lattice mismatch relative to the lattice of monocrystalline silicon. This allows silicon to grow on top of silicon-germanium with a monocrystalline structure. If a thin layer of monocrystalline silicon is applied to the surface of silicon-germanium, then the entire silicon layer acts as a seed for the growth of the monocrystalline silicon layer. This layering can be performed alternately (e.g., SiGe / Si / SiGe / Si, etc.) to produce a superlattice structure in a vertically stacked manner, such as... Figure 4 As shown in the image.

[0024] For example, a silicon-germanium seed layer can be formed with a thickness (height) of 100 angstroms and can be grown to, for example, 1000 angstroms. A thin silicon seed layer can be formed on the surface of a silicon-germanium layer, for example, 50 angstroms, and can be grown to a thickness of, for example, 300 angstroms. Unless expressly stated in a particular claim, these thicknesses are provided as examples only and should not be considered limiting.

[0025] This unpatterned (unpatterned within layers) vertical stack can then be attached to a CMOS wafer. Because no pattern exists within any of the vertical stack layers, the alignment between the CMOS wafer and the vertical stack may be less precise; for example, the interconnect between the vertical stack and the CMOS wafer is not yet defined within the vertical stack. The transistor device of this disclosure has better performance in terms of I-on, I-off, driveability, and / or leakage current because there are no grain boundaries, and therefore current does not leak through the grain boundaries, which are common sites of leakage in polysilicon. In some embodiments, the device may have, for example, three orders of magnitude lower I-off (leakage).

[0026] Advantages of the structures and processes described herein may include lower cutoff current (Ioff) for the access device (compared to silicon-based (Si-based) access devices (e.g., transistors)) and / or reduced gate / drain induced leakage (GIDL) for the access device.

[0027] The figures in this document follow a numbering convention, where the first one or more digits correspond to the figure number, and the remaining digits identify the elements or components in the figure. Similar elements or components between different figures can be identified by using similar digits. For example, reference numeral 104 in... Figure 2A The term "04" can refer to component "04", and similar components can be found in [the following text is incomplete and likely refers to another component]. Figure 2B The Chinese character is represented as 204. Multiple similar elements within a diagram can be represented using a reference numeral followed by a hyphen and another number or letter. For example, 302-1 could refer to... Figure 3Component 302-1 and 302-2 can refer to component 302-2, which can be similar to component 302-1. Such similar components can be generally referred to without hyphens and additional numbers or letters. For example, components 302-1 and 302-2 or other similar components can be generally represented as 302.

[0028] Figure 1A This is a block diagram of a device according to several embodiments of the present disclosure. Figure 1A The illustration shows a circuit diagram of a cell array of a three-dimensional (3D) semiconductor memory device according to an embodiment of the present disclosure. Figure 1A The cell array can have multiple sub-cell arrays 101-1, 101-2, ... 101-N. Sub-cell arrays 101-1, 101-2, ... 101-N can be arranged along a second direction (D2) 105. Each sub-cell array (e.g., sub-cell array 101-2) can contain multiple access lines 107-1, 107-2, ... 107-Q (which may also be called word lines). Additionally, each sub-cell array (e.g., sub-cell array 101-2) can contain multiple digital lines 103-1, 103-2, ... 103-Q (which may also be called bit lines, data lines, or sensing lines). Figure 1A The document describes access lines 107-1, 107-2, ..., 107-Q extending in a first direction (D1) 109, and digital lines 103-1, 103-2, ..., 103-Q extending in a third direction (D3) 111. According to an embodiment, the first direction (D1) 109 and the second direction (D2) 105 can be considered to be in a horizontal (“XY”) plane. The third direction (D3) 111 can be considered to be in a vertical (“Z”) plane. Therefore, according to the embodiment described herein, digital lines 103-1, 103-2, ..., 103-Q extend in a vertical direction (e.g., the third direction (D3) 111).

[0029] Memory cells (e.g., 110) may include access means (e.g., access transistors) and memory nodes located at the intersections of each access line 107-1, 107-2, ..., 107-Q and each digital line 103-1, 103-2, ..., 103-Q. Memory cells can be written to or read from memory cells using access lines 107-1, 107-2, ..., 107-Q and digital lines 103-1, 103-2, ..., 103-Q. Access lines 107-1, 107-2, ..., 107-Q may electrically interconnect memory cells along the horizontal rows of each sub-cell array 101-1, 101-2, ..., 101-N, and digital lines 103-1, 103-2, ..., 103-Q may electrically interconnect memory cells along the vertical columns of each sub-cell array 101-1, 101-2, ..., 101-N. A memory cell (e.g., 110) may be located between an access line (e.g., 107-2) and a digital line (e.g., 103-2). Each memory cell can be uniquely addressed by a combination of access lines 107-1, 107-2, ..., 107-Q and digital lines 103-1, 103-2, ..., 103-Q.

[0030] Access lines 107-1, 107-2, ... 107-P may be or include conductive patterns (e.g., metal lines) disposed on and spaced apart from the substrate. Access lines 107-1, 107-2, ... 107-Q may extend in a first direction (D1) 109. Access lines 107-1, 107-2, ... 107-Q in a sub-cell array (e.g., 101-2) may be spaced apart from each other in a vertical direction (e.g., in a third direction (D3) 111).

[0031] Digital lines 103-1, 103-2, ... 103-Q may be or be contained in conductive patterns (e.g., metal lines) extending in a vertical direction relative to the substrate (e.g., on a third direction (D3) 111). Digital lines in a sub-cell array (e.g., 101-2) may be spaced apart from each other in a first direction (D1) 109.

[0032] The gate of a memory cell (e.g., memory cell 110) may be connected to an access line (e.g., 107-2), and the first conductive node (e.g., a first source / drain region) of the access means (e.g., a transistor) of memory cell 110 may be connected to a digital line (e.g., 103-2). Each of the memory cells (e.g., memory cell 110) may be connected to a storage node, such as a capacitor. The second conductive node (e.g., a second source / drain region) of the access means (e.g., a transistor) of memory cell 110 may be connected to a storage node, such as a capacitor. Although the references to first and second source / drain regions are used herein to denote two separate and distinct source / drain regions, it is not intended that the source / drain regions referred to as "first" and / or "second" source / drain regions have a particular meaning. It is only desirable that one of the source / drain regions is connected to a digital line, such as 103-2, and the other may be connected to a storage node.

[0033] Figure 1B This illustration depicts a three-dimensional (3D) semiconductor memory device according to some embodiments of the present disclosure, such as... Figure 1A The sub-cell array 101-2 shown is a perspective view of the vertically oriented stacking of memory cells in the array.

[0034] like Figure 1B As shown, substrate 100 may have a bonding formed thereon. Figure 1A One of the described array of sub-cells (e.g., 101-2). For example, substrate 100 may be or comprise a silicon substrate, a germanium substrate, or a silicon-germanium substrate, etc. However, the embodiments are not limited to these examples.

[0035] like Figure 1B As shown in the example embodiments, memory cells extending in a vertical direction, such as a third direction (D3) 111, may be fabricated on the substrate 100 (e.g. Figure 1A The memory cells 110 in the memory are vertically stacked. According to some embodiments, the vertical stacking of the memory cells can be manufactured such that each memory cell (e.g., Figure 1A The memory cells 110 are formed in multiple vertical layers, such as a first layer (L1), a second layer (L2), and a third layer (L3). They can be arranged vertically (e.g., along the vertical direction). Figure 1AThe third-party (D3) 111) arrangement (e.g., “stacked”) of repeating vertical layers L1, L2, and L3 is shown and is separated from the substrate 100 by an insulating material 120. Each of the repeating vertical layers L1, L2, and L3 may include multiple discrete components (e.g., regions) of horizontally oriented access devices 130 (e.g., transistors) and memory nodes (e.g., capacitors), including access lines 107-1, 107-2, ... 107-Q connectors and digital lines 103-1, 103-2, ... 103-Q connectors. The multiple discrete components of the horizontally oriented access devices 130 (e.g., transistors) may be formed in multiple stacks of vertical repeating layers within each layer, as described below. Figure 4 A more detailed description, and may be available in similar formats. Figure 1A The second direction (D2) 105 shown in the middle extends horizontally on the second direction (D2) 105.

[0036] A plurality of discrete components of a lateral access device 130 (e.g., a transistor) may include a first source / drain region 121 and a second source / drain region 123 separated by a channel region 125 extending laterally in a second direction (D2) 105 and formed in the body of the access device. In some embodiments, the channel region 125 may comprise silicon, germanium, silicon-germanium, and / or indium gallium zinc oxide (IGZO). In some embodiments, the first source / drain region 121 and the second source / drain region 123 may comprise an n-type dopant region formed in the p-type doped body of the access device to form an n-type conductive transistor. In some embodiments, the first source / drain region 121 and the second source / drain region 123 may comprise a p-type dopant formed in the n-type doped body of the access device to form a p-type conductive transistor. By way of example, but not limitation, the n-type dopant may comprise phosphorus (P) atoms, and the p-type dopant may comprise boron (B) atoms formed in a relatively doped body region of a polycrystalline silicon semiconductor material. However, the embodiments are not limited to these examples.

[0037] Storage node 127 (e.g., a capacitor) can be connected to a corresponding terminal of the access device. For example... Figure 1B As shown, storage node 127 (e.g., a capacitor) can be connected to the second source / drain region 123 of the access device. Storage nodes can be or contain memory elements capable of storing data. Each of the storage nodes can be a memory element using one of a capacitor, a magnetic tunnel junction pattern, and / or a variable resistor body containing a phase change material, etc. However, embodiments are not limited to these examples. In some embodiments, with unit cells (e.g. Figure 1A Each memory node associated with an access device in memory cell 110 can be similarly located in a memory node with a memory node ... Figure 1A The second direction (D2) 105 shown in the middle extends upwards from the second direction (D2) 105.

[0038] like Figure 1B As shown in the diagram, multiple horizontally oriented access lines 107-1, 107-2, ... 107-Q are similar to... Figure 1A The first direction (D1) of 109 extends upwards from 109. Multiple horizontally oriented access lines 107-1, 107-2, ..., 107-Q can be similar to... Figure 1A Access lines 107-1, 107-2, ... 107-Q are shown in the diagram. Multiple horizontally oriented access lines 107-1, 107-2, ... 107-Q may be arranged (e.g., "stacked") along a third direction (D3) 111. The multiple horizontally oriented access lines 107-1, 107-2, ... 107-Q may contain a conductive material. For example, the conductive material may contain one or more of the following: doped semiconductors (e.g., doped silicon, doped germanium, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), metals (e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), cobalt (Co), molybdenum (Mo), etc.), and / or metal-semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.). However, the embodiments are not limited to these examples.

[0039] In each of the vertical levels (L1) 113-1, (L2) 113-2, and (L3) 113-P, the horizontally oriented memory cells (e.g.) Figure 1AThe memory cells 110 in the memory may be horizontally spaced apart from each other in the first direction (D1) 109. However, the multiple discrete components of the horizontally oriented access device 130 extending laterally in the second direction (D2) 105 (e.g., the first source / drain region 121 and the second source / drain region 123 separated by the channel region 125), and the multiple horizontally oriented access lines 107-1, 107-2, ... 107-Q extending laterally in the first direction (D1) 109 may be formed in different vertical layers within each level. For example, a plurality of horizontally oriented access lines 107-1, 107-2, ... 107-Q extending in the first direction (D1) 109 may be formed on the top surface of the channel region 125 opposite to and electrically coupled to the channel region 125, separated from the channel region 125 by a gate dielectric, and orthogonal to the horizontally oriented access device 130 (e.g., a transistor) extending laterally in the second direction (D2) 105. In some embodiments, the plurality of horizontally oriented access lines 107-1, 107-2, ... 107-Q extending in the first direction (D1) 109 are formed in a higher vertical layer within a layer (e.g., within layer (L1)), which is further away from the substrate 100 than the layer in which discrete components of the horizontally oriented access device (e.g., the first source / drain region 121 and the second source / drain region 123 separated by the channel region 125) are formed.

[0040] like Figure 1B As shown in the example embodiments, digital lines 103-1, 103-2, ... 103-Q extend in a vertical direction relative to the substrate 100 (e.g., on a third direction (D3) 111). Furthermore, as... Figure 1B As shown, a sub-cell array (e.g., Figure 1AThe digital lines 103-1, 103-2, ..., 103-Q in the sub-cell array 101-2 may be spaced apart from each other in the first direction (D1) 109. The digital lines 103-1, 103-2, ..., 103-Q may be provided to extend vertically relative to the substrate 100 in the third direction (D3) 111 in a form that is vertically aligned with the source / drain region 121 that serves as the first source / drain region 121, or as shown, to be vertically adjacent to the first source / drain region 121 that extends laterally in the second direction (D2) 105 of each of the horizontally oriented access devices 130 (e.g., transistors), but adjacent to each other in the first direction (D1) 109 at the level (e.g., the first level (L1)). Each of the digital lines 103-1, 103-2, ... 103-Q may extend vertically in a third direction (D3) on the sidewall of the adjacent first source / drain region 121 of a plurality of vertically stacked horizontally oriented access devices 130 (e.g., transistors). In some embodiments, the plurality of vertically oriented digital lines 103-1, 103-2, ... 103-Q extending in the third direction (D3) 111 may be directly and / or connected to the side surface of the first source / drain region 121 via additional contacts comprising metal silicide.

[0041] For example, the first vertically extending digital line (e.g., 103-1) may be adjacent to the sidewall of the first source / drain region 121 of the first horizontally oriented access device 130 (e.g., transistor) in the first level (L1) 113-1, the sidewall of the first source / drain region 121 of the first horizontally oriented access device 130 (e.g., transistor) in the second level (L2) 113-2, and the sidewall of the first source / drain region 121 of the first horizontally oriented access device 130 (e.g., transistor) in the third level (L3) 113-P, etc. Similarly, the second vertically extending digital line (e.g., 103-2) may be adjacent to the sidewall of the first source / drain region 121 of the second horizontally oriented access device 130 (e.g., transistor) in the first level (L1) 113-1, and spaced apart from the first horizontally oriented access device 130 (e.g., transistor) in the first direction (D1) 109. Furthermore, the second vertically extending digital line (e.g., 103-2) may be adjacent to the sidewall of the first source / drain region 121 of the second horizontally oriented access device 130 (e.g., transistor) in the second level (L2) 113-2, and the sidewall of the first source / drain region 121 of the second horizontally oriented access device 130 (e.g., transistor) in the third level (L3) 113-P, etc. The embodiments are not limited to a specific number of levels.

[0042] The vertically extending digital lines 103-1, 103-2, ... 103-Q may contain conductive materials, such as doped semiconductor materials, conductive metal nitrides, metals, and / or metal-semiconductor compounds. The digital lines 103-1, 103-2, ... 103-Q may correspond to... Figure 1A The described digital line (DL).

[0043] like Figure 1B As shown in the example embodiment, the conductive body contact region may be formed to extend along the end surface of the horizontally oriented access device 130 (e.g., a transistor) in each of the levels (L1) 113-1, (L2) 113-2, and (L3) 113-P above the substrate 100 in a first direction (D1) 109. The body contact region may be connected to each memory cell (e.g., Figure 1A The body of the horizontally oriented access device 130 (e.g., transistor) in the memory cell 110) (as in the memory cell 110) Figure 3 (As shown in 336), for example, the body contact region. The body contact region may contain a conductive material, such as a doped semiconductor material, a conductive metal nitride, a metal, and / or a metal-semiconductor compound.

[0044] although Figure 1B Not shown, but insulating material may fill other spaces in a vertically stacked array of memory cells. For example, the insulating material may comprise one or more of silicon oxide, silicon nitride, and / or silicon oxynitride. However, the embodiments are not limited to these examples. Figure 2A This is a block diagram of a device according to several embodiments of the present disclosure. Figure 2A The illustration shows a circuit diagram of a cell array of a three-dimensional (3D) semiconductor memory device according to an embodiment of the present disclosure. Figure 2A The cell array can have multiple sub-cell arrays 201-1, 201-2, ..., 201-N. Sub-cell arrays 201-1, 201-2, ..., 201-N can be arranged along a second direction (D2) 205. Each sub-cell array (e.g., sub-cell array 201-2) can contain multiple access lines 203-1, 203-2, ..., 203-Q (which may also be called word lines). Additionally, each sub-cell array (e.g., sub-cell array 201-2) can contain multiple digital lines 207-1, 207-2, ..., 207-Q (which may also be called bit lines, data lines, or sensing lines). Figure 2A The text describes the digital lines 207-1, 207-2, ..., 207-Q extending in the first direction (D1) 209, and the access lines 203-1, 203-2, ..., 203-Q extending in the third direction (D3) 211.

[0045] The first direction (D1) 209 and the second direction (D2) 205 can be considered to be in a horizontal (“XY”) plane. The third direction (D3) 211 can be considered to be in a vertical (“Z”) direction (e.g., transverse to the XY plane). Therefore, according to the embodiments described herein, access lines 203-1, 203-2, ... 203-Q extend in a vertical direction (e.g., the third direction (D3) 211).

[0046] Memory cells (e.g., 210) may include access means (e.g., access transistors) and memory nodes located at the intersections of each access line 203-1, 203-2, ..., 203-Q and each digital line 207-1, 207-2, ..., 207-Q. Memory cells can be written to or read from memory cells using access lines 203-1, 203-2, ..., 203-Q and digital lines 207-1, 207-2, ..., 207-Q. Digital lines 207-1, 207-2, ..., 207-Q may electrically interconnect memory cells along the horizontal columns of each sub-cell array 201-1, 201-2, ..., 201-N, and access lines 203-1, 203-2, ..., 203-Q may electrically interconnect memory cells along the vertical rows of each sub-cell array 201-1, 201-2, ..., 201-N. A memory cell (e.g., 210) may be located between an access line (e.g., 203-2) and a digital line (e.g., 207-2). Each memory cell can be uniquely addressed by a combination of access lines 203-1, 203-2, ..., 203-Q and digital lines 207-1, 207-2, ..., 207-Q.

[0047] Digital lines 207-1, 207-2, ... 207-Q may be or comprise conductive patterns (e.g., metal lines) disposed on and spaced apart from the substrate. Digital lines 207-1, 207-2, ... 207-Q may extend in a first direction (D1) 209. Digital lines 207-1, 207-2, ... 207-Q in a sub-cell array (e.g., 201-2) may be spaced apart from each other in a vertical direction (e.g., in a third direction (D3) 211).

[0048] Access lines 203-1, 203-2, ... 203-Q may be or be contained in a conductive pattern (e.g., a metal line) extending in a vertical direction relative to the substrate (e.g., in a third direction (D3) 211). Access lines in a sub-cell array (e.g., 201-2) may be spaced apart from each other in a first direction (D1) 209.

[0049] The gate of a memory cell (e.g., memory cell 210) may be connected to an access line (e.g., 203-2), and the first conductive node (e.g., a first source / drain region) of the access means (e.g., a transistor) of memory cell 210 may be connected to a digital line (e.g., 207-2). Each of the memory cells (e.g., memory cell 210) may be connected to a storage node (e.g., a capacitor). The second conductive node (e.g., a second source / drain region) of the access means (e.g., a transistor) of memory cell 210 may be connected to a storage node (e.g., a capacitor). The storage node (e.g., a capacitor) may be formed of a ferroelectric and / or dielectric material, such as zirconium oxide (ZrO2), hafnium oxide (HfO2), lanthanum oxide (La2O3), lead zirconate titanate (PZT, Pb[Zr(x)Ti(1-x)]O3), barium titanate (BaTiO3), aluminum oxide (e.g., Al2O3), combinations of these with or without dopants, or other suitable materials.

[0050] Although this paper uses the references of first and second source / drain regions to refer to two separate and distinct source / drain regions, it is not intended that the source / drain regions referred to as "first" and / or "second" have a specific meaning. It is only desirable that one of the source / drain regions is connected to a digital line (e.g., 207-2), and the other is connected to a memory node.

[0051] Figure 2B The illustration shows a three-dimensional (3D) semiconductor memory device according to some embodiments of the present disclosure (e.g., Figure 2A The perspective view shown is a portion of the sub-cell array 201-2 as a vertically oriented stack of memory cells in the array. Figure 3 Explanation and display Figure 2B The unit cell of the 3D semiconductor memory device shown in the image (e.g.) Figure 2A A perspective view of the memory cell 210 shown in the image.

[0052] like Figure 2B As shown, substrate 200 may have a bonding formed thereon. Figure 2A One of the described array of sub-cells (e.g., 201-2). For example, substrate 200 may be or comprise a silicon substrate, a germanium substrate, or a silicon-germanium substrate, etc. However, the embodiments are not limited to these examples.

[0053] like Figure 2B As shown in the example embodiments, memory cells (e.g., extending in a vertical direction (e.g., third direction (D3) 211) can be fabricated on the substrate 200. Figure 2A The memory cells 210 in the memory are vertically stacked. According to some embodiments, the vertical stacking of the memory cells can be manufactured such that each memory cell (e.g., Figure 2AThe memory cells 210 are formed on multiple vertical levels (e.g., a first level (L1), a second level (L2), and a third level (L3)). They can be arranged along the vertical direction (e.g., ...). Figure 2A The diagram shows a third-party (D3) 211) arrangement (e.g., “stacked”) of repeating vertical layers L1, L2, and L3, which are separated from the substrate 200 by an insulating material 220. Each of the repeating vertical layers L1, L2, and L3 may include multiple discrete components (e.g., regions) of laterally oriented access devices 230 (e.g., transistors) and memory nodes (e.g., capacitors), including access lines 203-1, 203-2, ..., 203-Q connectors and digital lines 207-1, 207-2, ..., 207-Q connectors. The multiple discrete components of the laterally oriented access devices 230 (e.g., transistors) may be formed in multiple stacks of vertical repeating layers within each layer, as described below. Figure 4 A more detailed description, and may be available in similar formats. Figure 2A The second direction (D2) 205 shown in the middle extends horizontally on the second direction (D2) 205.

[0054] A plurality of discrete components of a lateral access device 230 (e.g., a transistor) may include a first source / drain region 221 and a second source / drain region 223 separated by a channel region 225 extending laterally in a second direction (D2) 205 and formed in the body of the access device. In some embodiments, the channel region 225 may comprise silicon, germanium, silicon-germanium, and / or indium gallium zinc oxide (IGZO). In some embodiments, the first source / drain region 221 and the second source / drain region 223 may comprise an n-type dopant region formed in the p-type doped body of the access device to form an n-type conductive transistor. In some embodiments, the first source / drain region 221 and the second source / drain region 223 may comprise a p-type dopant formed in the n-type doped body of the access device to form a p-type conductive transistor. By way of example, but not limitation, the n-type dopant may comprise phosphorus (P) atoms, and the p-type dopant may comprise boron (B) atoms formed in a relatively doped body region of a polycrystalline silicon semiconductor material. However, the embodiments are not limited to these examples.

[0055] Storage node 227 (e.g., a capacitor) can be connected to a corresponding terminal of the access device. For example... Figure 2B As shown, storage node 227 (e.g., a capacitor) can be connected to the second source / drain region 223 of the access device. Storage nodes can be or contain memory elements capable of storing data. Each of the storage nodes can be a memory element using one of a capacitor, a magnetic tunnel junction pattern, and / or a variable resistor body containing a phase change material, etc. However, embodiments are not limited to these examples. In some embodiments, with unit cells (e.g. Figure 2AEach memory node associated with an access device in memory cell 210 can be similarly located in a memory node with a memory access device ... Figure 2A The second direction (D2) 205 shown in the middle extends upwards from the second direction (D2) 205.

[0056] like Figure 2B As shown, multiple horizontally oriented digital lines 207-1, 207-2, ... 207-Q are similar to... Figure 2A The first direction (D1) of 209 extends upwards from 209. Multiple horizontally oriented digital lines 207-1, 207-2, ..., 207-Q can be similar to... Figure 2A The digital lines 207-1, 207-2, ... 207-Q shown are illustrated. Multiple horizontally oriented digital lines 207-1, 207-2, ... 207-Q may be arranged (e.g., "stacked") along a third direction (D3) 211. The multiple horizontally oriented digital lines 207-1, 207-2, ... 207-Q may contain a conductive material. For example, the conductive material may contain one or more of the following: doped semiconductors (e.g., doped silicon, doped germanium, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), metals (e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), cobalt (Co), molybdenum (Mo), etc.), and / or metal-semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.). However, the embodiments are not limited to these examples.

[0057] In each of the vertical levels (L1) 213-1, (L2) 213-2, and (L3) 213-P, the horizontally oriented memory cells (e.g.) Figure 2A The memory cells 210 in the memory may be horizontally spaced apart from each other in the first direction (D1) 209. However, as described below... Figure 4As described in more detail, the laterally oriented access device 230 may have multiple discrete components extending laterally in the second direction (D2) 205 (e.g., a first source / drain region 221 and a second source / drain region 223 separated by a channel region 225), and multiple horizontally oriented digital lines 207-1, 207-2, ... 207-Q extending laterally in the first direction (D1) 209, which may be formed in different vertical layers within each level. For example, the multiple horizontally oriented digital lines 207-1, 207-2, ... 207-Q extending in the first direction (D1) 209 may be disposed on and electrically contacted with the top surface of the first source / drain region 221, and orthogonal to the laterally oriented access device 230 (e.g., a transistor) extending laterally in the second direction (D2) 205. In some embodiments, a plurality of horizontally oriented digital lines 207-1, 207-2, ... 207-Q extending in the first direction (D1) 209 are formed in a higher vertical layer within a layer hierarchy (e.g., within layer (L1)), which is further away from the substrate 200 than the layer in which discrete components of laterally oriented access devices (e.g., the first source / drain region 221 and the second source / drain region 223 separated by channel region 225) are formed. In some embodiments, the plurality of horizontally oriented digital lines 207-1, 207-2, ... 207-Q extending in the first direction (D1) 209 may be directly and / or connected to the top surface of the first source / drain region 221 via additional contacts comprising metal silicide.

[0058] like Figure 2B As shown in the example embodiments, access lines 203-1, 203-2, ... 203-Q extend in a vertical direction relative to substrate 200 (e.g., on third direction (D3) 211). Furthermore, as... Figure 2B As shown, a sub-cell array (e.g., Figure 2A Access lines 203-1, 203-2, ..., 203-Q in the sub-cell array 201-2 can be spaced apart from each other in a first direction (D1) 209. Access lines 203-1, 203-2, ..., 203-Q can be provided that extend vertically relative to the substrate 200 in a third direction (D3) 211 between a pair of laterally oriented access devices 230 (e.g., transistors) extending laterally in a second direction (D2) 205, but adjacent to each other in the first direction (D1) 209 at a level (e.g., a first level (L1)). Each of the access lines 203-1, 203-2, ..., 203-Q can extend vertically in a third direction (D3) on the sidewall of the corresponding of a plurality of laterally oriented access devices 230 (e.g., transistors) stacked vertically.

[0059] For example, and such Figure 3As shown in more detail, the first of the vertically extending access lines (e.g., 203-1) may be adjacent to the sidewall of the channel region 225 of the first laterally oriented access device 230 (e.g., transistor) in the first level (L1) 213-1, the sidewall of the channel region 225 of the first laterally oriented access device 230 (e.g., transistor) in the second level (L2) 213-2, and the sidewall of the channel region 225 of the first laterally oriented access device 230 (e.g., transistor) in the third level (L3) 213-P, etc. Similarly, the second vertically extending access line (e.g., 203-2) may be adjacent to the sidewall of the channel region 225 of the second laterally oriented access device 230 (e.g., transistor) in the first layer (L1) 213-1, and spaced apart from the first laterally oriented access device 230 (e.g., transistor) in the first direction (D1) 209. Furthermore, the second vertically extending access line (e.g., 203-2) may be adjacent to the sidewall of the channel region 225 of the second laterally oriented access device 230 (e.g., transistor) in the second layer (L2) 213-2, and the sidewall of the channel region 225 of the second laterally oriented access device 230 (e.g., transistor) in the third layer (L3) 213-P, etc. The embodiments are not limited to a specific number of layers.

[0060] The vertically extending access lines 203-1, 203-2, ... 203-Q may contain conductive materials, such as one of doped semiconductor materials, conductive metal nitrides, metals, and / or metal-semiconductor compounds. Access lines 203-1, 203-2, ... 203-Q may correspond to... Figure 2A The word line (WL) of the description.

[0061] like Figure 2B As shown in the example embodiment, the conductive body contact region 295 may be formed to extend along the end surface of the laterally oriented access device 230 (e.g., a transistor) in each of the layers (L1) 213-1, (L2) 213-2, and (L3) 213-P above the substrate 200 in a first direction (D1) 209. The body contact region 295 may be connected to each memory cell (e.g., Figure 2A The body (e.g., the main body region) of the laterally oriented access device 230 (e.g., a transistor) in the memory cell 210, such as Figure 3 As shown in 336. The main contact area 295 may contain a conductive material, such as a doped semiconductor material, a conductive metal nitride, a metal, and / or a metal-semiconductor compound.

[0062] although Figure 2BNot shown, but insulating material may fill other spaces in a vertically stacked array of memory cells. For example, the insulating material may comprise one or more of silicon oxide, silicon nitride, and / or silicon oxynitride. However, the embodiments are not limited to these examples.

[0063] Figure 3 A more detailed description of vertically stacked memory cell arrays according to some embodiments of the present disclosure (e.g.) Figure 2A The unit cells (e.g., within the sub-cell array 201-2) in the sub-cell array 201-2 Figure 2A (Memory unit 210 in the middle). For example Figure 3 As shown, the first source / drain region 321 and the second source / drain region 323 can be impurity-doped regions of a laterally oriented access device 330 (e.g., a transistor). The first source / drain region 321 and the second source / drain region 323 can be similar to... Figure 2B The first source / drain region 221 and the second source / drain region 223 are shown in the diagram. The first and second source / drain regions can be separated by a channel 325 formed in the body (e.g., body region 326) of the semiconductor material of the laterally oriented access device 330 (e.g., a transistor). The first source / drain region 321 and the second source / drain region 323 can be formed by an n-type or p-type dopant doped in the body region 326. The embodiments are not limited thereto.

[0064] For example, in an n-type conductive transistor configuration, the body region 326 of the laterally oriented access device 330 (e.g., a transistor) may be formed of a lightly doped (p-) p-type semiconductor material. In some embodiments, the body region 326 and the channel 325 separating the first source / drain region 321 and the second source / drain region 323 may comprise a lightly doped p-type (e.g., a lower dopant concentration (p-)) polysilicon material composed of boron (B) atoms as an impurity dopant for the polysilicon. The first source / drain region 321 and the second source / drain region 323 may also comprise metals and / or metal composites formed using processes such as atomic layer deposition containing ruthenium (Ru), molybdenum (Mo), nickel (Ni), titanium (Ti), copper (Cu), highly doped degenerate semiconductor materials, and / or indium oxide (In₂O₃) or indium tin oxide (In₂O₃). 2-x Sn x At least one of O3). However, the embodiments are not limited to these examples.

[0065] As used herein, degenerate semiconductor material refers to a semiconductor material, such as polycrystalline silicon, containing a high level of doping with significant interactions between dopants (e.g., phosphorus (P), boron (B), etc.). In contrast, non-degenerate semiconductors contain a moderate level of doping, where the dopant atoms are well separated from each other in the semiconductor bulk lattice with negligible interactions.

[0066] In this example, the first source / drain region 321 and the second source / drain region 323 may contain highly doped n-type conductive impurities (e.g., highly doped (n+)) doped into the first source / drain region 321 and the second source / drain region 323. In some embodiments, the highly doped n-type conductive first drain region 321 and the second drain region 323 may contain a high concentration of phosphorus (P) atoms deposited therein. However, the embodiments are not limited to this example. In other embodiments, the laterally oriented access device 330 (e.g., a transistor) may have a p-type conductive configuration, in which case the conductivity type of the impurities (e.g., dopants) will be reversed.

[0067] like Figure 3 As shown in the example embodiment, the first source / drain region 321 may occupy the upper portion of the body 326 of the laterally oriented access device 330 (e.g., a transistor). For example, the first source / drain region 321 may have a bottom surface 324 within the body 326 of the laterally oriented access device 330, which is vertically higher in a third direction (D3) 311 compared to the bottom surface of the body 326 of the laterally oriented access device 330. Thus, the laterally oriented transistor 330 may have a region lower than the first source / drain region 321 and in contact with the body (e.g., Figure 2B The main body portion 326 of the electrical contact shown in Figure 295. Furthermore, as... Figure 3 As shown in the example embodiments, similar to Figure 2B The numerical lines 207-1, 207-2, ..., 207-Q and Figure 2A The digital lines 207-1, 207-2, ... 207-Q shown in the figure (e.g., 307-1) can be placed on the top surface 322 of the first source / drain region 321 and electrically coupled thereto.

[0068] like Figure 3 As shown in the example embodiments, the access line (e.g., similar to) Figure 2B Access lines 203-1, 203-2, ..., 203-Q and Figure 2A 203-1, 203-2, ..., 203-Q of 303-1) may extend vertically on a third direction (D3) 311 adjacent to the sidewall of the channel region 325 portion of the body 326 of the laterally oriented access device 330 (e.g., a transistor), the channel region 325 being horizontally conductive along a second direction (D2) 305 between the first source / drain region 321 and the second source / drain region 323. A gate dielectric material 304 may be inserted between the access line 303-1 (a portion of which forms the gate of the laterally oriented access device 330 (e.g., a transistor)) and the channel region 325.

[0069] The gate dielectric material 304 may comprise, for example, a high-k dielectric material, a silicon oxide material, a silicon nitride material, a silicon oxynitride material, or a combination thereof. Embodiments are not limited thereto. For example, in a high-k dielectric material example, the gate dielectric material 304 may comprise one or more of the following: hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, etc.

[0070] Figure 4 The present invention describes an example process for generating a vertical three-dimensional (3D) memory using a single-crystal silicon stack, as illustrated in Figures 1 to 3 and according to several embodiments of the present disclosure. The vertical stack comprises multiple layers of single-crystal silicon germanium 430 and single-crystal silicon 432 formed on a substrate 437.

[0071] As discussed above, this can be achieved, for example, by providing a thin monocrystalline silicon-germanium layer as a seed layer, and then heating the layer to grow the thickness of the monocrystalline silicon-germanium layer through epitaxial growth. Once the desired layer thickness is formed, a silicon layer can be formed on the surface of the silicon-germanium layer. Similarly, this can be achieved, for example, by providing a thin monocrystalline silicon layer as a seed layer, and then heating the layer to grow the thickness of the monocrystalline silicon layer through epitaxial growth.

[0072] For example, single-crystal silicon germanium 430 can be epitaxially grown over a thin seed layer of single-crystal silicon germanium formed on the surface of a first layer of single-crystal silicon germanium on the surface of a substrate 437, and for subsequent single-crystal silicon germanium layers, over a thin seed layer of single-crystal silicon germanium formed on the surface of vertically stacked exposed single-crystal silicon layers. For example, disilane (Si2H6) gas can be used to epitaxially grow single-crystal silicon germanium from the exposed surface of a thin layer of single-crystal silicon germanium that has been deposited as a seed for the epitaxial growth of single-crystal silicon germanium. However, the embodiments are not limited to this. For example, dichlorosilane (SiH2Cl2) gas can flow over the seed layer to epitaxially grow single-crystal silicon germanium 430 onto the exposed surface of the seed layer.

[0073] In some embodiments, allowing a silicon-based gas to flow over the seed layer at a selected temperature (e.g., between 300 degrees Celsius and 1100 degrees Celsius) enables the epitaxial growth of monocrystalline silicon germanium 430 at a predictable rate. Based on this predictable growth rate, the monocrystalline silicon germanium layer can grow to the desired height within a predetermined time period. In some embodiments, for the epitaxial growth of monocrystalline silicon and / or monocrystalline silicon germanium, the temperature range may be, for example, below 900 degrees Celsius, where germanium can begin to diffuse and the monocrystalline silicon and monocrystalline silicon germanium can begin to mix, as at higher temperatures. This includes all individual values ​​and sub-ranges from 300°C to 1100°C; for example, silicon gas can be flowed at temperatures ranging from the lower limit of 300°C, 400°C, 450°C, 500°C, 550°C, 600°C, 650°C, 700°C, 750°C, 800°C, 850°C, or 900°C to the upper limit of 900°C, 950°C, 1000°C, 1050°C, or 1100°C. However, the embodiments are not limited to these examples. For instance, silicon-based gas can be flowed at temperatures from 300°C to 1100°C to enable the epitaxial growth of single-crystal silicon germanium. This includes all individual values ​​and sub-ranges from 300°C to 1100°C.

[0074] Furthermore, silicon-based gas can flow for 1 to 15 minutes to allow for the epitaxial growth of single-crystal silicon-germanium. This includes all individual values ​​and sub-ranges from 1 to 15 minutes; for example, timeframes from lower limits of 1, 2, 3, 4, 5, 6, 7, 8, 9, or 10 minutes to upper limits of 8, 9, 10, 11, 12, 13, 14, or 15 minutes that allow for silicon gas flow. For instance, silicon-based gas can flow at a temperature of 800°C to 900°C for 7 to 10 minutes to allow for the epitaxial growth of single-crystal silicon-germanium.

[0075] However, the embodiments are not limited to these examples. For instance, the duration for which the silicon-based gas flows over the single-crystal silicon-germanium seed layer can vary depending on the temperature of the silicon-based gas. For example, the silicon-based gas can flow for 1 minute to 500 minutes based on said temperature to allow for the epitaxial growth of single-crystal silicon. This includes all individual values ​​and sub-ranges from 1 minute to 500 minutes.

[0076] To form a monocrystalline silicon layer on top of a previously formed monocrystalline silicon-germanium layer, depending on the silicon-germanium concentration, if silicon is amount x and germanium is amount y, and if y is less than x, then the silicon / silicon-germanium ratio has a smaller lattice mismatch relative to the monocrystalline silicon lattice, as discussed above. This allows monocrystalline silicon to grow on top of monocrystalline silicon-germanium with a monocrystalline structure. If a thin layer of monocrystalline silicon is applied to the surface of the monocrystalline silicon-germanium, then the entire monocrystalline silicon layer acts as a seed for the growth of the monocrystalline silicon layer.

[0077] The processes and parameters used to form a single-crystal silicon layer are similar to those described above for single-crystal silicon-germanium layers. For example, single-crystal silicon 432 can be epitaxially grown by flowing a silicon-based gas over a thin seed layer of single-crystal silicon formed on the surface of a previously formed, vertically stacked, exposed single-crystal silicon-germanium layer. For example, disilane (Si₂H₆) gas can be used to epitaxially grow single-crystal silicon from the exposed surface of a thin layer of single-crystal silicon that has been deposited as a seed for the epitaxial growth of the single-crystal silicon layer.

[0078] However, the embodiments are not limited to this. For example, dichlorosilane (SiH2Cl2) gas may flow over the seed layer to allow single-crystal silicon 432 to be epitaxially grown onto the exposed surface of the single-crystal silicon seed layer.

[0079] In some embodiments, similar to the formation of a single-crystal silicon-germanium layer, the flow of a silicon-based gas over a single-crystal silicon seed layer at a selected temperature, for example, between 300°C and 1100°C, allows the single-crystal silicon 432 to be epitaxially grown at a predictable rate. Based on this predictable growth rate, the single-crystal silicon layer can be grown to the desired height within a predetermined time period. This includes all individual values ​​and sub-ranges of 300°C to 1100°C; for example, the silicon gas can be flowed at temperatures ranging from the lower limit of 300°C, 400°C, 450°C, 500°C, 550°C, 600°C, 650°C, 700°C, 750°C, 800°C, 850°C, or 900°C to the upper limit of 900°C, 950°C, 1000°C, 1050°C, or 1100°C. However, the embodiments are not limited to these examples. For instance, the silicon-based gas can be flowed at temperatures between 300°C and 4000°C to allow the single-crystal silicon to be epitaxially grown. It includes all individual values ​​and sub-ranges from 300℃ to 4000℃.

[0080] Furthermore, the silicon-based gas can flow for 1 to 15 minutes to allow for the epitaxial growth of monocrystalline silicon. This includes all individual values ​​and sub-ranges from 1 to 15 minutes; for example, timeframes from lower limits of 1, 2, 3, 4, 5, 6, 7, 8, 9, or 10 minutes to upper limits of 8, 9, 10, 11, 12, 13, 14, or 15 minutes that allow for silicon gas flow. For instance, the silicon-based gas can flow at a temperature of 800°C to 900°C for 7 to 10 minutes to allow for the epitaxial growth of monocrystalline silicon.

[0081] This layering can be performed alternately (e.g., SiGe / Si / SiGe / Si, etc.) to create a superlattice structure in a vertically stacked manner. This unpatterned (unpatterned within the layers) vertical stack can then be attached to a CMOS wafer, as per [reference needed]. Figure 5As described. One advantage of this process is that, because the vertical stack is not yet patterned, it does not require careful alignment with the CMOS wafer.

[0082] Figure 5 This describes example processes for stacking and bonding single-crystal silicon to a CMOS wafer 545 according to several embodiments of the present disclosure. In some embodiments, such as Figure 5 As explained, single-crystal silicon germanium 530 and single-crystal silicon 532 layers have been epitaxially grown onto substrate 537 and epitaxially grown together to form a structure as described above. Figure 4 After the vertical stacking of the layers described herein, the vertical stack 501 can be bonded to the complementary metal-oxide-semiconductor (CMOS) wafer 545.

[0083] In some embodiments, CMOS wafer 545 may include a silicon substrate material and transistors suitable for peripheral circuitry. That is, CMOS components may be formed on the silicon substrate material. In some embodiments, an unprocessed silicon layer may be bonded to a vertical stack 501 via an oxide intermediate, and once bonded to the vertical stack 501, the unprocessed silicon layer may be processed to form a CMOS component. In some embodiments, this may be because the process for forming the CMOS component can be performed at a lower temperature (e.g., 250°C) than the temperature used to form the silicon and silicon-germanium layers of the vertical stack.

[0084] like Figure 5 As shown in the example, vertically stacked 501 units can be rotated 180 degrees (e.g., flipped), making... Figure 4 The top silicon-germanium layer (with an exposed surface) becomes a bonding surface, onto which bonding material 540 (e.g., an "adhesive" layer) can be placed and used to bond the vertically stacked 501 to the CMOS wafer 545. Figure 5 In this configuration, both the vertical stack and the CMOS wafer have bonding materials (540 and 542, respectively) on them, and these materials are bonded together to join the vertical stack and the CMOS wafer. However, in some embodiments, the bonding materials may be positioned on the vertical stack or the CMOS wafer prior to bonding. Any suitable bonding material can be used to join the vertical stack and the CMOS wafer.

[0085] Figure 6 This describes another example of a process for stacking and bonding single-crystal silicon to a CMOS wafer according to several embodiments of this disclosure. For example... Figure 5 As illustrated in the embodiments, when the bonding materials are bonded together, a dielectric layer 644 can be formed between the vertical stack 601 and the CMOS wafer 645.

[0086] In some embodiments, such as Figure 6As described, the original substrate can be removed after the vertically stacked 601 is bonded to the CMOS wafer 645 (e.g., Figure 5 Substrate 537 in the middle). Figure 6 In one embodiment, the original substrate has been removed and a hard mask material 646 has been formed in its place. This can be used during the patterning of vertically stacked layers.

[0087] exist Figure 7 The image shows an example of a memory cell array that can be produced by patterned, vertically stacked layers. However, vertically stacked structures formed from single-crystal silicon and silicon-germanium are extremely versatile and can therefore be used to fabricate many different types of vertical memory cell arrays.

[0088] Figure 7 This describes example patterned vertical memory arrays formed from stacks of single-crystal silicon bonded to a CMOS wafer, according to several embodiments of the present disclosure. For example... Figure 7 As described, the memory array includes a CMOS wafer 745 bonded to a vertically stacked 701 via a bonding material 744, which has now been patterned to form a plurality of stacked memory cells. Each memory cell may be, for example, a horizontally oriented memory node (e.g., a capacitor cell) already formed by a semiconductor manufacturing process, wherein a first electrode 761 (e.g., a bottom electrode to be coupled to the source / drain region of a horizontal access device) and a second electrode 756 (e.g., a top electrode to be coupled to a common electrode plane, such as a ground plane) are separated by a cell dielectric 763 and may have conductive lines 777. However, the embodiments are not limited to the components shown in this example.

[0089] Conductive lines 777 (e.g., digital lines or word lines) may be formed from a conductive material provided within an interlayer dielectric (ILD) layer 778. In the illustrated structure, when a mask is removed, for example via an inner liner process (e.g., Figure 6 When the top layer having conductive lines 777 and ILD 778 is exposed after step 646), the top layer may be formed on top of the top monocrystalline silicon layer 730. The monocrystalline silicon layer 730 may form the channel region of the memory cell. The silicon-germanium layer or a portion thereof may be selectively removed to form a structure, for example, conductive lines 777, a first ILD layer 778, and a second ILD layer 779. Figure 7 The memory cell array described herein also demonstrates, as previously discussed... Figure 2B The main contact area 795 (e.g., conductive main contact area 295) and the mask layer 748 which can be used as part of the memory array formation process.

[0090] The memory cell array may also have source / drain regions formed therein. For example, a doped layer may be used to form the source / drain regions of the access transistors.

[0091] In some embodiments, the vertically stacked memory array can be bonded to a CMOS wafer after the memory cells are formed. This can be advantageous because the two components can be formed separately and then combined, which allows for more specialized manufacturing processes that can be focused on the CMOS wafer formation process or the memory array formation process.

[0092] like Figure 7 As illustrated in the embodiments, when the bonding materials are bonded together, a dielectric layer 744 can be formed between the vertical stack 701 and the CMOS 745.

[0093] Figure 8 This is a block diagram of a device in the form of a computing system including a memory device, according to several embodiments of the present disclosure. Figure 8 This is a block diagram of a device in the form of a computing system 800 including a memory device 803, according to several embodiments of the present disclosure. As used herein, the memory device 803, memory array 810, and / or host 802 may also be considered, for example, as “devices”. According to an embodiment, the memory device 802 may include at least one memory array 810 having a three-node access means of vertical three-dimensional (3D) memory, as described herein.

[0094] In this example, system 800 includes a host 802 coupled to memory device 803 via interface 804. The computing system 800 may be a personal laptop, desktop computer, digital camera, mobile phone, memory card reader, or Internet of Things (IoT) enabled device, as well as various other types of systems. Host 802 may include several processing resources (e.g., one or more processors, microprocessors, or other types of control circuitry) capable of accessing memory 803. System 800 may include a separate integrated circuit, or host 802 and memory device 803 may both be on the same integrated circuit. For example, host 802 may be a system controller for a memory system including multiple memory devices 803, wherein system controller 805 provides access to the respective memory devices 803 by another processing resource, such as a central processing unit (CPU).

[0095] exist Figure 8In the example shown, host 802 is responsible for executing an operating system (OS) and / or various applications (e.g., processes) that can be loaded onto memory device 803 (e.g., via controller 805). The OS and / or various applications can be loaded from memory device 803 by providing access commands from host 802 to memory device 803 for accessing data including the OS and / or various applications. Host 802 can also access the data used by the OS and / or various applications by providing access commands to memory device 803 for retrieving the data used to execute the OS and / or various applications.

[0096] For clarity, system 800 has been simplified to focus on features particularly relevant to this disclosure. Memory array 810 may be a DRAM array, SRAM array, STT RAM array, PCRAM array, TRAM array, RRAM array, NAND flash array, and / or NOR flash array, comprising at least one three-node access device of three-dimensional (3D) memory. For example, memory array 810 may be an unshielded DL 4F2 array, such as a 3D-DRAM memory array. Array 810 may include memory cells arranged in rows coupled via word lines (which may be referred to herein as access lines or select lines) and columns coupled via digital lines (which may be referred to herein as sense lines or data lines). Although in Figure 8 The illustration shows a single array 810, but the embodiments are not limited thereto. For example, the memory device 803 may include several arrays 810 (e.g., arrays of DRAM cells).

[0097] Memory device 803 includes address circuitry 806 to latch address signals provided via interface 804. The interface may include a physical interface employing, for example, a suitable protocol (e.g., a data bus, address bus, and command bus, or a combination of data / address / command buses). Such protocols may be custom or proprietary, or interface 804 may utilize standardized protocols such as PCIe, Gen-Z, CCIX, etc. Row decoder 808 and column decoder 812 receive and decode address signals to access memory array 810. Data can be read from memory array 810 by sensing voltage and / or current changes on a sensing line using sensing circuitry 811. Sensing circuitry 811 may include, for example, a sensing amplifier that can read and latch pages (e.g., rows) of data from memory array 810. I / O circuitry 807 can be used for bidirectional data communication with host 802 via interface 804. Read / write circuitry 813 is used to write data to or read data from memory array 810. As an example, circuit 813 may include various drivers, latching circuits, etc.

[0098] Control circuitry 805 decodes signals provided by host 802. These signals may be commands provided by host 802. These signals may include chip enable signals, write enable signals, and address latch signals, which control operations performed on memory array 810, including data read operations, data write operations, and data erase operations. In various embodiments, control circuitry 805 is responsible for executing instructions from host 802. Control circuitry 805 may include a state machine, a sequencer, and / or some other type of control circuitry, which may be implemented in hardware, firmware, or software, or any combination thereof. In some instances, host 802 may be a controller external to memory device 803. For example, host 802 may be a memory controller coupled to the processing resources of a computing device.

[0099] For example, the term semiconductor can refer to a material, wafer, or substrate, and includes any substrate semiconductor structure. "Semiconductor" should be understood to include silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin-film transistor (TFT) technology, doped and undoped semiconductors, epitaxial silicon supported by a substrate semiconductor structure, and other semiconductor structures. Furthermore, when referenced to semiconductor in the foregoing description, prior processing steps may have been used to form regions / junctions in the substrate semiconductor structure, and the term semiconductor may include a base material containing these regions / junctions.

[0100] Transistors formed using the processes described herein can have several advantages. For example, transistors will have better performance in terms of I-on and I-off, driveability, and leakage current. Polycrystalline silicon leaks due to the robustness of the polycrystalline silicon material, but monocrystalline layers are not robust, and therefore, current does not easily leak through the monocrystalline material. In some embodiments, embodiments of this disclosure can, for example, improve I-off by three orders of magnitude or better compared to prior art devices.

[0101] The figures in this document follow a numbering convention, wherein the first one or more digits correspond to the figure number, and the remaining digits identify elements or components in the figure. Similar (e.g., identical) elements or components between different figures may be identified by using similar digits. It should be understood that elements shown in the various embodiments herein may be added, interchanged, and / or excluded to provide several additional embodiments of this disclosure. Furthermore, it should be understood that the scale and relative dimensions of the elements provided in the figures are intended to illustrate embodiments of this disclosure and should not be construed as limiting.

[0102] As used herein, “several” or “a certain number” of something can refer to one or more of such things. For example, “several” or “a certain number” of memory cells can refer to one or more memory cells. “A certain number” of something means two or more. As used herein, multiple actions performed simultaneously refer to actions that overlap at least partially within a specific time period. As used herein, the term “coupling” can include electrical coupling, direct coupling and / or direct connection (e.g., by direct physical contact) without intermediate elements, or indirect coupling and / or connection with intermediate elements, or wireless coupling. The term coupling can further include two or more elements that cooperate or interact with each other (e.g., as in causality). An element coupled between two elements can be between and coupled to each of the two elements.

[0103] It should be recognized that the term "vertical" refers to variations in verticality due to routine manufacturing, measurement, and / or assembly variations, and the meaning of the term "vertical" will be understood by those skilled in the art. For example, vertical may correspond to the z-direction. As used herein, when a particular element is "adjacent" to another element, the particular element may cover the other element, be above or laterally to the other element, and / or be in direct physical contact with the other element. For example, laterally to may refer to a horizontal direction that may be perpendicular to the z-direction (e.g., the y-direction or x-direction).

[0104] Although specific embodiments have been illustrated and described herein, those skilled in the art will understand that arrangements calculated to achieve the same results may replace the specific embodiments shown. This disclosure is intended to cover modifications or variations of various embodiments of this disclosure. It should be understood that the above description is illustrative rather than restrictive. Combinations of the above embodiments and other embodiments not specifically described herein will be apparent to those skilled in the art after reviewing the above description. The scope of the various embodiments of this disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of the various embodiments of this disclosure should be determined by reference to the appended claims and the full scope of the equivalents granted by those claims.

Claims

1. A method comprising: Several CMOS components are formed on the first substrate; The second substrate is bonded to the first substrate using an adhesive layer; as well as Before bonding the second substrate to the first substrate, a vertical stack of repeated material layers is formed on the second substrate, wherein each repeated stack includes a monocrystalline silicon layer and a selectively removable layer. A plurality of vertically stacked memory cells are formed, wherein each of the plurality of vertically stacked memory cells includes an access transistor having a channel region formed by at least a portion of a corresponding monocrystalline silicon layer.

2. The method of claim 1, wherein the method comprises forming the plurality of CMOS components at a temperature of 300°C or lower.

3. The method according to claim 1, wherein the selectively removable layer is epitaxially grown single-crystal silicon-germanium.

4. The method of claim 1, wherein forming the plurality of vertically stacked memory cells includes replacing a portion of the selectively removable layer with a first interlayer dielectric layer.

5. The method of claim 4, wherein forming the plurality of vertically stacked memory cells includes replacing another portion of the selectively removable layer with a second interlayer dielectric layer.

6. The method of claim 4, wherein forming the plurality of vertically stacked memory cells includes forming a conductive line material in the first interlayer dielectric layer, and wherein the conductive line is a digital line or a word line.

7. The method of claim 1, wherein the method includes forming the plurality of vertically stacked memory cells prior to bonding the second substrate to the first substrate.

8. A memory device comprising: Several CMOS components are formed on the first substrate; as well as A second substrate is bonded to the first substrate via an adhesive layer; The second substrate includes a vertically stacked memory array formed thereon, the memory array comprising a plurality of single-crystal silicon layers, each single-crystal silicon layer being separated by at least one additional material layer; The vertically stacked memory array comprises multiple vertically stacked memory cells; Each of the plurality of vertically stacked memory cells includes an access transistor having a channel region formed by at least a portion of a corresponding monocrystalline silicon layer among the plurality of monocrystalline silicon layers.

9. The memory device of claim 8, wherein each of the plurality of single-crystal silicon layers is epitaxially grown, and wherein the adhesive layer is a dielectric material.

10. The memory device of claim 8, wherein each memory cell in the vertically stacked memory cells is coupled to a corresponding horizontally oriented capacitor.

11. The memory device of claim 8, wherein each of the at least one additional layer of the vertically stacked memory array comprises an interlayer dielectric formed therein, and each of the at least one additional layer of the vertically stacked memory array comprises word lines or digital lines formed therein.

12. A method comprising: Several CMOS transistors corresponding to the first substrate are formed; Before bonding the first substrate to the second substrate by means of bonding material layers, a vertical stack of repeated material layers is formed on the second substrate, wherein each repeated stack includes an epitaxially grown monocrystalline silicon layer. as well as A plurality of vertically stacked memory cells are formed, wherein each of the plurality of vertically stacked memory cells includes an access transistor having a channel region formed by at least a portion of a corresponding epitaxially grown monocrystalline silicon layer; as well as The first substrate is bonded to the second substrate.

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