X-ray detector

Abstract

The present invention provides an X-ray detector comprising: a pixel array panel comprising a plurality of pixels; a single photon avalanche diode disposed within the pixel; a diode driving circuit disposed within the pixel and including a pulse generating circuit that converts an electrical signal output from an output terminal of the single photon avalanche diode into an output signal in a pulse form; a pixel control circuit disposed within the pixel and including a first control circuit outputting the output signal as a clock signal; and a counter circuit disposed within the pixel and including a counter of n bits (n is an integer of 2 or more) counting the clock signal.

Description

Technical Field

[0001] This invention relates to an X-ray detector. Background Technology

[0002] Recently, digital detectors have been widely used in X-ray imaging.

[0003] X-ray detectors include photodiodes, and research is currently underway on avalanche diodes, which have the advantage of high signal gain, especially single-photon avalanche diodes (SPADs).

[0004] However, existing image sensors using single-photon avalanche diodes include analog counters to count pulses, which makes it difficult to achieve high resolution and wide dynamic range, and introduces noise during the conversion of analog signals to digital signals and the reading of analog signals.

[0005] Therefore, if the X-ray detector has the same pixel configuration as existing image sensors, the same problem will occur. Summary of the Invention Technical issues

[0006] The technical problem of this invention is to provide a solution that can achieve high resolution and wide dynamic range while preventing noise generation when using an X-ray detector with a single-photon avalanche diode. Technical solution

[0007] To address the technical problem described above, the present invention provides an X-ray detector, comprising: a pixel array panel including a plurality of pixels; a single-photon avalanche diode disposed within the pixels; a diode driving circuit disposed within the pixels, and including a pulse generation circuit for converting an electrical signal output from the output terminal of the single-photon avalanche diode into a pulse-shaped output signal; a pixel control circuit disposed within the pixels, and including a first control circuit for outputting the output signal as a clock signal; and a counter circuit disposed within the pixels, and including an n-bit counter (n is an integer greater than 2) for counting the clock signal.

[0008] The diode driving circuit may include: a recharge transistor connected to the output terminal of the single-photon avalanche diode; a recharge control circuit, with a first input terminal connected to the output terminal of the pulse generation circuit, a second input terminal receiving an enable control signal, and an output terminal connected to the gate electrode of the recharge transistor; and an enable transistor, with its gate electrode receiving the enable control signal, its source electrode connected to the output terminal of the single-photon avalanche diode, and its drain electrode receiving an inactive voltage.

[0009] The bias voltage applied to the cathode of the single-photon avalanche diode can be the sum of the breakdown voltage and the access voltage, and the inactive voltage can be greater than the access voltage.

[0010] The pixel control circuit may include: a second control circuit that receives an enable signal and an output control signal output from the counter and outputs the enable control signal, wherein the enable signal can determine an accumulation interval, and the output control signal can become a cutoff level when the count value of the counter reaches the maximum value of the n bits.

[0011] The counter circuit may include an output circuit that outputs the n-bit data signal stored in the counter to the data wiring, wherein the counter can divide the n bits of the data signal into k parts (k is an integer greater than or equal to 2 and less than n) to output the first segmented signal to the k-th segmented signal of n / k bits.

[0012] The output circuit may include n / k first driving transistors to the kth driving transistor and n / k first switching transistors and the kth switching transistor, respectively, corresponding to the first segmentation signal to the kth segmentation signal. Each of the first driving transistors to the kth driving transistor can connect its gate electrode to the corresponding output terminal of the counter and its drain electrode to the first switching transistor to the kth switching transistor. Each of the first switching transistors to the kth switching transistor can receive the first scan signal to the kth scan signal at its gate electrode and connect its drain electrode to the corresponding data wiring. The data wiring can transmit the corresponding bit of the segmentation signal output from the switching transistor connected to it.

[0013] The counter can receive a bit adjustment signal that adjusts the number of the n bits. Beneficial effects

[0014] According to the present invention, a digital data signal can be directly generated and read within a pixel by constructing a digital counter within a pixel equipped with a single-photon avalanche diode.

[0015] Therefore, during the data signal reading process, the generation of noise can be effectively reduced to zero, thereby maximizing image quality. Furthermore, a wide dynamic range and high-resolution image, which are difficult to achieve with analog counters, can be realized using an n-bit digital counter. Attached Figure Description

[0016] Figure 1 This is a schematic diagram illustrating the configuration of an X-ray detector according to an embodiment of the present invention.

[0017] Figure 2 This is a circuit diagram schematically illustrating an example of the configuration of pixels in an X-ray detector according to an embodiment of the present invention.

[0018] Figure 3 This is a circuit diagram illustrating a single-photon avalanche diode and a diode driving circuit for a pixel according to an embodiment of the present invention.

[0019] Figure 4 This is a schematic diagram illustrating the control circuit and counter circuit of a pixel according to an embodiment of the present invention.

[0020] Figure 5 This is a timing diagram illustrating the signals of the operating pixels according to an embodiment of the present invention. Detailed Implementation

[0021] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0022] Figure 1 This is a schematic diagram illustrating the configuration of an X-ray detector according to an embodiment of the present invention. Figure 2 This is a circuit diagram schematically illustrating an example of the configuration of pixels in an X-ray detector according to an embodiment of the present invention. Figure 3 This is a circuit diagram illustrating a single-photon avalanche diode and a diode driving circuit for a pixel according to an embodiment of the present invention. Figure 4 This is a schematic diagram illustrating the control circuit and counter circuit of a pixel according to an embodiment of the present invention.

[0023] Reference Figure 1 and Figure 2 According to an embodiment of the present invention, the X-ray detector 10 may include a pixel array panel (or sensor panel) 100 and a phosphor 200.

[0024] The phosphor 200 can be arranged on the light-receiving surface of the pixel array panel 100. The phosphor 200 can convert incident X-rays into visible light, which can be provided to the pixel array panel 100, and the avalanche photodiode (or avalanche light-receiving element) (e.g., single-photon avalanche diode SPAD) equipped on the pixel P can detect photons of the visible light and generate an electrical signal.

[0025] The pixel array panel 100 may include an effective area, which is the area that substantially receives and detects X-rays, and an ineffective area located outside the effective area.

[0026] Within the effective area, a pixel array consisting of multiple pixels P can be arranged, and the multiple pixels P can be arranged in a matrix form along multiple row lines and multiple column lines.

[0027] Pixel P can use a single-photon avalanche diode (SPAD) to detect photons of visible light generated from phosphor 200 and generate corresponding pulse signals to count the number of photons and output the count value.

[0028] Regarding the composition of pixel P, refer to... Figures 2 to 4 For example, each pixel P may include a single-photon avalanche diode SPAD, a diode driving circuit PDC, a pixel control circuit PCC, and a counter circuit COC.

[0029] One electrode (or first electrode) (e.g., anode) of a single-photon avalanche diode (SPAD) can be connected to a diode drive circuit (PDC). The other electrode (or second electrode) (e.g., cathode) of the SPAD can receive a bias voltage (or reverse voltage) Vb as the drive voltage.

[0030] Here, the bias voltage Vb is the voltage used to enable the single-photon avalanche diode (SPAD) to operate in Geiger mode and generate avalanche amplification. Preferably, it has a voltage greater than the breakdown voltage Vbd. For example, the bias voltage Vb can be expressed as the sum of the breakdown voltage Vbd and the access voltage VCX (i.e., (Vb = Vbd + VCX)), where the access voltage VCX is a voltage above the minimum level required to enable the single-photon avalanche diode to operate in Geiger mode.

[0031] Thus, in the state of being activated (i.e., when a bias voltage Vb higher than the breakdown voltage Vbd is applied to enable the single-photon avalanche diode SPAD to operate), the single-photon avalanche diode SPAD generates an electrical signal (or diode signal or detection signal) in response to the incident photon.

[0032] For example, a diode driver circuit PDC may include a pulse generation circuit (or delay circuit or shaping circuit) PSC, a recharge transistor (or first transistor) Mar, an enable transistor (or second transistor) Maq, and a recharge control circuit RCC.

[0033] A pulse generation circuit (PSC) can be connected as the output terminal of a single-photon avalanche diode (SPAD) to node N between the anode of the SPAD and the recharge transistor Mar. This PSC converts (or shapes) the electrical signal output by the SPAD in response to photons into a digital signal PS in pulse form (or rectangular wave) and outputs it. For example, this PSC can be constructed using multiple (more specifically, an even number) inverters connected in series. In this case, the PSC can delay the output signal PS for a predetermined time (for example, several ns to several microseconds) before outputting it.

[0034] The recharge transistor Mar can be connected in series with the single-photon avalanche diode SPAD, and the electrical signal can be output through the output terminal of node N, which serves as the link between the recharge transistor Mar and the single-photon avalanche diode SPAD. For example, the recharge transistor Mar can be constructed using an N-type transistor, but it is not limited to this.

[0035] If a recharge signal Φar, which serves as a control signal, is applied to the gate electrode of such a recharge transistor Mar, the recharge transistor Mar can be turned on. Accordingly, the single-photon avalanche diode SPAD can be recharged to its initial state, and a diode voltage corresponding to the bias voltage Vb can be applied across the single-photon avalanche diode SPAD.

[0036] The recharge control circuit RCC can generate and output a recharge signal Φar that controls the switching operation of the recharge transistor Mar. Relatedly, for example, the recharge control circuit RCC can be constructed using an AND gate. In this case, the AND gate receives the output signal PS from the pulse generation circuit PSC at its first input and the enable control signal Φaq from the pixel control circuit PCC at its second input. The AND gate circuit can then output the recharge signal Φar by performing an AND logic operation on the output signal PS and the enable control signal Φaq.

[0037] Relatedly, for example, when pixel P is in an active state (i.e., normal state), the enable control signal Φaq can have a high level with a logic value of "1". In this state, if a pulse-shaped output signal PS is generated, the recharge control circuit RCC can output a pulse-shaped recharge signal Φar in response. In this case, the recharge transistor Mar can be turned on by the recharge signal Φar, thereby recharging the single-photon avalanche diode SPAD. A diode voltage substantially corresponding to the bias voltage Vb can be applied across the single-photon avalanche diode SPAD, and it can become capable of detecting the photon activation state.

[0038] The enable transistor Maq has the opposite type to the recharge transistor Mar. For example, it can be constructed using a P-type transistor, but is not limited to this.

[0039] The drain (or source) electrode of the enable transistor Maq can be connected to node N between the recharge transistor Mar and the single-photon avalanche diode SPAD. Furthermore, the source (or drain) electrode of the enable transistor Maq can receive the inactive voltage Vna. And, the gate electrode of the enable transistor Maq can receive the enable control signal Φaq.

[0040] Here, the non-activation voltage Vna can be a voltage greater than the access voltage VCX of the bias voltage Vb. Furthermore, the non-activation voltage Vna can be a voltage less than the breakdown voltage Vbd.

[0041] Relatedly, for example, when the enable control signal Φaq is at a low level with a logic value of "0", the enable transistor Maq can be turned on, and a deactivation voltage Vna can be applied at node N between the recharge transistor Mar and the single-photon avalanche diode SPAD. In this case, the diode voltage applied to the single-photon avalanche diode SPAD becomes Vb - Vna = Vbd + Vex - Vna; Vna > Vex, causing a voltage less than the breakdown voltage Vbd to be stuck across the single-photon avalanche diode SPAD. Thus, the single-photon avalanche diode SPAD is in an inactive state and does not detect photons.

[0042] Furthermore, when the enable control signal Φaq is at a high level with a logic value of "1", the enable transistor Maq can be turned off, and the node N between the recharge transistor Mar and the single-photon avalanche diode SPAD can be free from the application of the deactivation voltage Vna. Therefore, the single-photon avalanche diode SPAD can remain active and can output an electrical signal in response to the input photon.

[0043] As described above, according to the logic value of the enable control signal Φaq, the pixel P (more specifically, the single-photon avalanche diode SPAD) can be activated or deactivated. In the activated state, an electrical signal is generated in the single-photon avalanche diode SPAD based on photons, and this electrical signal can be converted into a pulse-shaped output signal PS in the diode drive circuit PDC and output.

[0044] Therefore, the enable control signal Φaq can have a logic value of "1" (or a cutoff level), allowing the single-photon avalanche diode SPAD to be active during the integration time, which is the interval for detecting X-rays. Alternatively, the enable control signal Φaq can have a logic value of "0" (or a turn-on level), allowing the single-photon avalanche diode SPAD to be inactive during the readout time after the integration time has ended, when the data signal (or pixel signal) detected (or counted) in pixel P is read (or output).

[0045] For example, the pixel control circuit PCC may include a first control circuit CC1 and a second control circuit CC2.

[0046] The first control circuit CC1 can output the output signal PS from the diode driver circuit PDC as a clock signal Φclk. For example, as described above, the first control circuit CC1 can receive the output signal PS from the diode driver circuit PDC and the output control signal (or overflow signal) Φof provided by the counter circuit COC (more specifically, the counter CNT) as input signals.

[0047] Here, in relation to the output control signal Φof, if the value counted from the counter CNT reaches a preset number of bits (for example, the most significant bit of the preset number of bits), the operation of the single-photon avalanche diode SPAD is stopped (i.e., deactivated) to stop generating the output signal PS and the clock signal Φclk, which is equivalent to a signal used to stop the counting operation of the counter CNT. In other words, if the count value of the counter CNT reaches a preset saturation value, the output control signal Φof can be used to stop counting.

[0048] For example, the output control signal Φof can have a low level (or on level) with a logic value of "0" until the count value saturates in the accumulation range. If the count value reaches a preset saturation value, it can have a high level (or off level) with a logic value of "1".

[0049] Furthermore, for example, the first control circuit CC1 can be constructed using an OR gate, and the clock signal Φclk can be output by performing an OR logic operation on the output signal PS and the output control signal Φof.

[0050] When the output control signal Φof is “0”, the first control circuit CC1 can output the input output signal PS as the clock signal Φclk, and the counter CNT can count the clock signal Φclk.

[0051] In addition, if the count value is saturated, the output control signal Φof becomes "1" and no output signal PS is generated, and the first control circuit CC1 can stop the output of the clock signal Φclk.

[0052] The second control circuit CC2 can output an enable control signal Φaq to control the activation / deactivation of the single-photon avalanche diode (SPAD). For example, as described above, the second control circuit CC2 can receive an enable signal EN and an output control signal Φof as input signals.

[0053] The enable signal EN serves as a signal to determine the accumulation interval. For example, during the accumulation interval, the enable signal EN can have a high level with a logic value of "1", and during the read interval after the accumulation interval, the enable signal EN can have a low level with a logic value of "0".

[0054] For example, this second control circuit CC2 can be constructed using a NOR gate. The first input of the NOR gate can receive the output control signal Φof, and the second input of the NOR gate can be used as an inverting input to receive the enable signal EN.

[0055] In this case, the second control circuit CC2 can output the enable control signal Φaq by performing a NOR logic operation on the inverted signals of the output control signal Φof and the enable signal EN.

[0056] Here, if the counter circuit COC reaches saturation and the output control signal Φof goes high, the enable control signal Φaq goes low, turning on the enable transistor Maq. Furthermore, the deactivation voltage Vna can be applied to node N, deactivating the single-photon avalanche diode SPAD. Consequently, the operation of the SPAD stops, thus reducing power consumption.

[0057] Furthermore, if the accumulation interval ends, the enable signal EN can go low, thereby enabling the control signal Φaq to go low as the on level, and enabling the transistor Maq can be turned on, so that the single-photon avalanche diode SPAD can go into an inactive state.

[0058] For example, the counter circuit COC may include the counter CNT and the output circuit OC.

[0059] The counter CNT can receive and count the pulse-shaped clock signal Φclk output from the first control circuit CC1 during the accumulation interval, and can store the counted value. If the value counted by the counter CNT reaches the maximum value of a set bit (e.g., n bits (an integer greater than 2)) and saturates, the counting operation stops and an output control signal Φof is generated.

[0060] In addition, the counter CNT can receive the bit adjustment signal BIT_SEL and the reset signal Φrst.

[0061] The bit adjustment signal BIT_SEL is used to adjust (or set) the number of bits that can be counted by the counter CNT (i.e., the number of bits of the data signal of pixel P). As an example, n can be adjusted to 8 bits, 9 bits, 10 bits, etc. By adjusting the bit as described above, the required dynamic range of the X-ray detector 10 can be optimized, and power consumption can be reduced.

[0062] The reset signal Φrst can be used to initialize the count value by resetting the counter CNT. For example, the reset signal Φrst can be applied to reset the counter CNT before the start of the accumulation interval.

[0063] The output circuit OC can output the data signal, which is the digital value counted in the counter CNT, to the data wiring DL during the read interval.

[0064] For example, such an output circuit OC can be configured to divide an n-bit data signal into k (an integer greater than or equal to 2 and less than n) bits for output. In this embodiment, the following case will be used as an example for explanation: the n-bit data signal is divided into two parts to form a first segmented signal as an n / 2-bit signal and a second segmented signal as another n / 2-bit signal, and then output.

[0065] As described above, when the data signal is divided into two, the output circuit OC may include a first driving transistor Td1 and a first switching transistor Ts1 for outputting an n / 2-bit first segmented signal, and a second driving transistor Td2 and a second switching transistor Ts2 for outputting an n / 2-bit second segmented signal. Here, for example, the first segmented signal may be the upper n / 2 bits (or the lower n / 2 bits) of the data signal, and for example, the second segmented signal may be the lower n / 2 bits (or the upper n / 2 bits) of the data signal.

[0066] Here, each of the first driving transistor Td1 and the first switching transistor Ts1 can be configured to correspond to each of the n / 2 bits of the first segmentation signal. In other words, n / 2 first driving transistors Td1 and n / 2 first switching transistors Ts1 can be configured to correspond to each of the n / 2 bits of the first segmentation signal.

[0067] Similarly, each of the second driving transistor Td2 and the second switching transistor Ts2 can be configured to correspond to each of the n / 2 bits of the second segmentation signal. In other words, n / 2 second driving transistors Td2 and n / 2 second switching transistors Ts2 can be configured to correspond to each of the n / 2 bits of the second segmentation signal.

[0068] Furthermore, for the data routing DL connected to each pixel P, n / 2 data routing DLs of the number of bits of the first segmentation signal and the second segmentation signal can be provided. In other words, each of the n / 2 data routing DLs can be configured to be connected to n / 2 first switching transistors Ts1 and to n / 2 second switching transistors Ts2. In this case, during the interval of outputting the first segmentation signal, each of the n / 2 data routing DLs transmits each of the n / 2 bits of the first segmentation signal output from the n / 2 first switching transistors Ts1, and during the interval of outputting the second segmentation signal, each of the n / 2 data routing DLs can transmit each of the n / 2 bits of the second segmentation signal output from the n / 2 second switching transistors Ts2.

[0069] The gate electrode of the first driving transistor Td1 can be connected to the first output terminal of the counter CNT corresponding to the bit that outputs the first segmentation signal. The drain electrode of the first driving transistor Td1 can be connected to the first switching transistor Ts1, and the source electrode of the first driving transistor Td1 can be connected to ground voltage (or a low-level voltage). Furthermore, the gate electrode of the first switching transistor Ts1 can receive the first scan signal Φrow_A, its source electrode can be connected to the corresponding first driving transistor Td1, and its drain electrode can be connected to the corresponding data routing DL.

[0070] Furthermore, the gate electrode of the second driving transistor Td2 can be connected to the second output terminal of the counter CNT corresponding to the bit that outputs the second segmentation signal, the drain electrode of the second driving transistor Td2 can be connected to the second switching transistor Ts2, and the source electrode of the second driving transistor Td2 can be connected to ground voltage (or a low potential voltage). Additionally, the gate electrode of the second switching transistor Ts2 can receive the second scan signal Φrow_B, the source electrode can be connected to the corresponding second driving transistor Td2, and the drain electrode can be connected to the corresponding data routing DL.

[0071] As described above, during the application of the first scan signal Φrow_A at the on level, the first switching transistor Ts1 can be turned on, and an n / 2-bit first segmentation signal can be output to n / 2 data routes DL. Subsequently, during the application of the second scan signal Φrow_B at the on level, the second switching transistor Ts2 can be turned on, and an n / 2-bit second segmentation signal can be output to n / 2 data routes DL.

[0072] Thus, during the reading interval, an n-bit data signal in digital form can be segmented and output in the pixel P located on each row line.

[0073] In this way, by segmenting and outputting the data signal, the number of data cables connected to each column line can be reduced to the number of bits of the segmented signal, thereby reducing the area occupied by the data cables.

[0074] Please refer to the following: Figure 5 The operation of pixel P in the accumulation interval and the reading interval is explained. Figure 5 This is a timing diagram illustrating the signals of the operating pixels according to an embodiment of the present invention.

[0075] Reference Figures 2 to 4 and Figure 5 Before the accumulation interval Tint begins, a reset signal Φrst can be applied to the counter CNT to reset the counter CNT.

[0076] Subsequently, an enable signal EN can be applied to activate the single-photon avalanche diode SPAD, thereby initiating the accumulation interval Tint. During the accumulation interval Tint, if a photon is incident on the single-photon avalanche diode SPAD by X-ray irradiation, an electrical signal is generated and input to the diode driver circuit PDC.

[0077] The diode driver circuit PDC can delay the output signal PS in the form of a pulse in response to the input electrical signal and output it. It can also generate a recharge signal Φar based on the output signal PS.

[0078] The output signal PS can be input to the first control circuit CC1 of the pixel control circuit PCC, thereby outputting the clock signal Φclk.

[0079] The clock signal Φclk can be input to the counter CC of the counter circuit COC for counting. This counting can continue until the maximum value of the bit set in the accumulation interval Tint is reached. If the counted value in the accumulation interval Tint is the maximum value, the counting operation can be stopped.

[0080] During the read interval Trd following the end of the accumulation interval Tint, the digital data signal stored in the counter CNT can be output via data routing DL. Relatedly, for example, during the output time of the first scan signal Φrow_A, a first segmented signal as an n / 2-bit data signal can be output, and then during the output time of the second scan signal Φrow_B, a second segmented signal as the remaining n / 2-bit data signal can be output.

[0081] After the reading interval Trd ends as described above, apply the reset signal Φclk again to reset the counter CNT, and then the above operation can be repeated.

[0082] As described above, in this embodiment, the electrical signal detected by the single-photon avalanche diode SPAD can be converted into a pulse-shaped output signal PS, and the output signal PS can be counted using a digital counter CNT, thereby directly generating and reading digital data signals in pixel P.

[0083] Because this digital data signal is essentially unaffected by noise, noise generation is virtually eliminated during the digital data signal reading process, thereby maximizing image quality. Furthermore, by using an n-bit digital counter, it is possible to achieve images with a wide dynamic range and high resolution that are difficult to achieve with analog counters.

[0084] The above-described embodiments of the present invention are examples of the invention, and free modifications are possible within the scope of the spirit of the invention. Therefore, the present invention includes the appended claims and modifications of the invention within the same scope.

Claims

1. An X-ray detector, comprising: A pixel array panel, comprising multiple pixels; A single-photon avalanche diode is arranged within the pixel; A diode driving circuit is arranged within the pixel and includes a pulse generation circuit that converts the electrical signal output from the output terminal of the single-photon avalanche diode into a pulse-shaped output signal. A pixel control circuit is arranged within the pixel and includes a first control circuit that outputs the output signal as a clock signal. as well as A counter circuit is arranged within the pixel and includes an n-bit counter (n is an integer greater than 2) that counts the clock signal.

2. The X-ray detector according to claim 1, wherein, The diode driving circuit includes: A recharge transistor is connected to the output terminal of the single-photon avalanche diode; A recharge control circuit has a first input terminal connected to the output terminal of the pulse generation circuit, a second input terminal receiving an enable control signal, and an output terminal connected to the gate electrode of the recharge transistor; and The transistor has an enabling control signal at its gate, a source electrode connected to the output of the single-photon avalanche diode, and a drain electrode receiving an inactive voltage.

3. The X-ray detector according to claim 2, wherein, The bias voltage applied to the cathode of the single-photon avalanche diode is the sum of the breakdown voltage and the access voltage. The inactive voltage is greater than the access voltage.

4. The X-ray detector according to claim 1 or 2, wherein, The pixel control circuit includes: The second control circuit receives an enable signal and an output control signal from the counter, and outputs the enable control signal. The enable signal determines the accumulation interval. The output control signal becomes cutoff when the counter's count value reaches the maximum value of the n-bit.

5. The X-ray detector according to claim 1 or 2, wherein, The counter circuit includes: The output circuit outputs the n-bit data signal stored in the counter to the data wiring. The counter divides the n bits of the data signal into k bits (k is an integer greater than 2 and less than n) to output the first segmented signal to the kth segmented signal of n / k bits.

6. The X-ray detector according to claim 5, wherein, The output circuit includes n / k first driving transistors to the kth driving transistor, and n / k first switching transistors and the kth switching transistor, respectively, corresponding to the first segmentation signal to the kth segmentation signal. In this configuration, each of the first to the kth driving transistors connects its gate electrode to the corresponding output terminal of the counter and its drain electrode to the first to the kth switching transistors. Each of the first to the kth switching transistors receives the first to the kth scan signals at its gate electrode and connects its drain electrode to the corresponding data wiring. The data wiring transmits the corresponding bits of the segmented signal output from the switching transistor connected thereto.

7. The X-ray detector according to claim 1, wherein, The counter receives a bit adjustment signal that adjusts the number of the n bits.

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