Package-on-package device including redistributed die

Abstract

In one embodiment, a device includes: a bottom substrate including a first conductor; a top substrate including a second conductor; and a first die disposed between the bottom substrate and the top substrate. The first die includes a circuit and a first contact electrically connected to the circuit and the first conductor. The device also includes a redistribution die disposed between the bottom substrate and the top substrate adjacent to the first die. The redistribution die includes a second contact electrically connected to the first contact through the first conductor and a third contact electrically connected to the second conductor. The redistribution die also includes a redistribution trace electrically connected to the second contact and the third contact. The top substrate includes a fourth contact electrically connected to the third contact through a second conductor to define one or more signal paths between the fourth contact and the first die.

Description

Cross-reference to related applications

[0001] This application claims the benefit of priority to jointly owned U.S. non-provisional patent application No. 18 / 455,928, filed on August 25, 2023, the entire contents of which are expressly incorporated herein by reference. Technical Field

[0002] Various features are involved in integrated circuit devices. Background Technology

[0003] Electrical connections exist at every level of a system hierarchy. This hierarchy includes the interconnections of active devices at the lowest system level, all the way up to the system-level interconnections at the highest level. For example, interconnect layers connect different devices on an integrated circuit. As integrated circuits become more complex, more interconnect layers are used to provide electrical connections between devices. Recently, due to the sheer number of interconnected devices in modern electronics, the number of interconnect layers in a circuit has substantially increased. The increasing number of interconnect layers to support the growing number of devices involves more complex processes.

[0004] Existing mobile application devices require small form factor, low cost, tight power budgets, and high electrical performance. Mobile package designs have evolved to meet these diverse goals to enable multimedia-enhanced mobile applications. However, these mobile applications are susceptible to power and signal routing issues when multiple dies are arranged within a small form factor. The design and fabrication of devices for mobile applications are challenging due to the conflicting design goals. For example, as the performance of integrated circuits improves, the data input and output (I / O) rates of such integrated circuits also increase. One way to increase the I / O rate of an integrated circuit package is to provide more I / O connections; however, increasing I / O connections tends to increase the package size of the integrated circuit. Summary of the Invention

[0005] Various features are involved in integrated circuit (IC) devices.

[0006] One example provides an integrated device comprising: a bottom substrate including a first conductor; and a top substrate including a second conductor. The integrated device further includes a first die disposed between the bottom substrate and the top substrate. The first die includes circuitry and first contacts electrically connected to the circuitry and the first conductor. The integrated device also includes a redistributed die disposed between the bottom substrate and the top substrate adjacent to the first die. The redistributed die includes a second contact electrically connected to the first contact via the first conductor and a third contact electrically connected to the second conductor. The redistributed die also includes redistribution traces electrically connected to the second and third contacts. The top substrate includes a fourth contact electrically connected to the third contact via the second conductor to define one or more signal paths between the fourth contact and the first die.

[0007] Another example provides a device comprising: a bottom substrate including a first conductor; and a top substrate including a second conductor. The device further includes a first die disposed between the bottom and top substrates. The first die includes circuitry and first contacts electrically connected to the circuitry and the first conductor. The device includes a redistributed die disposed between the bottom and top substrates. The redistributed die includes a second contact electrically connected to the first contact via the first conductor and a third contact electrically connected to the second conductor. The redistributed die includes redistribution traces electrically connected to the second and third contacts. The device includes a second die with a fourth contact electrically connected to the top substrate, wherein the fourth contact is electrically connected to the third contact via the second conductor to define one or more signal paths between the first and second dies.

[0008] Another example provides a method of manufacturing an integrated device, the method including coupling a first die to a bottom substrate. Coupling the first die to the bottom substrate includes electrically connecting a first contact of the first die to a first conductor of the bottom substrate. The method also includes coupling a redistributed die to a bottom substrate adjacent to the first die. Coupling the redistributed die to the bottom substrate includes electrically connecting a second contact of the redistributed die to the first contact via the first conductor, and electrically connecting a third contact of the redistributed die to a second conductor of a top substrate to define one or more signal paths between the first die and a first subset of fourth contacts of the top substrate. Attached Figure Description

[0009] The various features, essence, and advantages will become apparent when the detailed description set forth below is understood in conjunction with the accompanying drawings, in which similar reference characters are correspondingly identified throughout.

[0010] Figure 1A A schematic top view of the bottom substrate of an exemplary device including one or more redistributed dies is shown.

[0011] Figure 1B Examples Figure 1A A schematic cross-sectional profile of an exemplary device.

[0012] Figure 2A A schematic top view of the bottom substrate of another exemplary device including a redistributed die is shown.

[0013] Figure 2B Examples Figure 2A A schematic top view of an exemplary device, wherein the top substrate is omitted.

[0014] Figure 3A A schematic top view of the bottom substrate of an exemplary device including one or more redistributed dies is shown.

[0015] Figure 3B Examples Figure 3A A schematic cross-sectional profile of an exemplary device.

[0016] Figure 4A and Figure 4B A first exemplary step is illustrated for manufacturing a device comprising one or more redistributed dies.

[0017] Figure 5 A second exemplary process for manufacturing a device comprising one or more redistributed dies is illustrated.

[0018] Figure 6 An exemplary flowchart illustrating a method for manufacturing a device comprising one or more redistributed dies is shown.

[0019] Figure 7 Examples of various electronic devices that can integrate devices including one or more redistributed dies as described herein are illustrated. Detailed Implementation

[0020] In the following description, specific details are set forth to provide a thorough understanding of the various aspects of this disclosure. However, those skilled in the art will understand that these aspects can be practiced without these specific details. For example, circuits may be shown as block diagrams to avoid complicating these aspects with unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail to avoid complicating these aspects of this disclosure.

[0021] Specific aspects of this disclosure are described below with reference to the accompanying drawings. In this description, common features are designated by common reference numerals. As used herein, various terms are used only for the purpose of describing particular embodiments and are not intended to limit the scope of the embodiments. For example, the singular forms “a,” “an,” and “the” are intended to also include the plural forms unless the context clearly indicates otherwise. Furthermore, some features described herein are singular in some embodiments and plural in others. For ease of reference herein, such features are generally introduced as “one or more” features and are subsequently referred to in the singular or optional plural form (as indicated by “(multiple)”), unless the aspect relating to multiples of features is being described.

[0022] In some figures, multiple instances of a particular type of feature are used. Although these features are physically and / or logically different, the same reference numerals are used for each feature, and these different instances are distinguished by adding letters to the reference numerals. When a feature is referred to herein as a group or a type (e.g., when a specific feature among these features is not referenced), reference numerals are used without distinguishing letters. However, when a specific feature among multiple features of the same type is referred to herein, reference numerals are used with distinguishing letters. For example, referring to Figure 1, multiple redistributed shards are illustrated and associated with reference numerals 108A and 108B. When referring to a specific redistributed shard among these redistributed shards (such as redistributed shard 108A), the distinguishing letter "A" is used. However, when referring to any arbitrary redistributed shard among these redistributed shards or referring to these redistributed shards as a group, reference numeral 108 is used without distinguishing letters.

[0023] As used herein, the term "comprise" may be used interchangeably with "include". As used herein, "exemplary" indicates an example, specific implementation, and / or aspect, and should not be construed as limiting or indicating a preference or preferred specific implementation. As used herein, ordinal numbers (e.g., "first", "second", "third", etc.) used to modify elements such as structures, components, operations, etc., do not themselves indicate any priority or order of that element relative to another element, but merely distinguish that element from another element with the same name (but using an ordinal number). As used herein, the term "group" refers to one or more elements within a specific set of elements, and the term "multiple" refers to multiple (e.g., two or more) elements within a specific set of elements.

[0024] As used herein, the term "layer" includes films and is not construed as indicating vertical or horizontal thickness unless otherwise stated. As used herein, the term "chiplet" can refer to a block of integrated circuits, a block of functional circuitry, or other similar circuitry specifically designed to work with one or more other chiplets to form a larger, more complex chiplet architecture.

[0025] Improvements in manufacturing technology and the demand for lower-cost and more capable electronic devices have led to increased complexity in ICs. Typically, more complex ICs have more complex interconnect schemes to enable interaction between ICs within a device. Due to the sheer number of interconnected devices in today's state-of-the-art mobile applications, the number of interconnect layers in the circuitry has also increased substantially.

[0026] These interconnects include back-end process (BEOL) interconnect layers, which can refer to conductive interconnect layers used for electrical coupling to front-end process (FEOL) active devices of the IC. Various BEOL interconnect layers are formed at corresponding BEOL interconnect levels, where lower BEOL interconnect levels typically use a thinner metal layer than upper BEOL interconnect levels. BEOL interconnect layers can be electrically coupled to middle-end process (MOL) interconnect layers, which interconnect to the IC's FEOL active devices.

[0027] Technological advancements and increasing demands, along with other factors, are driving improvements in integrated circuit performance. This performance improvement is typically accompanied by an increase in the number of I / O connections in newer integrated circuits. For example, the anticipated shift in dual data rate (DDR) memory technology from DDR5 to DDR6 foreshadowed a 25% increase in the number of I / O connections. Simultaneously, the demand for smaller IC packages is also increasing. This conflict between the need for smaller IC packages and the increased number of I / O connections presents challenges for IC package design and manufacturing.

[0028] The aspects disclosed herein relate to improvements in IC packaging to increase I / O connectivity density (the number of I / O connections per package area) relative to conventional PoP (PoP) devices. In a PoP device, two substrates are stacked. Each substrate is attached to at least one die, and signaling (e.g., I / O) between the die on the bottom substrate and the die on the top substrate is routed via a set of interconnect conductors electrically connected to the two substrates. The bottom substrate of a PoP device typically includes at least three distinct regions: a die attachment region comprising pads for connection to a flip-chip die; an interconnect region containing interconnect conductors for routing signals between the substrates; and a fan-out routing region between the die attachment region and the interconnect region.

[0029] The size of the die attachment area is typically controlled by the specific die used in a PoP device. The size of the interconnect area is related to the number and spacing of the interconnect conductors. Conventional PoP devices typically use solder balls as interconnect conductors, and the number of such solder balls that can be placed in the interconnect area of ​​the bottom substrate is limited by the diameter of the solder balls and the desired spacing between them. The diameter of the solder balls is sufficient to provide the target separation distance between the top and bottom substrates (e.g., based on the thickness of the die or other devices disposed between the substrates). Due to these limitations, the surface area of ​​the bottom substrate required to position a specific number of interconnect conductors in the interconnect area is limited.

[0030] The size of the fan-out routing region is limited by the number of traces that need to be routed, the size and spacing of such traces, and to some extent by the amount of untangling between the traces required to electrically connect the pads and interconnect conductors of the die. The aspects disclosed herein enable a reduction in the size of the fan-out region by moving many of the fan-out routes from the bottom substrate to a redistributed die.

[0031] A redistributed die is a component, such as a die, that facilitates electrical connections or signal transmission between other components, such as other dies. For example, a redistributed die facilitates an electrical connection between one component and another component, where the components have contacts or pads with different pitches and / or orientations and / or sizes. A redistributed die provides contacts that mate with each component to facilitate electrical connections without modifying the electrical characteristics of the signals transmitted between them. A redistributed die includes passive interconnects (referred to herein as “redistributed traces”) that define conductive paths between pairs of outward-facing contacts of the redistributed die, such that each pair of outward-facing contacts is configured to enable signal routing between two other components electrically connected to the redistributed die.

[0032] In one implementation, the primary function of the redistributed die is to facilitate electrical connections. In another implementation, the redistributed die may perform other die functions besides redistribution.

[0033] Redistributed dies can be fabricated using semiconductor manufacturing techniques, which enable the formation of denser packaged traces compared to those fabricated using substrate-based fabrication techniques. By using narrower, more closely spaced traces, redistributed dies can perform fan-out routing in a smaller area than is required to provide similar fan-out routing in the underlying substrate. Therefore, redistributed dies can increase I / O routing without correspondingly increasing the fan-out routing area. In some cases, redistributed dies can significantly reduce the fan-out routing area, allowing additional interconnect conductors to be added without correspondingly increasing the package size. For example, it is anticipated that using redistributed dies will enable the fabrication of DDR6-based PoP devices with the same or smaller form factor as conventionally used in DDR5-based PoP devices using substrate-based fan-out connections.

[0034] In some specific embodiments disclosed herein, the redistributed die includes fan-out routing connections and vias (e.g., through-silicon vias). Vias can replace some or all of the conventional interconnect conductors (e.g., solder balls) used for electrically connecting the top and bottom substrates. In such embodiments, the fan-out routing area is reduced (relative to substrate-based fan-out connections) and the interconnect area is reduced (relative to conventional solder ball-based interconnects), resulting in even smaller PoP packages. Furthermore, in such embodiments, the vias are integrated within the die and are therefore not subject to the same spacing constraints as solder balls used for substrate interconnects. For example, the redistributed die can be fabricated to provide any desired spacing height between substrates, and the spacing height does not limit the spacing of the vias. In contrast, when using solder balls, increasing the spacing height increases the diameter of the solder balls, thereby reducing the number of solder balls that can be placed side-by-side in a given area. As another example, semiconductor fabrication techniques can be used to form the vias of the redistributed die, enabling the formation of features for much smaller and more compact packages. Therefore, vias can be packaged smaller and more densely than solder balls.

[0035] In addition to more efficient use of the PoP substrate area, using redistributed dies instead of substrate-based fan-out connections provides a shorter signal path between the dies on the top and bottom substrates. Shorter signal paths improve communication speed between dies. Furthermore, long, thin traces used in conventional laminated substrates for fan-out routing can suffer from poor signal integrity and are typically associated with lower manufacturing yields. Using the redistributed dies disclosed herein enables the use of shorter traces in the substrate, which improves both substrate yield and signal integrity.

[0036] Therefore, the various specific embodiments disclosed herein offer technical advantages over conventional PoP packaging technology, including at least more efficient use of package area, enabling increased I / O connectivity (e.g., between dies in packages of the same or smaller size), reduced package size, or both. Additional technical advantages include improved I / O connectivity speed and signal integrity due to shorter signal paths, and improved laminate yield.

[0037] Exemplary devices including redistributed dies

[0038] Figure 1A A schematic top view illustrating various aspects of an exemplary device 100 including one or more redistributed dies 108 (including redistributed die 108A and redistributed die 108B). Specifically, Figure 1A A top view of the bottom substrate 102 of the device 100 is shown, and dashed lines are used to indicate the positions of the die 104, the redistribution die 108, and the redistribution trace 120 of the redistribution die 108 relative to the bottom substrate 102. Figure 1B Examples Figure 1A A schematic cross-sectional profile of an exemplary device 100.

[0039] Device 100 has a stacked package (PoP) configuration in which die 104 is disposed between a bottom substrate 102 and a top substrate 142. Device 100 optionally includes a die 144 coupled to the top substrate 142, illustrated in dashed lines to indicate that die 144 is optional and / or interchangeable in some specific implementations. The PoP configuration is configured to implement signaling between dies 104, 144, signaling between one or more dies 104, 144 and one or more external devices (e.g., via external contacts 130, such as a ball grid array), or both. Although two dies 104, 144 are illustrated, device 100 may include more than two dies and may optionally include other devices (not shown), such as passive devices.

[0040] Each of dies 104 and 144 may include an integrated circuit, such as multiple transistors and / or other circuit elements. Components of the integrated circuit may be formed in and / or on the semiconductor substrate. Different implementations may use different types of transistors to form active circuitry, such as field-effect transistors (FETs), planar FETs, finned FETs, gate-all-around FETs, or a mixture of various transistor types. Active circuitry may be arranged and interconnected to form processing logic blocks (e.g., transistor blocks), memory blocks, etc. In addition to active circuitry, the integrated circuit may also include a power distribution network (PDN). For example, a PDN may include, for instance, one or more power rails, one or more ground rails, etc. In some implementations, the integrated circuit may be fabricated in and / or on the semiconductor substrate using a front-end process (FEOL) technology.

[0041] Die 104 is illustrated with a flip-chip configuration including a set of contacts 110 electrically connected to an integrated circuit of die 104 and configured to couple to corresponding contacts 112 of a bottom substrate 102. The bottom substrate 102 includes conductors 114A electrically connected to corresponding contacts in the contacts 112 and to contacts 116 of the bottom substrate 102. Contacts 116 are configured to electrically connect to corresponding contacts 118 of a redistributed die 108.

[0042] The redistribution die 108 includes redistribution traces 120 electrically connected to contacts 118 and 124 of the redistribution die 108. The redistribution traces 120 are configured to untangle electrical connections from individual contacts in the contacts 110 of the die 104 to appropriate interconnect conductors 106. For example, the redistribution traces 120 may be arranged in two or more layers of the redistribution die 108 such that two or more of the redistribution traces 120 can jump above / below each other to route between pairs of contacts 110 and interconnect conductors 106. The redistribution die 108 may include a semiconductor die in which the redistribution traces 120 are integrated using semiconductor fabrication techniques such as wafer-level patterning and deposition. Therefore, the redistribution traces 120 can be finer (e.g., narrower) and more closely spaced than conductors 114 (which are formed, for example, using lamination techniques). The finer, more closely spaced lines of the redistribution trace 120 enable the redistribution trace 120 to untangle the electrical connection between the contact 110 and the interconnect conductor 106 in a smaller fan-out routing area 152 than is required to perform the same untangling using the conductor 114 of the substrate 102.

[0043] The contacts 124 of the redistributed die 108 are configured to be electrically connected to corresponding contacts 122 of the bottom substrate 102. Contacts 122 are electrically connected to conductors of the bottom substrate 102, such as conductor 114B. Conductor 114B is electrically connected to interconnect conductor 106.

[0044] Interconnect conductor 106 is electrically connected to conductor 148 of top substrate 142. Conductor 148 of top substrate 142 is electrically connected to contact 146 of top substrate 142. Contact 146 is configured to be electrically connected to contact of die 144.

[0045] exist Figure 1A and Figure 1B In the illustrated example, device 100 includes two redistributed dies 108A and 108B and two sets of interconnect conductors 106A and 106B. In this example, redistributed dies 108A and 108B are disposed in corresponding fan-out routing regions 152A and 152B. Interconnect conductors 106A and 106B are disposed in corresponding interconnect regions 154A and 154B, and die 104 is disposed in die attachment region 150. Therefore, the overall lateral dimension of the bottom substrate 102 is constrained by the dimensions of interconnect region 154, fan-out routing region 152, and die attachment region 150. The fan-out routing region 152 associated with the redistributed dies 108 is smaller than the fan-out routing region required to route the same signal path through the bottom substrate 102 (e.g., in...). Figure 1B (Shorter in lateral dimension as illustrated in the example). Therefore, interconnect region 154 can be enlarged to accommodate more interconnect conductors 106 without increasing the overall lateral dimension of bottom substrate 102. In some specific embodiments, the overall lateral dimension of bottom substrate 102 can even be reduced relative to the specific embodiment in which the same signal paths are routed through bottom substrate 102.

[0046] like Figure 1B As illustrated, device 100 may optionally include a molding compound 140 disposed between a bottom substrate 102 and a top substrate 142. For example, the molding compound 140 may at least partially encapsulate die 104, redistributed die 108, interconnect conductor 106, or a combination thereof. For example, interconnect conductor 106 may include through-holes or solder balls disposed within the molding compound 140.

[0047] Figure 2A and Figure 2B Aspects of another exemplary device 200 including redistributed dies 208 (including redistributed dies 208A, 208B, 208C, and 208D) are illustrated. Specifically, Figure 2A A schematic top view of the bottom substrate 102 of device 200 is shown, and Figure 2B An example is shown where the top substrate is omitted (e.g., Figure 1B A schematic top view of device 200 on top substrate 142. A cross-sectional side view of device 200. Figure 1B The views shown are the same as those in the examples, so they will not be repeated.

[0048] Figure 2A and Figure 2B Device 200 and Figure 1A and Figure 1B The device 100 is identical to the device 200, except that, in the case of device 200, a plurality of redistributed dies 208 are located on each side of die 104 to provide fan-out routing and untangling for signal paths between contacts 112 and interconnect conductors 106 of die 104. In some specific embodiments, each redistributed die 208 is similar to die 104 and die 144. Figure 1B Different communication channels are associated between (as illustrated in the example). For example, die 144 may include or correspond to a quad-channel DDR memory chip, in which case, Figure 2A and Figure 2B Each of the four redistributed dies 208 can be configured to route a signal associated with a corresponding one of the four channels.

[0049] The advantage of using multiple redistributed dies 208 on each side of die 104, instead of a single redistributed die 108 on each side, is that the redistributed dies 208 are smaller than the redistributed die 108, and the manufacture of smaller dies is generally associated with higher throughput and therefore lower cost. Additionally, using multiple redistributed dies 208 increases design flexibility. For example, if the design of device 200 changes, fewer than all of the redistributed dies 208 can be updated. Furthermore, one or more of the redistributed dies 208 can be used on several different product lines (e.g., different types of device 200), further reducing costs.

[0050] Figure 3A A schematic top view illustrating aspects of another exemplary device 300 including one or more redistributed dies 308 (including redistributed die 308A and redistributed die 308B) is shown. Specifically, Figure 3A A top view of the bottom substrate 302 of the device 300 is shown, and dashed lines are used to indicate the positions of the die 104 and the redistribution die 308 relative to the bottom substrate 302. Figure 3B Examples Figure 3A A schematic cross-sectional profile view of an exemplary device 300. Device 300 is similar to... Figure 1A and Figure 1B Device 100 or Figure 2A and Figure 2B Device 200, except that the interconnect conductor 306 of device 300 is integrated within the redistributed die 308.

[0051] Similar to devices 100 and 200, device 300 has a PoP configuration, wherein die 104 is disposed between a bottom substrate 302 and a top substrate 342. Device 300 may optionally include die 144 coupled to the top substrate 342. Although two dies 104, 144 are illustrated, device 300 may include more than two dies and may optionally include other devices (not shown), such as passive devices.

[0052] exist Figure 3A and Figure 3B In this configuration, contacts 110 of die 104 are electrically connected to the integrated circuit of die 104 and are configured to couple to corresponding contacts 112 of bottom substrate 302. Bottom substrate 302 includes conductors 314 electrically connected to corresponding contacts in contacts 112 and to corresponding contacts in contacts 316 of bottom substrate 302. Contacts 316 are configured to electrically connect to corresponding contacts 318 of redistributed die 308.

[0053] The redistribution die 308 includes a redistribution trace 320 electrically connected to a contact 318 and electrically connected to an interconnect conductor 306 integrated within the redistribution die 308. For example, the redistribution die 308 may include a semiconductor die in which the redistribution trace 320 and the interconnect conductor 306 are integrated using semiconductor fabrication techniques such as wafer-level patterning and deposition. For illustration, the interconnect conductor 306 may include or correspond to a through-silicon via formed in the redistribution die 308. The interconnect conductor 306 is coupled to a conductor 348 of a top substrate 342 via a contact 322.

[0054] For reference Figure 1A and Figure 1B As described, the redistribution traces 320 can be finer (e.g., narrower) and more closely spaced than conductors 314 (which are formed, for example, using lamination techniques). Furthermore, interconnect conductors 306 can be finer and more closely spaced than conventional interconnect conductors (such as solder balls or through-holes). Additionally, interconnect conductors 306 and redistribution traces 320 can be vertically aligned (in... Figure 3B (Stacked in the direction illustrated in the diagram). Therefore, device 300 exhibits a reference... Figure 1A and Figure 1B Each technique described has beneficial effects and has the ability to eliminate or reduce Figure 1B The interconnect region 154 has additional technical advantages. Therefore, the overall lateral dimensions of the bottom substrate 302 are constrained by the dimensions of the die attachment region 350 and the fan-out routing regions 352A and 352B. The fan-out routing region 352 associated with the redistributed die 308 is smaller than the fan-out routing region required to route the same signal path across the bottom substrate 302 (e.g., in...). Figure 3B(Shorter in lateral dimension as illustrated in the example). Additionally, the interconnection area required to accommodate conventional interconnect conductors (e.g., interconnect conductor 106) is eliminated. Figure 1B The interconnect region 154 reduces the overall lateral dimension of the bottom substrate 302.

[0055] Although Figure 3A and Figure 3B The example illustrated shows all interconnect conductors of interconnect conductors 306 integrated within redistributed die 308; however, in other specific embodiments, fewer than all interconnect conductors of interconnect conductors 306 are integrated within redistributed die 308. For example, signals transmitted between dies 104 and 144 can be routed through redistributed die 308, and device 300 may include conventional interconnect conductors (e.g., interconnect conductor 106) configured to route signals between die 144 and an external device via contact 330. Again, a first subset of signals transmitted between dies 104 and 144 can be routed through redistributed die 308, and a second subset of signals transmitted between dies 104 and 144 can be routed through conventional interconnect conductors (e.g., interconnect conductor 106).

[0056] exist Figure 3A and Figure 3B In the illustrated example, device 300 is shown having two redistributed dies 308A and 308B. However, in other specific embodiments, any one or both of the redistributed dies 308A and 308B may be replaced by two or more smaller redistributed dies, as referenced. Figure 2A and Figure 2B As described.

[0057] Figures 1A to 3B The figures illustrated herein are merely schematic and are intended to highlight specific features of the various devices illustrated. For example, the specific numbers of contacts, interconnects, and other components are illustrative and not limiting. Furthermore, certain internal structures are omitted from the figures. For instance, bottom substrate 102 or bottom substrate 302 may include additional conductors configured to electrically connect die 104, die 144, or both, to devices outside the package via contacts 130, 330, respectively. Additionally, certain components are illustrated in a particular manner only to illustrate specific aspects. For example, the connection between contacts 118, 124 of the redistributed die 108 and corresponding contacts 116, 122 of the bottom substrate is illustrated as being formed using solder bumps, solely to highlight where the individual components of the electrical connection are located. In other embodiments, other interconnect technologies, such as pad-to-pad bonding, are used to electrically connect the various contacts.

[0058] Although Figures 1A to 3BAn example is illustrated that includes a device for connecting two dies; however, in other examples, the device may include more than two dies. Furthermore, Figures 1A to 3B Devices 100, 200, and 300 can be integrated with or included within a wide variety of other devices. For example, devices including one or more of the devices 100, 200, and 300 disclosed herein may include components such as: power management integrated circuits (PMICs), application processors, modems, radio frequency (RF) devices, passive devices, filters, capacitors, inductors, transmitters, receivers, gallium arsenide (GaAs)-based integrated devices, surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, light-emitting diode (LED) integrated devices, silicon (Si)-based integrated devices, silicon carbide (SiC)-based integrated devices, memories, power management processors, and / or combinations thereof. In such devices, the devices disclosed herein can operate as any (or a combination of) these components that include active circuitry.

[0059] Exemplary steps for manufacturing devices including redistributed dies

[0060] In some implementations, manufacturing a device that includes one or more redistributed dies (e.g., any of device 100, 200, or 300) involves several processes. Figure 4A and Figure 4B Examples are illustrated for providing or manufacturing devices comprising one or more redistributed dies (e.g., in...). Figure 4B The first exemplary process of the device 490 illustrated in stage 8, as shown in reference . Figures 1A to 3B As described by any of them. In some specific implementations, Figure 4A and Figure 4B The process can be used to provide (e.g., during manufacturing). Figures 1A to 3B One or more of the devices 100, 200 or 300.

[0061] It should be noted that Figure 4A and Figure 4B The processes can be combined into one or more stages to simplify and / or clarify the processes used to provide or manufacture integrated devices. In some embodiments, the order of the processes can be changed or modified. In some embodiments, one or more processes can be substituted or replaced without departing from the scope of this disclosure. In the following description, reference is made to various exemplary stages of the processes, which are illustrated in... Figure 4A and Figure 4B The numbers are numbered using circled numbers. Figure 4A and Figure 4BEach stage of the process illustrated shows a device being formed; however, in some specific implementations, multiple devices may be formed concurrently, for example using wafer-level or strip-level processing techniques.

[0062] Figure 4A Phase 1 illustrates the state after the bare die 402 and one or more redistributed dies 406 (e.g., redistributed dies 406A and 406B) have been coupled to the carrier 404. Figure 4A In the example illustrated, die 402 includes an active region 410, which includes integrated circuits and contacts (e.g., Figure 1B or Figure 3B (Contact 110). In this example, the active region 410 is configured to be adjacent to the carrier 404.

[0063] Figure 4A and Figure 4B The redistribution die 406 is illustrated as including redistribution traces 408 (e.g., redistribution trace 408A of redistribution die 406A and redistribution trace 408B of redistribution die 406B) located on the side adjacent to the carrier 404, redistribution traces 414 (e.g., redistribution trace 414A of redistribution die 406A and redistribution trace 414B of redistribution die 406B) located on the side opposite to the carrier 404, and interconnect conductors 412 (e.g., interconnect conductor 412A of redistribution die 406A and interconnect conductor 412B of redistribution die 406B) located between them. Interconnect conductors 412 are optional and are omitted in some cases. For example, when the device being manufactured uses... Figures 1A to 2B When the interconnect conductor 106 routes signals between the top and bottom substrates, the interconnect conductor 412 may be omitted. Additionally or alternatively, in some embodiments, the redistribution die 406 includes redistribution traces only on one side. For example, redistribution trace 408 or redistribution trace 414 may be omitted from the redistribution die 406.

[0064] Phase 2 illustrates the state after the interconnect conductors 420 (e.g., interconnect conductors 420A and 420B) have been formed. Figure 4A In the example illustrated, interconnect conductor 420 is shown as a pillar (e.g., a copper pillar). Interconnect conductor 420 can be formed, for example, using an electroplating technique guided by one or more mask layers (e.g., a patterned dry film or photoresist layer). Although Figure 4A Interconnect conductor 420 is illustrated as a post, but in other examples, interconnect conductor 420 may include or correspond to solder balls or plated copper balls. In such embodiments, automated placement techniques can be used to position interconnect conductor 420.

[0065] In some specific implementations, the formation of interconnect conductor 420 may be omitted. For example, if the redistribution die 406 includes interconnect conductor 412 and the interconnect conductor 412 is sufficient to support all electrical connections required for the electrical connection between the top substrate and the bottom substrate, then interconnect conductor 420 is not required and may be omitted.

[0066] The state illustrated in Phase 2 also shows that contacts 418 (e.g., contacts 418A and 418B) have been formed on the redistribution die 406. The formation of contacts 418 is optional, and can be omitted if the redistribution die 406 does not include electrical connections to the top substrate, which may be the case when the redistribution die 406 does not include interconnect conductors 412 and redistribution traces 414. Figure 4A In the example illustrated, contact 418 can be formed, for example, using an electroplating technique guided by one or more mask layers (e.g., patterned dry film or photoresist layers).

[0067] Phase 3 illustrates the state after the molding compound 422 has been applied to the carrier 404, the die 402, the redistribution die 406, and the interconnect conductor 420 (if present). In a particular example, the molding compound 422 may be applied using a deposition process, a spin coating process, or a similar process, and may subsequently be cured or hardened by exposure to light, heat, and / or chemical hardeners.

[0068] Phase 4 illustrates the state after one or more material removal operations have been performed to expose portions of interconnect conductor 420, contact 418, or both, depending on the specific combination of previously formed interconnect conductor 420 and contact 418. Material removal operations may include, for example, etching operations, polishing operations, or both.

[0069] Figure 4B Stage 5 illustrates the state following the formation or attachment of the top substrate 430. The top substrate 430 includes contacts 432 configured to connect to another die and conductors 434 electrically connected to the contacts 432 and interconnect conductors 420, 418, or both, depending on a specific combination of previously formed interconnect conductors 420 and contacts 418. In some embodiments, the top substrate 430 is pre-shaped and attached to the interconnect conductors 420, contacts 418, or both to achieve the state illustrated in Stage 5. Alternatively, the top substrate 430 may be formed on the surface of the molding compound and the interconnect conductors 420, contacts 418, or both using a redistribution layer forming technique. For example, the redistribution layer forming technique may include, but is not limited to, applying alternating layers of dielectric material (e.g., dry film layer) and patterned metal layers, and forming interconnects between the metal layers.

[0070] Phase 6 illustrates the state after removing carrier 404 and attaching carrier 440 to top substrate 430. Removal of carrier 404 exposes contacts 438 (e.g., contacts 438A and 438B) of redistribution die 406 and contacts 436 of die 402. Contacts 436 of die 402 may correspond to or include... Figures 1A to 3B Contact 110 of either of the bare die 104. In some embodiments, contact 438 corresponds to or includes Figure 1B Contacts 118 and 124. In some embodiments, contact 438 corresponds to or includes... Figure 3B Contact element 318.

[0071] Stage 7 illustrates the state after the formation or attachment of the bottom substrate 450 (its state is reversed relative to that at stage 6). Figure 4B In the example illustrated, the bottom substrate 450 includes contacts 452, 454, 458, 462, 464, 468, and 470, and conductors electrically connecting the respective contacts 452, 454, 458, 462, 464, 468, and 470. In some embodiments, the bottom substrate 450 is pre-formed and attached to interconnect conductors 420, contacts 438, contacts 436, or combinations thereof to achieve the state illustrated at stage 7. Alternatively, a redistribution layer forming technique can be used to form the bottom substrate 450 on the surface of the molding compound 422 and the interconnect conductors 420, contacts 438, contacts 436, or combinations thereof. For example, the redistribution layer forming technique may include, but is not limited to, applying alternating layers of dielectric material (e.g., dry film layer) and patterned metal layers, and forming interconnects between the metal layers.

[0072] Contact 452 corresponds to or includes Figure 1B Contact 130 or Figure 3B Contact 330. Contact 452 is configured to provide connectivity to one or more external devices. For example, one or more contacts in contact 452 may be connected via conductor 472 to one or more interconnect conductors in interconnect conductor 420 to provide a signal path between the die (e.g., the second die 492 illustrated in stage 8) and the external device. For example, one or more contacts in contact 452 may be connected via conductor 456 to one or more contacts in contact 454 to provide a signal path between the die 402 and the external device. In this example, contact 454 corresponds to or includes Figure 1A , Figure 2A or Figure 3A One or more of the contacts 112 of any of them.

[0073] Contact 458 is electrically connected to die 402 and via conductor 460 to contact 462. Each contact in contact 462 is electrically connected to a corresponding contact in contact 438 of the redistributed die 406. For example, conductor 460 may correspond to or include... Figure 1A , Figure 1B or Figure 2B Conductor 114A. In this example, contact 462 corresponds to contact 116. Similarly, conductor 460 may correspond to or include... Figure 3A and Figure 3B Conductor 314. In this example, contact 462 corresponds to contact 316.

[0074] Contact 468 is electrically connected to interconnect conductor 420 and is electrically connected to contact 464 via conductor 466. It should be noted that in some embodiments, interconnect conductor 420 is omitted (e.g., as shown in...). Figure 3A and Figure 3B As shown), in this case, contact 468, conductor 466, and contact 464 are also omitted. If present, each contact in contact 464 is electrically connected to a corresponding contact in contact 438 of the redistributed die 406. For example, conductor 460 may correspond to or include Figure 1A , Figure 1B or Figure 2B Conductor 114B.

[0075] Phase 8 illustrates the state after the removal of carrier 440 (which is the reverse of the state at Phase 7). If the operations described above with reference to Phases 1-7 are performed in a manner that concurrently forms two or more devices (e.g., device 490), the state illustrated at Phase 8 is after the device is split. For example, device 490 can be removed from carrier 440 using one or more layering processes, and device 490 can be separated from each other using one or more dicing operations.

[0076] The formation of device 490 is in Figure 4B Phase 8 is completed. However, in some specific implementations, the second die 492 may be coupled to the top substrate 430 and electrically connected to the interconnect conductor 420, the redistribution die 406, or both, to enable communication between the die 402 and the second die 492 and / or communication between the second die 492 and one or more out-of-package devices via contact 442.

[0077] Figure 5 Examples are illustrated for providing or manufacturing devices comprising one or more redistributed dies (e.g., in...). Figure 5 The second exemplary process of the device 590 illustrated in stage 5, as shown in reference . Figures 1A to 3B As described by any of them. In some specific implementations, Figure 5 The process can be used to provide (e.g., during manufacturing). Figures 1A to 3B One or more of the devices 100, 200 or 300.

[0078] It should be noted that Figure 5 The processes can be combined into one or more stages to simplify and / or clarify the processes used to provide or manufacture integrated devices. In some embodiments, the order of the processes can be changed or modified. In some embodiments, one or more processes can be substituted or replaced without departing from the scope of this disclosure. In the following description, reference is made to various exemplary stages of the processes, which are illustrated in... Figure 5 The numbers are numbered using circled numbers. Figure 5 Each stage of the process illustrated shows a device being formed; however, in some specific implementations, multiple devices may be formed concurrently, for example using wafer-level or strip-level processing techniques.

[0079] Figure 5 process and Figure 4A and Figure 4B The main difference in the process lies in the use of pre-formed substrates and solder balls (e.g., copper core solder balls). Many other features are similar to those in the reference. Figure 4A and Figure 4B The described characteristics are similar or identical, and are assigned to... Figure 4A and Figure 4B The same reference numerals are used (or in some cases are omitted to simplify the figures).

[0080] Figure 5 Stage 1 illustrates the state after the bare die 402 has been placed on the bottom substrate 550. Figure 5 In the example illustrated, die 402 includes an active region 410, which includes integrated circuits and contacts (e.g., Figure 1B or Figure 3B The contact 110 is electrically connected via solder bumps 502 to a corresponding contact (e.g., contact 112) on the bottom substrate 550. The bottom substrate 550 includes, for example, a pre-formed laminated substrate comprising metal layers separated from each other by dielectric layers. The metal layers are patterned and interconnected to define a plurality of conductors. Figure 5The conductors include, for example, one or more conductors 456 configured to electrically connect contacts of the die 402 to corresponding contacts on opposite sides of the bottom substrate 550; one or more conductors 460 configured to electrically connect contacts of the die 402 to corresponding contacts of the redistributed die (e.g., the redistributed die 406 shown at stage 2); one or more conductors 466 configured to electrically connect contacts of the redistributed die to corresponding contacts of the interconnect conductor (e.g., the interconnect conductor 520 shown at stage 3); and one or more conductors 472 configured to electrically connect contacts of the interconnect conductor to corresponding contacts on opposite sides of the bottom substrate 550. In a particular example, conductor 460 corresponds to or includes... Figure 1B Conductor 114A or Figure 3B Conductor 314. In a particular example, conductor 466 corresponds to or includes Figure 1B Conductor 114B.

[0081] Figure 5 Phase 2 illustrates the state after the redistribution dies 406 (e.g., redistribution dies 406A and 406B) have been placed on the bottom substrate 550. The solder bumps 504 of the redistribution dies 406 are reflowed to form electrical connections to corresponding contacts (such as contacts of conductors 460, 466, or both) on the bottom substrate 550. Solder bumps 504 and 502 can be reflowed simultaneously, or solder bump 502 can be reflowed before Phase 2.

[0082] exist Figure 5 In this embodiment, the redistribution die 406 is illustrated as including a redistribution trace 408 on the side adjacent to the bottom substrate 550, a redistribution trace 414 on the side opposite to the bottom substrate 550, and an interconnect conductor 412 between them. (See reference...) Figure 4A As described, the interconnect conductor 412 and the redistribution trace 414 are optional and are omitted in some cases. In specific implementations in which the interconnect conductor 412 and the redistribution trace 414 are omitted, the contact 438 on the top of each redistribution die 406 may also be omitted.

[0083] Phase 3 illustrates the state after the interconnect conductors 520 (e.g., interconnect conductors 520A and 520B) and the top substrate 530 have been placed. Figure 5 In this configuration, interconnect conductor 520 includes or corresponds to solder balls or copper balls plated with solder. Interconnect conductor 520, top substrate 530, or both (e.g., top substrate 530 to which interconnect conductor 520 is attached) can be placed using automated placement techniques (e.g., pick-and-place robots).

[0084] exist Figure 5In this configuration, the top substrate 530 includes a pre-formed laminated substrate comprising metal layers separated from each other by dielectric layers. The metal layers are patterned and interconnected to define contacts 432, contacts 506, and a plurality of conductors 434 therebetween. Contacts 432 are configured to be electrically connected to another die (e.g., the second die 492 illustrated at stage 5). Contacts 506 are configured to be electrically connected to interconnect conductors, which may include interconnect conductors 520, interconnect conductors 412 of the redistributed die 406, or both. The conductors 434 of the top substrate 530 are configured to electrically connect a corresponding contact among contacts 432 and contacts 506. In a particular example, conductors 434 correspond to or include... Figure 1B Conductor 148 or Figure 3B Conductor 348. In some specific implementations, interconnect conductor 520 is omitted. For example, if the redistribution die 406 includes interconnect conductor 412 and interconnect conductor 412 is sufficient to support all electrical connections required between the top substrate (e.g., the top substrate 530 illustrated in stage 3) and the bottom substrate 550, then interconnect conductor 520 is not required and may be omitted.

[0085] If interconnect conductors 520 are present, some of the interconnect conductors in interconnect conductors 520 may be electrically connected to contacts on the redistribution die 406 via conductor 466. Additionally or alternatively, some of the interconnect conductors in interconnect conductors 520 may be electrically connected to contacts on opposite sides of the bottom substrate 550 via conductor 472.

[0086] Phase 4 illustrates the state after the molding compound 422 is applied in the region between the top substrate 530 and the bottom substrate 550. For example, the molding compound 422 can be applied between the top substrate 530 and the bottom substrate 550 using an overmolding operation, and can subsequently be cured or hardened by exposure to light, heat, and / or a chemical hardener.

[0087] Stage 5 illustrates the state after the contact 442 is formed on the bottom of the bottom substrate 550. If the operations described above with reference to stages 1-4 are performed in a manner that concurrently forms two or more devices (e.g., device 590), the state illustrated at stage 5 is after the device is divided. For example, one or more cutting operations may be used to separate device 590 from each other.

[0088] The formation of device 590 is in Figure 5 Phase 5 is completed. However, in some specific implementations, the second die 492 may be coupled to the top substrate 530 and electrically connected to the interconnect conductor 520, the redistribution die 406, or both, to enable communication between the die 402 and the second die 492 and / or communication between the second die 492 and one or more out-of-package devices via contact 442.

[0089] An exemplary flowchart of a method for manufacturing a device including a redistributed die.

[0090] In some implementations, manufacturing a device that includes one or more redistributed dies involves several processes. Figure 6 An exemplary flowchart illustrating a method 600 for providing or manufacturing a device comprising one or more redistributed dies is shown. In some specific embodiments, Figure 6 Method 600 can be used to provide or manufacture Figures 1A to 5 Any of the devices 100, 200, 300, 490 or 590.

[0091] It should be noted that Figure 6 Method 600 may combine one or more processes to simplify and / or clarify the methods for providing or manufacturing devices comprising one or more redistributed dies. In some implementations, the order of the processes may be changed or modified.

[0092] Method 600 includes coupling a first die to a bottom substrate at block 602, wherein coupling the first die to the bottom substrate includes electrically connecting a first contact of the first die to a first conductor of the bottom substrate. For example, the first die may correspond to Figures 1A to 3B The bare die 104 of either of them, and the bottom substrate may correspond to Figures 1A to 3B The bottom substrate 102 of any of them. For example, the first die may correspond to... Figure 4A and Figure 4B The bare die 402, and the bottom substrate can correspond to Figure 4B The bottom substrate is 450. For example, the first die can correspond to... Figure 5 The bare die 402, and the bottom substrate can correspond to Figure 5 The bottom substrate 550. The first contact (e.g., contact 110 of the die 104) can be made via solder (e.g., solder arranged in an array of microbumps) Figure 5 The solder bump 502 is electrically connected to the conductor of the bottom substrate. (Reference) Figure 4B Phase 7 and Figure 5 Phase 1 describes the operation of the contacts that electrically connect the conductors of the bottom substrate and the die.

[0093] Method 600 further includes coupling the redistributed die to a bottom substrate adjacent to the first die at block 604. For example, the redistributed die may correspond to Figure 1A and Figure 1B One of the redistributed bare pieces in the redistributed bare piece 108 Figure 2A and Figure 2B One of the redistributed nuggets in redistributed nuggets 208 Figure 3A and Figure 3BOne of the redistributed bare pieces in redistributed bare piece 308 or Figures 4A to 5 One of the redistributed bare pieces in redistributed bare piece 406. (Reference) Figure 4B Phase 7 and Figure 5 Phase 2 describes the operation of the contacts that couple the bottom substrate and the redistributed die. In a particular aspect, the redistributed die includes a semiconductor die, and a second contact (e.g., Figure 1A Contact 116), third contact (e.g., Figure 1A The contact elements 122) and the redistribution traces between them (e.g., Figure 1A The redistribution trace 120 is integrated within the semiconductor die.

[0094] exist Figure 6 In this configuration, coupling the redistributed die to the bottom substrate includes electrically connecting a second contact of the redistributed die to a first contact via a first conductor at block 606, and electrically connecting a third contact of the redistributed die to a second conductor of the top substrate at block 608 to define one or more signal paths between the first die and a first subset of fourth contacts of the top substrate. For example, as... Figure 4B As illustrated in stage 7, a first contact of the first die may correspond to contact 458, which is coupled to contact 462 (e.g., a second contact of the redistributed die) via conductor 460 of the bottom substrate 450. Furthermore, in this example, a redistributed third contact (e.g., contact 464 or contact 438) is coupled to conductor 434 of the top substrate 430 to define one or more signal paths between at least a subset of the first die (e.g., die 402) and the contacts 432 of the top substrate 430.

[0095] In some implementations, method 600 further includes a fourth contact coupling the second die to the top substrate. For example, the second die may include or correspond to... Figure 1B or Figure 3B Nude film 144, or Figure 4B or Figure 5 Die 492. The first die and the second die are configured to operate in cooperation. For example, in some embodiments, the first die includes first circuitry defining one or more processor cores, and the second die includes second circuitry defining one or more memory cells.

[0096] In some specific implementations, at least some of the interconnect conductors are integrated within the redistributed die. For example, the interconnect conductors integrated within the redistributed die may include or correspond to Figure 3B Interconnecting conductor 306 or Figure 4A , Figure 4B or Figure 5 Interconnecting conductor 412.

[0097] In the same or different embodiments, at least some interconnect conductors are outside the redistributed die and are electrically connected to a third contact of the redistributed die via a first conductor. When at least some of the interconnect conductors are outside the redistributed die, method 600 further includes electrically connecting the interconnect conductors outside the redistributed die to a second conductor on the top substrate, wherein the interconnect conductors are electrically connected to the third contact of the redistributed die. For example, the interconnect conductors outside the redistributed die may include or correspond to Figures 1A to 2B Interconnecting conductor 106 Figure 4A and Figure 4B Interconnecting conductor 420 or Figure 5 Interconnecting conductor 520.

[0098] In some embodiments, method 600 further includes distributing one or more additional redistributed dies on a bottom substrate adjacent to the first die, and electrically connecting the one or more additional redistributed dies between the first die and a second subset of the fourth contacts to define one or more additional signal paths between the first die and the second subset of the fourth contacts on the top substrate. For example, the redistributed dies may include... Figure 1A and Figure 1B The redistributed die 108A may include redistributed die 108B, and one or more additional redistributed dies may include redistributed die 108B. Alternatively, the redistributed die may include... Figure 2A and Figure 2B The redistributed die 208A may include one or more additional redistributed dies, such as redistributed dies 208B, 208C, or 208D. Alternatively, the redistributed die may include... Figure 3A and Figure 3B The redistributed die 308A, and one or more additional redistributed dies may include redistributed die 308B. As another example, the redistributed die may include... Figure 4A , Figure 4B or Figure 5 The redistributed die 406A may include one or more additional redistributed dies, which may include redistributed die 406B.

[0099] Exemplary electronic devices

[0100] Figure 7 Examples include Figures 1A to 5 Device 700 may be any of devices 100, 200, 300, 490, or 590, or various electronic devices integrated with any of these devices. For example, mobile phone device 702, laptop computer device 704, fixed-location terminal device 706, wearable device 708, or vehicle 710 (e.g., automotive or aerial equipment) may include device 700. Device 700 may include, for example, those described herein. Figures 1A to 5Any of the devices 100, 200, 300, 490 or 590. Figure 7 The devices 702, 704, 706, and 708 illustrated herein, as well as vehicle 710, are merely exemplary. Other electronic devices may also feature device 700, including but not limited to groups of devices (e.g., electronic devices) comprising: mobile devices, handheld personal communication system (PCS) units, portable data units such as personal digital assistants, GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading devices), communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0101] Figures 1A to 7 One or more of the components, processes, features, and / or functions illustrated herein may be rearranged and / or combined into a single component, process, feature, or function, or embodied in several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from this disclosure. It should also be noted that Figures 1A to 7 The descriptions thereof in this disclosure are not limited to bare dies and / or ICs. In some specific implementations, Figures 1A to 7 The descriptions and their corresponding information can be used to manufacture, create, provide, and / or produce devices and / or integrated devices. In some specific implementations, devices may include dies, integrated devices, integrated passive devices (IPDs), die packages, integrated circuit (IC) devices, device packages, integrated circuit (IC) packages, wafers, semiconductor devices, stacked package (PoP) devices, thermal devices, and / or interposers.

[0102] It should be noted that the accompanying drawings in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some instances, the drawings may not be to scale. In some instances, not all components and / or parts are shown for clarity. In some instances, the positioning, location, size, and / or shape of the various parts and / or components in the drawings may be exemplary. In some specific embodiments, the various components and / or parts in the drawings may be optional.

[0103] The term “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation or aspect described herein as “exemplary” is not necessarily to be construed as superior to or better than other aspects of this disclosure. Similarly, the term “aspect” does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed. The term “coupling” is used herein to refer to direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A physically contacts object B, and object B contacts object C, then object A and object C can still be considered coupled to each other, even if they are not in direct physical contact. Object A coupled to object B may be coupled to at least a portion of object B. The term “electrical coupling” may mean that two objects are directly or indirectly coupled together such that current (e.g., signal, power, ground) can flow between the two objects. Electrically coupled objects may or may not have current traveling between them. The use of the terms “first,” “second,” “third,” and “fourth” (and / or anything above the fourth) is arbitrary. Any component described can be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component can be a first component, a second component, a third component, or a fourth component. The terms “enclosing,” “enclosing,” and / or any derivative meaning can refer to an object that partially or completely encloses another object. The terms “top” and “bottom” are arbitrary. A component located at the top can be above a component located at the bottom. A top component can be considered a bottom component, and vice versa. As described in this disclosure, a first component located “above” a second component can mean that the first component is located above or below the second component, depending on how bottom or top is arbitrarily defined. In another example, a first component can be located above (e.g., above) a first surface of a second component, and a third component can be located above (e.g., below) a second surface of a second component, where the second surface is opposite to the first surface. It should also be noted that the term “above” as used in this application in the context of one component being above another component can be used to mean that a component is on and / or in another component (e.g., on the surface of a component or embedded in a component). Therefore, for example, "the first component is on top of the second component" can mean: (1) the first component is on top of the second component but does not directly contact the second component; (2) the first component is on the second component (e.g., on the surface of the second component); and / or (3) the first component is in the second component (e.g., embedded in the second component). A first component located "in" the second component can be partially or completely located in the second component. Values ​​from about X to XX can refer to values ​​between X and XX, including both X and XX. Values ​​between X and XX can be discrete or continuous. As used in this disclosure, the terms "about 'value X'" or "approximately value X" mean within 10% of "value X".For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9 to 1.1. "Multiple" components can include all possible components or only some of all possible components. For example, if a device comprises ten components, the term "multiple components" can refer to all ten components or only some of the ten components.

[0104] In some embodiments, an interconnect is a component or assembly in a device or package that allows or facilitates an electrical connection between two points, elements, and / or assemblies. In some embodiments, an interconnect may include traces, vias, pads, pillars, metallization layers, redistribution layers, and / or under-bump metallization (UBM) layers / interconnects. In some embodiments, an interconnect may include a conductive material configured to provide an electrical path for signals (e.g., data signals), ground, and / or power. An interconnect may include more than one element or assembly. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different embodiments may use different processes and / or steps to form interconnects. In some embodiments, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, spraying, and / or plating processes may be used to form interconnects.

[0105] It should also be noted that the various disclosures contained herein can be described as processes depicted as work diagrams, flowcharts, structural diagrams, or block diagrams. Although flowcharts may describe operations as sequential processes, many operations within an operation can be performed in parallel or concurrently. Furthermore, the order of operations can be rearranged. The process terminates when its operations are completed.

[0106] Further embodiments are described below to facilitate understanding of this disclosure.

[0107] According to Embodiment 1, an integrated device includes: a bottom substrate including a first conductor; a top substrate including a second conductor; a first die disposed between the bottom substrate and the top substrate, the first die including circuitry and a first contact electrically connected to the circuitry and the first conductor; and a redistributed die disposed between the bottom substrate and the top substrate adjacent to the first die. The redistributed die includes: a second contact electrically connected to the first contact via the first conductor; a third contact electrically connected to the second conductor; and a redistribution trace electrically connected to the second contact and the third contact. The top substrate includes a fourth contact electrically connected to the third contact via the second conductor to define one or more signal paths between the fourth contact and the first die.

[0108] Example 2 includes the integrated device according to Example 1, wherein the redistribution die includes a semiconductor die, and wherein the redistribution traces are integrated within the semiconductor die.

[0109] Example 3 includes the integrated device according to Example 1 or Example 2, and further includes interconnect conductors disposed between the bottom substrate and the top substrate and defining a portion of the one or more signal paths between the fourth contact and the first die.

[0110] Example 4 includes the integrated device according to Example 3, wherein at least one of the interconnect conductors is integrated within the redistributed die.

[0111] Example 5 includes an integrated device according to Example 3 or Example 4, wherein at least one of the interconnect conductors is external to the redistributed die and is electrically connected to the third contact of the redistributed die via the first conductor.

[0112] Example 6 includes an integrated device according to any one of Examples 1 to 5, wherein the fourth contact is configured to couple to a second die including a second circuit.

[0113] Example 7 includes the integrated device according to Example 6, wherein the circuitry of the first die defines one or more processor cores, and the second circuitry of the second die defines one or more memory cells.

[0114] Example 8 includes an integrated device according to any one of Examples 1 to 7, and further includes one or more additional redistributed dies disposed between the bottom substrate and the top substrate adjacent to the first die, and configured to define one or more additional signal paths between the first die and the fourth contact.

[0115] Example 9 includes an integrated device according to any one of Examples 1 to 8, and further includes a second redistributed die disposed on the side of the first die opposite to the redistributed die between the bottom substrate and the top substrate, the second redistributed die being configured to define a portion of a second signal path between the first die and the fourth contact.

[0116] Example 10 includes the integrated device according to Example 9, and further includes a third redistributed die disposed between the bottom substrate and the top substrate and configured to define a portion of a third signal path between the first die and the fourth contact.

[0117] Example 11 includes the integrated device according to Example 10, and further includes a fourth redistributed die disposed between the bottom substrate and the top substrate and configured to define a portion of a fourth signal path between the first die and the fourth contact.

[0118] Example 12 includes an integrated device according to any one of Examples 1 to 11, wherein the first die and the second die coupled to the fourth contact are integrated in a stacked package configuration.

[0119] According to Embodiment 13, a method of manufacturing an integrated device includes: coupling a first die to a bottom substrate, wherein coupling the first die to the bottom substrate includes electrically connecting a first contact of the first die to a first conductor of the bottom substrate; and coupling a redistributed die to the bottom substrate adjacent to the first die. Coupling the redistributed die to the bottom substrate includes: electrically connecting a second contact of the redistributed die to the first contact via the first conductor; and electrically connecting a third contact of the redistributed die to a second conductor of a top substrate to define one or more signal paths between the first die and a first subset of fourth contacts of the top substrate.

[0120] Example 14 includes the method according to Example 13, wherein the redistributed die includes a semiconductor die, and wherein the second contact, the third contact, and the redistribution trace therebetween are integrated within the semiconductor die.

[0121] Example 15 includes the method according to Example 13 or Example 14, the method further including coupling the second die to the fourth contact of the top substrate.

[0122] Example 16 includes the method according to Example 15, wherein the first die includes a first circuit defining one or more processor cores, and the second die includes a second circuit defining one or more memory cells.

[0123] Example 17 includes the method according to any one of Examples 13 to 16, and further includes electrically connecting an interconnect conductor to the second conductor of the top substrate, wherein the interconnect conductor is electrically connected to the third contact of the redistributed die.

[0124] Example 18 includes the method according to Example 17, wherein at least one of the interconnect conductors is integrated within the redistributed die.

[0125] Example 19 includes the method according to Example 17 or Example 18, wherein at least one of the interconnect conductors is outside the redistributed die and is electrically connected to the third contact of the redistributed die via the first conductor.

[0126] Example 20 includes the method according to any one of Examples 13 to 19, and further includes providing one or more additional redistributed dies on the bottom substrate adjacent to the first die; and electrically connecting the one or more additional redistributed dies between the first die and the fourth contact to define one or more additional signal paths between the first die and a second subset of the fourth contact on the top substrate.

[0127] According to Embodiment 21, a device includes: a bottom substrate including a first conductor; a top substrate including a second conductor; and a first die disposed between the bottom substrate and the top substrate. The first die includes circuitry and a first contact electrically connected to the circuitry and the first conductor. The device includes a redistributed die disposed between the bottom substrate and the top substrate. The redistributed die includes: a second contact electrically connected to the first contact via the first conductor; a third contact electrically connected to the second conductor; and a redistribution trace electrically connected to the second and third contacts. The device includes a second die with a fourth contact electrically connected to the top substrate, wherein the fourth contact is electrically connected to the third contact via the second conductor to define one or more signal paths between the first die and the second die.

[0128] Example 22 includes the device according to Example 21, wherein the redistribution die includes a semiconductor die, and wherein the redistribution traces are integrated within the semiconductor die.

[0129] Example 23 includes the device according to Example 21 or Example 22, the device further including interconnect conductors disposed between the bottom substrate and the top substrate and defining a portion of the one or more signal paths between the fourth contact and the first die.

[0130] Example 24 includes the device according to Example 23, wherein at least one of the interconnect conductors is integrated within the redistributed die.

[0131] Example 25 includes the device according to Example 23 or Example 24, wherein at least one of the interconnect conductors is outside the redistributed die and is electrically connected to the third contact of the redistributed die via the first conductor.

[0132] Example 26 includes a device according to any one of Examples 21 to 25, wherein the circuitry of the first die defines one or more processor cores, and wherein the second die includes second circuitry defining one or more memory cells.

[0133] Example 27 includes the device according to any one of Examples 21 to 26, and further includes one or more additional redistributed dies disposed between the bottom substrate and the top substrate adjacent to the first die, and configured to define one or more additional signal paths between the first die and the second die.

[0134] The various features of this disclosure described herein can be implemented in different systems without departing from this disclosure. It should be noted that the foregoing aspects of this disclosure are merely illustrative and should not be construed as limiting the scope of this disclosure. The description of aspects of this disclosure is intended to be exemplary and not to limit the scope of the appended claims. Therefore, the teachings herein can be readily applied to other types of devices, and many substitutions, modifications, and variations will be apparent to those skilled in the art.

Claims

1. An integrated device, the integrated device comprising: A bottom substrate, the bottom substrate including a first conductor; Top substrate, the top substrate including a second conductor; A first die is disposed between the bottom substrate and the top substrate, the first die including circuitry and a first contact electrically connected to the circuitry and the first conductor; and A redistributed die, the redistributed die disposed between the bottom substrate and the top substrate adjacent to the first die, the redistributed die comprising: The second contact is electrically connected to the first contact via the first conductor; A third contact, the third contact being electrically connected to the second conductor; and Redistribution traces, the redistribution traces being electrically connected to the second contact and the third contact; and The top substrate includes a fourth contact electrically connected to the third contact via the second conductor to define one or more signal paths between the fourth contact and the first die.

2. The integrated device of claim 1, wherein the redistribution die comprises a semiconductor die, and wherein the redistribution traces are integrated within the semiconductor die.

3. The integrated device according to claim 1, further comprising: An interconnect conductor is disposed between the bottom substrate and the top substrate and defines a portion of the one or more signal paths between the fourth contact and the first die.

4. The integrated device of claim 3, wherein at least one of the interconnect conductors is integrated within the redistributed die.

5. The integrated device of claim 3, wherein at least one of the interconnect conductors is outside the redistributed die and is electrically connected to the third contact of the redistributed die via the first conductor.

6. The integrated device of claim 1, wherein the fourth contact is configured to couple to a second die including the second circuitry.

7. The integrated device of claim 6, wherein the circuitry of the first die defines one or more processor cores, and the second circuitry of the second die defines one or more memory cells.

8. The integrated device of claim 1, further comprising one or more additional redistributed dies disposed between the bottom substrate and the top substrate adjacent to the first die, and configured to define one or more additional signal paths between the first die and the fourth contact.

9. The integrated device of claim 1, further comprising a second redistributed die disposed on a side of the first die opposite to the redistributed die between the bottom substrate and the top substrate, the second redistributed die being configured to define a portion of a second signal path between the first die and the fourth contact.

10. The integrated device of claim 9, further comprising a third redistributed die disposed between the bottom substrate and the top substrate and configured to define a portion of a third signal path between the first die and the fourth contact.

11. The integrated device of claim 10, further comprising a fourth redistributed die disposed between the bottom substrate and the top substrate and configured to define a portion of a fourth signal path between the first die and the fourth contact.

12. The integrated device of claim 1, wherein the first die and the second die coupled to the fourth contact are integrated in a stacked package configuration.

13. A method for manufacturing an integrated device, the method comprising: Couple the first die to the bottom substrate, wherein coupling the first die to the bottom substrate includes electrically connecting a first contact of the first die to a first conductor of the bottom substrate; as well as Couple the redistributed die to the bottom substrate adjacent to the first die, wherein coupling the redistributed die to the bottom substrate includes: The second contact of the redistributed die is electrically connected to the first contact via the first conductor; as well as The third contact of the redistributed die is electrically connected to the second conductor of the top substrate to define one or more signal paths between the first die and a first subset of the fourth contact of the top substrate.

14. The method of claim 13, wherein the redistributed die comprises a semiconductor die, and wherein the second contact, the third contact, and the redistribution trace therebetween are integrated within the semiconductor die.

15. The method of claim 13, further comprising coupling the second die to the fourth contact of the top substrate.

16. The method of claim 15, wherein the first die includes first circuitry defining one or more processor cores, and the second die includes second circuitry defining one or more memory cells.

17. The method of claim 13, further comprising electrically connecting an interconnect conductor to the second conductor of the top substrate, wherein the interconnect conductor is electrically connected to the third contact of the redistributed die.

18. The method of claim 17, wherein at least one of the interconnect conductors is integrated within the redistributed die.

19. The method of claim 17, wherein at least one of the interconnecting conductors is outside the redistributed die and is electrically connected to the third contact of the redistributed die via the first conductor.

20. The method according to claim 13, further comprising: One or more additional redistributed dies are disposed on the bottom substrate adjacent to the first die; as well as The one or more additional redistributed dies are electrically connected between the first die and the fourth contact to define one or more additional signal paths between the first die and a second subset of the fourth contact on the top substrate.

21. A device, the device comprising: A bottom substrate, the bottom substrate including a first conductor; Top substrate, the top substrate including a second conductor; A first die is disposed between the bottom substrate and the top substrate, the first die including circuitry and a first contact electrically connected to the circuitry and the first conductor; A redistributed die, disposed between the bottom substrate and the top substrate, comprises: The second contact is electrically connected to the first contact via the first conductor; A third contact, the third contact being electrically connected to the second conductor; and Redistribution traces, the redistribution traces being electrically connected to the second contact and the third contact; and A second die, electrically connected to a fourth contact of the top substrate, wherein the fourth contact is electrically connected to the third contact via the second conductor to define one or more signal paths between the first die and the second die.

22. The device of claim 21, wherein the redistribution die comprises a semiconductor die, and wherein the redistribution traces are integrated within the semiconductor die.

23. The device of claim 21, further comprising an interconnect conductor disposed between the bottom substrate and the top substrate and defining a portion of the one or more signal paths between the fourth contact and the first die.

24. The device of claim 23, wherein at least one of the interconnect conductors is integrated within the redistributed die.

25. The device of claim 23, wherein at least one of the interconnect conductors is external to the redistributed die and is electrically connected to the third contact of the redistributed die via the first conductor.

26. The device of claim 21, wherein the circuitry of the first die defines one or more processor cores, and wherein the second die includes second circuitry defining one or more memory cells.

27. The device of claim 21, further comprising one or more additional redistributed dies disposed between the bottom substrate and the top substrate adjacent to the first die, and configured to define one or more additional signal paths between the first die and the second die.

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