Secondary correlation time difference extraction method and system based on spectrum refinement
By using a secondary correlation time difference extraction method based on spectral refinement, the problems of noise interference and high resource consumption in passive target localization are solved, and efficient and accurate target localization is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-26
- Publication Date
- 2026-03-27
AI Technical Summary
Existing technologies for passive target localization suffer from problems such as high noise interference, spectral aliasing, and large leakage errors, resulting in poor positioning accuracy and high resource consumption.
A quadratic correlation time difference extraction method based on spectral refinement is adopted. Through steps such as data preprocessing, external data caching control, correlation weighting coefficient control, time-frequency conversion, conjugate multiplication, automatic amplitude truncation and correlation peak retrieval, noise interference is reduced and positioning accuracy is improved. Resource utilization is optimized through DMA.
It reduces overall resource consumption, improves the accuracy of passive target localization, and achieves efficient target localization in noisy environments.
Smart Images
Figure CN121741631A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application belongs to the field of passive positioning technology, and particularly relates to a twice correlation time difference extraction method and system based on spectrum refinement. BACKGROUND
[0002] The statements in this section merely provide background information related to the present application and do not necessarily constitute the prior art.
[0003] Passive positioning of a target plays a very important role in the fields of navigation, spaceflight, electronic station, etc. The paths of a space target to different receivers are different, and there is a distance difference. From the time point of view, the same radiation source reaches different receivers at different times, that is, the time difference contains the spatial position information of the target, and the target can be positioned by measuring the time difference. Three different measuring stations can measure two signal time differences (TDOA), form the intersection of hyperboloids, and the target is located at the intersection point.
[0004] At present, in the process of extracting the time difference of arrival of two signals, the signals are interfered by noise, and when a digital filter is used to process the source signal, the aliasing and leakage errors in the spectrum are large, and the overall resource consumption is large and the accuracy of passive positioning of the target is poor. SUMMARY
[0005] In order to solve the above technical problems, the present application provides a twice correlation time difference extraction method and system based on spectrum refinement, which can reduce the overall resource consumption and improve the accuracy of passive positioning of the target.
[0006] In order to achieve the above purpose, the present application adopts the following technical solutions: The first aspect of the present application provides a twice correlation time difference extraction method based on spectrum refinement.
[0007] In one or more embodiments, a twice correlation time difference extraction method based on spectrum refinement is provided, comprising: a data preprocessor, an external data buffer controller, a correlation weighting coefficient controller, a time-frequency converter, a correlation scheduler, a conjugate multiplier, an amplitude automatic clipper and a correlation peak retriever; The data preprocessor is configured to pass the received two-way to-be-extracted signals through mixing, decimation and window filtering operations in sequence to obtain two-way filtered baseband data to form a data packet; The external data buffer controller is configured to read and write data packets in the external buffer DDR in a DMA manner; The correlation weighting coefficient controller is configured to read the preloaded correlation coefficient packet from the external buffer DDR in a DMA manner according to the correlation coefficient reading request instruction initiated by the correlation scheduler, and send it to the conjugate multiplier to complete the weighting operation; The time-frequency converter is configured to convert the incoming data packet according to the correlation scheduler configuration conversion mode, conversion point number, and truncation setting parameter, and perform fast Fourier transform / inverse transform processing; The amplitude automatic truncator is configured to perform truncation processing on the original data according to the set effective bit width, so that the maximum effective amplitude is maintained after truncation of all data in the data packet; The correlation peak retriever is configured to convert the time-domain data packet output by the amplitude automatic truncator into a time-domain amplitude data packet, retrieve the maximum amplitude, the maximum amplitude position, the second largest amplitude, and the second largest amplitude position according to the amplitude, form a time difference correlation data packet, and cache the time difference correlation data packet in the correlation scheduler.
[0008] As an embodiment, the data preprocessor includes an NCO generator, a complex mixer, and a low-pass decimation filter that interact in sequence. The NCO generator is configured to generate sine and cosine waveform data output corresponding to the frequency according to the input frequency point configuration parameter, and output the sine and cosine waveform data to the complex mixer. When the external data cache controller indicates that the cache is writable, the data packet is taken out from the source data cache. The complex mixer multiplies the wideband digital intermediate frequency signal taken out from the source data cache with the sine input waveform signal and the cosine waveform signal, respectively, to obtain the data moved to zero intermediate frequency, and sends the data to the low-pass decimation filter. When the external data cache controller indicates that the cache is full, the source data is no longer taken out for digital down-conversion processing.
[0009] As an embodiment, in the external data cache controller, the cache write address segment is pre-set, and the read and write addresses are both operated according to the cyclic addition operation.
[0010] As an embodiment, the correlation scheduler includes a data cache reader, an FFT configurator, a correlation coefficient reader, a source data scheduler, and a flow controller. The data cache reader is configured to read the cache data packet from different data caches according to the sending original data request instruction of the source data scheduler, and send the cache data packet to the time-frequency converter / conjugate multiplier. The FFT configurator is configured to send the time-frequency converter according to the specific mode, transform length, and intermediate truncation parameter configured by the flow controller. The correlation coefficient reader is configured to read the corresponding set of correlation coefficients from the correlation weighting coefficient cache according to the correlation coefficient group reading request sent by the flow controller. The source data scheduler is configured to read the corresponding data from different data caches according to the data taking request parameter sent by the flow controller, and send the corresponding data to the corresponding module, so as to realize time division multiplexing of module resources. A flow controller, as a controller of the whole time difference extraction logic, sequentially initiates the integer sample time difference extraction process and the fractional sample time difference extraction process in time sequence.
[0011] As an embodiment, in the flow controller, the integer sample time difference extraction process is: The flow controller controls the source data scheduler to send the A path data packet input from the external data cache controller into the time-frequency converter, and the frequency domain conversion result data is sent into the cache module after the amplitude automatic truncator truncation processing; the B path data packet input from the external data cache controller is sent into the time-frequency converter for frequency domain conversion, and the frequency domain conversion result data is sent into the cache module after the amplitude automatic truncator truncation processing; When the automatic truncator outputs data, the A path processing result stored in the internal cache is taken out and sent into the conjugate multiplier together; after the A path and B path conjugate product result is processed by the automatic truncator, it is sent into the time-frequency converter, converted into time domain data through the configuration of the inverse fast Fourier transform, and sent into the correlation peak retriever to detect the input time domain correlation data packet converted into amplitude data according to the signal amplitude, and detect the maximum peak value, maximum peak position, secondary maximum peak value and secondary maximum peak position parameters in the amplitude data packet, and make a decision according to the maximum peak position and maximum peak setting condition.
[0012] As an embodiment, in the flow controller, the fractional sample time difference extraction process is: The flow controller sends the two-way padding data packets input from the external data cache controller into the time-frequency converter, the automatic truncator and the conjugate multiplier in sequence to obtain a data packet S waiting for correlation weighting processing, and writes it into the internal cache module; The flow controller first sends the first half data S0 of the data packet waiting for correlation weighting processing into the correlation coefficient COE0 sent into the conjugate multiplier to complete complex multiplication, and obtains the frequency domain weighting data SF0 through the time-frequency converter after zero padding, and then sends the weighting COE2 coefficient into the conjugate multiplier, and obtains the data packet SG0 through the amplitude automatic truncator; according to the same principle, the flow controller generates the data packet SG1, the data packet SG2 and the data packet SG3 by scheduling different source data input into the conjugate multiplier, the time-frequency converter and the amplitude automatic truncator in a pipelined manner by increasing time overhead, and writes them into the internal cache module; The flow controller sends the correlation coefficient COE3 and the cache data SGC2 into a conjugate multiplier, multiplies them, processes the result through an amplitude automatic clipper, and adds the result to the SGC0 data packet to write the first half of the fractional time difference correlation sequence into the internal cache; the flow controller sends the conjugate of the correlation coefficient COE3 and the cache data SGC3 into a conjugate multiplier, multiplies them, processes the result through an amplitude automatic clipper, and adds the result to the SGC1 data packet to write the second half of the fractional time difference correlation sequence into the internal cache; The flow controller sends the fractional time difference correlation data packet in the internal cache into a correlation peak retriever, outputs the fractional time difference correlation peak position and the correlation peak amplitude result, and converts the result into a time difference extraction result.
[0013] As an embodiment, the amplitude automatic clipper comprises a data buffer, an amplitude detector, and a clip controller. The data buffer is used to buffer the input data packet and wait for the clip controller to read and complete the clip processing. The amplitude detector is used to detect the amplitude of the packet data synchronously when the input data is written into the data buffer, and statistically analyze the amplitude according to the maximum value, intermediate value, and minimum value thresholds, and output the amplitude detection result to the clip controller when the packet ends. The clip controller is used to select the clip parameters according to the amplitude detection result and a predetermined range setting, and clip the buffered data when read from the data buffer and send the clip processing result to the clip processing result buffer module.
[0014] The second aspect of the application provides a secondary correlation time difference extraction system based on spectral refinement.
[0015] In one or more embodiments, a secondary correlation time difference extraction system based on spectral refinement comprises: The received two-way extraction signals are sequentially subjected to mixing, decimation, and window filtering operations to obtain two-way filtered baseband data to form a data packet. The data packet is read and written to the external cache DDR through DMA. The conversion mode, conversion point number, and clip setting parameters are configured to process the input data packet through fast Fourier transform / inverse transform. According to the correlation coefficient read request instruction, the preloaded correlation coefficient packet is read from the external cache DDR through DMA, and then subjected to conjugate multiplication with the fast Fourier transform / inverse transform processing result to complete the weighted operation. The original data is subjected to clip processing according to the set effective bit width to maintain the maximum effective amplitude after all data in the data packet is clipped. The time domain data packet after clip processing is converted into a time domain amplitude data packet, the maximum amplitude, maximum amplitude position, second largest amplitude, and second largest amplitude position are retrieved according to the amplitude to form a time difference correlation data packet.
[0016] A third aspect of the present application provides a computer readable storage medium.
[0017] A computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the method for extracting secondary correlation time difference based on spectrum refinement as described above.
[0018] A fourth aspect of the present application provides an FPGA platform.
[0019] An FPGA platform comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the steps of the method for extracting secondary correlation time difference based on spectrum refinement as described above when executing the program.
[0020] Compared with the prior art, the present application has the following beneficial effects: The present application reduces noise interference by sequentially passing the received two-way to-be-extracted signals through mixing, decimation and window filtering operations to obtain two-way filtered baseband data, and can improve the accuracy of target passive positioning. According to the correlation coefficient reading request instruction initiated by the correlation scheduler, the preloaded correlation coefficient package is read out from the external cache DDR in a DMA manner, sent into the conjugate multiplier, and the weighting operation is completed. The original data is truncated according to the set effective bit width, all data in the data package are truncated to maintain the maximum effective amplitude, and then converted into a time domain amplitude data package. The maximum amplitude, maximum amplitude position, second largest amplitude and second largest amplitude position are retrieved according to the amplitude, the time difference correlation data package is formed and cached in the correlation scheduler, the flexible cache module is used to complete the cache processing of the correlation coefficient and intermediate processing results, the hardware function module reuse is realized, and the purpose of reducing overall resource consumption is achieved. BRIEF DESCRIPTION OF DRAWINGS
[0021] The drawings constituting a part of the present application are used to provide a further understanding of the present application, and the illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application.
[0022] Figure 1 is a structure schematic diagram of a spectrum refinement-based secondary correlation time difference extraction system according to an embodiment of the present application; Figure 2 Figure 2 is a structure block diagram of a data preprocessor 00 according to an embodiment of the present application; Figure 3 is a structure block diagram of a correlation scheduler 40 according to an embodiment of the present application; Figure 4 is a structure block diagram of an amplitude automatic truncator 60 according to an embodiment of the present application; Figure 5is a flow chart of a spectrum refinement based secondary correlation time difference extraction method of an embodiment of the present application.
[0023] Wherein, 00-data preprocessor; 01-NCO generator, 02-complex mixer block, 03-low pass filter; 10-external data buffer controller, 20-correlation weighting coefficient controller, 30-time frequency converter, 40-correlation scheduler, 41-data buffer reader, 42-FFT module configurator, 43-correlation coefficient reader, 44-source data scheduler, 45-flow controller; 50-conjugate multiplier, 60-amplitude automatic clipper, 61-data buffer, 62-amplitude detector, 63-clip control; 70-correlation peak retriever. DETAILED DESCRIPTION
[0024] The present application is further described below in conjunction with the accompanying drawings and embodiments.
[0025] It should be noted that the following detailed description is exemplary in nature and is intended to provide further description of the application. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
[0026] It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments in accordance with the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, steps, operations, devices, components and / or combinations thereof, but do not preclude the presence or addition of one or more other features, steps, operations, devices, components and / or combinations thereof.
[0027] Terminology: FPGA: Field Programmable Gate Array.
[0028] FFT: Fast Fourier Transform.
[0029] MCZT: Modified Chirp-Z Transform.
[0030] NCO: Numerically Controlled Oscillator.
[0031] DDC: Digital Down Converter.
[0032] As Figure 1As shown, the secondary correlation time difference extraction system based on spectrum refinement in the embodiment can include: a data preprocessor 00, an external data cache controller 10, a correlation weighting coefficient controller 20, a time-frequency converter 30, a correlation scheduler 40, a conjugate multiplier 50, an amplitude automatic clipper 60, and a correlation peak retriever 70. The data preprocessor 00 and the external data cache controller 10 are connected in sequence. The external data cache controller 10, the correlation scheduler 40, the correlation weighting coefficient controller 20, the conjugate multiplier 50, the time-frequency converter 30, the amplitude automatic clipper 60, and the correlation peak retriever 70 are connected in sequence. The correlation scheduler 40, the conjugate multiplier 50, and the amplitude automatic clipper 60 are connected in sequence. The correlation scheduler 40, the time-frequency converter 30, the amplitude automatic clipper 60, and the correlation peak retriever 70 are connected in sequence.
[0033] (1) Data preprocessor 00: The data preprocessor 00 is configured to sequentially pass the received two-way to-be-extracted signals through mixing, decimation, and window filtering operations to obtain two-way filtered baseband data and form a data packet.
[0034] As shown in Figure 2 The data preprocessor 00 includes an NCO generator 01, a complex mixer 02, and a low-pass decimation filter 03 connected in sequence.
[0035] The input digital intermediate frequency baseband signal is subjected to DDC processing to move the intermediate frequency baseband signal to a zero intermediate frequency position, and a digital zero intermediate frequency signal of a specific bandwidth is obtained through decimation filtering processing, thereby providing zero intermediate frequency baseband data of a specific frequency point.
[0036] The working process is as follows: the host computer issues frequency point configuration parameters to the baseband data generator 00, the NCO generator 01 generates sine and cosine waveform data of a corresponding frequency according to the input frequency point configuration parameters and outputs the data to the complex mixer 02; when the external data cache controller 10 indicates that the cache can be written, the data packet is taken out from the source data cache, the complex mixer 02 multiplies the wideband digital intermediate frequency signal taken out from the source data cache with the sine input waveform signal and the cosine waveform signal to obtain data moved to a zero intermediate frequency, and sends the data to the low-pass decimation filter 03; the low-pass decimation filter 03 is composed of a low-pass filter set, and completes the setting data decimation and filtering of out-of-band spurious signals on the input data through a low-pass filter to obtain aliasing-free zero intermediate frequency data, which is transmitted to the external data cache controller 10; if the external data cache controller 10 indicates that the cache is full, the source data is not taken out for DDC processing.
[0037] (2) External data cache controller 10 The external data cache controller 10 is configured to read and write data packets to and from the external cache DDR in a DMA manner.
[0038] The cache write address segment is preset, and the read and write addresses are both operated in a cyclic self-increment mode. The external data cache controller 10 writes the zero intermediate frequency narrowband data packet sent by the data preprocessor 00 into the external cache DDR, and after a data packet of a relevant length is written, the relevant scheduler 40 is informed that the data is ready, and the data preprocessor 00 is informed when the cache is full, to stop the DDC processing process and no longer write into the cache; when the relevant scheduler 40 sends a request for reading external cache data, the external data cache controller 10 reads out the data packet from the external cache DDR according to the read address, read length and other parameters contained in the request instruction, and sends it to the relevant scheduler 40.
[0039] (3) Relevant weighting coefficient controller 20 The relevant weighting coefficient controller 20 is configured to read the preloaded correlation coefficient packet from the external cache DDR in a DMA mode according to the correlation coefficient read request instruction initiated by the relevant scheduler, and send it to the conjugate multiplier to complete the weighting operation.
[0040] The host computer sets appropriate parameters such as FFT length Nfft, correlation peak interpolation data length insert_N, correlation weighting coefficient quantization bit width Nbits, according to the time difference extraction accuracy requirement of the input 2-way data, generates 4 groups of correlation coefficients, and writes them into the cache in the order of correlation coefficient groups COE0, COE1, COE2, COE3, as the read cache address of the relevant weighting coefficient controller 20. The relevant weighting coefficient controller 20 reads the preloaded correlation coefficient packet from the external cache DDR in a DMA mode according to the correlation coefficient read request instruction initiated by the relevant scheduler 40, and sends it to the conjugate multiplier 50 to complete the weighting operation.
[0041] Among them, the relevant weighting coefficient is as follows: N2 =Nfft*insert_N; N=Nfft / 2; coef0 = exp(-1j*pi*(0:N-1).^2 / N2); coef1 = exp(1j*2*pi*N / N2*(0:N-1)).*coef0; h0 = exp(1j*pi*(0:N-1).^2 / N2); h1 = zeros(1,N); h1(1)= exp(1j*pi / N2); h1(2:N)= exp(1j*pi*(N-(1:N-1)).^2 / N2); coef2 = fft([h0,h1]); coef3 = exp(-1j*2*pi*N / N2*(0:N-1)); Coefficient quantization, bit width N bits COE0 = floor(coef0*(2^(Nbits-1))); COE1 = floor(coef1*(2^(Nbits-1))); COE2 = floor(coef2 / max(abs(coef2))*(2^(Nbits-1))); COE3 = floor(coef3*(2^(Nbits-1))).
[0042] (4) Time-frequency converter 30 The time-frequency converter 30 is configured to perform fast Fourier transform / inverse transform processing on the incoming data packets according to the conversion mode, number of conversion points, and truncation setting parameters configured by the relevant scheduler.
[0043] The time-frequency converter 30 is configured with parameters such as conversion mode (FFT / IFFT), number of conversion points (8~65536), and truncation setting according to the relevant scheduler 40. It performs fast Fourier transform or inverse fast Fourier transform on the input data packets to achieve data switching between the time domain and the frequency domain, and sends the processing result to the intermediate buffer module.
[0044] (5) Related scheduler 40 like Figure 3 As shown, the correlation scheduler 40 controls the entire time difference extraction device to proceed from the integer sample point time difference extraction process to the fractional sample point time difference extraction process, and finally outputs the time difference results that meet the accuracy and resolution requirements. The correlation scheduler 40 includes a data buffer reader 41, an FFT configurator 42, a correlation coefficient reader 43, a source data scheduler 44, and a process controller 45; (5.1) Data cache reader 41 The data cache reader 41 mainly implements the function of reading cached data packets from different data caches according to the original data request instruction sent by the source data scheduler 44, sending them to the time-frequency converter 30 for frequency-domain-time domain conversion processing, and sending them to the conjugate multiplier 50 to complete the multiplication processing.
[0045] (5.2) FFT configurator 42 The main function of the process controller 45 is to select and configure the FFT logic module to a specific mode (Fast Fourier Transform or Inverse Fast Fourier Transform), transform length (256~65536), intermediate truncation parameters, etc., and send them to the time-frequency converter 30.
[0046] (5.3) Correlation coefficient reader 43 The correlation coefficient group reading request sent by the flow controller 45 is mainly implemented to read the corresponding correlation coefficient group from the correlation weighting coefficient buffer 20. In the decimal sample point time difference extraction process, the aligned data packets need to be read from the source data buffer and the correlation weighting coefficient buffer 20, sent into the complex multiplier 50 for complex multiplication, and the result is sent into the time-frequency converter 30 to obtain the corresponding frequency domain or time domain data result.
[0047] (5.4) Source data scheduler 44 The source data scheduler 44 is mainly implemented to read the corresponding data from different data buffers according to the data reading request parameters sent by the flow controller 45, including the external data buffer controller 10, the correlation weighting coefficient controller 20, the product buffer module output by the complex multiplier 50, the result buffer module output by the automatic truncator 60, and the corresponding data packets are taken out and sent into the complex multiplier 50, the time-frequency converter 30, and the amplitude automatic truncator 60 for processing, to realize time division multiplexing of module resources.
[0048] (5.5) Flow controller 45 The flow controller 45 is the controller of the entire time difference extraction logic work, and sequentially starts the integer sample point time difference extraction process and the decimal sample point time difference extraction process according to the time sequence. The working principle of the entire flow controller 45 is as follows: The integer sample point time difference extraction process is as follows: The flow controller 45 controls the source data scheduler 44 to send the A path data packet input from the external data buffer controller 10 into the time-frequency converter 30, and the frequency domain conversion result data is processed by the amplitude automatic truncator 60 and sent into the buffer module; the B path data packet input from the external data buffer controller 10 is also processed as described above, and the A path processing result in the internal buffer is taken out when the automatic truncator 60 outputs the data, and sent into the complex multiplier 50 together. After the A path and B path conjugate product results are processed by the automatic truncator 60, they are sent into the time-frequency converter 30, converted into time domain data through the configuration of the inverse fast Fourier transform, sent into the correlation peak retriever (70), and converted into amplitude data according to the signal amplitude detection input time domain correlation data packet, and the maximum peak value, maximum peak position, secondary maximum peak value, secondary maximum peak position and other parameters in the amplitude data packet are detected, and a decision is made according to the maximum peak position and the maximum peak setting condition.
[0049] The decimal sample point time difference extraction process is as follows: The process controller 45 receives two data packets from the external data buffer controller 10, which are padded with data packets. Following the process described above, the packets are sequentially processed through modules such as the time-frequency converter 30, the automatic truncation unit 60, and the conjugate multiplier 50 to obtain a data packet S awaiting correlation weighting processing. This data packet is then written into the internal buffer module. The process controller 45 first takes the first half of the data packet S0 awaiting correlation weighting processing, sends the correlation coefficient COE0 from the correlation weighting coefficient controller 20, and then sends it to the conjugate multiplier 50 for complex multiplication. After zero-padding, the data packet is processed by the time-frequency converter 30 to obtain the frequency domain weighted data SF0. This SF0 is then processed by the weighting coefficient COE2 and sent to the conjugate multiplier 50. The result is then processed by the amplitude automatic truncation unit 60 to obtain the data packet SG0. Following the same principle, the process controller 45 schedules data packets from different sources input to the conjugate multiplier 50, the time-frequency converter 30, and the amplitude automatic truncation unit 60, increasing time overhead and generating data packets SG1, SG2, and SG3 in a pipelined manner, and then writes all of them into the internal buffer module. 5. The correlation coefficient COE3 and the cached data SGC2 are fed into the conjugate multiplier (50), multiplied, and the result is processed by the amplitude automatic truncation unit 60 and added to the SGC0 data packet. This is written into the internal cache as the first half of the fractional time difference correlation sequence. The correlation coefficient COE3 is conjugated and fed into the conjugate multiplier 50 together with the cached data SGC3. The result is multiplied, and the result is processed by the amplitude automatic truncation unit 60 and added to the SGC1 data packet. This is written into the internal cache as the second half of the fractional time difference correlation sequence. The process controller 45 sends the fractional time difference correlation data packets in the internal cache to the correlation peak retriever 70, outputs the fractional time difference correlation peak position, correlation peak amplitude, and other results, and converts them into time difference extraction results, which are then sent to the host computer module.
[0050] (6) Conjugate multiplier 50 The conjugate multiplier 50 implements complex conjugate multiplication processing. It uses the Comloex Multiplier IP as the multiplication processing logic. An external control signal controls the conjugate processing of one of the data involved in the operation to obtain the conjugate multiplication result of the two data.
[0051] (7) Automatic amplitude truncation device 60 like Figure 4 As shown, the amplitude automatic truncation unit 60 is configured to truncate the original data according to the set effective bit width, so as to maintain the maximum effective amplitude after all data in the data packet is truncated. The automatic amplitude truncation unit 60 implements the principle of truncating the input data packet according to the maximum effective amplitude and according to the set effective bit width, so as to maintain the maximum effective amplitude after all data in the data packet is truncated. The automatic amplitude truncation unit 60 includes a data buffer 61, an amplitude detector 62, and a truncation controller 63.
[0052] (7.1) Data buffer 61 Mainly using internal FIFO IP implementation, the input data packet is cached and waits for the read of the truncation controller 63 to complete the truncation processing.
[0053] (7.2) Amplitude detector 62 When the input data is written into the data buffer 61, the amplitude of the packet data is detected synchronously, and statistical analysis is performed according to the maximum value, intermediate value, and minimum value threshold. The amplitude detection result is output to the truncation controller 63 at the end of the packet. (7.3) Truncation controller 63 According to the amplitude detection result, the truncation parameters are selected according to the predetermined range setting. When reading from the data buffer 61, the cached data is truncated and processed, and sent to the truncation processing result buffer module.
[0054] (7.4) Correlation peak retriever 70 The correlation peak retriever 70 converts the input time domain data packet into a time domain amplitude data packet, and retrieves the maximum amplitude, maximum amplitude position, second maximum amplitude, and second maximum amplitude position according to the amplitude.
[0055] The working mechanism of the secondary correlation time difference extraction system based on spectral refinement in this embodiment is as follows: The data preprocessor 00 sets the center frequency point, frequency band parameters, decimation factor, etc. according to the configuration, and performs DDC processing on the data collected by two stations (A station and B station) to generate zero intermediate frequency baseband data corresponding to the frequency point, which is sent to the external data buffer controller 10 respectively; the external data buffer controller 10 writes the zero intermediate frequency baseband data into the external buffer DDR, and notifies the correlation scheduler 40 that the data is ready after writing a full integer time difference extraction process required data packet; the correlation scheduler 40 starts the integer sample point time difference extraction process, sends a data request instruction to the external data buffer controller 10, reads out the A road narrowband data, processes it through the time-frequency converter 30 to get the frequency domain full amplitude data, then according to the set strategy through the amplitude automatic truncator 60, retains the set position width data, and caches the A road frequency domain data result after truncation; the B road data is processed in the same way, and the B road frequency domain data is aligned with the A road frequency domain data and sent to the conjugate multiplier (50), then the result is converted to time domain through the time-frequency converter 30 and sent to the correlation peak retriever 70; the correlation peak retriever 70 converts the input time domain correlation data packet into amplitude data according to the signal amplitude, detects the maximum peak value, maximum peak value position, second maximum peak value, second maximum peak value position, etc. in the amplitude data packet, and makes a decision according to the maximum peak value position and maximum peak value setting condition, and sends the result to the correlation scheduler 40; If the integer correlation peak result is invalid, the correlation scheduler 40 updates the data packet position, reads the next data packet, and enters the integer time difference sample point search process again; otherwise, the correlation scheduler 40 starts the fractional time difference sample point search: taking the maximum peak position as the starting point, the correlation scheduler 40 sends a data request instruction to the external data buffer controller 10, reads data from the 2-way (A-way, B-way) data packet buffer offset address, and pads zeros at the end to make a complete sample point packet, and then re-obtains the 2-way (A-way, B-way) time domain source data. According to the order of A-way time domain data first and B-way time domain data second, the 2-way (A-way, B-way) frequency domain data after conversion and alignment is sent to the conjugate multiplier 50, and then the first half of the product result is taken as S0 and the second half is taken as S1; According to the correlation coefficient reading instruction sent by the correlation scheduler 40, the correlation weighting coefficient controller 20 reads the weighting coefficients COE0, COE1, and COE2, and the complex product of the data S0 and the COE0 is obtained. After zero padding, the frequency domain weighted data SF0 is obtained through the time-frequency converter 30, and then the weighted COE2 coefficient is sent to the conjugate multiplier 50, and the result is obtained through the amplitude automatic slicer 60 to obtain the data packet SG0; the complex product of S0 and COE1 is obtained after zero padding, and the frequency domain weighted data SF1 is obtained through the time-frequency converter 30, and then the weighted COE2 coefficient is subjected to complex multiplication, and the result is obtained through the amplitude automatic slicer 60 to obtain the data packet SG1; the data S1 and the COE1 are sent to the conjugate multiplier 50, and the product is zero-padded at the tail, and the frequency domain weighted data SF2 is obtained through the time-frequency converter 30, and then the weighted COE2 coefficient is sent to the conjugate multiplier 50, and the result is obtained through the amplitude automatic slicer 60 to obtain the data packet SG2; the S1 and the COE1 are sent to the conjugate multiplier 50, and the product is zero-padded at the tail, and the frequency domain weighted data SF3 is obtained through the time-frequency converter 30, and then the weighted COE2 coefficient is sent to the conjugate multiplier 50, and the result is obtained through the amplitude automatic slicer 60 to obtain the data packet SG3; The frequency domain weighted data packet SG0 is converted into time domain data by the time-frequency converter 30, and the first half data is sent into the conjugate multiplier 50 with COE0, and the result is conjugated, and the result is obtained through the amplitude automatic clipper 60 to obtain the buffered data packet SGC0; the frequency domain weighted data packet SG1 is converted into time domain data by the time-frequency converter 30, and the first half data is sent into the conjugate multiplier 50 with COE1, and the result is conjugated, and the result is obtained through the amplitude automatic clipper 60 to obtain the data packet SGC1; the frequency domain weighted data packet SG2 is converted into time domain data by the time-frequency converter 30, and the first half data is sent into the conjugate multiplier 50 with COE0, and the result is conjugated, and the result is obtained through the amplitude automatic clipper 60 to obtain the data packet SGC2; the frequency domain weighted data packet SG2 is converted into time domain data by the time-frequency converter 30, and the first half data is sent into the conjugate multiplier 50 with COE1, and the result is conjugated, and the result is obtained through the amplitude automatic clipper 60 to obtain the data packet SGC3; The relevant weighted coefficient controller 20 sends the relevant coefficient reading instruction COE3 according to the relevant scheduler 40, sends the buffered data SGC2 and COE3 into the conjugate multiplier 50, multiplies, and after the result is processed through the amplitude automatic clipper 60, adds the SGC0 data packet, and processes as the first half of the decimal time difference correlation sequence; after COE3 is conjugated, and the buffered data SGC3 are sent into the conjugate multiplier 50, the product is multiplied, and after the result is processed through the amplitude automatic clipper 60, the SGC1 data packet is added, and processed as the second half of the decimal time difference correlation sequence. The entire correlation sequence is sent into the correlation peak retriever 70, and the position of the decimal time difference correlation peak value, the correlation peak value amplitude and other results are output, and are converted into time difference extraction results, and are sent to the upper computer module; The relevant scheduler 40 offsets the source time domain data buffer reading address, and starts the time difference detection process of the next packet 2-way (A-way, B-way) data. In one or more embodiments, a secondary correlation time difference extraction method based on spectrum refinement includes: The received two-way to-be-extracted signals are sequentially subjected to mixing, extraction and window filtering operations to obtain filtered two-way baseband data to form data packets; The data packets are read and written into the external buffer DDR through the DMA mode; The conversion mode, conversion point number and bit setting parameters are configured, and the data packets are subjected to fast Fourier transform / inverse transform processing; According to the correlation coefficient reading request instruction, the preloaded correlation coefficient packet is read out from the external buffer DDR in the DMA mode, and then subjected to conjugate multiplication with the fast Fourier transform / inverse transform processing result to complete the weighting operation; The original data is subjected to bit clipping processing according to the set effective bit width, so that all the data in the data packet is clipped to maintain the maximum effective amplitude; The time-domain data packet after the clipping processing is converted into a time-domain amplitude data packet, and the maximum amplitude, the maximum amplitude position, the second maximum amplitude and the second maximum amplitude position are retrieved according to the amplitude to form a time difference correlation data packet.
[0056] As Figure 5 , the secondary correlation time difference extraction process based on spectrum refinement is as follows: Step A, time difference extraction parameter configuration-501; The FFT length Nfft of the correlation data, the correlation peak interpolation data length insert_N, the correlation weighting coefficient quantization bit width Nbits, etc. are configured, a correlation weighting coefficient file is generated, and is cached to the external DDR; the data preprocessing parameters are configured, and the digital zero intermediate frequency signal of a specific bandwidth is obtained by processing, and step B is entered; Step B, integer sample time difference extraction processing-502; An A channel and a B channel data packet are read from the zero intermediate frequency data cache in sequence, and are sent into a time-frequency converter in time, and the conjugate multiplication of the two frequency domain signals is performed, and the result is sent into the time-frequency converter to be converted into time domain signal data, and is sent into a correlation peak value retriever to extract the integer sample time difference parameters of the current group of data, and step C is entered; Step C, correlation scheduling processing-503; The integer sample time difference parameters extracted are judged according to the preset condition: if the integer sample time difference exceeds the deviation range, the current group of data is discarded, and the next group of integer sample time difference extraction processing is performed again; if the deviation range is satisfied, the integer sample time difference is taken as the data offset address starting point, and 0 is appended at the end after taking the data, and the two frequency domain signals are sent into the time-frequency converter in time, and the product data of the conjugate multiplication is processed by the amplitude automatic intercepting device, and is written into the product cache, and the decimal sample time difference parameter extraction processing process is started, and step D is entered; Step D, primary correlation weighting processing SG0-504; The two-way conjugate product data cache obtained from step C is first taken out (0~Nfft / 2-1) data respectively, and is multiplied with the correlation weighting coefficient COE0 output from the weighting coefficient controller, and is processed by the amplitude automatic intercepting device, and is sent into the time-frequency converter to convert the time domain data; the processed time domain data is multiplied with the weighting correlation coefficient COE2, and the result of the amplitude automatic intercepting device is the primary correlation weighting processing data SG0, which is written into the secondary correlation weighting processing data cache, and step E is entered; Step E, primary correlation weighting processing SG1-505; The two-way conjugate product data buffer from step C takes out the first half (0~Nfft / 2-1) data, respectively, and multiplies with the relevant weighting coefficient COE1 output from the weighting coefficient controller, and through the amplitude automatic intercepter intercepting processing, sends the time domain data into the time-frequency converter; the processed time domain data and the weighting coefficient COE2 product, and the result of the amplitude automatic intercepter intercepting processing, that is, the once correlation weighting processing data SG1, is written into the secondary correlation weighting processing data buffer, and step F is entered; Step F, once correlation weighting processing SG2-506; The two-way conjugate product data buffer from step C takes out the first half (0~Nfft / 2-1) data, respectively, and multiplies with the relevant weighting coefficient COE1 output from the weighting coefficient controller, and through the amplitude automatic intercepter intercepting processing, sends the time domain data into the time-frequency converter; the processed time domain data and the weighting coefficient COE2 product, and the result of the amplitude automatic intercepter intercepting processing, that is, the once correlation weighting processing data SG1, is written into the secondary correlation weighting processing data buffer, and step F is entered; Step G, once correlation weighting processing SG3-507; The two-way conjugate product data buffer from step C takes out the first half (0~Nfft / 2-1) data, respectively, and multiplies with the relevant weighting coefficient COE1 output from the weighting coefficient controller, and through the amplitude automatic intercepter intercepting processing, sends the time domain data into the time-frequency converter; the processed time domain data and the weighting coefficient COE2 product, and the result of the amplitude automatic intercepter intercepting processing, that is, the once correlation weighting processing data SG1, is written into the secondary correlation weighting processing data buffer, and step F is entered; Step H, secondary correlation weighting processing SGC0-508; The frequency domain weighting data packet SG0 is converted into time domain data by the time-frequency converter, and the first half data is sent into the conjugate multiplier with COE0, and the result is conjugated, and the result is obtained through the amplitude automatic intercepter to obtain the cache data packet SGC0, and step I is entered; Step I, secondary correlation weighting processing SGC1-509; The frequency domain weighting data packet SG1 is converted into time domain data by the time-frequency converter, and the first half data is sent into the conjugate multiplier with COE1, and the result is conjugated, and the result is obtained through the amplitude automatic intercepter to obtain the cache data packet SGC1, and step J is entered; Step J, secondary correlation weighting processing SGC2-510; The frequency domain weighted data packet SG2 is converted into time domain data by a time-frequency converter, the first half data is input into a conjugate multiplier with COE0, the result is conjugated, the result is input into a buffer data packet SGC2 through an amplitude automatic clipper, and the step K is entered; Step K, secondary correlation weighted processing SGC3-511; The frequency domain weighted data packet SG2 is converted into time domain data by a time-frequency converter, the first half data is input into a conjugate multiplier with COE1, the result is conjugated, the result is input into a buffer data packet SGC3 through an amplitude automatic clipper, and the step L is entered; Step L, fractional sample time difference correlation sequence processing-512; The buffer data SGC2 is input into a conjugate multiplier with COE3, the product is processed through an amplitude automatic clipper, and then added with the data packet SGC0, as the first half of the fractional time difference correlation sequence; COE3 is conjugated, and then input into a conjugate multiplier with the buffer data SGC3, the product is processed through an amplitude automatic clipper, and then added with the data packet SGC1, as the second half of the fractional time difference correlation sequence. The whole correlation sequence is input into a correlation peak retriever, the fractional time difference correlation peak position, correlation peak amplitude and other results are output, the time difference extraction result is converted, and sent to an upper computer module, and the step M is entered; Step M, updating the read address and other parameters of the source time domain data buffer-513, and returning to the step A.
[0057] In one or more embodiments, a computer readable storage medium is also provided, which stores a computer program, the program being executed by a processor to implement the steps in the secondary correlation time difference extraction method based on spectrum refinement as described above.
[0058] In one or more embodiments, an FPGA platform is also provided, which includes a memory, a processor and a computer program stored on the memory and executable on the processor, the processor executing the program to implement the steps in the secondary correlation time difference extraction method based on spectrum refinement as described above.
[0059] The present application has the following advantages: (1) The time difference extraction precision and resolution can be improved: the configurable DDC logic can select different signal bandwidths, remove out-of-band noise, improve signal SNR, and improve time difference extraction precision; through integer sample correlation and fractional sample process, the method of interpolating the correlation peak and then correlating again is used to improve the time difference extraction precision, and the correlation time is improved, and the signal correlation performance is improved; (2) High utilization rate of FPGA resources: by pre-caching relevant weighting coefficients and pre-processed (DDC, etc.) time domain source data through external caching devices, and by using a flow scheduling method, only one FFT module is used to repeatedly implement fast Fourier transform and fast inverse Fourier transform, with small resource overhead. The multi-channel data parallel time difference extraction product can directly serve multiple sets of time difference extraction modules.
[0060] (3) Suitable for small-sized and low-cost time difference extraction product applications.
[0061] The above is only a preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.
Claims
1. A system for extracting time difference based on spectral refinement of quadratic correlation, characterized in that, include: Data preprocessor, external data cache controller, correlation weighting coefficient controller, time-frequency converter, correlation scheduler, conjugate multiplier, automatic amplitude truncation unit, and correlation peak retriever; The data preprocessor is configured to sequentially perform mixing, decimation, and windowing filtering operations on the two received signals to be extracted to obtain two filtered baseband data streams, forming a data packet. The external data cache controller is configured to read and write data packets to the external cache DDR via DMA. The relevant weighting coefficient controller is configured to read the preloaded relevant coefficient packet from the external cache DDR in DMA mode according to the relevant coefficient read request instruction initiated by the relevant scheduler, and send it to the conjugate multiplier to complete the weighting operation; The time-frequency converter is configured to perform fast Fourier transform / inverse transform processing on the incoming data packets according to the conversion mode, number of conversion points, and truncation setting parameters configured by the relevant scheduler. The amplitude automatic truncation device is configured to truncate the original data according to a set effective bit width, so as to maintain the maximum effective amplitude after all data in the data packet is truncated. The relevant peak retriever is configured to convert the time-domain data packets output by the amplitude auto-truncater into time-domain amplitude data packets, retrieve the maximum amplitude value, the position of the maximum amplitude value, the second largest amplitude value, and the position of the second largest amplitude value according to the amplitude, form time difference-related data packets, and cache them in the relevant scheduler.
2. The quadratic correlation time difference extraction system based on spectral refinement as described in claim 1, characterized in that, The data preprocessor includes an NCO generator, a complex mixer, and a low-pass decimation filter that interact sequentially. The NCO generator is configured to generate sine and cosine waveform data of the corresponding frequency according to the input frequency configuration parameters and output them to the complex mixer. When the external data buffer controller indicates that the buffer is writable, the data packet is retrieved from the source data buffer. The complex mixer multiplies the broadband digital intermediate frequency signal retrieved from the source data buffer with the sine and cosine waveform signals respectively to obtain the data shifted to zero intermediate frequency and sends it to the low-pass decimation filter. When the external data buffer controller indicates that the buffer is full, the source data is no longer retrieved and digital down-conversion processing is performed.
3. The quadratic correlation time difference extraction system based on spectral refinement as described in claim 1, characterized in that, In the external data cache controller, the cache write address range is preset, and both the read and write addresses are incremented in a loop.
4. The quadratic correlation time difference extraction system based on spectral refinement as described in claim 1, characterized in that, The relevant scheduler includes a data cache reader, an FFT configurator, a correlation coefficient reader, a source data scheduler, and a process controller; The data cache reader is used to read cached data packets from different data caches according to the original data request instruction sent by the source data scheduler and send them to the time-frequency converter / conjugate multiplier. The FFT configurator is used to send the time-frequency converter to the process controller according to the specific mode, transform length and intermediate truncation parameters. The correlation coefficient reader is used to read the corresponding group correlation array from the correlation weighted coefficient buffer when a correlation coefficient group read request is sent by the process controller. The source data scheduler is used to read the corresponding data from different data caches and send it to the corresponding module according to the data retrieval request parameters sent by the process controller, so as to realize the time-division multiplexing of module resources. The process controller, which acts as the controller for the entire time difference extraction logic, sequentially initiates the integer sample time difference extraction process and the fractional sample time difference extraction process according to the time sequence.
5. The quadratic correlation time difference extraction system based on spectral refinement as described in claim 4, characterized in that, In the process controller, the integer sample time difference extraction process is as follows: The process controller controls the source data scheduler to send the A-channel data packet input from the external data buffer controller to the time-frequency converter. The frequency domain conversion result data is processed by the amplitude automatic truncation device and sent to the buffer module. Then, the B-channel data packet input from the external data buffer controller is sent to the time-frequency converter for frequency domain conversion. The frequency domain conversion result data is processed by the amplitude automatic truncation device. When the automatic truncate outputs data, the A-path processing result in the internal buffer is retrieved and fed into the conjugate multiplier. The conjugate product of paths A and B is processed by an automatic truncation unit and then sent to a time-frequency converter. After being converted into time-domain data by a configured inverse fast Fourier transform, it is sent to a correlation peak lookup unit to detect the input time-domain correlation data packets according to the signal amplitude. The lookup unit converts the data packets into amplitude data and detects the maximum peak value, maximum peak value position, second maximum peak value, and second maximum peak value position parameters in the amplitude data packets. The lookup unit then makes a decision based on the maximum peak value position and the maximum peak value setting conditions.
6. The quadratic correlation time difference extraction system based on spectral refinement as described in claim 4, characterized in that, In the process controller, the decimal sample time difference extraction process is as follows: The process controller takes two supplementary data packets from the external data buffer controller, passes them sequentially through a time-frequency converter, an automatic truncation unit, and a conjugate multiplier, and obtains a data packet S that is waiting for relevant weighted processing, and writes it into the internal buffer module; The process controller first sends the first half of the data packet S0, which is waiting for related weighting processing, to the related weighting coefficient controller. The related weighting coefficient COE0 is then sent to the conjugate multiplier to complete complex multiplication. After zero-padding, the data packet is converted to frequency domain weighted data SF0 through the time-frequency converter. Then, it is sent to the conjugate multiplier along with the weighting coefficient COE2. The result is then passed to the amplitude auto-truncate unit to obtain data packet SG0. Following the same principle, the process controller generates data packets SG1, SG2, and SG3 in a pipelined manner by scheduling the input data from different sources to the conjugate multiplier, time-frequency converter, and amplitude auto-truncate unit, and writes them all into the internal buffer module. The process controller sends the correlation coefficient COE3 and the cached data SGC2 into the conjugate multiplier, multiplies them, processes the result through the amplitude automatic truncation device, adds it to the SGC0 data packet, and writes it into the internal cache as the first half of the fractional time difference correlation sequence. After taking the conjugate of the correlation coefficient COE3, it is fed into the conjugate multiplier along with the cached data SGC3. The product is then processed by the amplitude automatic truncation device and added to the SGC1 data packet. This result is written into the internal cache as the second half of the fractional time difference correlation sequence. The process controller sends the fractional time difference related data packets in the internal cache to the correlation peak retriever, outputs the position and amplitude of the fractional time difference related peaks, and converts them into time difference extraction results.
7. The quadratic correlation time difference extraction system based on spectral refinement as described in claim 1, characterized in that, The automatic amplitude truncation device includes a data buffer, an amplitude detector, and a truncation controller; The data buffer is used to buffer the input data packets and wait for the truncation controller to read them and complete the truncation process; The amplitude detector is used to synchronously detect the amplitude of the data packet when the input data is written to the data buffer, and to perform statistical analysis according to the maximum, median and minimum thresholds. At the end of the packet, the amplitude detection result is output to the truncation controller. The truncation controller is used to select truncation parameters according to the amplitude detection results and a predetermined range. When reading from the data buffer, the buffered data is truncated and sent to the truncation processing result buffer module.
8. A method for extracting time difference based on quadratic correlation using spectral refinement, characterized in that, include: The two received signals to be extracted are sequentially subjected to mixing, decimation and windowing filtering operations to obtain two filtered baseband data streams, forming a data packet. Data packets are read from and written to the external DDR cache via DMA. Configure the conversion mode, number of conversion points, and truncation settings to perform Fast Fourier Transform / Inverse Transform on the incoming data packets; According to the correlation coefficient read request instruction, the preloaded correlation coefficient packet is read from the external cache DDR in DMA mode, and then the weighted operation is completed by conjugate multiplication with the result of fast Fourier transform / inverse transform processing. The original data is truncated according to the set effective bit width to ensure that the maximum effective amplitude is maintained after all data in the data packet is truncated. The truncated time-domain data packets are converted into time-domain amplitude data packets. The maximum amplitude, the position of the maximum amplitude, the second maximum amplitude, and the position of the second maximum amplitude are retrieved according to the amplitude to form time-difference related data packets.
9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the steps in the spectral refinement-based quadratic correlation time difference extraction method as described in claim 8.
10. An FPGA platform, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the steps in the spectral refinement-based quadratic correlation time difference extraction method as described in claim 8.