A slow drift compensation method for beam-by-beam position measurement

Abstract

The application provides a slow drift compensation method for beam position measurement, comprising: setting up a slow drift compensation circuit for beam position measurement; switching the access signal of a fast switching switch circuit to a BPM signal, automatically detecting a filling mode, and obtaining a mode mask of the filling mode; generating a pilot signal; switching the access signal between the pilot signal and the BPM signal according to the mode mask of the filling mode; processing the BPM signal and the pilot signal of each channel to obtain the calculated amplitude information of the beam of each channel and the calculated amplitude of the pilot signal for compensating the beam signal; normalizing and compensating the beam signal by using the calculated amplitude of the pilot signal for compensating the beam signal, and calculating the position information of the beam by using a difference ratio algorithm. The method of the application realizes the slow drift compensation of the beam position measurement by injecting the pilot signal which does not overlap with the BPM signal in the time domain at the position of the empty beam, and processing in the time domain.

Description

A method for slow drift compensation in bundle position measurement Technical Field

[0001] This invention relates to the field of particle accelerator beam diagnostics, and more particularly to a slow drift compensation method for measuring the position of each bundle, which is applicable to electron storage rings. Background Technology

[0002] Cluster-by-cluster beam position measurement is an important cutting-edge research direction in electron storage rings, and it is of great significance for improving the brightness and stability of synchrotron radiation sources, especially next-generation diffraction-limited ring sources. Current beam position measurement processors used in engineering applications only have loop-by-loop position measurement capabilities, and developing a cluster-by-cluster position measurement processor that meets engineering applications faces numerous technical challenges. Taking the Shanghai Synchrotron Radiation Facility (SSRF) storage ring as an example, its high-frequency is 499.654 MHz, its harmonic number is 720, its loop-by-loop frequency is 694 kHz, and the corresponding cluster-by-cluster frequency is also 499.654 MHz. Current position processors used in engineering applications can only provide measurement results at a loop-by-loop rate of 694 kHz, while a cluster-by-cluster position measurement processor requires measurement results at frequencies approaching 500 MHz, significantly increasing the technical difficulty. A series of new technical challenges urgently need to be solved, one of which is measurement drift in electronics.

[0003] Synchrotron radiation sources require extremely high measurement stability, and the slow drift phenomenon in electronic measurements is a key technical problem that needs to be addressed. The four signals output by the beam position probe (BPM) must undergo multiple stages, including front-end analog conditioning, ADC sampling, and digital signal processing, to obtain the final beam position information. Due to inconsistencies between RF devices and ADC chips, the gain of the four BPM signal processing channels varies with ambient temperature and humidity, ultimately leading to slow drift in the beam position measurement results.

[0004] To address the slow drift problem, current engineering applications employ a pilot signal compensation scheme in their per-loop position measurement processors. As shown in Figure 1, the existing pilot signal compensation scheme simultaneously feeds a reference signal (i.e., the pilot signal) with a frequency close to the main frequency component of the bundle signal but with known amplitude and phase into each BPM channel. Within the FPGA, both the pilot signal and the bundle signal's corresponding BPM signals undergo down-conversion (DDC), decimation filtering, and amplitude extraction using a coordinate rotating digital computer (CORDIC) to ultimately achieve position compensation.

[0005] Taking the Shanghai Synchrotron Radiation Facility (SSRF) as an example, the loop-by-loop position measurement processor processes the 500MHz signals output from the four ports A, B, C, and D of the BPM probe. The pilot signal is set at a frequency around 500MHz, between two 694kHz harmonics. This pilot signal follows almost the same system transmission path as the bundle signal in the spectrum. Due to their close frequencies, the pilot signal and the actual bundle signal are similarly affected by channel amplitude, phase, and gain drift. The mixed signal, coupled with the BPM signal, is then undersampled at 117MHz by the front-end analog conditioning module (i.e., the RF link) and the ADC sampling module to become an intermediate frequency (IF) signal.

[0006] Figure 2 illustrates the spectrum shifting process of the signal when the ADC sampling module undersamples, with a sampling rate fs of 117MHz. In Figure 2, the blue spectrum represents the bundled signal spectrum, which is shifted from 499.654MHz to 30.54MHz after undersampling by the ADC sampling module. The green spectrum represents the pilot signal spectrum, which is shifted from 501.3MHz to 32.18MHz after undersampling by the ADC sampling module.

[0007] Referring again to Figure 1, the BPM signal and pilot signal of each channel are extracted from the frequency domain in the FPGA. Then, the pilot signal and bundle signal are processed by downconversion (DDC), decimation filtering, and amplitude extraction by coordinate rotation digital computer (CORDIC) in the FPGA to obtain the amplitude and phase of the pilot signal and BPM signal. The BPM signal of each channel is normalized and compensated based on the pilot signal of each channel to eliminate inconsistencies between channels.

[0008] However, the existing pilot signal compensation schemes described above are not applicable to bunch-by-bunch processors. Loop-by-loop processors perform signal processing in the frequency domain, extracting the BPM signal and pilot signal separately. Figure 3 shows the timing diagram of the bunch-by-bunch signal obtained by the Shanghai Synchrotron Radiation Facility's bunch-by-bunch processor performing four-point sampling on the four-channel output of the BPM bunch signal at a sampling rate of 2 GHz. The horizontal axis of Figure 3 represents time, and the vertical axis represents the signal amplitude. Because bunch-by-bunch measurements require that adjacent bunch signals with a 2 ns interval not aliased, only time-domain processing is possible. The current method of coupling pilot signals in the frequency domain used in loop-by-loop processors cannot achieve separation; therefore, a new slow drift compensation scheme needs to be researched. Summary of the Invention

[0009] The present invention aims to provide a slow drift compensation method for bunch-by-bundle position measurement, so as to realize slow drift compensation for bunch-by-bundle measurement through pilot signal.

[0010] To achieve the above objectives, the present invention provides a slow drift compensation method for bundle-by-bundle position measurement, comprising:

[0011] S1: Construct a slow drift compensation circuit for bunch-by-bundle position measurement; the slow drift compensation circuit for bunch-by-bundle position measurement includes a fast switching circuit, an analog front end, an ADC module and a data processing module connected in sequence, as well as a pilot and clock signal generation circuit that simultaneously provides pilot signals, sampling clock signals and processing clock signals to the fast switching circuit, the ADC module and the data processing module respectively.

[0012] S2: Using the data processing module, the input signal of the fast switching circuit is switched to a BPM signal, and the data processing module is used to automatically detect the filling mode and obtain the mode mask of the filling mode.

[0013] S3: Use pilot and clock signal generation circuits to generate pilot signals; use data processing module to control fast switching circuit to switch the input signal between pilot signals and BPM signals according to the pattern mask of the filling mode;

[0014] S4: Using the data processing module, the BPM signal and pilot signal of each channel are processed at different times to obtain the calculated amplitude information of the bundle in each channel and the calculated amplitude of the pilot signal used to compensate for the bundle.

[0015] S5: The bundle signal is normalized and compensated using the calculated amplitude of the pilot signal used to compensate for the bundle signal, and the position information of the bundle is calculated using the difference ratio algorithm.

[0016] The frequency of the pilot signal is N times the cyclotron frequency; the sampling clock signal is L times the frequency of the processing clock signal, where L is the number of bus lines for interaction between the ADC module and the data processing module; the sampling clock signal is M times the pilot signal, where M is the sampling multiple for a single bundle.

[0017] The switching frequency of the fast-switching circuit reaches the nanosecond level.

[0018] The data processing module receives a processing clock signal as the reference clock for all its internal logic operations, and receives an external trigger signal from the accelerator as the start time of processing.

[0019] In step S2, the data processing module is used to automatically detect the fill pattern, specifically including: setting a threshold and confirming the fill pattern by threshold detection in the data processing module.

[0020] In step S2, an amplitude value is selected as a threshold between the amplitudes of the BPM signal with and without a bundle. When the amplitude is higher than the threshold, the mode mask of the filling mode is set to 1; when the amplitude is lower than the threshold, the mode mask of the filling mode is set to 0. A mode mask of 1 corresponds to the BPM signal with a bundle. In step S3, when the mode mask is 1, the data processing module controls the fast switching circuit to switch the access signal to the BPM signal; otherwise, the data processing module controls the fast switching circuit to switch the access signal to the pilot signal.

[0021] In step S2, detection stops when the sequence of the pattern mask satisfies the pre-set sequence cycle of the pattern mask, and then the process switches to step S3.

[0022] Step S3 further includes using a data processing module to adjust the pilot and clock signal generation circuits according to the amplitude of the detected BPM signal, so that the amplitude of the pilot signal is close to the amplitude of the BPM signal when there is a bundle.

[0023] For each channel, the calculated amplitude information of the bundle and the calculated amplitude of the pilot signal used to compensate the bundle are calculated by performing a square summation and square root operation on multiple sampling points of each pilot signal filled in each bundle and empty bundle. The calculated amplitude of the pilot signal used to compensate the bundle signal is obtained by averaging the calculated amplitude information of the pilot signals filled in all empty bundles during the gap period between two bundle strings.

[0024] The calculated amplitude of the pilot signal used to compensate for bunches is used to compensate for bunches after the gap period in which the pilot signal is located; the amplitude of the compensated bunches obtained by normalization compensation is A. C / A P A C For the calculation amplitude information of the bundle, A P The amplitude of the pilot signal used to compensate for the bundle signal is calculated.

[0025] The slow drift compensation method for bunch-by-bundle position measurement of the present invention achieves slow drift compensation for bunch-by-bundle measurement by injecting a pilot signal that does not overlap with the BPM signal in the time domain at the empty bunch position and processing it in the time domain. Attached Figure Description

[0026] Figure 1 is a hardware schematic diagram of an existing loop-by-loop position measurement processor.

[0027] Figure 2 is a schematic diagram of the signal spectrum shifting between the pilot signal and the bundle signal in an existing loop-by-loop position measurement processor.

[0028] Figure 3 is a timing diagram of the bundle signal obtained by four-point sampling of the bundle signal output from the four channels of BPM by the bundle processor of Shanghai Synchrotron Radiation Facility at a sampling rate of 2 GHz. The horizontal axis of Figure 3 is time, and the vertical axis is the signal amplitude value.

[0029] Figure 4 is a schematic diagram of a typical electron storage ring filling method when filling a cluster.

[0030] Figure 5 is a schematic diagram of the slow drift compensation method for bundle position measurement of the present invention during pilot insertion.

[0031] Figure 6 is a hardware schematic diagram of the slow drift compensation circuit used in the slow drift compensation method for bundle position measurement of the present invention.

[0032] Figure 7 is a schematic diagram of the threshold detection and filling mode confirmation of the slow drift compensation method for bundle position measurement of the present invention.

[0033] Figure 8 is a signal processing block diagram in FPGA for the slow drift compensation method for bundle position measurement of the present invention.

[0034] Figure 9 is a timing diagram of the actual bundle-by-bundle signal detected in step S2 by the slow drift compensation method for bundle-by-bundle position measurement of the present invention.

[0035] Figure 10 is a schematic diagram of the actual pattern mask sequence obtained in step S2 by the slow drift compensation method for bundle position measurement of the present invention. Detailed Implementation

[0036] The preferred embodiments of the present invention are given below with reference to the accompanying drawings and described in detail.

[0037] The slow drift compensation method for bundle-by-bundle position measurement in this invention is based on the following principle:

[0038] Cluster position measurement cannot be performed using traditional loop-by-loop processors for signal processing and slow drift compensation in the frequency domain because cluster position measurement requires that signals from adjacent clusters with a 2ns interval not overlap. The slow drift compensation method for cluster position measurement in this invention achieves slow drift compensation by injecting a pilot signal that does not overlap with the BPM signal in the time domain at the empty cluster position and processing it in the time domain.

[0039] In the process of filling the electron storage ring with clusters, the electron storage ring can theoretically be completely filled with clusters. However, if it is completely filled, it is easy to induce instability in the coupled clusters. Therefore, in actual operation, a long empty cluster position is left after the cluster string without injecting beam current. As shown in Figure 4, for example, the electron storage ring of the Shanghai Synchrotron Radiation Facility can theoretically be filled with 720 clusters. In actual operation mode, the electron storage ring is filled with four cluster strings containing 125 clusters each, with 55 empty clusters in the middle of the cluster strings (corresponding to 110 ns). Therefore, as shown in Figure 5, this invention utilizes these empty cluster positions to inject pilot signals that do not overlap with the BPM signal in the time domain, thereby separating the pilot signal and the BPM signal in the time domain and realizing slow drift compensation for cluster-by-cluster measurements.

[0040] As shown in Figure 6, the slow drift compensation method for bundle-by-bundle position measurement of the present invention specifically includes:

[0041] Step S1: Construct a slow drift compensation circuit for bundle position measurement;

[0042] As shown in Figure 6, the slow drift compensation circuit for the bundle position measurement includes a fast switching circuit 10, an analog front end 20, an ADC module 30, and a data processing module 40 connected in sequence, as well as a pilot and clock signal generation circuit 50 that simultaneously provides pilot signals, sampling clock signals, and processing clock signals to the fast switching circuit 10, the ADC module 30, and the data processing module 40, respectively.

[0043] The pilot and clock signal generation circuit 50 includes a digital phase-locked loop (PLL) chip, which generates a pilot signal, a sampling clock signal, and a processing clock signal. Specifically, the PLL receives an accelerator cyclotron frequency clock (frequency fr) provided by the accelerator timing mechanism as an external clock, multiplies it by N (N being the harmonic number) to generate a pilot signal (the pilot signal's frequency is fr × N), and then multiplies it again to generate a sampling clock signal required for sampling by the ADC module 30 and a processing clock signal required for synchronous processing with the data processing module 40. The pilot and clock signal generation circuit 50 may also include an amplifier and / or an attenuator for adjusting the amplitude of the pilot signal according to instructions from the data processing module 40.

[0044] The pilot signal has a frequency that is N times the cyclotron frequency (where N is the harmonic number), ensuring that the frequency difference between the pilot signal and the bundle signal is within 1kHz. Specifically, the pilot signal is obtained by directly multiplying the synchronous clock (which is a high-frequency frequency divided by N) by N times. The frequency error between the pilot signal and the bundle signal is determined by the phase-locked loop (PLL) chip, and the difference is generally within 1kHz. The sampling clock signal has a frequency that is L times the frequency of the processing clock signal, where L is the number of lines on the bus (JESD204B bus) used for interaction between the ADC module and the data processing module. The sampling clock signal also has a frequency that is M times the pilot signal, where M is the sampling multiple for a single bundle.

[0045] In this embodiment, the frequency of the current-carrying signal is 499.654MHz. The digital phase-locked loop (PLL) chip is preferably LMK04832 to generate the 2GHz sampling clock signal required by the ADC and the 250MHz processing clock signal required by the FPGA.

[0046] The fast switching circuit 10 is used to switch the access signal between the pilot signal and the BPM signal. In this embodiment, when the switch of the fast switching circuit 10 is open, the BPM signal is accessed; otherwise, the pilot signal is accessed. The switching frequency of the fast switching circuit 10 reaches the nanosecond level.

[0047] The analog front end 20 is used to preprocess the signal from the fast switching circuit 10 to remove noise and control the gain.

[0048] The ADC module 30 employs a high sampling rate ADC to achieve multi-point sampling of the bundled signal. Preferably, the ADC module 30 uses the AD9689 chip with a sampling rate set to 2GHz.

[0049] The data processing module 40 employs an FPGA, on which operating mode detection algorithms, switching control, and slow drift compensation are deployed. Preferably, the FPGA is a Xilinx Zynq UltraScale+ MPSoC ZU15EG. The data processing module 40 receives a processing clock signal as the reference clock for all its internal logic operations and receives an external trigger signal from the accelerator as the start time of processing. From the start time of processing, it controls the fast switching circuit 10 to switch between the BPM signal and the pilot signal, and can also adjust the amplitude of the pilot signal; it receives the signal after processing by the analog front-end 20 and high-speed sampling by the ADC.

[0050] Step S2: Perform automatic filling mode detection; that is, use the data processing module 40 to switch the access signal of the fast switching circuit 10 to a BPM signal, and use the data processing module 40 to automatically detect the filling mode and obtain the mode mask of the filling mode.

[0051] As shown in Figure 7, the automatic detection of the filling mode using the data processing module 40 specifically includes: setting a threshold and confirming the filling mode through threshold detection in the data processing module 40. Specifically, an amplitude value between the amplitudes of the BPM signal with and without a bundle is selected as the threshold. When the amplitude is higher than the threshold, the mode mask for the filling mode is set to 1; when it is lower than the threshold, the mode mask is set to 0, thus generating a mode mask in the form of 0s and 1s, consistent with the harmonic number. A mode mask of 1 corresponds to the BPM signal with a bundle. The threshold value is not fixed; for example, 80% of the maximum amplitude of the BPM signal with a bundle can be chosen as the threshold.

[0052] The actual BPM signal is shown in Figure 9, where the ADC sampling signal amplitude is around 5000, and an amplitude of 3500 is set as the threshold. Correspondingly, the mode mask detected in the data processing module 40 is shown in Figure 10. The filling mode is confirmed by the sequence of this mode mask, and pilot signals are filled at 0.

[0053] Step S3: Use the pilot and clock signal generation circuit 50 to generate a pilot signal; use the data processing module 40 to control the fast switching circuit 10 to switch the input signal between the pilot signal and the BPM signal according to the pattern mask of the filling mode.

[0054] When the mode mask is 1 (i.e., the mode mask corresponds to a bundled signal), the data processing module 40 controls the fast switching circuit 10 to switch the access signal to the BPM signal; otherwise, when the mode mask is 0, the data processing module 40 controls the fast switching circuit 10 to switch the access signal to the pilot signal. The switching rate of the fast switching circuit 10 reaches the nanosecond level.

[0055] In other words, during detection in step S2, the BPM signal needs to be continuously connected, while during detection in step S3, the signal needs to be switched between the BPM signal and the pilot signal. In this embodiment, in step S2, when the sequence of the mode mask satisfies the pre-set sequence cycle of the mode mask (i.e., a sequence cycle of X 1s + M 0s), the detection can be stopped (X and M correspond to 125 and 55 in the embodiment of the Shanghai Synchrotron Radiation Facility accelerator, as shown in Figure 4), and then the process switches to step S3. When the detection result in step S2 outputs the pre-set sequence (X 1s + M 0s) twice consecutively, step S2 is considered to be over. However, step S3 continues to output X 1s + M 0s. By counting, when a 0 is output, the switch is activated to connect the pilot signal. The state of step S3 must be maintained because the switch continuously switches to insert the pilot signal when the processor is working normally.

[0056] Furthermore, step S3 may also include: using the data processing module 40, adjusting the pilot and clock signal generation circuit 50 according to the amplitude of the detected BPM signal, so that the amplitude of the pilot signal is close to the amplitude of the BPM signal with a bundle. The ratio of the amplitude of the pilot signal to the amplitude of the BPM signal with a bundle is around 1, that is, within the range of 0.9-1.1. In this embodiment, the amplitude of the pilot signal sampled by the ADC module is around 5000.

[0057] Step S4: Using the data processing module 40, the BPM signal and pilot signal of each channel are processed at different times to obtain the calculated amplitude information of the bundle in each channel and the calculated amplitude of the pilot signal used to compensate for the bundle.

[0058] In Figure 7, the signal amplitudes of the 125 bunches are roughly the same, but because the bunch positions change, the amplitudes of the BPM signals in the four channels will differ, resulting in different measured bunch positions. Therefore, bunch-by-bundle measurement can measure position changes. There are a total of four probes, and the position information of each bunch is calculated using the amplitude information from these four probes.

[0059] For each channel, the calculated amplitude information of the bundle and the calculated amplitude of the pilot signal used to compensate for the bundle are calculated by performing a square summation and square root operation on multiple sampling points of each pilot signal filled in each bundle and empty bundle.

[0060] Taking channel A as an example, the formula for calculating the amplitude information of the bunch is Equation (1), the formula for calculating the amplitude information of the pilot signal filling the empty bunch is Equation (2), and the formula for calculating the amplitude of the pilot signal used to compensate for the bunch is Equation (3):

[0061] (1)

[0062] (2)

[0063] (3)

[0064] Among them, A Ci (i=1,2,...,N) represents the amplitude values ​​of N sampling points for a single bundle, A C For the calculated amplitude information of the bundle; A Pli (i=1,2,...,N) represent the amplitude values ​​of N sampling points of the pilot signal filling a single empty bundle, A Pl (l=1,2,...,M) represents the calculated amplitude information of the pilot signal filling a single empty bunch, where i and l are the sampling points and the count of the calculated amplitude information, respectively, and M indicates that there are M empty bunches during the gap between two bunch strings. A PThe amplitude of the pilot signal used to compensate for the bundle signal is calculated.

[0065] In other words, the calculated amplitude A of the pilot signal used to compensate for the bunch signal. P A is the calculated amplitude information A of the pilot signal filling all empty bunches during the gap between two bunch strings. Pl The result is obtained by averaging the measurement results of multiple pilot signals during the gap period. This is done by averaging and filtering the results to further improve the slow drift compensation performance of the pilot signals.

[0066] In this embodiment, N is 4, representing that one bunch corresponds to 4 sampling points, and M is 55, representing that one gap period contains 55 empty bunches.

[0067] Step S5: The bundle signal is normalized and compensated using the calculated amplitude of the pilot signal used to compensate for the bundle signal, and the position information of the bundle is calculated using the difference ratio algorithm. Thus, slow drift compensation is achieved, and the processing block diagram is shown in Figure 8.

[0068] In this embodiment, the calculated amplitude of the pilot signal used to compensate for the bunch is used to compensate for the bunch after the gap period in which the pilot signal is located. The amplitude of the compensated bunch obtained by normalization compensation is A. C / A P A C For the calculation amplitude information of the bundle, A P The amplitude of the pilot signal used to compensate for the bundle signal is calculated.

[0069] The positional information of the bunch includes its X and Y coordinates. Based on the difference ratio algorithm, the X and Y coordinates of the bunch are:

[0070] (4)

[0071] (5)

[0072] Where A C B C C C D C The calculation amplitude information for the bundles in channels A, B, C, and D, A P B P C P D P K is the calculated amplitude of the pilot signals used to compensate for the bundle signals in channels A, B, C, and D. X K Y These are all mechanical dimension-related constants of the BPM probe.

[0073] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of the invention. Various variations can be made to the above embodiments of the present invention. All simple and equivalent changes and modifications made in accordance with the claims and description of this application fall within the protection scope of the claims of this patent. All aspects not described in detail in this invention are conventional technical content.

Claims

1. A method for compensating for slow drift in bundle-by-bundle position measurement, characterized in that, include: Step S1: Construct a slow drift compensation circuit for bunch-by-bundle position measurement; the slow drift compensation circuit for bunch-by-bundle position measurement includes a fast switching circuit, an analog front end, an ADC module, and a data processing module connected in sequence, as well as a pilot and clock signal generation circuit that simultaneously provides pilot signals, sampling clock signals, and processing clock signals to the fast switching circuit, the ADC module, and the data processing module, respectively; Step S2: Using the data processing module, switch the input signal of the fast switching circuit to a BPM signal, and use the data processing module to automatically detect the filling mode and obtain the mode mask of the filling mode; Step S3 Step S4: Using a pilot and clock signal generation circuit, a pilot signal is generated; using a data processing module, based on the pattern mask of the filling mode, a fast switching switch circuit is controlled to switch the access signal between the pilot signal and the BPM signal; Step S5: Using a data processing module, the BPM signal and pilot signal of each channel are processed at different times to obtain the calculated amplitude information of the bunches in each channel and the calculated amplitude of the pilot signal used to compensate the bunches; Step S6: The calculated amplitude of the pilot signal used to compensate the bunches signal is used to normalize and compensate the bunches signal, and the position information of the bunches is calculated using the difference ratio algorithm.

2. The slow drift compensation method for bundle-by-bundle position measurement according to claim 1, characterized in that, The frequency of the pilot signal is N times the cyclotron frequency, where N is the harmonic number; the sampling clock signal is L times the frequency of the processing clock signal, where L is the number of bus lines for interaction between the ADC module and the data processing module; the sampling clock signal is M times the pilot signal, where M is the sampling multiple for a single bundle.

3. The slow drift compensation method for bundle-by-bundle position measurement according to claim 1, characterized in that, The switching frequency of the fast-switching circuit reaches the nanosecond level.

4. The slow drift compensation method for bundle-by-bundle position measurement according to claim 1, characterized in that, The data processing module receives a processing clock signal as the reference clock for all its internal logic operations, and receives an external trigger signal from the accelerator as the start time of processing.

5. The slow drift compensation method for bundle-by-bundle position measurement according to claim 1, characterized in that, In step S2, the data processing module is used to automatically detect the fill pattern, specifically including: setting a threshold and confirming the fill pattern by threshold detection in the data processing module.

6. The slow drift compensation method for bundle-by-bundle position measurement according to claim 5, characterized in that, In step S2, an amplitude value is selected as a threshold between the amplitudes of the BPM signal with and without a bundle. When the amplitude is higher than the threshold, the mode mask of the filling mode is set to 1; when the amplitude is lower than the threshold, the mode mask of the filling mode is set to 0. A mode mask of 1 corresponds to the BPM signal with a bundle. In step S3, when the mode mask is 1, the data processing module controls the fast switching circuit to switch the access signal to the BPM signal; otherwise, the data processing module controls the fast switching circuit to switch the access signal to the pilot signal.

7. The slow drift compensation method for bundle-by-bundle position measurement according to claim 1, characterized in that, In step S2, detection stops when the sequence of the pattern mask satisfies the pre-set sequence cycle of the pattern mask, and then the process switches to step S3.

8. The slow drift compensation method for bundle-by-bundle position measurement according to claim 1, characterized in that, Step S3 further includes using a data processing module to adjust the pilot and clock signal generation circuits according to the amplitude of the detected BPM signal, so that the amplitude of the pilot signal is close to the amplitude of the BPM signal when there is a bundle.

9. The slow drift compensation method for bundle-by-bundle position measurement according to claim 1, characterized in that, For each channel, the square summation and square root operation are performed on multiple sampling points of each pilot signal filled in each bundle and empty bundle to calculate the calculated amplitude information of the bundle and the calculated amplitude of the pilot signal used to compensate for the bundle. The calculated amplitude of the pilot signal used to compensate for the bunch signal is obtained by averaging the calculated amplitude information of the pilot signals filling all empty bunches during the gap period between two bunch strings.

10. The slow drift compensation method for bundle-by-bundle position measurement according to claim 1, characterized in that, The calculated amplitude of the pilot signal used to compensate for bunches is used to compensate for bunches after the gap period in which the pilot signal is located. The amplitude of the compensated bundle obtained by normalization compensation is A. C / A P A C For the calculation amplitude information of the bundle, A P The amplitude of the pilot signal used to compensate for the bundle signal is calculated.

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