Photonic stack for multilayer photonic integrated circuit package assembly

Abstract

Multi-layer photonic integrated circuit (PIC) die package assemblies and related devices, systems, and methods of manufacture are disclosed. A package assembly includes a lower layer having a base PIC die that provides at least some functionality of a PIC core or unit. A photonic coupler is in an upper layer of the package assembly and optically connects the assembly to an external optical device. At least one intermediate layer of the package assembly is between the base PIC die and the photonic coupler, including PIC die (s), electronic integrated circuit (EIC) die (s), or hybrid photonic and electronic IC (hybrid IC) die (s), or a combination thereof. The interlayer die (s) may provide the remaining functionality of the PIC core or unit. A photonic via extends vertically through the intermediate layer and optically couples the PIC die and the photonic coupler.

Description

BACKGROUND

[0001] Photonic integrated circuits are becoming increasingly important in high performance computing, data center, and cloud computing applications. Currently, photonic packages include monolithic photonic integrated circuits (PICs) that have a larger form factor than electronic integrated circuits (EICs), which increases the package form factor in the x-y plane. This leads to assembly difficulties, particularly where hybrid bonding is to be used, and attachment difficulties for optical couplers. For example, the different form factors of EICs and PICs prevent wafer-to-wafer bonding of source wafers containing both types of dies, and attachment of optical couplers is typically done on a non-planar surface and must avoid contact with the overlying EIC.

[0002] Difficulties in packaging and coupling photonic circuits to other devices remain. It is with respect to these and other considerations that the improvements presented herein have been made. BRIEF DESCRIPTION OF DRAWINGS

[0003] The materials described herein are illustrated by way of example and not limitation in the accompanying drawings. The elements shown in the figures can not necessarily be to scale. For example, the dimensions of some of the elements can be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals have been repeated among the figures to indicate corresponding or analogous elements (e.g., functions thereof). In the drawings: Figure 1 is an illustration of a cross-sectional side view of a PIC assembly having a multi-layer architecture with hybrid photonic and electronic integrated circuit dies; Figure 2 is an illustration of a cross-sectional side view of a PIC assembly having a multi-layer architecture with discrete photonic and electronic integrated circuit dies; Figure 3 is an illustration of a cross-sectional side view of a PIC assembly having a multi-layer architecture with discrete electronic integrated circuit dies and photonic vias extending through laterally adjacent fill material; Figure 4 is an illustration of a cross-sectional side view of a PIC assembly having a multi-layer architecture with photonic vias through the dies and photonic vias through the fill material; Figure 5 is a flowchart illustrating an example method for fabricating and assembling a PIC structure including vertically aligned photonic vias; Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 、 Figure 11 ,Figure 15 、 Figure 16 、 Figure 17 、 Figure 21 、 Figure 24 、 Figure 26 and Figure 27 are illustrations of cross-sectional side views of photonic structures when practicing the method of Figure 5 to form photonic vias; Figure 10 is a top view of the photonic structure of Figure 9 illustrating cylindrical photonic vias; Figure 12 is a top view of the photonic structure of Figure 11 illustrating a grid of cylindrical photonic vias; Figure 13 is a top view of the photonic structure of Figure 9 illustrating photonic vias with square cross-sections; Figure 14 is a top view of the photonic structure of Figure 11 illustrating a grid of cylindrical photonic vias with square cross-sections; Figure 18 is a top view of the photonic structure of Figure 17 illustrating photonic vias with each having an outer material and an inner material each with a circular cross-section; Figure 19 is a top view of the photonic structure of Figure 17 illustrating photonic vias with an outer material with a square cross-section and an inner material with a circular cross-section; Figure 20 is a top view of the photonic structure of Figure 17 illustrating photonic vias with an outer material with a circular cross-section and an inner material with a square cross-section; Figure 22 is a top view of the photonic structure of Figure 21 illustrating a grid of photonic vias each with an outer material and an inner material each with a circular cross-section; Figure 23 is a top view of the photonic structure of Figure 21 illustrating a grid of photonic vias each with an outer material with a circular cross-section and an inner material with a square cross-section; Figure 25 is a top view of the photonic structure of Figure 24 illustrating a grid of photonic vias each with a cylindrical material within a bulk material; Figure 28 、 Figure 29 、 Figure 30 、 Figure 31 and Figure 32 are illustrations of cross-sectional side views of photonic structures when practicing the method of Figure 5a method of assembling a multilayer photonic assembly with a photonic via; Figure 33 an exemplary system employing a photonic via in a multilayer photonic assembly is illustrated; and Figure 34 is a block diagram of a computing device arranged in accordance with at least some implementations of the present disclosure. DETAILED DESCRIPTION

[0004] One or more embodiments or implementations are now described with reference to the enclosed figures. While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Persons skilled in the relevant art will recognize that other configurations and arrangements can be employed without departing from the spirit and scope of the description. It will be apparent to those skilled in the relevant art that techniques and / or arrangements described herein can also be employed in a variety of other systems and applications other than what is described herein.

[0005] Reference is made in the following detailed description to the accompanying drawings, which form a part hereof, wherein like numerals can designate like parts throughout the various figures. It will be appreciated that for simplicity and / or clarity of illustration, elements illustrated in the figures can not necessarily be drawn to scale. For example, the dimensions of some of the elements can be exaggerated relative to other elements. In addition, it will be understood that other embodiments can be utilized and that structural and / or logical changes can be made without departing from the scope of the claimed subject matter. It should also be noted that the direction and reference terms, such as, for example, upper, lower, top, bottom, above, below, and the like, can be used in the description and the drawings for purposes of clarity and convenience and are not intended to limit the claimed subject matter to any one spatial arrangement or orientation.

[0006] In the following description, numerous specific details are set forth. However, it is understood that the invention can be practiced without these specific details. In some instances, well-known methods and devices are not described in detail in order not to obscure the invention. Where reference is made to an "embodiment" or "one embodiment", it means that a particular feature, structure, function, or characteristic described in connection with the embodiment is included in at least one implementation of the invention. The appearances of the phrase "in one embodiment" or "in an embodiment" in various places in the specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, functions, or characteristics can be combined in any suitable manner in one or more embodiments. For example, a first embodiment can be combined with a second embodiment in any manner that the particular features, structures, functions, or characteristics associated with the first embodiment and the second embodiment are not mutually exclusive.

[0007] The singular forms "a," "an," and "the" as used in the specification and the appended claims are intended to include plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "and / or," as used herein, refers to and encompasses any and all possible combinations of one or more of the associated listed items. In this document, the term "primarily" indicates that a particular material or component is not less than 50%, the term "substantially pure" indicates that a particular material or component is not less than 99%, and the term "pure" indicates that a particular material or component is not less than 99.9%. Such material percentages are based on atomic percentages unless otherwise indicated. In this document, the term concentration is used interchangeably with material percentage and also indicates atomic percentage unless otherwise indicated.

[0008] The terms "coupled" and "connected," along with their derivatives, can be used herein to describe structural relationships between components. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, "connected" can be used to indicate that two or more elements are in direct physical or electrical contact with each other. "Coupled" can be used to indicate that two or more elements are in either direct physical or electrical contact with each other, or that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other (e.g., as in a causal relationship).

[0009] The terms "over," "under," "between," and "on" as used herein refer to a relative position of one material layer or component with respect to other layers or components. For example, a layer disposed over or under another layer can be directly in contact with that other layer, or one or more intervening layers can also be present. Moreover, a layer disposed between two layers can be directly in contact with the two layers or there can be one or more intervening layers present. In contrast, a first layer "on" a second layer is in direct contact with that second layer. Similarly, unless otherwise explicitly stated, a feature disposed between two features means that feature can be directly in contact with the adjacent features or there can be one or more intervening features. The term "adjacent" indicates that such features are directly in contact. Furthermore, the terms "substantially," "approximately," "near," "about," and "nearly" are often used to describe a value or condition close to a target value or condition. The term "layer" as used herein can include a single material or multiple materials. As used throughout this specification and in the claims, a list of items joined by the term "at least one of' or "one or more of' can mean any single one of the listed items but can also mean any combination of two or more of the listed items. For example, the phrases "at least one of A, B, or C" or "one or more of A, B, or C" can mean A; B; C; A and B; A and C; B and C; or A, B, and C.

[0010] Photonics integrated circuit structures, hybrid devices, apparatuses, systems, and methods are described herein that involve assembling and packaging a photonics integrated circuit by disassembling a photonics integrated circuit die and assembling the photonics integrated circuit die using photonics vias.

[0011] As described above, a photonics integrated circuit (PIC) such as a PIC die can be assembled into a hybrid system that includes the PIC die and an electronic integrated circuit (EIC) die. The assembly includes a photonic coupler that is connected to an external fiber, waveguide, or other photonic device. The form factor of the package and assembly are important considerations. In some embodiments, the PIC is folded into a stack of two or more fused or hybrid bonded components that use photonics vias (photonics through vias, PTVs). In some embodiments, a base PIC contains some of the PIC functionality, while a top PIC (a PIC on the base PIC, which can be disposed in an intermediate layer of a multi-layer package) contains the remaining PIC functionality. For example, the base PIC and the top PIC can form a PIC core, a PIC cell, or a PIC intellectual property (IP) block, such that the base PIC and the top PIC provide one PIC capability cell that is a fully functional interface (input / output) for any number of PIC tasks. A photonic coupler can be attached on or above the top PIC to provide coupling to an external device such as a laser source, a fiber, or other photonic device. For example, the base PIC can be in a lower layer of a multi-layer assembly, the top PIC can be in an intermediate layer of the multi-layer assembly, and the photonic coupler can be in an upper layer of the multi-layer assembly.

[0012] In some embodiments, optical coupling between the photonic coupler and the base PIC is provided using photonics vias that extend vertically between the photonic coupler and the base PIC. For example, the photonic coupler and the base PIC can vertically overlap (i.e., have an overlap when projected onto a horizontal plane), and any number of photonics vias can couple the photonic coupler and the base PIC by extending vertically between a lower surface of the photonic coupler and an upper surface of the base PIC. The photonics via(s) can extend through the top PIC, a fill material laterally adjacent to the top PIC, or both. The material(s) of the photonics via are selected to provide total internal reflection within the photonics via relative to surrounding materials. The one or more photonics vias can be a single material within the surrounding materials, or the photonics via can include two coaxial materials, as discussed further herein.

[0013] The multi-layer photonics stack and corresponding photonics vias provide various advantages, including improved optimization of the PIC and package form factor, enabling wafer-to-wafer bonding in some contexts, simplifying photonic coupler attachment due to removal of surface topography, and other advantages.

[0014] Figure 1This is a cross-sectional side view of a PIC assembly 100 having a multilayer architecture with hybrid photonics and electronic integrated circuit dies, arranged according to at least some implementations of this disclosure. Figure 1 As shown, the basic PIC die 101 is in the lower layer 151 of the multilayer architecture of the PIC assembly 100, and the photonic coupler 103 is in the upper layer 153 of the multilayer architecture of the PIC assembly 100. Between the lower layer 151 and the upper layer 153, the PIC assembly 100 may include any number of intermediate layers, such as an intermediate layer 152. In the context of the PIC assembly 100, the terms upper, lower, and intermediate are used to indicate the relative positions of the layers. It is worth noting that the lower layer and the upper layer are not necessarily the lowest and / or highest layers of the PIC assembly 100, although in some embodiments, the lower layer 151 is the lowest layer of the PIC assembly 100 and / or the upper layer 153 is the highest layer of the PIC assembly 100.

[0015] As shown in the figure, the basic PIC die 101 has an upper surface 111 and a lower surface 112, both of which are substantially parallel to the horizontal plane (i.e., the xy plane) of the PIC assembly 100. The basic PIC die 101 also has an edge 117 extending between and orthogonal to the upper surface 111 and the lower surface 112 (i.e., edge 117 extends in the vertical or z-direction, orthogonal to the horizontal plane or the xy plane). In some embodiments, the basic PIC die 101 is a PIC or integrated optical circuit having two or more photonic components that form at least a portion of a functional circuit, enabling the basic PIC die 101 to detect, generate, transmit, and process light. The basic PIC die 101 may include some or all of any functional block, cell, IP block, or the like. The basic PIC die 101 may be any suitable material, such as silicon, although other material systems may be used. In some embodiments, the base PIC die 101 includes some of the overall PIC functionality, while another die deployed in the intermediate layer 152 contains the remaining PIC functionality to build a complete functional block, cell, IP block, or the like. For example, the base PIC die 101 and one or more dies in the intermediate layer 152 may together form a photonic functional block, cell, IP block, or the like.

[0016] The PIC assembly 100 also includes a photonic coupler 103 in the upper layer 153 of the PIC assembly 100. The photonic coupler 103 has an upper surface 131 and a lower surface 132, both of which are substantially parallel to the horizontal plane (x-y plane) of the PIC assembly 100, and the photonic coupler 103 includes an edge 137 extending between and normal to the upper surface 131 and the lower surface 132. The photonic coupler 103 can be of any suitable substrate material and structure. In some embodiments, the photonic coupler 103 is or includes a glass core substrate having optical waveguides formed therein, such that the optical waveguides extend in the x-y plane. In some embodiments, optical routing to and from the PIC assembly 100 is provided via optical connections 105 optically coupled with the photonic coupler 103, where the optical connections 105 can be optical fibers extending through the edge 137 of the photonic coupler 103. For example, light can be received from the optical connections 105, routed through the photonic coupler 103, and routed through the intermediate layer 152 to the die(s) of the intermediate layer 152 (as described below) and to the base PIC die 101 for processing. Electrical signals resulting therefrom can be routed from the PIC assembly 100 using package-level interconnects (not shown) known in the art. Photonic signals resulting therefrom can be routed through the optical connections 105 or another optical connection of the PIC assembly 100.

[0017] The photonic coupler 103 can include a glass substrate body (which can be characterized as a glass layer) and any number of optical waveguides or similar optical features formed on or within the glass substrate body. Although discussed herein with respect to optical waveguides, the photonic coupler 103 can include any optical features or couplers. In some embodiments, the photonic coupler 103 includes a glass layer (e.g., a glass core). In some embodiments, the glass layer of the photonic coupler 103 is an amorphous solid glass layer. In some embodiments, the glass layer is one of an aluminosilicate, a borosilicate, an aluminoborosilicate, quartz, and fused quartz. The glass layer can include one or more of an additive including AI2O3, B2O3, MgO, CaO, SrO, BaO, SnO2, Na2O, K2O, P2O3, ZrO2, Li2O, Ti, or Zn. For example, the glass layer can include an additive including one or more of aluminum, boron, magnesium, calcium, strontium, barium, tin, sodium, potassium, phosphorus, zirconium, lithium, titanium, or zinc. In some embodiments, the glass layer can include silicon and oxygen, and one or more of aluminum, boron, magnesium, calcium, strontium, barium, tin, sodium, potassium, phosphorus, zirconium, lithium, titanium, and zinc. In some embodiments, the glass layer includes at least 23% silicon and at least 26% oxygen by weight, and further includes at least 5% aluminum by weight. In some embodiments, the glass layer is rectangular in shape in plan view. However, other shapes can be used. In some embodiments, the glass layer is free of any organic binder or other organic material.

[0018] As discussed, the PIC assembly 100 also includes any number of intermediate layers, such as intermediate layer 152. Further, the optical signal is routed through the intermediate layer 152 using a photonic via 104 that extends vertically through any number of intermediate layers, such as the intermediate layer 152, to interconnect the photonic coupler 103 and the base PIC die 101. The photonic via 104 can span any number of intermediate layers, such as the intermediate layer 152. As shown, the photonic via 104 optically couples the base PIC die 101 and the photonic coupler 103. The photonic via 104 extends from the upper surface 111 of the base PIC die 101 substantially normal to the horizontal x-y plane of the PIC assembly 100 to the lower surface 132 of the photonic coupler 103 and through one or more intermediate layers of the PIC assembly 100, such as the intermediate layer 152. The intermediate layer(s) 152 can include any number of horizontally aligned dies as illustrated herein.

[0019] In Figure 1In some embodiments, the intermediate layer 152 of the PIC assembly 100 includes a hybrid photonic and electronic integrated circuit (hybrid IC) die 102 of the PIC assembly 100, such that one or more of the photonic vias 104 extend through the hybrid IC die 102. The hybrid IC die 102 can be of any suitable material, such as silicon, although other material systems can be used. As used herein, the term hybrid IC die indicates a monolithic die having both PIC and EIC functionality. As used herein, the term PIC or PIC functionality indicates a circuit module that detects, generates, transmits, and / or processes light. The term EIC or EIC functionality indicates a circuit module that processes electrical signals. The term hybrid or hybrid functionality indicates a circuit module (integrated or non-integrated) that provides both photonic and electronic functionality. As used herein, the term PIC die indicates a monolithic die or structure that provides only photonic functionality (without electronic functionality, except for power supplies for the photonic functionality, such as a power supply for a laser source). The term EIC die indicates a monolithic die or structure that provides only electronic functionality (without photonic functionality). The term hybrid die indicates a monolithic die or structure that provides both electronic and photonic functionality. In some embodiments, a PIC die or hybrid die contains only a portion of a fully functional block, cell, IP block, or the like, without some features of the fully functional block, cell, or IP block. In such a context, two or more PIC dies and / or hybrid dies can together form a fully functional block, cell, IP block, while none of them individually can. Notably, the PIC assembly 100 can decompose such functionality to reduce the footprint of the underlying PIC die 101. In the context of the PIC assembly 100, the hybrid IC die 102 and the underlying PIC die 101 together form a PIC IP block, PIC core, PIC cell, or the like.

[0020] The hybrid IC die 102 has an upper surface 121 and a lower surface 122, both substantially parallel to the horizontal x-y plane of the PIC assembly 100. An edge 127 of the hybrid IC die 102 extends between the upper surface 121 and the lower surface 122, and is orthogonal thereto (i.e., the edge 127 extends in a vertical or z-direction, orthogonal to the horizontal or x-y plane). In some embodiments, the photonic coupler 103 is on the hybrid IC die 102, and the hybrid IC die 102 is on the underlying PIC die 101, such that the lower surface 132 of the photonic coupler 103 is on the upper surface 121 of the hybrid IC die 102, and the lower surface 122 of the hybrid IC die 102 is on the upper surface 111 of the underlying PIC die 101. However, other intervening intermediate layers can be deployed.

[0021] As shown, monolithic hybrid IC die 102 can include an electronic portion 123 and a photonic portion 124 separated by a boundary 125. In some embodiments, photonic vias 104 extend only through photonic portion 124 of hybrid IC die 102, and electronic portion 123 is free of any photonic vias. However, other layouts and architectures can be used. Photonic coupler 103 has a footprint 141, and base PIC die 101 has a footprint 142, such that the footprints are the horizontal areas of the components or the vertical projections of the components on the horizontal x-y plane. As shown, footprint 141 of photonic coupler 103 is over one region of hybrid IC die 102 (i.e., footprints 141, 142 vertically overlap). In some embodiments, the overlapping region (in this case, all of footprint 141) includes a plurality of photonic vias 104, while a second region of hybrid IC die 102 (a region outside of footprint 141) is free of any photonic vias, and there is no photonic coupler 103 over the second region. The bonding between hybrid IC die 102 and base PIC die 101 can be any suitable bonding, such as hybrid bonding, solder bonding, or fusion bonding. In some embodiments, hybrid or solder bonding is used between electronic portion 123 and base PIC die 101, while hybrid or fusion bonding is used between photonic portion 124 and base PIC die 101.

[0022] As also shown, hybrid IC die 102 and base PIC die 101 can share the same dimensions in the horizontal x-y plane, such that footprint 142 is shared by hybrid IC die 102 and base PIC die 101. In some embodiments, hybrid IC die 102 is coupled to base PIC die 101 using wafer-to-wafer bonding, and the stack illustrated with respect to PIC assembly 100 (without photonic coupler 103) is simultaneously singulated or diced from the bonded wafers. For example, edge 117 of base PIC die 101 and edge 127 of hybrid IC die 102 can be formed in the same singulation operation (such as a sawing operation), such that edge 117 and edge 127 are vertically aligned.

[0023] As discussed, portions of PIC functionality of base PIC die 101 can be moved to PIC functionality of intermediate layer 152. In some embodiments, intermediate layer 152 is a hybrid IC die that is coupled to base PIC die 101 using wafer-to-wafer bonding, and the stack illustrated with respect to PIC assembly 100 (without photonic coupler 103) is simultaneously singulated or diced from the bonded wafers. For example, edge 117 of base PIC die 101 and edge 127 of hybrid IC die 102 can be formed in the same singulation operation (such as a sawing operation), such that edge 117 and edge 127 are vertically aligned. Figure 1In the context of PIC assembly 100, this PIC functionality is moved to hybrid IC die 102. In some embodiments, the EIC functionality as well as the PIC functionality offloaded from base PIC die 101 is part of the same die (hybrid IC die 102), such that electronic portion 123 and photonic portion 124 are fabricated on the same wafer. In some embodiments, the fabricated wafer is then bonded to base PIC die 101. The bonding interface can include, for example, hybrid bonding or fusion bonding. In some embodiments, the two die sizes (i.e., the size of hybrid IC die 102 and base PIC die 101) are a perfect match to enable wafer-to-wafer bonding, facilitating assembly and increasing yield. As also shown, a flat surface (i.e., upper surface 121) is provided for attachment of photonic coupler 103, which eliminates some of the challenges when photonic coupler 103 has to be bonded to a surface with topography. As shown, photonic via 104 can be formed first through hybrid IC die 102. Techniques for forming such photonic vias 104 are discussed herein below.

[0024] Figure 2 is a view of a cross-sectional side view of a PIC assembly 200 having a multi-layer architecture with discrete photonic and electronic integrated circuit dies, arranged in accordance with at least some implementations of the present disclosure. Herein, like components are labeled with the same reference numerals, and such components can have any of the features or characteristics discussed throughout. In the context of PIC assembly 200, hybrid IC die 102 is replaced by EIC die 201, PIC die 202, and filler material 203 in middle layer 152. As shown, both EIC die 201 and PIC die 202 are in middle layer 152, and are laterally adjacent (i.e., substantially aligned in the horizontal x-y plane).

[0025] As shown, base PIC die 101 is in lower layer 151, and photonic coupler 103 is in upper layer 153. As with PIC assembly 100, photonic via 104 couples lower surface 132 of photonic coupler 103 to upper surface 111 of base PIC die 101. In the context of PIC assembly 200, photonic via 104 extends through PIC die 202 (e.g., the top PIC die), which is in middle layer 152. As also shown, EIC die 201 does not have any photonic vias. As discussed, base PIC die 101 is a PIC or integrated optical circuit having two or more photonic components that form at least a partially functional photonic circuit. In some embodiments, base PIC die 101 includes a portion of the overall PIC functionality, while PIC die 202 contains the remaining PIC functionality, which together establish a fully functional block, cell, IP block, or the like.

[0026] In some embodiments, the PIC die 202 is coupled to the base PIC die 101 by optical coupling structures 216, which can be part of the fusion bond between the PIC die 202 and the base PIC die 101. In some embodiments, the bond between the PIC die 202 and the base PIC die 101 is a hybrid bond. Further, the PIC assembly 200 includes a photonic coupler 103 in the upper layer 153 that is coupled to the base PIC die 101 by a photonic via 104. In the PIC assembly 200, the photonic via 104 extends from the upper surface 121 of the base PIC die 101 substantially normal to the horizontal x-y plane of the PIC assembly 200 to the lower surface 132 of the photonic coupler 103 and through one or more intervening layers, such as the intervening layer 152, of the PIC assembly 200. The intervening layer(s) 152 can include any number of horizontally aligned dies, such as the PIC die 202 and the EIC die 201.

[0027] The EIC die 201 can include any suitable electronic integrated circuit functionality, such as a processor, a memory, a controller, or a combination thereof. As shown, the EIC die 201 has an upper surface 211 and a lower surface 212, both of which are substantially parallel to the horizontal x-y plane of the PIC assembly 200. The lower surface 212 of the EIC die 201 is bonded to the upper surface 121 of the base PIC die 101. Such a bond can be a hybrid bond including metal (i.e., copper) bond structures 215 (which provide signal routing) interspersed in a dielectric bond (see Figure 3 ). In some embodiments, the bond between the EIC die 201 and the base PIC die 101 is a solder bond. The EIC die 201 also has an edge 217 extending between and normal to the upper surface 211 and the lower surface 212. The EIC die 201 can be of any suitable material, such as silicon, although other material systems can be used. For example, the EIC die 201 can include interconnect transistors in a device layer, and the EIC die 201 can include other devices, such as diodes, capacitors, solid state memory devices, or the like.

[0028] In Figure 2In the embodiment shown, the middle layer 152 of the PIC assembly 200 includes a discrete EIC die 201 and a discrete PIC die 202, such that each is a monolithic IC die or device. As discussed, the EIC die is a die or structure that provides only electronic functionality, while the PIC die is a die or structure that provides only photonic functionality, except for power supplies needed to power the photonic functionality (such as a power supply for a laser source). A fill material 203 is laterally between the EIC die 201 and the discrete PIC die 202, such that the fill material 203 is on the edges 127, 217. The fill material 203 can be any suitable material. In some embodiments, the fill material 203 is an organic material, such as a molding material. In some embodiments, the fill material 203 is an inorganic material, such as silicon oxide (i.e., comprising silicon and oxygen), silicon nitride (i.e., comprising silicon and nitrogen), silicon carbon nitride (i.e., comprising silicon, carbon, and nitrogen), aluminum nitride (i.e., comprising aluminum and nitrogen), or the like. In some embodiments, the fill material 203 extends to an edge 227 that is aligned with the edge 117 of the base PIC die 101.

[0029] The photonic coupler 103 has a footprint 141, the PIC die 202 has a footprint 242, the EIC die 201 has a footprint 241, and the base PIC die 101 has a footprint 243. As shown, the footprints 241, 141 can be within the footprint 243, and the area and perimeter established by the fill material 203 can share the footprint 243. In some embodiments, the EIC die 201 and the PIC die 202 are coupled to the base PIC die 101 using die-to-wafer bonding, the fill material 203 is deposited and planarized, and the stack illustrated with respect to the PIC assembly 200 (without the photonic coupler 103) is simultaneously singulated or diced from the bonding wafer. For example, the edge 117 of the base PIC die 101 and the edge 227 of the fill material 203 can be formed in the same singulation operation (such as a sawing operation), with the edge 117 and the edge 227 being vertically aligned.

[0030] As discussed, portions of the PIC functionality of the base PIC die 101 can be moved to the PIC functionality of the middle layer 152. For example, the base PIC die 101 can include a laser source, and the PIC die 202 can include a photonic modulator. In some embodiments, the base PIC die 101 includes a laser source and a photonic modulator, and the PIC die 202 includes a photonic modulator. In some embodiments, the base PIC die 101 includes a laser source and a photonic modulator, and the PIC die 202 includes a photonic modulator and a photonic detector. Figure 2PIC functionality is moved to the PIC die 202 in the context of this PIC assembly 200. In some embodiments, the EIC die 201 and the PIC die 202 are fabricated as separate dies that are separately bonded to the base PIC die 101, and the gap between them is filled with a fill material 203, such as an organic (e.g., molding) or inorganic (e.g., silicon oxide, silicon nitride, silicon carbon nitride, aluminum nitride, or the like) material. In some embodiments, the top surface is then planarized, and the photonic coupler 103 is attached to form the PIC assembly 200. Embodiments of the PIC assembly 200 provide greater flexibility in fabricating the top PIC die 202 and the EIC die 201 (i.e., they can be fabricated using different process nodes), as well as the shape factor and photonic coupler 103 attachment benefits described above, at the cost of requiring die-to-wafer or die-to-die bonding. As shown, the photonic via 104 can be formed first through the PIC die 202, as discussed herein. The bonding interface between the EIC die and the base PIC die can include a hybrid bond or a solder bond. The bonding interface between the top PIC die and the base PIC die can include a hybrid bond or a fusion bond.

[0031] Figure 3 is a diagram of a cross-sectional side view of a PIC assembly 300 with a multi-layer architecture with a discrete electronic integrated circuit die and a photonic via extending through a laterally adjacent fill material, arranged in accordance with at least some implementations of the present disclosure. In the context of the PIC assembly 300, the middle layer 152 includes the discrete EIC die 201 and the fill material 203 laterally adjacent to the EIC die 201. In the PIC assembly 300, the middle layer 152 is devoid of any PIC die, and the photonic via 304 extends through the fill material 203.

[0032] The base PIC die 101 is in the lower layer 151, and the photonic coupler 103 is in the upper layer 153, with the photonic via 304 coupling the lower surface 132 of the photonic coupler 103 to the upper surface 111 of the base PIC die 101. The photonic via 304 extends through the fill material 203, and the EIC die 201 is devoid of any photonic via. In some embodiments, the photonic via 304 can be characterized as a photonic via through a fill material, and the photonic via 104 can be characterized as a photonic via through a die or a photonic via through silicon.

[0033] As shown, the lower surface 212 of the EIC die 201 is bonded to the upper surface 111 of the base PIC die 101. For example, the EIC die 201 can be hybrid bonded to the base PIC die 101 such that the hybrid bond includes the metal bonding structure 215 dispersed in the dielectric bonding structure 315. In some embodiments, the bond between the EIC die 201 and the base PIC die 101 is a solder bond. In some embodiments, the bond between the top PIC die 202 and the base PIC die 101 is a fusion bond.Figure 3 In an embodiment of the PIC assembly 300, the middle layer 152 includes the EIC die 201 and the fill material 203 laterally adjacent the EIC die 201. In some embodiments, the fill material 203 extends to an edge 227 that is aligned with the edge 117 of the base PIC die 101.

[0034] For example, the photonic coupler 103 has a footprint 141, the EIC die 201 has a footprint 241, and the base PIC die 101 has a footprint 243 that matches the footprint 141 in an example. However, in some embodiments, the footprint 141 can be smaller than the footprint 243, such that the photonic coupler 103 only partially vertically overlaps the base PIC die 101. For example, the photonic via 304 can be provided within the overlap region. As shown, the footprint 241 is within the footprint 243, and the footprint established by the fill material 203 can share the footprint 243. In some embodiments, the EIC die 201 is coupled to the base PIC die 101 using a die-to-wafer bonding, the fill material 203 is deposited and planarized, the photonic via is fabricated, and the stack illustrated with respect to the PIC assembly 300 (without the photonic coupler 103) is simultaneously singulated or diced from the bonded wafer. For example, the edge 117 of the base PIC die 101 and the edge 227 of the fill material 203 can be formed in the same singulation operation, such that the edge 117 and the edge 127 are vertically aligned, as discussed above. Figure 3

[0035] In the context of the PIC assembly 300, there is no PIC die deployed in the middle layer 152 (i.e., no top PIC die). As discussed, the EIC die 201 is attached to the base PIC die 101 using, for example, a die-to-wafer or die-to-die bonding, and the fill material 203 is formed in the empty area surrounding the EIC die 201 using gap filling. Advantageously, the size of the base PIC die 101 is made smaller by using the photonic via 304 (i.e., a photonic through via) that creates a direct vertical optical interconnect from the base PIC die 101 to the photonic coupler 103 through the fill material 203 (rather than using a larger portion of the horizontal x-y area of the base PIC die 101 to directly couple light to the photonic coupler).

[0036] Figure 4 ​is a diagram of a cross-sectional side view of a PIC assembly 400 having a multi-layer architecture with photonic vias through a die and photonic vias through a fill material, arranged in accordance with at least some implementations of the present disclosure. In the context of the PIC assembly 400, the middle layer 152 includes the EIC die 201, the PIC die 202 having photonic vias 104, and the fill material 203 having photonic vias 304. In some contexts, the middle layer 152 can include photonic vias 304 disposed through the fill material 203 adjacent to the hybrid IC die 102.

[0037] As shown, the base PIC die 101 is in the lower layer 151, the photonic coupler 103 is in the upper layer 153, and the photonic vias 104, 304 couple the lower surface 132 of the photonic coupler 103 to the upper surface 111 of the base PIC die 101. In the context of the PIC assembly 400, the photonic vias 104 extend through the PIC die 202 (e.g., the top PIC die), and the photonic vias 304 extend through the fill material 203, with the EIC die 201 having no photonic vias. In some embodiments, the base PIC die 101 includes a portion of the overall PIC functionality, while the PIC die 202 contains the remaining PIC functionality, which together establish a fully functional block, cell, IP block, or the like.

[0038] The PIC die 202 is coupled to the base PIC die 101 by, for example, optical coupling structures 216, which can be part of a fusion or hybrid bond between the PIC die 202 and the base PIC die 101, and the EIC die 201 is bonded to the base PIC die 101 by, for example, metallic bonding structures 215 of the hybrid bond or by a solder bond. In some embodiments, the PIC die 202 is a top PIC die, and the EIC die 201 is a bottom EIC die. Figure 4In embodiments, the middle layer 152 of the PIC assembly 400 includes the EIC die 201 and the discrete PIC die 202, such that each is a monolithic IC die or device, and the fill material 203 is laterally between the EIC die 201 and the discrete PIC die 202, with the fill material 203 on the edge 127, 217. In some embodiments, the fill material 203 extends to the edge 217 that is aligned with the edge 117 of the base PIC die 101. As shown, the photonic coupler 103 has a footprint 141, the PIC die 202 has a footprint 242, the EIC die 201 has a footprint 241, and the base PIC die 101 has a footprint 243, with the footprints 241, 141 within the footprint 243, and the area and perimeter established by the fill material 203 share the footprint 243. In some embodiments, the EIC die 201 and the PIC die 202 (including the pre-fabricated photonic via 104) are coupled to the base PIC die 101 using die-to-wafer bonding, the fill material 203 is deposited and planarized, the photonic via 304 is fabricated in the fill material 203, and the stack illustrated with respect to the PIC assembly 400 (without the photonic coupler 103) is simultaneously singulated or diced from the bonded wafer to establish the vertically aligned edges 117, 227.

[0039] In the context of the PIC assembly 400, some of the PIC functionality is offloaded from the base PIC die 101 to the PIC die 202. The PIC assembly 400 again provides greater flexibility in terms of manufacturing the top PIC die 202 and the EIC die 201 (i.e., they can be manufactured using different process nodes), as well as the shape factor and photonic coupler 103 attachment benefits described above. In addition, the deployment of the photonic via 104 and the photonic via 304 can provide increased flexibility in terms of the architecture and layout of the PIC assembly 400.

[0040] Figure 4 An enlarged view of the photonic via 104 is also illustrated in the inset. As shown, the PIC die 202 (or hybrid IC die 102) includes a substrate material or substrate 401, which can be any of the materials discussed herein. The PIC die 202 and the substrate 401 include an upper surface 121 and a lower surface 122 that is opposite or facing the upper surface 121, with the edge 127 extending therebetween. An opening 402 extends from the upper surface 121 to the lower surface 122, such that the opening 402 is substantially parallel to the edge 127. For example, the opening 402 can have a centerline 404 that is parallel to the edge 127 and orthogonal to the upper surface 121 and the lower surface 122.

[0041] Further, the opening 402 defines a sidewall 403 of the material of the substrate 401. That is, the sidewall 403 is a surface of the material of the substrate 401. The photonic via 104 is within the opening 402, such that the material of the photonic via 104, or the first material, is on the sidewall 403. That is, the material of the photonic via 104, or the first material, meets the interface of the material of the substrate 401 at the sidewall 403. Notably, one or more materials of the photonic via 104 can be selected to provide total internal reflection of light within the photonic via 104. Such materials are discussed further herein below.

[0042] In some embodiments, the substrate 401 is a first material, and the photonic via 104 is a second material, such that the second material has a second index of refraction that is greater than a first index of refraction of the first material. In some embodiments, the photonic via 104 further includes a third material (see Figure 17 ) extending at least partially through the opening 402 and within the second material parallel to the centerline 404 (and parallel to the edge 127), such that the third material is on a sidewall of the second material, and such that the third material has a third index of refraction that is greater than the second index of refraction.

[0043] Figure 5 is a flowchart illustrating an example method 500 for fabricating and assembling a PIC structure including a vertically aligned photonic via, arranged in accordance with at least some implementations of the present disclosure. For example, the method 500 can be implemented to fabricate the PIC assembly 100, 200, 300, 400, the assembled structure 3200, or any other photonic via or structure discussed herein. In the illustrated embodiment, the method 500 includes one or more operations illustrated by operations 501-506. However, embodiments herein can include additional operations, omit certain operations, or perform operations in a different order than provided. Figures 6-32 structures and components in practicing the method 500 are illustrated.

[0044] Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 11 , Figure 15 , Figure 16 , Figure 17 , Figure 21 , Figure 24 , Figure 26 and Figure 27 are illustrations of cross-sectional side views of photonic structures in practicing the method 500 to form a photonic via, arranged in accordance with at least some implementations of the present disclosure. Figure 10 is a top view of the photonic structure of Figure 9 illustrating a cylindrical photonic via; Figure 12 is a top view of the photonic structure of Figure 11is a top view of a photonic structure illustrating a grid of cylindrical photonic vias; Figure 13 is Figure 9 is a top view of a photonic structure illustrating photonic vias having square cross sections; and Figure 14 is Figure 11 is a top view of a photonic structure illustrating a grid of cylindrical photonic vias having square cross sections, all arranged in accordance with at least some implementations of the present disclosure.

[0045] Figure 18 is Figure 17 is a top view of a photonic structure illustrating photonic vias each having an outer and inner material each with a circular cross section; Figure 19 is Figure 17 is a top view of a photonic structure illustrating photonic vias having an outer material with a square cross section and an inner material with a circular cross section; Figure 20 is Figure 17 is a top view of a photonic structure illustrating photonic vias having an outer material with a circular cross section and an inner material with a square cross section; Figure 22 is Figure 21 is a top view of a photonic structure illustrating a grid of photonic vias each having an outer material with a circular cross section and an inner material; Figure 23 is Figure 21 is a top view of a photonic structure illustrating a grid of photonic vias having an outer material with a circular cross section and an inner material with a square cross section, all arranged in accordance with at least some implementations of the present disclosure.

[0046] Figure 25 is Figure 24 is a top view of a photonic structure illustrating a grid of photonic vias each having a cylindrical material within a bulk material, arranged in accordance with at least some implementations of the present disclosure.

[0047] Figure 28 , Figure 29 , Figure 30 , Figure 31 and Figure 32 are illustrations of cross-sectional side views of photonic structures when assembling a multi-layered photonic assembly having photonic vias in the method 500 of practice, arranged in accordance with at least some implementations of the present disclosure.

[0048] Method 500 begins at operation 501, where a die having a photonic via is prepared, such as a PIC die or a hybrid IC die. For example, a photonic via can be fabricated in a PIC die or a hybrid IC die. While discussed with respect to fabrication within a die, the techniques discussed can be used to form photonic vias in any suitable substrate, including a silicon substrate, a glass substrate, or a fill material on a base PIC die. Further, while discussed with respect to forming photonic vias in a PIC die or a hybrid IC die (i.e., an active die having a photonic circuit module), photonic vias can be fabricated in any die or chiplet, such as a dummy die or a dummy chiplet (i.e., a monolithic die without functional circuit modules).

[0049] The photonic via can be fabricated using any suitable technique or techniques. In some embodiments, a single material photonic via is fabricated by forming an opening in a substrate, bulk filling the opening with a single material, planarizing the substrate and the single material to remove overburden and form the single material photonic via, and optional backside reveal if needed. In some embodiments, a dual material photonic via is fabricated by forming a first opening in a substrate, bulk filling the first opening with a first material, planarizing the substrate and the first material to remove overburden, forming a second opening in the first material, bulk filling the second opening with a second material, planarizing the substrate and the second material to remove overburden and form the dual material photonic via, and optional backside reveal if needed. For example, the dual material photonic via can include the second material substantially coaxial with the first material within the first opening established in the substrate.

[0050] Figure 6 is an illustration of a cross-sectional side view of a photonic structure 600 including a material received for processing of a photonic via. For example, the photonic structure 600 can include any suitable material for fabricating a photonic via therein. As shown, the photonic structure 600 includes a material layer or substrate 601 and an optional underlying substrate 602. For example, a photonic via can be formed completely through a substrate, through a material layer (which can also be characterized as a substrate), or partially through a substrate. As needed, the photonic via can then be backside revealed by, for example, removing the substrate 602 (e.g., using a backside grind or etch technique). Notably, the photonic via includes a higher index of refraction material within a lower index of refraction material to provide total internal reflection within the higher index of refraction material. The higher index of refraction material can fill an opening within the lower index of refraction material substrate (see Figure 9 ), or the higher index of refraction material can fill an opening of the lower index of refraction material, which in turn is in an opening of the substrate (see Figure 17 ).

[0051] Substrate 601 can comprise any suitable material or materials. In some embodiments, substrate 601 is or comprises a Group IV material (e.g., silicon). In some embodiments, substrate 601 is or comprises a substantially single crystalline material. In some embodiments, substrate 601 is or comprises a buried insulating layer (e.g., Si02) such as a semiconductor-on-insulator (SOI) substrate and / or an isolated insulator region. In some embodiments, substrate 601 is a silicon oxide layer or other dielectric material. In some embodiments, substrate 601 is or comprises a glass substrate body, which can be characterized as a glass layer. In some embodiments, the layer substrate 601 is an amorphous solid glass layer. In some embodiments, the glass layer is one of an aluminosilicate, a borosilicate, an aluminoborosilicate, quartz, and fused quartz. The glass layer can include one or more of an additive comprising AI2O3, B2O3, MgO, CaO, SrO, BaO, Sn02, Na20, K2O, P2O3, Zr02, Li20, Ti, or Zn. For example, the glass layer can include an additive comprising one or more of aluminum, boron, magnesium, calcium, strontium, barium, tin, sodium, potassium, phosphorus, zirconium, lithium, titanium, or zinc. In some embodiments, the glass layer can include silicon and oxygen, and one or more of aluminum, boron, magnesium, calcium, strontium, barium, tin, sodium, potassium, phosphorus, zirconium, lithium, titanium, and zinc. In some embodiments, the glass layer includes at least 23% silicon and at least 26% oxygen by weight, and further includes at least 5% aluminum by weight. In some embodiments, the glass layer is rectangular in shape in plan view. However, other shapes can be used. In some embodiments, the glass layer is free of any organic binder or other organic material. Optional support structure or substrate 602 can be any suitable material and form factor, such as a support panel, a support wafer, or the like. In subsequent figures, support structure or substrate 602 and edge 127 are not shown for clarity of presentation.

[0052] As shown, substrate 601 includes an upper surface 121 and a lower surface 122 between which a photonic via is to be fabricated. Substrate 601 also has an edge 127 that extends between and is orthogonal to upper surface 111 and lower surface 112 (i.e., edge 127 extends in a vertical or z-direction that is orthogonal to a horizontal plane or x-y plane). For example, any photonic via 104 of hybrid IC die 102 or PIC die 202 can be formed using the disclosed techniques, with other circuitry modules and components of hybrid IC die 102 or PIC die 202 being included in substrate 601. However, any photonic via 104, photonic via 304, or other photonic via for deployment in any suitable photonic package can be fabricated using the discussed techniques, with photonic via 104 being illustrated for clarity of presentation. In some embodiments, the fabricated photonic via is in a virtual die or virtual chip.

[0053] Figure 7 is an illustration of a cross-sectional side view of a photonic structure 700 similar to the photonic structure 600 after forming openings 402 in the substrate 601. Forming the openings 402 can use any suitable technique or techniques, such as patterning a photoresist layer, etching the openings 402, and removing the patterned photoresist layer. However, other techniques can be used, such as laser ablation. The openings 402 can have any suitable cross-sectional size and shape to define photonic vias, depending on the application. In some embodiments, the openings 402 have a depth (in the z-dimension) in a range from 5 microns to 500 microns. However, other depths can be used. In some embodiments, a grid or array of openings 402 is provided to define a corresponding grid or array of photonic vias. As shown, in some embodiments, the openings 402 have substantially vertical sidewalls 403. However, in some embodiments, the openings 402 have tapered sidewalls (see FIG. 7B). Figure 26 .

[0054] Figure 8 is an illustration of a cross-sectional side view of a photonic structure 800 similar to the photonic structure 700 after depositing a high refractive index material to form photonic vias 104 within the openings 402 and form overhangs 801 over the upper surface 121 of the substrate 601. Depositing the bulk material can use any suitable technique or techniques, such as chemical vapor deposition (CVD) or other bulk deposition techniques. In the context of a single material photonic via 104, the deposited material has a refractive index that is greater than the refractive index of the substrate 601 material. In some embodiments, the refractive index of the deposited material is no less than 110% of the refractive index of the substrate 601 material. In some embodiments, the refractive index of the deposited material is no less than 120% of the refractive index of the substrate v material. In some embodiments, the refractive index of the deposited material is no less than 130% of the refractive index of the substrate 601 material. Other refractive index ratios can be used. In some embodiments, the deposited material is one of silicon oxide (i.e., comprising silicon and oxygen) or silicon nitride (i.e., comprising silicon and nitrogen).

[0055] Figure 9 is an illustration of a cross-sectional side view of a photonic structure 900 similar to the photonic structure 800 after removing the overhangs 801 to form a single material photonic via 104 that can be deployed in any of the contexts discussed herein, including the context discussed with respect to the photonic via 304. The overhangs 801 can be removed using any suitable technique or techniques to leave a substantially planar top surface of the photonic structure 900. In some embodiments, a chemical mechanical polishing (CMP) technique is used to remove the overhangs 801. In some embodiments, the overhangs are also removed from the lower surface 122, or the lower surface 122 can be revealed using a backside reveal technique. Such backside material removal (if needed) can include etching and / or CMP techniques.

[0056] As shown, the opening 402 extends from the upper surface 121 to the lower surface 122 such that the opening 402 (i.e., as defined by the centerline 404) is substantially parallel to the edge 127 and orthogonal to the upper surface 121 and the lower surface 122. The photonic via 104 is within the opening 402 such that the material of the single-material photonic via 104 is on the sidewall 403 to establish an interface at the sidewall 403 between the material of the single-material photonic via 104 and the material of the substrate 601. As discussed, one or more materials of the photonic via 104 can be selected to provide total internal reflection of light within the photonic via 104.

[0057] Figure 10 is a top view of a photonic structure 900 illustrating a cylindrical photonic via 104. Figure 10 illustrates Figure 9 the top view A-A' shown in FIG. 11B, along with other top views Figure 1 As shown, in some embodiments, the photonic via 104 has a circular cross-sectional shape 1001 in the horizontal x-y plane. As used herein, a cross-sectional shape in a plane can be established at any suitable location along an axis orthogonal to the cross-sectional plane (i.e., the z-axis) in the assembly, such as at the midpoint of the assembly or at either end of the assembly. For example, a circular cross-sectional shape 1001 extending along the depth (i.e., in the z-direction) of the photonic via 104 establishes the photonic via 104 as a cylindrical photonic via 104. While illustrated with respect to a circular cross-sectional shape 1001 and a square cross-sectional shape (below), the photonic via 104 can have any suitable cross-sectional shape, such as an elliptical, rectangular, or other shape.

[0058] Figure 11 is a cross-sectional side view of a photonic structure 1100 illustrating the manufacture of a grid 1101 of photonic vias 104. Figure 12 is a top view of a photonic structure 1100 illustrating a grid 1101 of cylindrical photonic vias 104 having circular cross-sectional shapes 1001. For example, the techniques discussed can be deployed to manufacture any number of photonic vias 104 of any size and shape. In the context of the photonic structure 1100, the photonic vias 104 can provide a universal grid for attaching a corresponding grid of optical connectors, which can be actively connected with all or a portion of the grid 1101 of photonic vias 104. For example, some of the photonic vias 104 can be active vias (i.e., coupled to optical connectors and configured to carry light), while other photonic vias 104 can be virtual vias (i.e., not coupled to optical connectors). Also as discussed with respect to FIG. 11B, the grid 1101 of photonic vias 104 can be configured to provide a universal grid for attaching a corresponding grid of optical connectors, which can be actively connected with all or a portion of the grid 1101 of photonic vias 104. Figure 9The illustrated photonic via 104 can have any suitable cross-sectional size (e.g., diameter). While a grid 1101 of photonic vias 104 each having the same size and shape is illustrated, in some embodiments, the grid 1101 can include photonic vias 104 having different sizes and / or different cross-sectional shapes.

[0059] Figure 13 is a top view of a photonic structure 1300 similar to the photonic structure 900, where the photonic structure 1300 has a square cross-sectional shape 1301 in the horizontal x-y plane. As discussed, the photonic via 104 can have any suitable cross-sectional shape (such as the square cross-sectional shape 1301) and size. In some embodiments, the square cross-sectional shape 1301 of the photonic via 104 can provide improved coupling with other components. For example, the cross-sectional shape of the photonic via 104 can be selected to match an external optical device or to accommodate attachment with an external optical device.

[0060] Figure 14 is a top view of a photonic structure 1400 similar to the photonic structure 1100, where the photonic structure 1400 has a grid 1101 of photonic vias 104 with square cross-sectional shapes 1301. As discussed, the method 500 can be deployed to fabricate any number of photonic vias 104 of any size and shape. In the context of the photonic structure 1400, the photonic via 104 can provide a universal grid for attachment to photonic vias 104 having square cross-sectional shapes 1301.

[0061] Turning now to a discussion of a dual- or multi-material photonic via 104, which can be deployed in any of the contexts discussed herein. In some embodiments, a dual- or multi-material photonic via deploys an outer material on a sidewall of an opening in a substrate and deploys an inner material inside the outer material, such that, for example, the inner material is on the sidewall of the first material. For example, the inner material and the outer material can be coaxial with respect to a centerline of the opening. In some embodiments, the inner material of the photonic via is a first material, the outer material of the photonic via is a second material, and the substrate is a third material. In some embodiments, the first material has a first index of refraction, the second material has a second index of refraction lower than the first index of refraction, and the third material has a third index of refraction lower than the second index of refraction. In some embodiments, the first index of refraction is higher than the second index of refraction, and the third material can be a higher or lower index of refraction material because light has total internal reflection in the first material.

[0062] Figure 15is an illustration of a cross-sectional side view of a photonic structure 1500 similar to photonic structure 900 after forming an opening 1501 in first via material 1502, which previously filled opening 402. Forming opening 1501 in first via material 1502 can use any suitable technique or techniques, such as a layer of photoresist patterned, etching opening 1501, and removing the patterned photoresist layer. Depending on the application, opening 1501 can have any suitable cross-sectional size and shape to define an outer material layer of a photonic via. In some embodiments, opening 1501 has a depth (in the z-dimension) in a range of 5 microns to 500 microns and extends across the entire depth of opening 402. However, in some embodiments, opening 1501 is formed to a finite depth, such as half the depth of opening 402 and first via material 1502 (see Figure 27 ). Other depths can be used. In some embodiments, a grid or array of openings 1501 is formed, each within a corresponding grid or array of discrete first via material. In some embodiments, a grid or array of openings 1501 is formed within a single body of first via material (see Figure 24 ). As shown, opening 1501 defines a sidewall 1503 of first via material 1502.

[0063] Figure 16 is an illustration of a cross-sectional side view of a photonic structure 1600 similar to photonic structure 1500 after depositing a second via material 1602 within opening 1501 (and within opening 402) to form a photonic via 104 within opening 402 and an overhang 1601 above upper surface 121 of substrate 601. Depositing second via material 1602 can use any suitable technique or techniques, such as chemical vapor deposition (CVD) or other bulk deposition techniques. In the context of a dual-material photonic via 104, second via material 1602 has a greater refractive index than the refractive index of first via material 1502. In some embodiments, the refractive index of second via material 1602 is no less than 110% of the refractive index of first via material 1502. In some embodiments, the refractive index of second via material 1602 is no less than 120% of the refractive index of first via material 1502. In some embodiments, the refractive index of second via material 1602 is no less than 130% of the refractive index of first via material 1502. Other refractive index ratios can be used. In some embodiments, second via material 1602 is silicon nitride (i.e., comprising silicon and nitrogen), and first via material 1502 is silicon oxide (i.e., comprising silicon and oxygen). In some embodiments, second via material 1602 is silicon nitride (i.e., comprising silicon and nitrogen), first via material 1502 is silicon oxide (i.e., comprising silicon and oxygen), and substrate 601 is single-crystal silicon. However, other material systems can be used.

[0064] Figure 17 is an illustration of a cross-sectional side view of a photonic structure 1700 similar to photonic structure 1600 after removal of overburden 1601 to form a dual-material photonic via 104 that can be deployed in any of the contexts discussed herein, including the context discussed with respect to photonic via 304. Overburden 1601 can be removed using any suitable technique or techniques to leave a substantially planar top surface of photonic structure 1700. In some embodiments, overburden 1601 is removed using a CMP technique. In some embodiments, overburden is also removed from lower surface 122, or lower surface 122 can be revealed using a backside reveal technique. Such backside material removal, if needed, can include etching and / or CMP techniques.

[0065] In the context of photonic structure 1700, opening 402 extends from upper surface 121 to lower surface 122 such that opening 402 (i.e., as defined by centerline 404) is substantially normal to upper surface 121 and lower surface 122. Photonic via 104 is within opening 402 such that first via material 1502 is on sidewall 403 to establish an interface at sidewall 403 between first via material 1502 and the material of substrate 601. In addition, photonic via 104 includes second via material 1602 on sidewall 1503 of first via material 1502 to establish an interface at sidewall 1503 between second via material 1602 and first via material 1502. As discussed, one or more of the materials of photonic via 104 can be selected to provide total internal reflection of light within photonic via 104, either within second via material 1602 and first via material 1502, or only within second via material 1602.

[0066] Figure 18is a top view of a photonic structure 1700 illustrating a cylindrical photonic via 104 having an inner cylinder of second via material 1602 surrounded by an outer tube of first via material 1502. As shown, in some embodiments, the photonic via 104 includes first via material 1502 having a circular or annular cross-sectional shape 1801 in the horizontal x-y plane, and second via material 1602 having a circular cross-sectional shape 1802 in the horizontal x-y plane. For example, the circular cross-sectional shape 1802 extending along the depth of the photonic via 104 (i.e., in the z-direction) establishes a photonic via 104 having a cylindrical second via material 1602 and a tube (or hollow cylinder) of first via material 1502 surrounding the second via material 1602. While illustrated with respect to circular cross-sectional shapes 1801, 1802 and square cross-sectional shapes (below), the first via material 1502 and the second via material 1602 of the photonic via 104 can have any cross-sectional shape, such as elliptical, rectangular, or other shapes, in any combination. In some embodiments, the cross-sectional shapes of the first via material 1502 and the second via material 1602 are the same. In some embodiments, the cross-sectional shapes of the first via material 1502 and the second via material 1602 are different.

[0067] Figure 19 is a top view of a photonic structure 1900 illustrating a cylindrical photonic via 104 in a block having an inner cylinder of second via material 1602 surrounded by an outer structure of first via material 1502 having an outer sidewall 403 defining a square cross-sectional shape 1901 and an inner sidewall 1503 defining a circular cross-sectional shape 1802. As shown, in some embodiments, the photonic via 104 includes first via material 1502 having a coaxial circular-in-square cross-sectional shape 1902 in the horizontal x-y plane, and second via material 1602 having a circular cross-sectional shape 1802 in the horizontal x-y plane. For example, the circular cross-sectional shape 1802 extending along the depth of the photonic via 104 (i.e., in the z-direction) establishes a photonic via 104 having a cylindrical second via material 1602 and a tube with an outer square wall of first via material 1502 surrounding the second via material 1602.

[0068] Figure 20is a top view of the photonic structure 2000 illustrating a photonic via 104 in a cylinder of a block of second via material 1602 surrounded by an outer tube of first via material 1502 having an outer sidewall 403 defining a circular cross-sectional shape 1801 and an inner sidewall 1503 defining a square cross-sectional shape 2002. As shown, in some embodiments, the photonic via 104 includes the first via material 1502 having a coaxial square-in-circle cross-sectional shape 2003 in the horizontal x-y plane, and the second via material 1602 having a square cross-sectional shape 2002 in the horizontal x-y plane. For example, the square cross-sectional shape 2002 extending along the depth of the photonic via 104 (i.e., in the z-direction) establishes the photonic via 104 as a tube with an extended block of second via material 1602 and an inner square wall of first via material 1502 surrounding the second via material 1602. In some embodiments, the photonic via 104 can have the square cross-sectional shape 2002 of the second via material 1602 within the square cross-sectional shape 1901 of the first via material 1502.

[0069] Figure 21 is a cross-sectional side view of a photonic structure 2100 illustrating fabrication of a grid 2101 of dual-material photonic vias 104. Figure 22 is a top view of the photonic structure 2100 illustrating a grid 2101 of cylindrical photonic vias 104 each having an inner cylinder of second via material 1602 surrounded by an outer tube of first via material 1502. As shown, in some embodiments, each photonic via 104 of the grid 2101 includes the first via material 1502 having a circular or annular cross-sectional shape 1801 in the horizontal x-y plane, and the second via material 1602 having a circular cross-sectional shape 1802 in the horizontal x-y plane. As discussed with respect to Figure 18 the circular cross-sectional shape 1802 establishes a cylindrical second via material 1602 and a tube (or hollow cylinder) of first via material 1502 surrounding the cylindrical second via material 1602. While illustrated with respect to circular cross-sectional shapes 1801, 1802 and square cross-sectional shapes (below), the first via material 1502 and the second via material 1602 of the photonic via 104 can have any cross-sectional shape, such as elliptical, rectangular, or other shapes, in any combination.

[0070] Figure 23is a top view of a photonic structure 2300 illustrating a grid 2101 of photonic vias 104 with multiple blocks in a cylinder, the photonic vias having an inner block of second via material 1602 surrounded by an outer structure of first via material 1502 having an outer sidewall defining a circular cross-sectional shape 1801 and an inner sidewall defining a square cross-sectional shape 2002. As shown, in some embodiments, each photonic via 104 of grid 2101 includes first via material 1502 having a coaxial square-in-circle cross-sectional shape 2003 in the horizontal x-y plane, and second via material 1602 having a square cross-sectional shape 2002 in the horizontal x-y plane. For example, the square cross-sectional shape 2002 extending along the depth of photonic via 104 (i.e., in the z-direction) establishes a photonic via 104 having an extended block of second via material 1602 and a tube with an inner square wall of first via material 1502 surrounding the second via material 1602. In some embodiments, each photonic via 104 of grid 2101 includes a photonic via 104 in a block in a cylinder as discussed with respect to Figure 19

[0071] Figure 24 is an illustration of a cross-sectional side view of a photonic structure 2400 showing fabrication of a grid 2401 of photonic vias 104 with multiple grids of second via material 1602 extending through a same monolithic block of first via material 1502. Figure 25 is a top view of a photonic structure 2400 illustrating a grid 2401 of cylindrical photonic vias 104 each including a cylinder of second via material 1602 surrounded by a same monolithic block of first via material 1502. As shown, in some embodiments, each photonic via 104 of grid 2401 includes surrounding first via material 1502, and second via material 1602 having a circular cross-sectional shape 1802 in the horizontal x-y plane. While illustrated with respect to a circular cross-sectional shape 1802 and an outer square cross-sectional shape 2501 of first via material 1502, any suitable shape can be used. For example, each instance of second via material 1602 can have a square cross-sectional shape 2002, a rectangular cross-sectional shape, an elliptical cross-sectional shape, or other shape.

[0072] Figure 26 is an illustration of a cross-sectional side view of a photonic structure 2600 showing a photonic via 104 with tapered sidewalls 2601. While illustrated with respect to a single-material photonic via 104, tapered sidewalls 2601 can be deployed in a photonic via 104 having an outer tapered sidewall 2601 and / or an inner tapered sidewall containing second via material 1602 (see Figure 17 ​) in the context of a dual-material photonic via 104. Forming the tapered sidewall 2601 can use any suitable technique or techniques, such as varying etch rates and parameters. In some embodiments, a controlled undercut etch technique is used to form the taper 2604 by undercutting in the illustrated orientation. In some embodiments, the taper 2604 is formed by reversing the illustrated orientation by increasing the etch intensity during the etch process. The taper 2604 provides a varying cross-section (in the z-dimension) of the photonic via 104 to achieve specific optical properties for use by the PIC assembly.

[0073] The photonic via 104 can be deployed in any suitable PIC assembly in the illustrated orientation or reversed from the illustrated orientation to effectively capture and propagate light through the photonic via 104 and the PIC assembly. As shown, the photonic via 104 can have the taper 2604 from the upper surface 121 to the lower surface 122 (or reversed) such that a cross-section of the photonic via 104 at a first surface of the surfaces defines a first region 2602 having a first area Al and a cross-section at a second surface of the surfaces defines a second region 2603 having a second area A2 that is less than the first area Al of the first region 2602. In some embodiments, the first area Al of the first region 2602 is not less than 125% of the second area A2 of the second region 2603. In some embodiments, the first area Al of the first region 2602 is not less than 150% of the second area A2 of the second region 2603. In some embodiments, the first area Al of the first region 2602 is not less than 200% of the second area A2 of the second region 2603. In some embodiments, the first area Al of the first region 2602 is not less than twice the second area A2 of the second region 2603. In some embodiments, the first area Al of the first region 2602 is not less than four times the second area A2 of the second region 2603.

[0074] Figure 27 is an illustration of a cross-sectional side view of a photonic structure 2700 showing a photonic via 104 having a second via material 1602 that extends only partially through a depth or thickness Tv of the photonic via 104. As shown, the second via material 1602 extends from the upper surface 121 or the lower surface 122 (as shown) to a depth or thickness Tm2 within the photonic via 104. While illustrated with respect to a vertical sidewall photonic via 104, the tapered sidewall 2601 can be deployed in the context of a photonic via 104 having a controlled depth 2701 (see Figure 26 ). Forming the controlled depth 2701 (i.e., thickness Tm2) of the second via material 1602 can use any suitable technique or techniques, such as a timed etch technique (see Figure 15). The photonic structure 2700 can be implemented in any suitable PIC assembly in the illustrated orientation or in an orientation reversed from the illustrated orientation to effectively capture and propagate light through the photonic via 104 and the PIC assembly. The controlled depth 2701 provides a discontinuity in the photonic via 104 to achieve particular optical properties for use by the PIC assembly.

[0075] As shown, the photonic via 104 can have a second via material 1602 with a controlled depth 2701 (i.e., thickness Tm2), which can be any suitable length measured in the z-dimension. In some embodiments, the total thickness Tvof the photonic via 104 is in the range of 5 microns to 500 microns. In some embodiments, the thickness Tm2of the second via material 1602 is no less than 20% and no more than 80% of the thickness Tvof the photonic via 104. In some embodiments, the thickness Tm2of the second via material 1602 is no less than 40% of the thickness Tvof the photonic via 104. In some embodiments, the thickness Tm2of the second via material 1602 is no less than 50% of the thickness Tvof the photonic via 104. In some embodiments, the thickness Tm2of the second via material 1602 is no more than 75% of the thickness Tvof the photonic via 104. In some embodiments, the thickness Tm2of the second via material 1602 is no more than 60% of the thickness Tvof the photonic via 104. In some embodiments, the second via material 1602 extends from one of the upper surface 121 or the lower surface 122 to a midpoint of the photonic via 104 and the opening 402.

[0076] Returning to Figure 5 , the method 500 continues at operation 502 with coupling one or more dies including photonic vias, as discussed above, and / or one or more dies without photonic vias to a base PIC die. The one or more dies including photonic vias can include any suitable dies, such as hybrid IC die(s), PIC die(s), or virtual die(s). Similarly, the one or more dies without photonic vias can include any suitable dies, such as EIC die(s). Such dies, including the base PIC die, can have any of the properties discussed herein. Notably, the one or more dies including photonic vias can include any photonic via having any suitable properties as described above. The one or more dies including photonic vias and / or the one or more dies without photonic vias can be coupled to the base PIC die using any suitable technique or techniques, such as hybrid bonding, fusion bonding, or solder bonding. The coupling or attachment can be die-to-wafer bonding or wafer-to-wafer bonding, with wafer-to-wafer bonding being preferred when the layout of the assembled structure permits.

[0077] Figure 28is an illustration of a cross-sectional side view of photonic assembly structure 2800 after attachment of PIC die 202 and EIC die 201 to base PIC die 101. PIC die 202, EIC die 201, and base PIC die 101 can have any of the properties discussed herein. While illustrated with respect to PIC die 202 and EIC die 201, any number of any type of die can be attached to base PIC die 101. In some embodiments, PIC die 202 and EIC die 201 are attached to base PIC die 101 using die-to-wafer attachment techniques, such as pick-and-place operations, or first attaching PIC die 202 and EIC die 201 to a carrier and wafer-to-wafer attachment using optical alignment. The carrier (e.g., wafer) can then be released using a UV-releasable adhesive or the like. In some embodiments, hybrid IC die 102 is coupled to base PIC die 101 using wafer-to-wafer attachment techniques (see Figure 1 ).

[0078] Returning to Figure 5 , method 500 continues at operation 503 with depositing optional fill material laterally adjacent to and / or between the one or more dies attached at operation 502. Note that when using wafer-to-wafer bonding of dies of the same size, fill material can not be used (see Figure 1 ). Further, use of fill material can be optional, but is preferred due to advantageous heat dissipation properties, package robustness, and to provide a flat top surface for mounting couplers and / or other devices. Forming the fill material can use any suitable technique or techniques, such as bulk depositing the fill material followed by a planarization process.

[0079] Figure 29 is an illustration of a cross-sectional side view of photonic assembly structure 2900, similar to photonic assembly structure 2800, after formation of fill material 203. As discussed, fill material 203 can be formed by bulk depositing the fill material followed by a planarization process. Fill material 203 can be any suitable material discussed above. As illustrated, planarization of fill material 203 exposes upper surface 211 of EIC die 201 and upper surface 121 of PIC die 202, and forms a substantially planar upper surface 2901 of photonic assembly structure 2900. Note that planar upper surface 2901 is advantageous for attachment of subsequent components, such as one or more optical couplers.

[0080] Returning to Figure 5Method 500 continues at operation 504 with forming a photonic via in the fill material optionally deposited at operation 503. The photonic via can be fabricated using any suitable technique or techniques, such as those discussed with respect to operation 501. The photonic via fabricated in the fill material can be a single-material photonic via or a dual-material photonic via as discussed herein. The photonic via (and fill material) can be any of the materials discussed herein with respect to fabricating photonic via 104 in substrate 601, and the photonic via can have any of the discussed properties, such as a grid layout, tapered sidewalls, discontinuities of the second via material, different shapes between the first and second via materials, etc. It is noted that forming a photonic via in the fill material is optional, but can advantageously provide increased interconnectivity and routing flexibility for the photonic assembly.

[0081] Figure 30 FIG. 30 is an illustration of a cross-sectional side view of a photonic assembly structure 3000 similar to photonic assembly structure 2900 after forming a photonic via 304 in fill material 203. As discussed, photonic via 304 can be formed using any suitable technique or techniques. In some embodiments, a single-material photonic via 304 is fabricated by forming an opening in fill material 203, bulk filling a single material in the opening, and planarizing fill material 203 and the single material to remove. In some embodiments, a dual-material photonic via 304 is fabricated by forming a first opening in fill material 203, bulk filling a first via material in the first opening, planarizing to remove overhangs, forming a second opening in the first via material, bulk filling a second via material in the second opening, and second planarizing to remove overhangs and form dual-material photonic via 304.

[0082] Returning to Figure 5 Method 500 continues at operation 505 with mounting an optical coupler to the exposed surface(s) of the photonic via(s) prepared at operation 501 (i.e., photonic via formed within a die such as a hybrid IC die or a PIC die) and / or the photonic via formed at operation 504 (i.e., photonic via within fill material between dies). The optical coupler can be mounted using any suitable technique or techniques, such as pick and place followed by annealing to form a fusion bond between the optical coupler and the exposed surface(s). Other mounting techniques can be used.

[0083] Figure 31is an illustration of a cross-sectional side view of a photonic assembly structure 3100 similar to photonic assembly structure 3000 after attachment of a photonic coupler 103. The photonic coupler 103 can be mounted to the planar upper surface 2901 using pick and place operations followed by an anneal operation to form a fusion bond, or using other techniques, including coupling to the photonic via 104 and the photonic via 304. Advantageously, the planar upper surface 2901 has little or no topography, such that placement of the photonic coupler 103 can be performed quickly and efficiently. While illustrated with respect to attachment of the photonic coupler 103 to the photonic via 104 within the PIC die 202 and the photonic via 304 within the fill material 203, the photonic coupler 103 can be coupled to any suitable photonic via, such as the photonic via 104 of the hybrid IC die 102.

[0084] Returning to Figure 5 , the method 500 continues at operation 506 with singulation (or cutting) of the photonic assembly structure from the wafer or panel level bonding using known dicing techniques, if needed, and where the resulting device (e.g., PIC structure) can be packaged, assembled and implemented in any suitable form factor device, such as a server implementation or other smaller form factor device.

[0085] Figure 32 is an illustration of a cross-sectional side view of a packaged or assembled structure 3200 similar to PIC assembly 400 after attachment to an external fiber array connector, packaged with an electronic IC die, and deployment of a heat dissipation solution, arranged in accordance with at least some implementations of the present disclosure. As shown, the PIC assembly 400 can be incorporated into the packaged or assembled structure 3200. While illustrated with respect to the PIC assembly 400, any of the PIC assemblies or other structures discussed herein can be deployed in the assembled structure 3200. The assembled structure 3200 also includes any number of electronic integrated circuit (EIC) dies 3211 mounted to a substrate 3212 via interconnects 3213, which are optionally embedded in molding or underfill material. The substrate 3212 can be a package substrate, interposer, or board, such as a motherboard. Any number of PIC assemblies 400 or other PIC assemblies can be attached to the substrate 3212. As shown, the substrate 3212 can be coupled to a microelectronic board 3241 by interconnects 3209. Figure 4

[0086] ​The photonic coupler 103 can be coupled to an external fiber array connector 3220 (e.g., a fiber connector or coupler). As shown in the magnified view, the external fiber array connector 3220 can include a body 3221 and a pin 3222 extending from the body 3221. The external fiber array connector 3220 can be detachably coupled 3224 to the photonic coupler 103 by inserting / removing the alignment pin 3222 into / out of an alignment hole 3225 of the photonic coupler 103. In some embodiments, the photonic coupler 103 is an intermediate coupler that can be coupled to an external fiber array 3223 using standard alignment pins 3222 and pin holes 3225. The photonic coupler 103 can include any number of holes 3225, such as two alignment pin holes 3225, to implement a receptacle for receiving an external fiber array connector having matching alignment pins 3222.

[0087] The assembled structure 3200 also includes a battery / power supply 3226 coupled with one or more of the substrate 3212 (i.e., board, package substrate, or interposer), the EIC die 3211, the PIC assembly 400, and / or other components of the assembled structure 3200. The power supply 3226 can include a battery, a voltage converter, a power supply circuit module, or the like. The assembled structure 3200 also includes a thermal interface material (TIM) 3201 disposed on a top surface of the EIC die 3211 and optionally on the PIC assembly 400. The TIM 3201 can include any suitable thermal interface material and can be characterized as TIM 1. An integrated heat spreader 3202 having a surface on the TIM 3201 extends over the EIC die 3211, the PIC assembly 400, and / or other components of the assembled structure 3200 and is mounted to the substrate 3212. The assembled structure 3200 also includes a TIM 3203 disposed on a top surface of the integrated heat spreader 3202. The TIM 3203 can include any suitable thermal interface material and can be characterized as TIM 2. The TIM 3201 and the TIM 3203 can be the same material, or they can be different. A heat sink 3204 (e.g., an exemplary heat dissipation device or thermal solution) is on the TIM 3203 and dissipates heat. For example, the assembled structure 3200 can be used in a server form factor.

[0088] Figure 33An exemplary system 3300 employing a PIC assembly including vertically aligned photonic vias is illustrated, arranged in accordance with at least some implementations of the present disclosure. For example, system 3300 can include a data server platform 3301 having a PIC assembly including vertically aligned photonic vias, such as a stacked-die PIC assembly with photonic vias 3302 as discussed elsewhere herein. As shown, data server platform 3301 can be powered in part by a battery / power supply 3305, which can include any suitable power circuitry. While illustrated with respect to data server platform 3301, stacked-die PIC assembly with photonic vias 3302 can be deployed in any computing environment, such as a desktop or mobile computing platform. Any of the photonic structures or assembly structures discussed herein can be deployed in stacked-die PIC assembly with photonic vias 3302.

[0089] Data server platform 3301 can be any commercial server, for example, including any number of high-performance computing platforms or computing units networked together for electronic data processing. As shown in the magnified view, stacked-die PIC assembly with photonic vias 3302 is optically coupled to an optical fiber 3303, which in turn is coupled to a computing unit or system I / O 3304. In some examples, the disclosed systems can include subsystems, such as a system on a chip (SOC) or an integrated system of multiple PICs and EICs.

[0090] Whether disposed within the data server platform 3301 or other computing platform, the system 3300 can further include memory circuitry and / or processor circuitry (e.g., RAM, microprocessors, multi-core microprocessors, graphics processors, etc.), a power management integrated circuit (PMIC), a controller, and a radio-frequency integrated circuit (RFIC) (e.g., including a wideband RF transmitter and / or receiver (TX / RX)). Any of such components can be packaged, assembled, and implemented such that the package includes a stacked-die PIC assembly 3302 with photonic vias. In some embodiments, the RFIC includes a digital baseband and an analog front-end module that further includes a power amplifier on the transmit path and a low-noise amplifier on the receive path). The RFIC can have an output coupled to an antenna (not shown) to enable any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+,

[0091] Figure 34 is a block diagram of a computing device 3400 according to some embodiments. For example, one or more components of the computing device 3400 can include any of the PIC structures or assemblies discussed elsewhere herein. Figure 34 A number of components are illustrated in FIG. 34, but any one or more of these components can be omitted or repeated depending on application suitability. In some embodiments, some of the components included in the computing device 3400 can be attached to one or more printed circuit boards (e.g., a motherboard). In some embodiments, various ones of these components can be fabricated on a single system-on-a-chip (SoC) die, or packaged together in a split multi-chip or tile implementation. Any of such packaged components can include vertically-aligned photonic vias implemented in components with disaggregated PIC functionality, e.g., as discussed herein. Further, in various embodiments, the computing device 3400 can not include Figure 34The illustrated computing device 3400 can include a number of components, not all of which are shown in Figure 34. For instance, the computing device 3400 can not include the display device 3403, but can include a display device interface circuit module (e.g., a connector and drive circuit module) with which the display device 3403 can be coupled.

[0092] The computing device 3400 can include a processing device 3401 (e.g., one or more processing devices). The term processing device or processor as used herein refers to a device that processes electronic data from registers and / or memory to transform that electronic data into other electronic data that can be stored in registers and / or memory. The processing device 3401 can include a memory 3421, a communication device 3422, a refrigeration / active cooling device 3423, a battery / power conditioning device 3424, logic 3425, an interconnect 3426, a thermal regulation device 3427, and a hardware security device 3428.

[0093] The processing device 3401 can include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (specialized processors that perform cryptographic algorithms within hardware), server processors, or any other suitable computing unit.

[0094] The processing device 3401 can include a memory 3402, which can itself include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read only memory (ROM)), flash memory, solid state memory, and / or a hard drive. In some embodiments, the processing device 3401 shares a package with the memory 3402. Such memory can be used as cache memory, and can include embedded dynamic random access memory (eDRAM) or spin-transfer torque magnetic random access memory (STT-MRAM).

[0095] The computing device 3400 can include a thermal regulation / refrigeration device 3406. The thermal regulation / refrigeration device 3406 can maintain the processing device 3401 (and / or other components of the computing device 3400) at a predetermined low temperature during operation. This predetermined low temperature can be any of the temperatures discussed elsewhere herein.

[0096] In some embodiments, the computing device 3400 can include a communication chip 3407 (e.g., one or more communication chips). For example, the communication chip 3407 can be configured to manage wireless communications for the transfer of data to and from the computing device 3400. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that can communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The communication chip 3407 can implement any of a number of wireless

[0097] For example, the computing device 3400 can include any of the photonic structures discussed herein, which can facilitate communication between one or more instances of the processing device 3401 and / or one or more instances of the memory 3402.

[0098] The computing device 3400 can include a battery / power circuit module 3408. The battery / power circuit module 3408 can include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of the computing device 3400 to an energy source separate from the computing device 3400 (e.g., an AC line power source).

[0099] The computing device 3400 can include a display device 3403 (or corresponding interface circuitry, as discussed above). For example, the display device 3403 can include any visual

[0100] The computing device 3400 can include an audio output device 3404 (or corresponding interface circuitry, as discussed above). For example, the audio output device 3404 can include any device that generates an audible indicator, such as speakers, headphones, or earbuds.

[0101] The computing device 3400 can include an audio input device 3410 (or corresponding interface circuitry, as discussed above). The audio input device 3410 can include any device that generates a signal representative of an acoustic sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments with a musical instrument digital interface (MIDI) output).

[0102] The computing device 3400 can include a global positioning system (GPS) device 3409 (or corresponding interface circuitry, as discussed above). The GPS device 3409 can communicate with satellite-based systems and can receive a location of the computing device 3400, as is known in the art.

[0103] The computing device 3400 can include another output device 3405 (or a corresponding interface circuitry, as discussed above). Examples can include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0104] The computing device 3400 can include another input device 3411 (or a corresponding interface circuitry, as discussed above). Examples can include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a barcode reader, a quick response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0105] The computing device 3400 can include a security interface device 3412. The security interface device 3412 can include any device that provides security measures for the computing device 3400, such as intrusion detection, biometric verification, secure encoding or decoding, managing access lists, malware detection, or spyware detection.

[0106] The computing device 3400 can include an antenna 3413. The antenna 3413 can include any device that translates electrical currents to radio waves and / or radio waves to electrical currents.

[0107] The computing device 3400, or a subset of its components, can have any appropriate shape factor, such as a server or other networked computing component, a mobile device, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device.

[0108] While certain features set forth herein have been described with reference to various implementations, this description is not intended to be construed in a limiting sense. Thus, various modifications to the implementations described herein, as well as other implementations, which are apparent to persons skilled in the art of the disclosure, are deemed to lie within the spirit and scope of the present disclosure.

[0109] It will be appreciated that the application is not limited to the embodiments thus described, and that modifications and variations are possible without departing from the scope of the appended claims. For example, the above-described embodiments can include particular combinations of the features further provided below.

[0110] The following examples pertain to exemplary embodiments.

[0111] In one or more first embodiments, an apparatus comprises: a photonic integrated circuit (PIC) die in a lower layer of a multi-layer assembly, the PIC die having an upper surface substantially parallel to a horizontal plane; a photonic coupler in an upper layer of the multi-layer assembly, the photonic coupler having a lower surface substantially parallel to the horizontal plane, such that the PIC die and the photonic coupler are at least partially vertically aligned; and a photonic via optically coupling the PIC die and the photonic coupler, the photonic via extending from the upper surface of the PIC die substantially normal to the horizontal plane to the lower surface of the photonic coupler and through one or more intermediate layers of the multi-layer assembly.

[0112] In one or more second embodiments, further to the first embodiments, the apparatus further comprises a hybrid photonic and electronic integrated circuit (hybrid IC) die in one of the intermediate layers of the multi-layer assembly, such that the photonic via extends through the hybrid IC die.

[0113] In one or more third embodiments, further to the first or second embodiments, the photonic coupler is on the hybrid IC die and the hybrid IC die is on the PIC die.

[0114] In one or more fourth embodiments, further to the first through third embodiments, the photonic coupler is over a first region of the hybrid IC die that includes a plurality of photonic vias, and a second region of the hybrid IC die that is free of photonic vias is free of the photonic coupler over the second region.

[0115] In one or more fifth embodiments, further to the first through fourth embodiments, the hybrid IC die and the PIC die together form a photonic integrated circuit intellectual property block.

[0116] In one or more sixth embodiments, further to the first through fifth embodiments, the hybrid IC die and the PIC die share a same size in the horizontal plane.

[0117] In one or more seventh embodiments, further to the first through sixth embodiments, the apparatus further comprises: an electronic integrated circuit (EIC) die in one of the intermediate layers of the multi-layer assembly; and a second PIC die in one of the intermediate layers of the multi-layer assembly laterally adjacent to the EIC die, such that the photonic via extends through the second PIC die.

[0118] In one or more eighth embodiments, further to the first through seventh embodiments, the photonic coupler is on the second PIC die and the second PIC die is on the PIC die.

[0119] In one or more ninth embodiments, further to the first through eighth embodiments, the second PIC die and the PIC die together form a photonic integrated circuit intellectual property block.

[0120] In one or more tenth embodiments, further to the first through ninth embodiments, the apparatus further comprises: an electronic integrated circuit (EIC) die in one of the intermediate layers of the multi-layer assembly; and a fill material laterally adjacent to the EIC die in the one of the intermediate layers of the multi-layer assembly, such that the photonic via extends through the fill material.

[0121] In one or more eleventh embodiments, further to the first through tenth embodiments, the photonic coupler is over at least a portion of the fill material.

[0122] In one or more twelfth embodiments, further to the first through eleventh embodiments, the apparatus further comprises a power supply coupled to the PIC die and / or a fiber array connector coupled to the photonic coupler.

[0123] In one or more thirteenth embodiments, an apparatus comprises: a first photonic integrated circuit (PIC) die having an upper surface substantially parallel to a horizontal plane; a photonic coupler having a lower surface substantially parallel to the horizontal plane, such that the first PIC die and the photonic coupler are at least partially vertically aligned; a second PIC die or a hybrid photonic and electronic integrated circuit (hybrid IC) die at least partially between the first PIC die and the photonic coupler; and a photonic via extending from the upper surface of the first PIC die substantially orthogonal to the horizontal plane to the lower surface of the photonic coupler and through the second PIC die or the hybrid IC die.

[0124] In one or more fourteenth embodiments, further to the thirteenth embodiment, the PIC die and one of the second PIC die or the hybrid IC die together form a photonic integrated circuit intellectual property block.

[0125] In one or more fifteenth embodiments, further to the thirteenth or second embodiment, the photonic coupler is on the second PIC die or the hybrid IC die, and the second PIC die or the hybrid IC die is on the PIC die.

[0126] In one or more sixteenth embodiments, further to the thirteenth through third embodiments, the apparatus further comprises a power supply coupled to the PIC die and / or a fiber array connector coupled to the photonic coupler.

[0127] In one or more seventeenth embodiments, an apparatus comprises: a first photonic integrated circuit (PIC) die in a lower horizontal layer of a multi-layer assembly; a photonic coupler in an upper horizontal layer of the multi-layer assembly such that the PIC die and the photonic coupler are at least partially vertically aligned; a second PIC die or a hybrid photonic and electronic integrated circuit (hybrid IC) die in a middle horizontal layer of the multi-layer assembly such that the PIC die and one of the second PIC die or the hybrid IC die together form a photonic integrated circuit intellectual property block; and a photonic via optically coupling the PIC die and the photonic coupler, the photonic via extending vertically from the PIC die to the photonic coupler and through the second PIC die or the hybrid IC die.

[0128] In one or more eighteenth embodiments, further to the seventeenth embodiment, the photonic coupler is on the second PIC die or the hybrid IC die and the second PIC die or the hybrid IC die is on the PIC die.

[0129] In one or more nineteenth embodiments, further to the seventeenth or eighteenth embodiment, the apparatus further comprises: an electronic integrated circuit (EIC) die laterally adjacent to the second PIC die or the hybrid IC die; a fill material laterally between the EIC die and the second PIC die or the hybrid IC die; and a second photonic via extending vertically through the fill material.

[0130] In one or more twentieth embodiments, further to the seventeenth through nineteenth embodiments, the apparatus further comprises a power supply coupled to the PIC die and / or a fiber array connector coupled to the photonic coupler.

[0131] It will be appreciated that the application is not limited to the embodiments thus described, but can be practiced with modification and alteration within the scope of the appended claims. For example, the above-described embodiments can include specific combinations of features. However, the above-described embodiments are not limited to this aspect, and in various implementations, the above-described embodiments can include only a subset of such features, a different order of such features, a different combination of such features, and / or additional features not expressly listed. Accordingly, the scope of the application should be determined not by the foregoing description, but by the appended claims, along with their full scope of equivalents.

Claims

1. An apparatus comprising: A photonic integrated circuit (PIC) die in the lower layer of a multilayer assembly, the PIC die having an upper surface that is substantially parallel to a horizontal plane; A photonic coupler in the upper layer of the multilayer assembly, the photonic coupler having a lower surface substantially parallel to the horizontal plane, wherein the PIC die and the photonic coupler are at least partially vertically aligned; as well as A photonic via is optically coupled between the PIC die and the photonic coupler, the photonic via being substantially orthogonal to the horizontal plane, extending from the upper surface of the PIC die to the lower surface of the photonic coupler and passing through one or more intermediate layers of the multilayer assembly.

2. The device as claimed in claim 1, further comprising: A hybrid photonic and electronic integrated circuit (hybrid IC) die in one of the intermediate layers of the multilayer assembly, wherein the photonic via extends through the hybrid IC die.

3. The device as described in claim 2, wherein, The photonic coupler is on the hybrid IC die, and the hybrid IC die is on the PIC die.

4. The device as described in claim 3, wherein, The photonic coupler is located above a first region of the hybrid IC die, which includes multiple photonic vias, and the second region of the hybrid IC die, which does not have photonic vias, is not located above the second region.

5. The device as described in claim 2, wherein, The hybrid IC die and the PIC die together form a photonic integrated circuit intellectual property block.

6. The device as claimed in claim 2, wherein, The hybrid IC die and the PIC die share the same dimensions in the horizontal plane.

7. The device as claimed in any one of claims 1 to 6, further comprising: An electronic integrated circuit (EIC) die in one of the intermediate layers of the multilayer assembly; as well as A second (PIC) die, laterally adjacent to the EIC die in one of the intermediate layers of the multilayer assembly, wherein the photonic via extends through the second PIC die.

8. The device as claimed in claim 7, wherein, The photonic coupler is on the second PIC die, and the second PIC die is on the PIC die.

9. The device as claimed in claim 7, wherein, The second PIC die and the PIC die together form a photonic integrated circuit intellectual property block.

10. The device as claimed in any one of claims 1 to 6, further comprising: An electronic integrated circuit (EIC) die in one of the intermediate layers of the multilayer assembly; as well as A filler material laterally adjacent to the EIC die in one of the intermediate layers of the multilayer assembly, wherein the photonic via extends through the filler material.

11. A system comprising: A photonic integrated circuit (PIC) die in the lower layer of a multilayer assembly, the PIC die having an upper surface that is substantially parallel to a horizontal plane; A photonic coupler in the upper layer of the multilayer assembly, the photonic coupler having a lower surface substantially parallel to the horizontal plane, wherein the PIC die and the photonic coupler are at least partially vertically aligned; A photonic via is optically coupled between the PIC die and the photonic coupler, the photonic via being substantially orthogonal to the horizontal plane, extending from the upper surface of the PIC die to the lower surface of the photonic coupler and passing through one or more intermediate layers of the multilayer assembly; as well as A power supply coupled to the PIC die and / or a fiber optic array connector coupled to the photonic coupler.

12. The system of claim 11, further comprising: A hybrid photonic and electronic integrated circuit (hybrid IC) die in one of the intermediate layers of the multilayer assembly, wherein the photonic via extends through the hybrid IC die.

13. The system of claim 12, wherein, The photonic coupler is on the hybrid IC die, and the hybrid IC die is on the PIC die.

14. The system of claim 13, wherein, The photonic coupler is located above a first region of the hybrid IC die, which includes multiple photonic vias, and the second region of the hybrid IC die, which does not have photonic vias, is not located above the second region.

15. The system of claim 12, wherein, The hybrid IC die and the PIC die together form a photonic integrated circuit intellectual property block.

16. The system of claim 12, wherein, The hybrid IC die and the PIC die share the same dimensions in the horizontal plane.

17. The system of any one of claims 11 to 16, further comprising: An electronic integrated circuit (EIC) die in one of the intermediate layers of the multilayer assembly; as well as A second (PIC) die, laterally adjacent to the EIC die in one of the intermediate layers of the multilayer assembly, wherein the photonic via extends through the second PIC die.

18. The system of claim 17, wherein, The photonic coupler is on the second PIC die, and the second PIC die is on the PIC die.

19. The system of claim 17, wherein, The second PIC die and the PIC die together form a photonic integrated circuit intellectual property block.

20. The system of any one of claims 11 to 16, further comprising: An electronic integrated circuit (EIC) die in one of the intermediate layers of the multilayer assembly; as well as A filler material laterally adjacent to the EIC die in one of the intermediate layers of the multilayer assembly, wherein the photonic via extends through the filler material.

21. A method comprising: A photonic integrated circuit (PIC) die is placed in the lower layer of a multilayer assembly, the PIC die having an upper surface that is substantially parallel to a horizontal plane; A photonic coupler is placed in the upper layer of the multilayer assembly. The photonic coupler has a lower surface that is substantially parallel to the horizontal plane, wherein the PIC die and the photonic coupler are at least partially vertically aligned. as well as A photonic via is formed to optically couple the PIC die and the photonic coupler. The photonic via is substantially orthogonal to the horizontal plane, extends from the upper surface of the PIC die to the lower surface of the photonic coupler, and passes through one or more intermediate layers of the multilayer assembly.

22. The method of claim 21, further comprising: A hybrid photonic and electronic integrated circuit (hybrid IC) die in one of the intermediate layers of the multilayer assembly, wherein the photonic via extends through the hybrid IC die.

23. The method of claim 22, wherein, The photonic coupler is on the hybrid IC die, and the hybrid IC die is on the PIC die.

24. The method of claim 23, wherein, The photonic coupler is located above a first region of the hybrid IC die, which includes multiple photonic vias, and the second region of the hybrid IC die, which does not have photonic vias, is not located above the second region.

25. The method according to any one of claims 22 to 24, wherein, The hybrid IC die and the PIC die together form a photonic integrated circuit intellectual property block, or the hybrid IC die and the PIC die share the same size in the horizontal plane.

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