Data acquisition method and device and processor

Abstract

The invention provides a data acquisition method and device and a processor, the method is applied to the processor, and the method comprises the steps that a cache receives a data search request sent by a distribution queue or a transmission queue; wherein the data searching request comprises a first source address and a first transmitting address; the cache determines first source data from the at least one piece of cache information based on the first source address, and updates the at least one piece of cache information; the cache sends target data information to the transmission queue based on the first source data and the first transmission address; the transmitting queue writes the first source data into the first entry information, so that part of the source data in the register is stored in the cache; after the cache receives the data search request, the first source data required by the first entry information can be acquired from the cache information, so that the access times of the transmitting queue to the register are reduced, the pressure of a reading port of the register is reduced, the movement of the data between the register and the transmitting queue is also reduced, and the data acquisition efficiency is improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of data processing, and particularly relates to a data acquisition method, device and processor. BACKGROUND

[0002] In the launch queue, the required source operands of entries are often stored in registers, but there are multiple entries in the launch queue, which causes multiple entries to read source operands from registers through read ports, and the conflicts of the read ports of the registers also increase. SUMMARY

[0003] To overcome the problems in the related art, the present disclosure provides a data acquisition method, device and processor to reduce the conflicts of the read ports of the registers.

[0004] According to a first aspect of an embodiment of the present disclosure, a data acquisition method is provided, the method is applied to a processor, the processor includes a cache, a distribution queue and a launch queue; the distribution queue and the launch queue are used to store entry information, and the cache is used to store at least one cache information, the cache information including source data; the method includes:

[0005] The cache receives a data search request sent by the distribution queue or the launch queue; wherein the data search request includes a first source address and a first launch address, the first source address including an address of first source data required by first entry information, and the first launch address including an address where the first entry information is located in the launch queue;

[0006] The cache determines the first source data from the at least one cache information based on the first source address, and updates the at least one cache information;

[0007] The cache sends target data information to the launch queue based on the first source data and the first launch address; wherein the target data information includes the first source data;

[0008] The launch queue writes the first source data into the first entry information.

[0009] In some embodiments, the cache information further includes a source address and a data validity identifier; the cache determines the first source data from the at least one cache information based on the first source address, including:

[0010] The cache determines first cache information matching the first source address from the at least one cache information based on the first source address; wherein the data validity identifier of the first cache information is used to indicate that the first cache information is in an effective state, and the second source address of the first cache information matches the first source address.

[0011] The cache includes source data included in the first cache information as the first source data.

[0012] In some embodiments, the cache information further includes a confidence value; and the cache updates at least one of the cache information, including at least one of:

[0013] The cache increases a first confidence value of the first cache information by A first step values;

[0014] The cache decreases a second confidence value of second cache information by B second step values; wherein the second cache information is information other than the first cache information in the plurality of cache information;

[0015] The cache decreases the confidence value of each of the cache information by C third step values based on a preset period;

[0016] Wherein A, B, and C are integers greater than or equal to 1.

[0017] In some embodiments, the method further includes at least one of:

[0018] The cache determines cache information with a confidence value less than or equal to a first preset threshold as third cache information, and determines a corresponding state of a data validity identifier of the third cache information as an invalid state;

[0019] The cache determines cache information with a confidence value less than or equal to a first preset threshold as third cache information, and deletes the third cache information.

[0020] In some embodiments, the cache is configured to store at least one of the cache information in a full connection form; and the cache determines, based on the first source address, first cache information matching the first source address from the at least one of the cache information, including:

[0021] The cache determines a first index identifier based on the first source address; wherein the first index identifier is related to the first source address.

[0022] The cache determines the second source address based on the first index identifier.

[0023] The cache includes cache information in which the second source address is located as the first cache information.

[0024] In some embodiments, the cache is configured to store at least one of the cache information in a group connection form, and the cache information in each group has partially same index identifiers; and the cache determines, based on the first source address, first cache information matching the first source address, including:

[0025] The cache determines the second index identifier based on the first source address; wherein, the first source address includes a first part address and a second part address, and the second index identifier is related to the first part address;

[0026] The cache determines at least one fourth cache information based on the second index identifier; wherein each of the fourth cache information corresponds to the second index identifier;

[0027] The cache determines a third index identifier based on the first source address; wherein the third index identifier is related to the second part of the address;

[0028] The cache determines the first cache information from at least one fourth cache information based on the third index identifier.

[0029] In some embodiments, the method further includes:

[0030] The cache obtains first indicator information; wherein, the first indicator information includes source address and source data;

[0031] The cache determines the confidence value corresponding to the first indicator information and the data validity identifier corresponding to the first indicator information;

[0032] The cache generates and stores fifth cache information based on the first indicator information, the confidence value corresponding to the first indicator information, and the data validity identifier corresponding to the first indicator information.

[0033] In some embodiments, the processor further includes registers and an execution module, and the method further includes at least one of the following:

[0034] The cache obtains first indicator information from the register; wherein the register is used to store at least one indicator information;

[0035] The cache receives first indicator information broadcast by the execution module or the transmission queue;

[0036] The cache receives the first indicator information sent by the execution module.

[0037] In some embodiments, the cache is used to store at least one sixth cache information, the sixth cache information including a confidence value; the cache stores fifth cache information, including:

[0038] In response to the fifth cache information to be written, the cache compares a storage space value with a second preset threshold; wherein the storage space value is used to indicate the storage space for storing the fifth cache information.

[0039] The cache determines a limit confidence value based on the confidence value of the sixth cache information when the storage space value is less than a second preset threshold value.

[0040] The cache deletes the sixth cache information in which the limit confidence value is located.

[0041] The cache writes the fifth cache information.

[0042] In some embodiments, the cache is configured to store at least one of the sixth cache information in a group connection manner; and the method further comprises:

[0043] The cache determines a fourth index identifier based on the fifth cache information; wherein the fourth index identifier is related to the source address stored in the fifth cache information.

[0044] The cache determines a storage space value based on the fourth index identifier.

[0045] In some embodiments, the processor further comprises a wake-up module; and the method further comprises at least one of the following:

[0046] The distribution queue sends the first entry information to the transmission queue and sends a data search request corresponding to the first entry information to the cache.

[0047] The transmission queue determines the first entry information corresponding to the wake-up information based on the wake-up information sent by the wake-up module; generates a data search request based on the first entry information corresponding to the wake-up information, and sends the data search request to the cache; wherein the wake-up information is used to indicate that the first source data required by the first entry information is stored in the cache.

[0048] In some embodiments, the first entry information comprises second index information, and the second index information comprises first source data and a first source address; and the method further comprises:

[0049] The transmission queue broadcasts the second index information through a broadcast bus.

[0050] The transmission queue writes the first source data into the second entry information matched with the first source address.

[0051] In a second aspect, the present disclosure provides a data acquisition device, which comprises a cache, a distribution queue and a transmission queue; the distribution queue and the transmission queue are configured to store entry information.

[0052] The cache is configured to receive a data lookup request sent by the distribution queue or the transmission queue, wherein the data lookup request comprises a first source address and a first transmission address, the first source address comprises an address of first source data required by the first entry information, and the first transmission address comprises an address of the first entry information in the transmission queue; first source data is determined from at least one cache information stored based on the first source address, and at least one cache information is updated; wherein the cache information comprises source data; target data information is sent to the transmission queue based on the first source data and the first transmission address; wherein the target data information comprises the first source data.

[0053] The transmission queue is configured to write the first source data into the first entry information.

[0054] In a third aspect, the present disclosure provides a processor comprising the data acquisition device of the second aspect.

[0055] The technical scheme provided by the embodiments of the present disclosure can have the following beneficial effects:

[0056] The cache information stored in the cache comprises source data, that is, part of the source data in the register is stored in the cache; after receiving the data lookup request sent by the distribution queue or the transmission queue, the first source data required by the first entry information can be obtained from the cache information, the number of times of accessing the register by the transmission queue is reduced, the pressure on the read port of the register is reduced, and the movement of data between the register and the transmission queue is reduced; and the cache information can be updated, so that the commonly used source address and the source data corresponding to the commonly used source address are stored in the cache, thereby ensuring the timeliness and commonality of the cache information stored in the cache, and long-term occupation of invalid data can be avoided.

[0057] It should be understood that the foregoing general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0058] The accompanying drawings, which are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure and, together with the specification, serve to explain the principles of the present disclosure.

[0059] Figure 1 is a schematic diagram of a data pre-delivery in related technologies;

[0060] Figure 2 is a flowchart of a data acquisition method provided by an embodiment of the present disclosure;

[0061] Figure 3 is a schematic diagram of cache information in a full-connection form provided by an embodiment of the present disclosure;

[0062] Figure 4 is a schematic diagram of group connected cache information provided by an embodiment of the present disclosure;

[0063] Figure 5 is a schematic diagram of a stage provided by an embodiment of the present disclosure;

[0064] Figure 6 is a flowchart of distributing instructions provided by an embodiment of the present disclosure;

[0065] Figure 7 is a flowchart of obtaining source operands from registers provided by an embodiment of the present disclosure;

[0066] Figure 8 is a flowchart of emitting instructions provided by an embodiment of the present disclosure;

[0067] Figure 9 is a structural schematic diagram of a data acquisition apparatus provided by an embodiment of the present disclosure;

[0068] Figure 10 is a structural schematic diagram of another data acquisition apparatus provided by an embodiment of the present disclosure;

[0069] Figure 11 is a structural schematic diagram of a processor provided by an embodiment of the present disclosure;

[0070] Figure 12 is a structural schematic diagram of another processor provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0071] The exemplary embodiments will be described in detail herein with reference to the attached drawings. The description of the exemplary embodiments is intended to apply to various alternative embodiments as well. The following description is not limited to the exemplary embodiments, but rather, is applicable to any apparatuses in which the present disclosure is applicable. The following description is presented for the purpose of clarity and understanding, and is not intended to limit the scope of the disclosure as set forth in the claims. The description of the exemplary embodiments is intended to apply to all alternative embodiments, unless otherwise indicated.

[0072] In related technologies, within a pipeline, the issue queue may include multiple Entries. An Entry can store instructions to be processed, and these instructions may include operations performed on source operands. Each Entry stores a source address, which refers to the address in a register where the source operand is stored. An Entry can retrieve the source operand from the source address via the register's read port. For example, the instruction stored in Entry0 is "add x1 x2 x3," meaning it retrieves a value from registers x2 and x3 respectively, adds them together, and stores the result in register x1. The two source addresses are x2 and x3, and the destination address is x1. The source operand retrieved from register x2 is 1000, and the source operand retrieved from register x3 is 200. The execution module calculates the instruction stored in Entry0, resulting in a destination operand of 1200, which is stored in register x1.

[0073] For superscalar processors, register file read ports are a crucial resource, and the number of read ports is a key factor determining processor performance. A larger number of read ports allows entries in the issue queue to immediately occupy them, resulting in a faster rate of obtaining the required source operands. However, the number of entries in the issue queue often exceeds the number of read ports. This causes some entries to wait for preceding entries to obtain their required source operands before they can occupy a read port and read data from the registers, thus slowing down the rate of obtaining the required source operands.

[0074] To reduce register read conflicts, processors often employ data forwarding. When the number of back-end pipelines is relatively small, data forwarding is an effective way to alleviate register read conflicts and reduce latency.

[0075] Figure 1 This is a schematic diagram of a data forwarding process in related technologies, such as... Figure 1 As shown, issue queue 101 contains N Entries, each storing instructions. Each instruction requires two source operands, where N is an integer greater than or equal to 1. Assume one pipeline corresponds to one issue queue, meaning the processor includes M issue queues. After executing instructions in the M issue queues, the processor can broadcast the destination operands and destination addresses obtained from the executed instructions in different issue queues. Each pipeline can represent multiple destination operands and destination addresses that need to be forwarded, where M is an integer greater than or equal to 1.

[0076] exist Figure 1The transmit queue 101 shown receives multiple pipeline broadcasts of destination operands and destination addresses. Based on the destination address, transmit queue 101 uses the destination operand as the source operand and writes it into the instruction stored in transmit queue 101 that matches the destination address. If the source address and destination address in the first instruction stored in transmit queue 101 are the same, then the first instruction is considered to match the destination address.

[0077] As the number of backend pipelines increases, the amount of data that needs to be forwarded also increases. It's necessary to compare the destination address of each forwarded data with the source address stored in the transmit queue 101 to determine if an instruction matching the destination address exists. At the same time, the link relationships become increasingly complex, such as... Figure 1 As shown, this combination of links is a 2N * M fully interconnected structure, which requires a very large number of connections, leading to an increase in the number of connections needed, increased complexity, increased broadcast data, and an increase in the number of addresses that need to be compared, resulting in worse timing, increased power consumption, and reduced processor performance.

[0078] Furthermore, when the transmit queue is initially powered on, the first round of instructions received by the transmit queue cannot use the data forwarding technique, resulting in the read port resources of the registers still being strained, and the number of read port conflicts cannot be reduced.

[0079] To reduce register port conflicts, this disclosure provides a data acquisition method, apparatus, and processor. The aim is to store a portion of the register's source data in a cache, enabling the cache to receive data lookup requests from a distribution queue or a transmission queue. This allows the cache to retrieve the first source data required for the first entry from the cached information, reducing the number of times the transmission queue accesses the register, lowering the pressure on the register's read port, and reducing data movement between the register and the transmission queue. Furthermore, the portion of source data stored in the cache can be frequently used source data, increasing the probability of retrieving the first source data from the cached information, allowing more entry information to retrieve source data from the cache. The cached information can also be updated to store frequently used source addresses and their corresponding source data, ensuring the timeliness and usability of the cached information and preventing the long-term occupation of invalid data.

[0080] Figure 2 This is a flowchart of a data acquisition method provided in an embodiment of this disclosure. The method is applied to a processor, which includes a cache, a distribution queue, and a launch queue. Both the distribution queue and the launch queue are used to store entry information, and the cache is used to store at least one cached piece of information, including source data. The method includes:

[0081] Step 201: Cache the data lookup request sent by the distribution queue or the transmission queue; wherein, the data lookup request includes a first source address and a first transmission address, the first source address includes the address of the first source data required by the first entry information, and the first transmission address includes the address of the first entry information in the transmission queue.

[0082] In this embodiment of the disclosure, both the distribution queue and the transmission queue may include at least one entry. Each entry stores entry information, which may include a complete instruction, a part of an instruction, or multiple instructions. Entry information may include at least one of the following: source data, source address, immediate value, opcode, destination address, data preparation identifier, entry validity identifier, and an instruction identifier (IID). Source data includes source operands, and each entry may require one or more source operands.

[0083] The entry information stored in the distribution queue is different from that stored in the launch queue. The distribution queue stores entry information to be distributed, while the launch queue stores entry information to be launched. The position of the entry information in the launch queue can be determined by the first launch address. The source data also corresponds to the first launch address, which includes the entry number of the launch queue where the entry information is located.

[0084] The source data (SRC DATA) is stored at the source address of the register, and the immediate value is the numerical value stored in the entry information. The opcode includes at least one of the following: add, subtract (SUB), multiply (MUL), divide (DIV), square root, etc. An entry is marked as valid. ), ), Valid entry identifiers include entry placeholder identifiers or entry free identifiers, when When =1, it indicates that the entry's valid identifier is a placeholder identifier. The placeholder identifier indicates that the entry information is reliable, and the output entry information includes the placeholder identifier; when... When SRC Ready = 0, the entry validity identifier is the entry idle identifier, which indicates that the entry information is untrusted. The data preparation identifier is SRC Ready, which includes either a data prepared identifier or a data not prepared identifier. When SRC Ready = 0, it indicates that the data is not prepared, meaning the entry information does not include the source operand; when SRC Ready = 1, it indicates that the data is prepared, meaning the entry information includes the source operand, or that the required source operand for the entry information is stored in the register or cache, and a request can be made to read the source operand from the register or cache. The age identifier reflects the duration of the entry information in the pipeline or launch queue, or the dependencies between entry information.

[0085] Table 1 is an example table of entry information. As shown in Table 1, entry information may include multiple fields, namely source data (SRC DATA), source address (SRC Index), immediate value, opcode, destination address, data preparation identifier, and entry validity identifier. ) and age identifiers (IID), etc.

[0086] Table 1

[0087]

[0088] As shown in Table 1 above, the transmit queue includes N entry submodules, each storing one entry information, and each entry information is an instruction. Assume the first entry information is the first instruction stored in Entry0, which is "add x1 x2 x3". The source operand stored at register x2 is 1000, and the source operand stored at x3 is 200. That is, the source address of SRC0 is x2, SRC0 Ready=1, SRC0 DATA=1000; the source address of SRC1 is x3, SRC1 Ready=1, SRC1 DATA=200; the opcode is add. The first instruction may also include or correspond to an entry placeholder identifier, i.e. =1.

[0089] The entry information stored in Entry1 is the second instruction "sub x4 x2 100", which means subtracting 100 from the source operand stored in x2 to obtain the destination operand. The destination operand is stored in x4, with the opcode "sub" and the immediate value "100". That is, in the issue queue, the instruction stored in Entry0 has already obtained the required source operand, while the instruction stored in Entry1 has not yet obtained the required source operand.

[0090] The age identifier (IID) is represented by binary numbers. The oldest IID is "001" (equal to 1), the youngest IID is "100" (equal to 4), and the first instruction's IID is 011 (equal to 3).

[0091] The cache is used to store a portion of the source data in the register and the source address corresponding to that source data. For example, the cache can be used to store frequently used source data. As shown in Table 1 above, the cache can store the source address and source data of the first instruction in Entry0. The two cache information are "the source data stored at x2 is 1000" and "the source data stored at x3 is 200". The maximum storage space of the cache can be less than or equal to the maximum storage space of the register.

[0092] A data lookup request is used to indicate the first source data required to retrieve the first entry information in the launch queue, and the first source data is stored at the first source address of the register. For example, when the distribution queue sends any entry information to the launch queue, the distribution queue can generate a data lookup request corresponding to the distributed entry information, thereby attempting to obtain the source data required for the distributed entry information from the cache, which can reduce the number of register accesses; or, after the launch queue receives new entry information, it can generate a new data lookup request corresponding to the new entry information in real time. Of course, the distribution queue or the launch queue can also generate data lookup requests in other scenarios, which will not be elaborated here.

[0093] Of course, the hardware on the processor for storing source data is not limited to registers or caches. Static Random Access Memory (SRAM) and High Bandwidth Memory (HBM) can also be used to quickly access data. This disclosure does not limit the module for accessing data, nor does it limit the module for receiving data lookup requests.

[0094] Step 202: The cache determines the first source data from at least one cached information based on the first source address, and updates at least one cached information.

[0095] In this embodiment of the disclosure, the cache can determine the first source data based on the first source address; the cache information can also be updated so that the cache includes frequently used source data and the source addresses corresponding to the frequently used source data, thereby ensuring the timeliness and frequent use of the cache information stored in the cache and avoiding the long-term occupation of invalid data.

[0096] Step 203: The cache sends target data information to the transmission queue based on the first source data and the first transmission address; wherein, the target data information includes the first source data.

[0097] In this embodiment of the disclosure, the cache can send target data information to the transmission queue based on the first transmission address. The target data information may also include at least one of the following: the first transmission address, the first source address, the cache address, etc. The cache address refers to the location of the cached information in the cache; for example, the cached information stored at cache address C1 is "the source data stored at x2 is 1000", and the cached information stored at cache address C2 is "the source data stored at x3 is 200".

[0098] The first transmission address can refer to the Entry number in the transmission queue where the first entry information is located. In this case, the target data information may include the first source data and the first source address. The transmission queue can determine whether to write the first source data to SRC0 DATA or SRC1 DATA based on the first source address. Alternatively, the first transmission address can refer to the Entry number where the first source data is located and the SRC DATA number. In this case, the target data information may include the first source data but not the first source address.

[0099] The cache can be connected to the transmit queue point-to-point to send target data information to the transmit queue in a point-to-point manner; alternatively, the cache can be connected to the transmit queue through other devices, which can send target data information to the transmit queue. For example, other devices include multiplexers (MUX), and the processor includes multiple transmit queues. The multiplexer can determine the transmit queue corresponding to the target data information based on a first transmit address; alternatively, the cache can be connected to the broadcast bus, and the transmit queue can obtain target data information by listening to the broadcast bus.

[0100] Step 204: The launch queue writes the first source data into the first entry information.

[0101] In this embodiment of the disclosure, when the target data information includes a first source address, the transmit queue can determine the SRC DATA to be written to the first source data based on the first source address, as shown in Table 1 above. Assuming the transmit queue writes the first source data to SRC1 DATA, it will also set SRC1 Ready to 1. Since the first source data has already been provided by the cache, it is not necessary to read the first source data from the register through the register read port, which reduces the number of register accesses and also reduces the pressure on the register read port.

[0102] This disclosure provides a data acquisition method. The cache information stored in the cache includes the source address and the source data corresponding to the source address. That is, the cache stores part of the source address in the register and the source data corresponding to the source address. After receiving a data lookup request sent by the distribution queue or the transmission queue, the cache can then obtain the first source data required for the first entry information from the cache information, reducing the number of times the transmission queue accesses the register, reducing the pressure on the register read port, and reducing the movement of data between the register and the transmission queue. Moreover, the cache information can be updated so that the cache stores commonly used source addresses and the source data corresponding to commonly used source addresses, thereby ensuring the timeliness and common use of the cache information stored in the cache and avoiding the long-term occupation of invalid data.

[0103] Furthermore, in this disclosure, since the cache stores frequently used cache information, some entry information can obtain the required source data from the cache, reducing the number of register accesses. Also, since the amount of data stored in the cache can be less than the amount of data stored in the registers, the cache occupies a smaller area in the processor. Compared to the distance between the registers and the dispatch queue and the issue queue, the closer the distance between the cache and the dispatch queue and the issue queue, the faster the data communication rate, reducing data transmission latency, accelerating the source data acquisition efficiency of the issue queue, and improving data processing performance.

[0104] In some embodiments, the method further includes at least one of the following:

[0105] Step 205: If the first source data is not found in at least one cached item, receive the next data lookup request;

[0106] Step 206: If the first source data is not found in at least one cached information, a lookup failure message is sent to the launch queue based on the first launch address.

[0107] In this embodiment of the disclosure, when the first source data is not included in the multiple cached information, no message may be sent to the transmission queue. Based on the fact that no cached information has been obtained within the first time period, the transmission queue sends a data read request for the first entry information to the register to read the first source data from the register. The data read request is "request to read the data at the first source address". Caching can also reduce the amount of data sent and reduce power consumption.

[0108] Alternatively, if the first source data is not included in multiple cached entries, the cache can first send a lookup failure message to the launch queue to inform it that the first source data required for the first entry does not exist in the cache. The lookup failure message indicates that the first source data required for the first entry does not exist in the cache. Based on the lookup failure message, the launch queue can generate a data read request for the first entry to read the first source data from the register. When a next data lookup request exists, the cache receives the next data lookup request.

[0109] In some embodiments, the cache information further includes a source address and a valid data identifier; the cache determines the first source data from at least one cache information based on the first source address, including steps 2021 to 2022:

[0110] Step 2021: Based on the first source address, the cache determines the first cache information that matches the first source address from at least one cache information; wherein, the data validity identifier of the first cache information is used to indicate that the first cache information is in a valid state, and the second source address of the first cache information matches the first source address;

[0111] Step 2022: The cache uses the source data included in the first cache information as the first source data.

[0112] In this embodiment of the disclosure, the cached information includes the source address, source data, and a data validity identifier. The data validity identifier indicates the validity of the cached information; for example, the data validity identifier is... ,when When =1, it indicates that the cached information is valid; when When the value is 0, it indicates that the cached information is invalid. When updating frequently used cached information, priority should be given to resetting the cached information. The cached information with a value of 0 is overwritten.

[0113] The cache compares the first source address with the source addresses in each cached information. When the source address of any cached information is the same as the first source address, it is determined that the source address of the cached information matches the first source address. The cached information including the first source address is also determined to be the first cached information. This allows the first source data to be obtained from the frequently used entry information stored in the cache, rather than from the register. This reduces the number of register accesses and the number of read port conflicts, thus improving data processing efficiency.

[0114] In some embodiments, the cache information further includes a confidence value; the cache updates at least one piece of cache information, including at least one of the following:

[0115] Step 301: The cache increments the first confidence value of the first cached information by A first step length values;

[0116] Step 302: The cache reduces the second confidence value of the second cache information by B second step size values; wherein, the second cache information is the information other than the first cache information among multiple cache information;

[0117] Step 303: Based on a preset period, the confidence value of each cached piece of information is reduced by C third step length values;

[0118] Where A, B, and C are all integers greater than or equal to 1.

[0119] In this embodiment of the disclosure, Table 2 is an example table of cache information. As shown in Table 2, the cache information includes source data, source address, data validity identifier and confidence value.

[0120] Table 2

[0121]

[0122] As shown in Table 2 above, each row represents a cached information. In the first cached information, the source address (tag) is x2, the source data is 1000, the data validity flag is 1, and the confidence value is 100, indicating that the first cached information is valid. The source data stored in the first cached information is the same as the source data stored in register x2. Similarly, the source data included in the second cached information is the same as the source data at register x3, the source data included in the fourth cached information is the same as the cached information at register x5, and the source data included in the fifth cached information is the same as the cached information at register x7. In the third cached information, the source address is x6, the source data is 400, the data validity flag is 0, and the confidence value is 0, indicating that the third cached information is invalid. The source data stored in the third cached information is the same as the source data stored in register x6.

[0123] The value of the data validity identifier is related to the confidence value. The data validity identifier indicates whether the cached information is valid, while the confidence value indicates whether the cached information is frequently used. The confidence value increases with the number of times the cached information is read. Conversely, the confidence value decreases with the number of times the cached information is not read, and the cached information also decreases with the increase of a preset period, which includes the clock cycle. As shown in Table 2 above, the five confidence values, from largest to smallest, are 100, 90, 80, 20, and 0. A larger confidence value indicates that the cached information is more frequently used. When the confidence value is 0, it indicates that the third cached information is infrequently used. For example, if the third cached information is not read during multiple reads of the cached information, the confidence value gradually decreases to 0 as the third cached information is not read, and the data validity identifier of the third cached information also switches to 0 as the confidence value becomes 0.

[0124] Taking the data lookup request as "request to retrieve source data at x2" as an example, the first source address is x2. The cache can determine from multiple cache information that the source address included in the first cache information is the same as the first source address, and thus determine the first cache information as the first cache information.

[0125] The confidence value of the first cached information can be increased to indicate that the first cached information is frequently used. Assuming that the length of the first step of A is 10, the confidence value of the first cached information will be updated to 110.

[0126] Similarly, the confidence value of the first cached information can be reduced instead of increased, indicating that the second cached information is not frequently used in this cached information read; or the confidence value of the first cached information can be increased while the confidence value of the second cached information is reduced. Multiple second cached information entries are designated as the second cached information, ..., the fifth cached information. Assuming B second step sizes are 5, the confidence value of the second cached information will be updated from 90 to 85. The cache can synchronously or sequentially update the confidence value of at least one second cached information entry.

[0127] The second cached information can be any information among multiple cached information other than the first cached information. In this case, the confidence value of the third cached information can also be reduced. Alternatively, the second cached information can be any information among multiple cached information other than the first cached information and the cached information including the data free flag. The data valid flag includes a data placeholder flag or a data free flag. For example, the data placeholder flag is... =1 indicates that the cached information is valid; the data idle flag is... When the confidence value is 0, it indicates that the cached information is invalid; in this case, there is no need to update the confidence value of the third cached information. Of course, if the first cached information is not included in at least one cached information, the cache can reduce the confidence value of all cached information; or, reduce the confidence value of all cached information that includes data placeholder identifiers.

[0128] The confidence value of each cached information can decrease as the preset period increases, for example, the preset period is a clock cycle. That is, regardless of whether the cached information is the first cached information, the confidence value can decrease as the preset period increases. For example, if C first steps have a value of 1, it means that the confidence value of the cached information will decrease by 1 every preset period. The confidence value of the cached information can be executed in real time as the preset period increases.

[0129] Confidence value can also be referred to as confidence level, hit count, etc., reflecting the popularity or frequency of use of cached information. When cached information is hit, it means that the cached information includes the first source address of the data lookup request. The cache can reflect whether each cached information is frequently used by at least one of the following: increasing the confidence value of the first cached information, decreasing the confidence value of the second cached information; and, when the first source address is not included in the cached information, that is, the first source data cannot be found in the cache. Alternatively, to speed up the update frequency of cached information, the confidence value of each cached information can be reduced by C third step values ​​over a preset period.

[0130] The first, second, and third step length values ​​can be equal, for example, all three can be equal to 1. A, B, and C can also be equal, for example, all three can be equal to 5. This disclosure does not limit the values ​​of the first, second, and third step length values, nor does it limit the values ​​of A, B, and C. Table 2 above is merely an example of cached information. The source data, source address, data validity identifier, and confidence value in the cached information can also be other values. For example, the confidence value can be a binary number or other preset characters, indicating whether the entry information is frequently used. This disclosure also does not limit the source data, source address, data validity identifier, and confidence value.

[0131] In some embodiments, the method further includes at least one of the following:

[0132] Step 401: The cache uses cache information with a confidence value less than or equal to the first preset threshold as the third cache information, and determines the state corresponding to the valid data identifier of the third cache information as invalid.

[0133] Step 402: The cache uses cache information with a confidence value less than or equal to the first preset threshold as the third cache information and deletes the third cache information.

[0134] In this embodiment of the disclosure, as shown in Table 2 above, the first preset threshold is 0. When the confidence value is less than or equal to 0, the data valid identifier is switched from the data placeholder identifier to the data idle identifier, the data valid identifier of the third cache information is the data idle identifier, and the third cache information is the third cache information.

[0135] The cache can either not delete the third cache information, but simply switch the data validity identifier of the third cache information from a data placeholder identifier to a data free identifier. When new cache information is obtained, the third cache information can be directly overwritten, or the third cache information can be directly deleted.

[0136] As shown in Table 2 above, assuming that the second step size of B is 20, the cache executes step 302, updating the confidence value of the fourth cache information from 20 to 0. At this time, the cache determines the fourth cache information as the third cache information based on the confidence value of the fourth cache information being equal to 0. The fourth cache information can be deleted in real time to increase the cache's storage space.

[0137] In some embodiments, the cache is used to store at least one cached piece of information in a fully associative manner; step 2021 includes steps 5011 to 5013, wherein:

[0138] Step 5011: The cache determines a first index identifier based on the first source address; wherein, the first index identifier is related to the first source address;

[0139] Step 5012: The cache determines the second source address based on the first index identifier;

[0140] Step 5013: The cache uses the cache information of the second source address as the first cache information.

[0141] In this embodiment of the disclosure, full associativity is a data caching method that allows cached information to be stored in any location when there is sufficient storage space in the cache. When searching for cached information, a first source address can be used as an index identifier, and the source addresses of each cached piece of information are compared in parallel with the first index identifier. When the source address of any cached piece of information is the same as the first source address, the source address that is the same as the first source address is designated as the second source address.

[0142] Figure 3 This is a schematic diagram of a fully interconnected form of cached information provided in an embodiment of this disclosure, such as... Figure 3 As shown, each line represents a cached piece of information. The cache stores D cached pieces of information, where D is an integer greater than or equal to 1. The cached information includes a valid data identifier. The cached information includes a source address (Reg), a confidence value, and source data (DATA). The cached information may include up to 77 bits of data, the size of the valid data identifier may be up to 1 bit (Binary digit), the size of the source address may be up to 9 bits, the size of the confidence value may be up to 3 bits, and the size of the source data may be up to 64 bits.

[0143] The source address is Reg, and index indicates that the source address is an index identifier. The cache can determine whether there is a source address that is the same as the first source address among D source addresses, based on the obtained first source address as the index identifier; the source address that is the same as the first source address among D source addresses is taken as the second source address; the cache information where the second source address is located is taken as the first cache information, so that it can determine whether the stored D cache information includes the first source data based on the first source address.

[0144] For example, taking a data lookup request as "request to retrieve source data at x2", the first source address is x2, the first index identifier is x2, and the cache can compare the various source addresses in Table 2 above in parallel. Figure 3 Check if the source addresses and the first index identifier are the same; if it is determined that the source address and the first index identifier of the first cached information are the same, then the source address of the first cached information is used as the second source address, the second source address is x2, the first cached information is used as the first cached information, and the second source data stored in the first cached information is 1000.

[0145] In some embodiments, the cache is used to store at least one cached piece of information in a group-associative manner, wherein the cached information in each group has a partially identical index identifier; step 2021 includes steps 5021 to 5024, wherein:

[0146] Step 5021: The cache determines the second index identifier based on the first source address; wherein, the first source address includes a first part address and a second part address, and the second index identifier is related to the first part address;

[0147] Step 5022: The cache determines at least one fourth cache information based on the second index identifier; wherein each fourth cache information corresponds to the second index identifier;

[0148] Step 5023: The cache determines the third index identifier based on the first source address; wherein the third index identifier is related to the second part of the address;

[0149] Step 5024: The cache determines the first cache information from at least one fourth cache information based on the third index identifier.

[0150] In this embodiment of the disclosure, group associativity is a data caching method. The cache space can be divided. Taking 4-way group associativity as an example, this means the cache space is divided into 4 groups. Each group can store cached information. The cached information stored in the same group has partially identical index identifiers. For example, the partially identical index identifiers are part of the source address in the cached information within the same group. The cached information stored in the first group all includes source addresses starting with 'x', the cached information stored in the second group all includes source addresses starting with 'y', the cached information stored in the third group all includes source addresses starting with 'z', and the cached information stored in the fourth group all includes source addresses starting with 'w'. That is, the cached information in the first group has partially identical index identifiers of 'x', the cached information in the second group has partially identical index identifiers of 'y', the cached information in the third group has partially identical index identifiers of 'z', and the cached information in the fourth group has partially identical index identifiers of 'w'.

[0151] Figure 4 This is a schematic diagram of group-linked cache information provided in an embodiment of this disclosure, such as... Figure 4 As shown, the cache space is divided into two groups. The first group stores M cached items, and the second group stores N cached items, where M and N are both integers greater than or equal to 1. Figure 3 Let M + N = D, meaning that D cached information items can be stored in the cache in a fully associative or set-associative manner. Each line represents one cached item, and the cached information includes a data validity identifier. The cached information includes a source address (Reg), a confidence value, and source data (DATA). The cached information may include up to 77 bits of data, the size of the valid data identifier may be up to 1 bit (Binary digit), the size of the source address may be up to 9 bits, the size of the confidence value may be up to 3 bits, and the size of the source data may be up to 64 bits.

[0152] The source address is Reg, and index indicates that the source address is an index identifier. The cache can determine the first part of the first source address as the second index identifier based on the obtained first source address; when determining the second index identifier, the first part of the first source address can be determined according to preset rules. The cache first determines the group based on the second index identifier, and then compares in parallel whether each source address within the group matches the third index identifier, thereby reducing the number of source addresses compared, reducing energy consumption, and speeding up data retrieval efficiency.

[0153] For example, taking the data lookup request as "request to retrieve source data at x2", the first source address is x2, assuming the first part of the address is "x" and the second part of the address is "2"; the second index identifier is "x", and the cache can determine the source address in the first group of cached information and compare it with the first source address based on the second index identifier; the third index identifier is "2", and the first group of source addresses and the third index identifier are compared in parallel to see if they match, that is, to determine whether each source address in the first group is the same as "2" except for x, and thus the source address of the first cached information can be determined as the second source address, and the first cached information is used as the first cached information.

[0154] Of course, this disclosure uses two indexes as an example to illustrate the process of determining the first cached information in storing at least one cached information in a group-linked manner. Multiple indexes can also be set. That is, when there are many cached information in a group, the cached information in the group can be further divided into groups based on the source address of the cached information. This disclosure does not limit the number of groups, whether each group is further divided, or the number of indexes.

[0155] In some embodiments, the method further includes steps 601 to 603, wherein:

[0156] Step 601: Cache and obtain the first indicator information; wherein, the first indicator information includes the source address and source data;

[0157] Step 602: Cache the confidence value corresponding to the first indicator information and the data validity identifier corresponding to the first indicator information;

[0158] Step 603: The cache generates and stores fifth cache information based on the first indicator information, the confidence value corresponding to the first indicator information, and the data validity identifier corresponding to the first indicator information.

[0159] In this embodiment of the disclosure, the cache can add new cache information, and the fifth cache information refers to the new cache information. The cache adds a confidence value and a data validity identifier to the first indicator information. The added confidence value can be a preset confidence value, for example, a preset confidence value of 100; the added data validity identifier is a data placeholder identifier, that is, the newly added cache information is valid cache information, so that the cache can update the stored cache information, add new cache information in a timely manner, and facilitate subsequent data retrieval.

[0160] In some embodiments, the processor further includes registers and an execution module, and the method further includes at least one of the following:

[0161] Step 701: The cache retrieves the first indicator information from the register; wherein the register is used to store at least one indicator information.

[0162] Step 702: Cache the first indicator information broadcast by the receiving execution module or the transmission queue;

[0163] Step 703: Cache the first indicator information sent by the execution module.

[0164] In this embodiment of the disclosure, the first indicator information may be obtained through at least one of the following methods: randomly obtaining the first indicator information from a register, receiving the first indicator information sent or broadcast by the execution module through data forwarding technology, or obtaining the first indicator information broadcast by the transmission queue by listening to the broadcast bus.

[0165] When the processor is first powered on, the cache does not contain cached data. The cache is connected to the registers, and the cache can randomly read the first indicator information from the registers.

[0166] As shown in Table 1 above, Entry2 stores the third instruction, which is "add x2 x5 x6". The execution module processes the third instruction and calculates the destination data as 1000, meaning that the data stored at register x2 is 1000. The execution module, the transmit queue, and the buffer are all connected to the broadcast bus. The execution module can use data forwarding technology to broadcast the first indicator information via the broadcast bus. The first indicator information is "the source data stored at x2 is 1000". The buffer can obtain the first indicator information by listening to the broadcast bus. Alternatively, the execution module can also be connected to the register and the buffer. The execution module controls the register to write 1000 at x2 and sends the first indicator information to the buffer. For example, a point-to-point cable connection can be used between the execution module and the buffer to ensure the transmission efficiency of the first indicator information and to ensure that the buffer receives the first indicator information.

[0167] Assuming the cache is not directly connected to the execution module, and the execution module does not broadcast the first indicator information, the execution module control register stores 1000 at x2. In the first instruction stored in Entry0, SRC0 DATA has a value of 1000, and SRC1 DATA has a value of 200. When the transmit queue outputs the first instruction, it can broadcast two first indicator information via the broadcast bus: "the source data stored at x2 is 1000" and "the source data stored at x3 is 200". Thus, the cache can learn that the registers "the source data stored at x2 is 1000" and "the source data stored at x3 is 200" by listening to the broadcast bus.

[0168] The cache stores at least one third source address and the third source data corresponding to the third source address. The first indicator information includes a fourth source address and fourth source data. When the first indicator information is received, the fourth source address included in the first indicator information can be compared with at least one third source address stored in the cache. When it is determined that any third source address and the fourth source address are the same, the third source data corresponding to the third source address that is the same as the fourth source address can be updated. Alternatively, the first indicator information containing the fourth source address that is the same as any third source address can be deleted.

[0169] For example, processors can support address renaming, a technique to eliminate memory alias ambiguity and improve out-of-order execution efficiency. By establishing renaming mappings for the addresses of load / store instructions, subsequent non-conflicting memory operations can be scheduled in advance even if the address has not been fully calculated, thus hiding memory access latency. With address renaming supported, when the cache receives the first indicator information broadcast by the issue queue via the broadcast bus, it can compare the fourth source address with the third source address in the first indicator information to avoid duplicate data storage; if a third source address identical to the fourth source address exists, the first indicator information can be deleted. In processors without address renaming support, when the cache receives the first indicator information broadcast by the issue queue via the broadcast bus, it can compare the fourth source address with the third source address in the first indicator information; if a third source address identical to the fourth source address exists, the third source data corresponding to the third source address can be set equal to the fourth source data, thus achieving timely updates of data within the cache.

[0170] In some embodiments, the cache is used to store at least one sixth cache information, the sixth cache information including a confidence value; the cache stores fifth cache information, including steps 6031 to 6034, wherein:

[0171] Step 6031: In response to the fifth cache information to be written, the cache compares the storage space value with the second preset threshold; wherein, the storage space value is used to indicate the storage space for storing the fifth cache information.

[0172] Step 6032: If the cache storage space value is less than the second preset threshold, determine the limit confidence value based on the confidence value of the sixth cache information;

[0173] Step 6033: Delete the sixth cached information containing the limit confidence value;

[0174] Step 6034: Write the fifth cache information to the cache.

[0175] In this embodiment, cache information that is effectively identified as a data placeholder is used as the sixth cache information. The sixth cache information includes the source address, source data, confidence value, and data placeholder. The cache can delete cache information that is effectively identified as a data free flag in real time.

[0176] The fifth cache information refers to new cache information that needs to be stored. Before storing new cache information, it is first determined whether there is enough storage space in the cache, that is, by comparing the storage space value with the second preset threshold, such as... Figure 3 or Figure 4 As shown, the storage space for each sixth cached information in the cache can be the same, meaning the maximum length of the sixth cached information is 77 bits. The second preset threshold can be set to 77 bits. When the storage space is less than 77 bits, it indicates that the cache cannot store new cached information, and one sixth cached information needs to be deleted from at least one stored sixth cached information. The value of the second preset threshold is within the range of being greater than or equal to the actual length of the fifth cached information and less than or equal to the maximum length of the sixth cached information.

[0177] When the cache is used to store at least one cached piece of information in a fully associative manner, the storage space value is used to indicate the remaining storage space of the cache; when the cache is used to store at least one cached piece of information in a group-associative manner, the storage space value is used to indicate the remaining storage space of the group corresponding to the fifth cached piece of information.

[0178] When determining the sixth cache information to be deleted from at least one stored sixth cache information, the confidence value of each sixth cache information can be used to determine the sixth cache information to be deleted. That is, from the confidence values ​​of at least one sixth cache information, the smallest confidence value is determined, and the smallest confidence value is used as the limit confidence value. The sixth cache information including the limit confidence value is then deleted.

[0179] For example, as shown in Table 2 above, cache deletion includes data validity identification. =0 cache information. The confidence values ​​of the sixth cache information stored in the cache, from top to bottom, are 100, ..., 90, 20, 80, respectively. Assuming 20 is the minimum confidence value, the maximum confidence value is 20. Cache deletion includes "tag=x5, DATA=600, The sixth cached information is "=1, confidence value=20".

[0180] In some embodiments, the cache is used to store at least one sixth cache information in a group-associative format; the method further includes steps 801 to 802, wherein:

[0181] Step 801: The cache determines the fourth index identifier based on the fifth cache information; wherein, the fourth index identifier is related to the source address where the fifth cache information is stored;

[0182] Step 802: The cache determines the storage space value based on the fourth index identifier.

[0183] In this embodiment of the disclosure, the group containing the fifth cached information is first determined, such as... Figure 4 As shown, the sixth cache information is divided into groups based on its source address, with each group containing the same source address portion. The fourth index identifier and the fourth source address portion are identical. For example, if the fourth source address is x1 and the fourth index identifier is x, and assuming the sixth cache information in the first group has a partially identical index identifier x, then it can be determined that the fifth cache information needs to be stored in the first group. The storage space value at this time is the value of the remaining storage space in the first group. Thus, the group used to store the fifth cache information can be determined by the fourth index identifier, and the remaining storage space of this group can be determined. This ensures that the cache information within the same group has a partially identical source address, and the identical source address portion can be used as the index identifier of the group, thereby reducing the number of cache information items searched each time.

[0184] In some embodiments, the processor further includes a wake-up module; the method further includes at least one of the following:

[0185] Step 901: The distribution queue sends the first entry information to the launch queue and sends a data lookup request corresponding to the first entry information to the cache;

[0186] Step 902: The transmit queue determines the first entry information corresponding to the wake-up information based on the wake-up information sent by the wake-up module; generates a data lookup request based on the first entry information corresponding to the wake-up information, and sends the data lookup request to the cache; wherein, the wake-up information is used to indicate that the first source data required by the first entry information is stored in the cache.

[0187] In this embodiment, the first entry information can refer to the latest entry information sent from the distribution queue to the launch queue. This allows the cache to immediately retrieve the first source data required by the first entry information while it is stored in the launch queue, thereby reducing the number of register accesses, lowering the pressure on the register read ports, and reducing data movement between the registers and the launch queue. Furthermore, the number of entry information sent from the distribution queue to the launch queue each time is often less than the number of entry information that the launch queue can store. Therefore, the cache can process data lookup requests in real time or with low latency, accelerating the source data lookup rate. Additionally, the maximum storage space of the cache can be less than the maximum storage space of the registers, the cache size is smaller than the register size, and the distance between the cache and the launch queue can be less than the distance between the registers and the launch queue, reducing data transmission latency and the latency of obtaining the first source data from the first entry information, thus accelerating the data processing rate and improving data processing performance.

[0188] When the first source data required for the first entry information has not yet been calculated by the execution module, neither the register nor the cache contains the first source data. The wake-up module can connect to the cache to determine in real time whether the cache stores the first source data. When the cache execution step 702 obtains the first indicator information through the broadcast bus or the execution step 703 receives the first indicator information sent by the execution module, and the fourth source address included in the first indicator information is the same as the first source address, the wake-up module can remind the transmit queue. The wake-up information is used to indicate that the cache contains the first source data corresponding to the first source address. The transmit queue takes the entry information where the first source address is located as the first entry information, so that it can obtain the first source data from the cache. The distance between the cache and the transmit queue can be less than the distance between the register and the transmit queue, which reduces the data transmission latency and the latency of obtaining the first source data for the first entry information, speeds up the data processing rate, and improves the data processing performance. It also reduces the number of register accesses and reduces the pressure on the register read port.

[0189] In some embodiments, the first entry information includes second indicator information, which includes first source data and a first source address; the method further includes steps 207 to 208, wherein:

[0190] Step 207: The transmission queue broadcasts the second indicator information via the broadcast bus;

[0191] Step 208: The transmit queue writes the first source data into the second entry information that matches the first source address.

[0192] In this embodiment of the disclosure, step 207 is executed after step 204, that is, the transmission queue can broadcast the second indicator information of the first entry information after the source data of the first entry information is obtained; or, the transmission queue can broadcast the second indicator information of the first entry information during the output of the first entry information, etc. The source address included in the second entry information is the same as the first source address, so that the second entry information does not obtain the first source data from the register or cache, reducing the number of accesses to the register or cache; and the rate at which the second entry information obtains the first source data through broadcast is higher than the rate at which the first source data is obtained through the register or cache, so that the first source data can be obtained faster through broadcast, speeding up the data processing efficiency and reducing the latency of obtaining the first source data; it can also reduce the number of times the first source data is moved between the register and the transmission queue, and reduce the number of times the first source data is moved between the cache and the transmission queue.

[0193] In some embodiments, source data includes source operands, and destination data includes destination operands. Figure 5 This is a schematic diagram of a stage provided in an embodiment of this disclosure, such as... Figure 5 As shown, the processing of entry information involves multiple stages: IFU stage 51, IDU stage 52, Disp stage 53, Instruction Issue Stage (IIS) 54, Register Read (RR) stage 55, Execute (EX) stage 56, and Write Back (WB) stage 57. Disp refers to either a Dispatch Queue or a Dispatch Buffer.

[0194] In this embodiment, during the IFU stage 51, the Instruction Fetch Unit (IFU) acquires uncracked entry information; during the IDU stage 52, the Instruction Decode Unit (IDU) decodes the uncracked entry information to obtain decoded entry information; during the Disp stage 53, the dispatch queue acquires the decoded entry information and uses it as fourth entry information. The dispatch queue can store a second set, which includes at least one fourth entry information. The dispatch queue can send the stored fourth entry information to the dispatch queue, and can also use the sent fourth entry information as first entry information, generate data lookup requests for each first entry information, and send at least one data lookup request to the cache. During the instruction dispatch stage 54, the dispatch queue can send third entry information, including source data, to the execution module. During the EX stage 56, the execution module receives the third entry information sent by the dispatch queue and processes the source data in the third entry information based on the opcode in the third entry information to obtain destination data; the third entry information also includes a destination address. In WB phase 37, the execution module control register writes the destination data to the destination address.

[0195] In some embodiments, the entry information includes instructions. Figure 6 This is a flowchart of a distribution instruction provided in an embodiment of this disclosure, such as... Figure 6 As shown, steps 61 to 67 are included, wherein:

[0196] Step 61, the distribution queue determines the launch queue. The number of entries n that are 0, and the number of instructions m in the dispatch queue;

[0197] Step 62: The distribution queue checks whether n is greater than or equal to m. If yes, proceed to step 63; otherwise, proceed to step 64.

[0198] Step 63: The distribution queue sends m instructions to the launch queue, and assigns the m allocated Entry items to the corresponding... Set to 1; simultaneously send the data lookup request corresponding to each of the m instructions to the cache;

[0199] Step 64: The distribution queue sends n instructions to the launch queue, and assigns the corresponding n Entry items to the distribution queue. Set to 1; the number of instructions in the dispatch queue is mn; simultaneously, send the data lookup request corresponding to each of the m instructions to the cache;

[0200] Step 65: Does the cache contain the source data required by any instruction? If yes, proceed to step 66; otherwise, proceed to step 67.

[0201] Step 66: The cache sends the source data required for a certain instruction to the SRC DATA in the Entry corresponding to that instruction in the launch queue, and sets SRC DATA Ready to 1;

[0202] Step 67: The wake-up module obtains source addresses that are not included in the cache, and wakes up the transmit queue when such source addresses are included in the register or cache.

[0203] In this embodiment of the disclosure, the Entry item in the launch queue stores... Instructions with a value of 0 are invalid instructions. The dispatch queue can determine the first number n of invalid instructions in the dispatch queue, and can also determine the second number m of instructions stored in the dispatch queue. By comparing the first number n and the second number m, the number of instructions to be sent to the dispatch queue is determined. The number of instructions to be sent to the dispatch queue is the smaller value between m and n.

[0204] For example, if m equals 3 and n equals 2, it means that the transmit queue stores 2 invalid instructions, the dispatch queue stores 3 instructions to be sent, and the dispatch queue can provide 2 instructions to be sent to the transmit queue. When the dispatch queue sends 2 instructions to be sent to the transmit queue, it can also send a data lookup request for each instruction to be sent to the cache. The data lookup request is used to indicate how to retrieve the source data of the instruction being sent.

[0205] Assume two instructions being sent are the first instruction "add x1 x2 x3" and the second instruction "sub x4 x2 100" as shown in Table 1. The data lookup request corresponding to the first instruction is "request to retrieve source data at source address x2, request to retrieve source data at source address x3", and the data lookup request corresponding to the second instruction is "request to retrieve source data at source address x2". The cache can determine that the source data at source address x2 is 1000 and the source data at source address x3 is 200 based on the first data lookup request. The first data lookup request also includes the position of the first instruction in the launch queue. The position of the first instruction in the launch queue can be "1", indicating that the first instruction is stored in the first entry in the launch queue, and then the first target data information is sent to the launch queue. The first target data information can be "in the entry information stored in the first entry, write source data 1000 at source address x2, and write source data 200 at source address x3".

[0206] As shown in Table 1 above, the entry information also includes SRC0 DATA Ready and SRC1 DATA Ready. SRC0 DATA Ready indicates that SRC0 DATA has been written to the entry information, and SRC1 DATA Ready indicates that SRC1 DATA has been written to the entry information. SRC0 Ready indicates that SRC0 DATA is stored in a register or buffer, and SRC1 Ready indicates that SRC0 DATA is stored in a register or buffer. When the transmit queue writes 1000 and 200 to the entry information stored in the first Entry, it also sets SRC0 Ready and SRC0 DATA Ready, SRC1 Ready and SRC1 DATA Ready of the entry information stored in the first Entry to 1.

[0207] When the cache does not contain the source data required for the first entry information, the wake-up module can be informed of the first source address corresponding to the first source data not included in the cache. Thus, when the wake-up module determines that the register includes the first source address not included in the cache, it can instruct the launch queue to obtain the first source data required for the first entry information from the register. When the register does not include the first source address, it indicates that the first source data corresponding to the first source address has not yet been calculated by the execution module. When the wake-up module determines that the cache or register includes the first source data corresponding to the first source address, it can instruct the launch queue to obtain the first source data required for the first entry information from the cache or register.

[0208] Figure 7 This is a flowchart illustrating how to obtain a source operand from a register, as provided in an embodiment of this disclosure. Figure 7 As shown, steps 71 to 75 are included, wherein:

[0209] Step 71: The wake-up module wakes up the instruction in the transmit queue. The SRC0 Ready or SRC1 Ready of the wake-up instruction is set to 1.

[0210] Step 72: The second arbitration module counts the number r of entries in the transmit queue where the instruction's VLD is 1 and SRC0 Ready is 1 and / or SRC1 Ready is 1;

[0211] Step 73: The second arbitration module determines whether r is greater than 0. If yes, proceed to step 74; otherwise, proceed to step 71.

[0212] Step 74: The second arbitration module selects the oldest instruction from the r instructions based on its IID.

[0213] Step 75: The second arbitration module determines the selected instruction I and reads the source operands required by instruction I from the register. After the transmit queue receives the source operands, it writes the source operands into SRC0 DATA or SRC1 DATA of instruction I and sets SRC0 DATA Ready or SRC1 DATA Ready to 1.

[0214] In this embodiment of the present disclosure, as shown in Table 1 above, the first instruction stored in Entry 0 is "add x1 x2 x3", and the third instruction stored in Entry 2 is "add x2 x5 x6". That is, the destination operand 1000 of the third instruction can only be written to the SRC0 DATA of the first instruction after the execution module calculates it. After the destination operand is written to register x2, the wake-up module can compare the source addresses of the instructions stored in each Entry, determine the wake-up Entry 0 based on the SRC0 Index of the first instruction being x2, and control the transmit queue to set the SRC0Ready of the first instruction to 1, meaning the source operand required for the SRC0 of the first instruction is ready.

[0215] The second arbitration module may include a multiplexer, a transmit queue, and register connections. The second arbitration module can count whether the number r of entries that have not yet obtained the required source data and whose SRC0 Ready is 1 and / or SRC1 Ready is 1 is greater than 0, and determine the number of register accesses. As shown in Table 1 above, Entry 0 stores the first instruction, Entry 1 stores the second instruction, and Entry 3 stores the fourth instruction. Assuming that the SRC0 Ready value for Entry 0, Entry 1, and Entry 3 is 1, and none of them have obtained the source operand, the second arbitration module can determine that the age identifiers of the first, second, and fourth instructions, from oldest to youngest, are 010, 011, and 100. That is, it first obtains the source operand required by the fourth instruction, obtaining the source operand stored at x5 as 600, and sets the SRC0 DATA of the fourth instruction to 600; then it obtains the source operand required by the first instruction, obtaining the source operand stored at x2 as 1000, and sets the SRC0 DATA of the first instruction to 1000, thus enabling it to obtain the source data required by the older instruction first.

[0216] The launch queue can generate data read requests corresponding to entry information. The processor also includes a second arbitration module, which determines a target data read request based on at least one data read request and sends the target data read request to a register. The data read request includes an age identifier for the entry information. The second arbitration module can determine the oldest age identifier based on at least one age identifier and use the data read request containing the oldest age identifier as the target data read request. The register determines and returns the source data required for the entry information based on the data read request, and the launch queue can write the required source data for the entry information.

[0217] The transmit queue takes the entry information with the required source operands as the fifth entry information and sends the age identifier of the fifth entry information to the first arbitration module. The first arbitration module determines the target age identifier from at least one age identifier. Assuming that the first arbitration module determines the fifth entry information containing the target age identifier as the first entry information to be output, it controls the transmit queue to output the first entry information corresponding to the target age identifier. The issue queue simultaneously broadcasts the first indicator information of the first entry to be output. This allows the issue queue to obtain not only source data from the registers but also the source data needed to obtain the entry information matching the first source address via the broadcast first source data in the first entry to be output. Furthermore, it can also obtain the source data needed to obtain the entry information matching the first source address via broadcast when the processor is initially powered on. This reduces the number of register reads and avoids the number of times source data is moved between the registers and the issue queue, reducing unnecessary data movement and lowering power consumption. Moreover, the issue queue is limited by the issue port width, allowing for a smaller number of first entries to be output at a time. Broadcasting the first indicator information while the first entry is being output or is being output further reduces the number of first indicator messages broadcast simultaneously, reducing the number of addresses that need to be compared at the same time, ensuring processor timing, and improving processor performance. Additionally, the broadcast bus reduces the number of connections between different issue queues, lowering the complexity of the link relationships.

[0218] In EX phase 56, the execution module receives the first entry information and processes the first source data based on the opcode in the first entry information to obtain the second destination data; the first entry information also includes the second destination address. In WB phase 37, the execution module control register writes the second destination data to the second destination address.

[0219] Figure 8 This is a flowchart of a launch command provided in an embodiment of this disclosure, such as... Figure 8 As shown, steps 81 to 89 are included, wherein:

[0220] Step 81: The first arbitration module counts the number p of entries in the transmit queue (VLD is 1, and SRC0 DATA Ready is 1 and / or SRC1 DATA Ready is 1);

[0221] Step 82: The first arbitration module determines whether p is greater than 0. If yes, proceed to step 82; otherwise, proceed to step 81.

[0222] Step 83: The first arbitration module selects the oldest instruction L from p instructions based on IID;

[0223] Step 84: The transmit queue transmits instruction L to the execution module, and at the same time broadcasts the source address and source operands of instruction L to all entries in the transmit queue with VLD set to 1.

[0224] Step 85: For all entries with VLD of 1, the transmit queue determines whether the SRC0 Index and / or SRC1 Index match the SRC0 Index and / or SRC1 Index of the L command.

[0225] Step 86: The transmission queue determines whether there is a successfully matched address. If yes, proceed to step 87; otherwise, proceed to step 81.

[0226] Step 87: The SRC0 Index of Entry2 matches the SRC0 Index of instruction L;

[0227] Step 88: Write the SRC0 DATA of instruction L into the SRC0 DATA in Entry2, and set SRC0 DATAReady=1;

[0228] Step 89: Instruction L is sent to the corresponding execution module to begin execution, and the VLD of the Entry item corresponding to instruction L is set to 0.

[0229] exist Figure 8 In this context, 'p' represents an instruction that is ready to be transmitted. When 'p' is greater than or equal to 1, it means the transmission queue can transmit at most 'p' instructions. Limited by the transmission port width, when 'p' is greater than the transmission port width, it indicates that the transmission queue cannot send 'p' instructions in parallel, and the instruction to be sent first needs to be determined from among the 'p' instructions. The first arbitration module can be used to determine the transmission order of each instruction among the 'p' instructions. Based on the instruction's age identifier (IID), the instruction L with the oldest instruction identifier is determined, and instruction L is the instruction to be transmitted. Instruction L is then transmitted. Simultaneously with the transmission of instruction L, the source address (SRC Index) and source operand (SRC DATA) of instruction L are broadcast.

[0230] For example, instruction L is the first instruction, broadcasting "SRC0 Index=x2, SRC0 DATA=1000" and "SRC0 Index=x3, SRC0 DATA=200". Assuming the second instruction does not receive the required source operand, Entry 1 in the transmit queue can determine, based on the broadcast "SRC0 Index=x2, SRC0 DATA=1000", that the SRC0 Index of the second instruction is the same as the broadcast source address, setting the SRC0 DATA of the second instruction to 1000 and SRC0 Ready=1. Entry 3 in the transmit queue can determine, based on the broadcast "SRC0 Index=x3, SRC0 DATA=200", that the SRC1 Index of the stored fourth instruction is the same as the broadcast source address, setting the SRC1 DATA of the second instruction to 200 and SRC1 Ready=1.

[0231] After the first instruction is issued, the VLD of the first instruction in Entry0 is set to 0, indicating that Entry0 is not currently occupied. The dispatch module can send the stored instruction to the issue queue and simultaneously send the data lookup request corresponding to the instruction to the cache. The issue queue saves the new instruction to Entry0, thereby broadcasting the source operand and source address of instruction L at the same time as issuing instruction L. This allows the remaining instructions in the issue queue to compare the included source address with the broadcast source address to determine the instruction to be written to the broadcast source operand, reducing the number of register accesses and improving data processing efficiency.

[0232] This disclosure describes the processing of entry information in the pipeline. Following the EX stage, there may be an Address Generation Unit (AGU) stage. When the entry information is a memory access instruction, the address generation unit can access memory based on the calculated destination data. For example, the address generation unit uses the destination data as a memory address to access the memory data stored at that address. Following the AGU stage, there may also be a Data Cache (DC) stage. The data cache stage involves the interaction between the processor and the data cache. For example, the processor attempts to read data from or write data to the data cache. The pipeline may also include other stages besides... Figure 5 In addition to the multiple stages shown, this disclosure does not limit the multiple stages of the pipeline, nor does it limit the instruction type to which the entry information belongs.

[0233] Figure 9 This is a schematic diagram of the structure of a data acquisition device provided in an embodiment of this disclosure, as shown below. Figure 9As shown, the data acquisition device 900 includes a buffer 910, a distribution queue 920, and a transmission queue 930; both the distribution queue 920 and the transmission queue 930 are used to store entry information.

[0234] Cache 910 is used to receive data lookup requests sent by distribution queue 920 or transmission queue 930; wherein the data lookup request includes a first source address and a first transmission address, the first source address includes the address of the first source data required by the first entry information, and the first transmission address includes the address of the first entry information in the transmission queue 930; the cache 910 determines the first source data from at least one cache 910 information stored based on the first source address, and updates at least one cache 910 information; wherein the cache 910 information includes source data; and the cache 910 sends target data information to the transmission queue 930 based on the first source data and the first transmission address; wherein the target data information includes the first source data.

[0235] Transmission queue 930 is used to write the first source data into the first entry information.

[0236] In some embodiments, cache 910 information further includes a source address and a valid data identifier; cache 910 is used for:

[0237] Based on the first source address, determine the first cache 910 information that matches the first source address from at least one cache 910 information; wherein, the data validity identifier of the first cache 910 information is used to indicate that the first cache 910 information is in a valid state, and the second source address of the first cache 910 information matches the first source address;

[0238] The source data included in the first cache 910 information is used as the first source data.

[0239] In some embodiments, the cache 910 information further includes a confidence value; cache 910 is used for:

[0240] Increase the first confidence value of the first cached 910 information by A first step length values;

[0241] The second confidence value of the second cache 910 information is reduced by B second step values; wherein, the second cache 910 information is the information other than the first cache 910 information among the multiple cache 910 information;

[0242] Based on a preset period, the confidence value of each cached 910 information is reduced by C third-step values;

[0243] Where A, B, and C are all integers greater than or equal to 1.

[0244] In some embodiments, cache 910 is used for:

[0245] Cache 910 information with a confidence value less than or equal to the first preset threshold is used as third cache 910 information, and the state corresponding to the data validity identifier of the third cache 910 information is determined as invalid state;

[0246] Cache 910 information with a confidence value less than or equal to the first preset threshold is used as third cache 910 information and then deleted.

[0247] In some embodiments, where cache 910 is used to store at least one cache 910 information in a fully associative form, cache 910 is used for:

[0248] The first index identifier is determined based on the first source address; wherein, the first index identifier is related to the first source address;

[0249] The second source address is determined based on the first index identifier;

[0250] Cache 910 uses the cache 910 information where the second source address is located as the first cache 910 information.

[0251] In some embodiments, where cache 910 is used to store at least one cache 910 piece of information in a group-associative manner, the cache 910 information in each group has partially identical index identifiers; cache 910 is used for:

[0252] The second index identifier is determined based on the first source address; wherein the first source address includes a first part address and a second part address, and the second index identifier is related to the first part address;

[0253] Based on the second index identifier, at least one fourth cache 910 information is determined; wherein each fourth cache 910 information corresponds to the second index identifier;

[0254] The third index identifier is determined based on the first source address; wherein, the third index identifier is related to the second part of the address;

[0255] Based on the third index identifier, the first cache 910 information is determined from at least one fourth cache 910 information.

[0256] In some embodiments, cache 910 is used for:

[0257] Obtain the first indicator information; wherein, the first indicator information includes the source address and the source data;

[0258] Determine the confidence value corresponding to the first indicator information and the valid data identifier corresponding to the first indicator information;

[0259] Based on the first indicator information, the confidence value corresponding to the first indicator information, and the data validity identifier corresponding to the first indicator information, the fifth cache 910 information is generated and stored.

[0260] In some embodiments, the data acquisition device 900 further includes a register 940 and an execution module 950; a cache 910 is used for:

[0261] Obtain first indicator information from register 940; wherein register 940 is used to store at least one indicator information;

[0262] Receive the first indicator information broadcast by the execution module 950 or the transmission queue 930;

[0263] Receive the first indicator information sent by the execution module 950.

[0264] In some embodiments, cache 910 is used to store at least one sixth cache 910 information, the sixth cache 910 information including a confidence value; cache 910 is used for:

[0265] In response to the fifth cache 910 information to be written, a storage space value and a second preset threshold are compared; wherein, the storage space value is used to indicate the storage space for storing the fifth cache 910 information;

[0266] If the storage space value is less than the second preset threshold, the limit confidence value is determined based on the confidence value of the sixth cache 910 information;

[0267] Delete the sixth cache information 910 containing the limit confidence value;

[0268] Write information 910 to the fifth cache.

[0269] In some embodiments, where cache 910 is used to store at least one sixth cache 910 information in a group-associative manner, cache 910 is used for:

[0270] The fourth index identifier is determined based on the fifth cache 910 information; wherein, the fourth index identifier is related to the source address where the fifth cache 910 information is stored;

[0271] The storage space value is determined based on the fourth index identifier.

[0272] In some embodiments, Figure 10 This is a schematic diagram of another data acquisition device provided in an embodiment of this disclosure, as shown below. Figure 10 As shown, the data acquisition device 900 also includes a wake-up module 960;

[0273] The distribution queue 920 is used to send the first entry information to the transmission queue 930 and to send the data lookup request corresponding to the first entry information to the cache 910;

[0274] The transmit queue 930 is used to determine the first entry information corresponding to the wake-up information sent by the wake-up module 960; generate a data lookup request based on the first entry information corresponding to the wake-up information, and send the data lookup request to the cache 910; wherein, the wake-up information is used to indicate that the first source data required by the first entry information is stored in the cache 910.

[0275] In some embodiments, the first entry information includes second indicator information, which includes first source data and a first source address;

[0276] Transmit queue 930 is used to broadcast second indicator information via the broadcast bus; and to write first source data into second entry information that matches the first source address.

[0277] The operations performed by each device have been described in the method embodiments, and will not be repeated here.

[0278] Figure 11 This is a schematic diagram of the structure of a processor provided in an embodiment of this disclosure, such as... Figure 11 As shown, the processor 1100 includes a data acquisition device 900.

[0279] In this embodiment of the disclosure, Figure 12 This is a schematic diagram of another processor structure provided in an embodiment of this disclosure, such as... Figure 12 As shown, the processor 1100 includes a DispQ 1201, a forwarding data cache (FDC) 1202, a wake-up module 1203, a issue queue 1204, an AGE MUX 1205, a register 1206, an AGE MUX 1207, and an execution module 1208. Combined with... Figures 5 to 11 The part numbers of some devices have been changed, but the names of the devices have not been changed. The distribution queue includes DispQ 1201, the cache includes FDC 1202, the first arbitration module includes AGE MUX 1207, and the second arbitration module includes AGEMUX 1205.

[0280] In Disp 33, DispQ 1201 sends the third, fourth, or fifth number of fourth entry information to the transmit queue 1204, and simultaneously informs the wake-up module 1203 of the source address of each fourth entry information. The wake-up module 1203 determines whether the register 1206 contains the source operand required for the entry information in the transmit queue 1204. For example, as shown in Table 1 above, after the execution module 1208 executes the third instruction "add x2 x5 x6", it writes the destination data 1000 to x2. The wake-up module 1203 determines to write 1000 at x2 in the register 1206 and wakes up Entry0 in the transmit queue 1204. The AGE MUX 1205 can obtain the first age identifier 012 of the first instruction stored in Entry1, the second age identifier 100 of the second instruction stored in Entry1, and the third age identifier 010 of the fourth instruction stored in Entry3, based on the placeholder identifier of the instruction stored in Entry, the source address, and the source data corresponding to the source address that has not been obtained. Based on the age identifier, the third age identifier 010 is determined to be the oldest age identifier. The AGE MUX 1205 controls the transmit queue 1204 to read the source data stored at x5 in register 1206, thereby obtaining the source data required for Entry3.

[0281] SRC DATA Ready indicates that the source data required by the instruction has been written into the instruction. When the source data required by the first, second, and fourth instructions has been written, the AGE MUX 1207 can obtain the first age identifier 012 of the first instruction stored in Entry 1, the second age identifier 100 of the second instruction stored in Entry 1, and the third age identifier 010 of the fourth instruction stored in Entry 3, based on the placeholder identifier and source address of the instruction stored in Entry 1 and the source data corresponding to that source address. Based on the age identifier, the third age identifier 010 is determined to be the oldest age identifier, and the transmit queue 1204 is controlled to output the fourth instruction stored in Entry 3. The transmit queue 1204 will also broadcast the source data 1000 and source address x2 included in the fourth instruction. Since the broadcast source address x2 is the same as the SRC0 Index=x2 of Entry 0, the transmit queue 1204 sets the SRC0DATA of the first instruction to 1000. Thus, without reading the register, the source data required when SRC0 Index=x2 in the first instruction can be obtained through broadcast, reducing the number of register accesses. The execution module 1208 performs calculations on the fourth instruction and writes the calculated destination operand into register x7.

[0282] The issue queue 1204 can not only obtain source data from register 1206, but also obtain the source data required for the entry information matching the first source address by broadcasting the first source data in the first entry information to be output; it can also obtain the source data required for the entry information matching the first source address by broadcasting when the processor is initially powered on, which can reduce the number of register reads when the processor is initially powered on; it also avoids the number of times source data is moved between the register and the issue queue, reducing unnecessary data movement and reducing power consumption; and since the issue queue is limited by the width of the issue port, the number of first entry information that can be output at one time is small. Broadcasting the first indicator information when the first entry information is waiting to be output or is being output can reduce the number of first indicator information broadcast at the same time, and the number of addresses that need to be compared at the same time is also reduced, which ensures the timing of the processor and improves the performance of the processor; it can also reduce the connection between different issue queues by broadcasting the bus, reducing the complexity of the link relationship.

[0283] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0284] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A data acquisition method, characterized in that, The method is applied to a processor, the processor including a cache, a dispatch queue, and a launch queue; the dispatch queue and the launch queue are both used to store entry information, the cache is used to store at least one cached information, the cached information including source data; the method includes: The cache receives a data lookup request sent by the distribution queue or the launch queue; wherein, the data lookup request includes a first source address and a first launch address, the first source address includes the address of the first source data required by the first entry information, and the first launch address includes the address of the first entry information in the launch queue; The cache determines the first source data from at least one cached information based on the first source address, and updates at least one of the cached information; The cache sends target data information to the transmission queue based on the first source data and the first transmission address; wherein, the target data information includes the first source data; The transmission queue writes the first source data into the first entry information.

2. The method according to claim 1, characterized in that, The cache information also includes a source address and a valid data identifier; the cache determines the first source data from at least one cache information based on the first source address, including: The cache determines, based on the first source address, first cache information that matches the first source address from at least one cache information; wherein, the data validity identifier of the first cache information is used to indicate that the first cache information is in a valid state, and the second source address of the first cache information matches the first source address; The cache uses the source data included in the first cache information as the first source data.

3. The method according to claim 2, characterized in that, The cache information also includes a confidence value; the cache update of at least one of the cache information includes at least one of the following: The cache increments the first confidence value of the first cached information by A first step length values; The cache reduces the second confidence value of the second cache information by B second step values; wherein, the second cache information is information other than the first cache information among the plurality of cache information; The cache is based on a preset period, reducing the confidence value of each cached information by C third-step values; Where A, B, and C are all integers greater than or equal to 1.

4. The method according to claim 3, characterized in that, The method further includes at least one of the following: The cache uses cache information with a confidence value less than or equal to a first preset threshold as third cache information, and determines the state corresponding to the data validity identifier of the third cache information as invalid. The cache will use cache information with a confidence value less than or equal to a first preset threshold as third cache information and delete the third cache information.

5. The method according to any one of claims 2 to 4, characterized in that, The cache is used to store at least one of the cache information in a fully interconnected form; The cache, based on the first source address, determines first cache information that matches the first source address from at least one of the cache information, including: The cache determines a first index identifier based on the first source address; wherein, the first index identifier is related to the first source address; The cache determines the second source address based on the first index identifier; The cache uses the cache information of the second source address as the first cache information.

6. The method according to any one of claims 2 to 4, characterized in that, The cache is used to store at least one cached piece of information in a group-associative manner, wherein the cached information in each group has partially identical index identifiers; The cache determines first cache information that matches the first source address based on the first source address, including: The cache determines the second index identifier based on the first source address; wherein, the first source address includes a first part address and a second part address, and the second index identifier is related to the first part address; The cache determines at least one fourth cache information based on the second index identifier; wherein each of the fourth cache information corresponds to the second index identifier; The cache determines a third index identifier based on the first source address; wherein the third index identifier is related to the second part of the address; The cache determines the first cache information from at least one fourth cache information based on the third index identifier.

7. The method according to any one of claims 1 to 4, characterized in that, The method further includes: The cache obtains first indicator information; wherein, the first indicator information includes source address and source data; The cache determines the confidence value corresponding to the first indicator information and the data validity identifier corresponding to the first indicator information; The cache generates and stores fifth cache information based on the first indicator information, the confidence value corresponding to the first indicator information, and the data validity identifier corresponding to the first indicator information.

8. The method according to claim 7, characterized in that, The processor further includes registers and an execution module, and the method further includes at least one of the following: The cache obtains first indicator information from the register; wherein the register is used to store at least one indicator information; The cache receives first indicator information broadcast by the execution module or the transmission queue; The cache receives the first indicator information sent by the execution module.

9. The method according to claim 7, characterized in that, The cache is used to store at least one sixth cache information, the sixth cache information including a confidence value; the cache stores fifth cache information, including: In response to the fifth cache information to be written, the cache compares a storage space value with a second preset threshold; wherein the storage space value is used to indicate the storage space for storing the fifth cache information. When the storage space value of the cache is less than the second preset threshold, the limit confidence value is determined based on the confidence value of the sixth cache information. The cache deletes the sixth cache information containing the limit confidence value; The cache is written to the fifth cache information.

10. The method according to claim 9, characterized in that, The cache is used to store at least one of the sixth cache information in a group-associative format; the method further includes: The cache determines the fourth index identifier based on the fifth cache information; wherein the fourth index identifier is related to the source address where the fifth cache information is stored; The cache determines its storage space value based on the fourth index identifier.

11. The method according to any one of claims 1 to 4, characterized in that, The processor further includes a wake-up module; the method further includes at least one of the following: The distribution queue sends the first entry information to the launch queue and sends a data lookup request corresponding to the first entry information to the cache. The transmission queue determines the first entry information corresponding to the wake-up information based on the wake-up information sent by the wake-up module; generates a data lookup request based on the first entry information corresponding to the wake-up information, and sends the data lookup request to the cache; wherein, the wake-up information is used to indicate that the first source data required by the first entry information is stored in the cache.

12. The method according to any one of claims 1 to 4, characterized in that, The first entry information includes second indicator information, which includes first source data and a first source address; the method further includes: The transmission queue broadcasts the second indicator information via a broadcast bus; The transmission queue writes the first source data into a second entry that matches the first source address.

13. A data acquisition device, characterized in that, The device includes a buffer, a distribution queue, and a launch queue; both the distribution queue and the launch queue are used to store entry information. The cache is configured to receive data lookup requests sent by the distribution queue or the transmission queue; wherein the data lookup request includes a first source address and a first transmission address, the first source address including the address of the first source data required by the first entry information, and the first transmission address including the address of the first entry information in the transmission queue; determine the first source data from at least one stored cached information based on the first source address, and update at least one cached information; wherein the cached information includes source data; and send target data information to the transmission queue based on the first source data and the first transmission address; wherein the target data information includes the first source data; The transmission queue is used to write the first source data into the first entry information.

14. A processor, characterized in that, Includes the apparatus of claim 13.

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