Integrated circuit memory fault management method and system based on NPU processor architecture

Abstract

The invention belongs to the technical field of integrated circuit design and manufacturing, and particularly relates to an integrated circuit memory fault management method and system based on an NPU processor architecture, firstly, multi-dimensional detection is specially carried out for the memory size, a storage area and handshake protocol effectiveness of a physical address, and the current situation that abnormal signals are passively transmitted in a traditional scheme is changed. According to a fault detection result, a control signal is reversely output to intervene mapping logic, fault diffusion caused by continuous transmission of an abnormal address is effectively avoided, and when the address is detected to be abnormal, a subsequent physical address can be forcibly relocated to a preset security address area, a reliable security support is provided, and the operation stability is improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of integrated circuit design and manufacturing, and particularly relates to an integrated circuit memory fault management method and system based on an NPU processor architecture. BACKGROUND

[0002] With the rapid development of the field of artificial intelligence and deep learning, a neural network processor (NPU) as a special computing core of an artificial intelligence chip needs to process large-scale tensor operations, multi-task concurrent reasoning and other complex scenarios, and therefore puts forward extremely high requirements on the bandwidth, delay and memory capacity of on-chip data transmission. An on-chip network (NoC) has become a core architecture for interconnecting functional modules such as computing core clusters, storage units and interface modules in an NPU, due to the advantages of distributed interconnection, scalable bandwidth and low-delay transmission. An AXI (Advanced eXtensible Interface) bus has become a mainstream interconnection bus protocol between a NoC and functional modules in an NPU, due to the characteristics of a standardized interface and support for burst transmission and out-of-order access.

[0003] In a memory access process of a monolithic NPU NoC architecture, a core link is a virtual address (VA) -> a segment memory management unit (SMMU, Segment Memory Management Unit) -> a physical address (PA) -> a target storage area, a hardware system includes a NoC Core (including an AXI Master master device), an SMMU (including an smmu_core core submodule and an smmu_in_order ordering submodule), a target storage area (such as a DDR, a Local Memory, an on-chip cache and the like) and a corresponding Slave slave device, wherein the SMMU is a core component for implementing VA to PA address conversion. A specific process of traditional memory management is as follows: a Master of the NoC Core initiates a memory access request and outputs a VA, control signals limit_size and base_address for VA to PA mapping are input to the smmu_core, the smmu_core performs address region judgment on the VA and completes VA to PA mapping conversion, the converted PA is processed by a two-way data selector, is sorted by the smmu_in_order according to a receiving order, and is finally transmitted to a Slave slave device of the NoC Cluster to complete data reading and writing.

[0004] However, the traditional NPU memory management method has significant technical defects, which cannot actively detect the size, region and AXI handshake protocol effectiveness of the PA, cannot output fault identification, and can only passively receive and transmit abnormal signals; and lacks a fault active regulation mechanism, so that even if problems such as address size out-of-limit and region mapping error occur, the mapping logic of smmu_core cannot be reversely intervened to adjust limit_size or correct the region identifier of the PA, and only abnormal addresses can be continuously output, without active remedial measures; and since no safety region switching logic is designed under fault scenarios, when the address is abnormal, the subsequent PA cannot be actively directed to a safe address region, and the system lacks safety bottoming-out ability under fault conditions, and the risk resistance is insufficient. SUMMARY

[0005] To solve the problems in the background art, the application provides a memory fault management method and system based on an NPU processor architecture integrated circuit.

[0006] The technical scheme of the application is as follows: The application provides a memory fault management method based on an NPU processor architecture integrated circuit, comprising: S1: After outputting a virtual address according to a memory access request, combining a memory size limit parameter and a base address parameter of address mapping, performing storage region judgment on the virtual address, and completing conversion of the virtual address to a physical address according to a preset mapping rule; according to an enable signal, selecting to output the converted physical address or the original virtual address, and sorting address access operations according to a receiving order; S2: Based on the sorted physical address or the original virtual address and a matching bus signal, performing fault detection, and the operation is as follows: If the fault detection switch signal value is 1, the effectiveness of the bus handshake protocol is detected; If the protocol is effective, the memory size of the sorted physical address and the storage region mapped by the physical address are detected, the fault type is identified, and fault identification data is synchronously output; S3: According to the fault identification data, corresponding regulation signals are generated and reversely transmitted to S1 to adjust the memory size limit parameter of address mapping and replace the storage region identifier of the physical address.

[0007] Based on the memory fault management method based on the NPU processor architecture integrated circuit, the memory size of the sorted physical address and the storage region mapped by the physical address are detected, the fault type is identified, and the fault identification data is synchronously output, and the specific operation is as follows: It is judged whether the memory size of the sorted physical address exceeds the memory size limit parameter, and if it exceeds the limit, an address size out-of-limit fault identification is output; It is judged whether the mapped physical address conforms to the preset region rule, and if it violates the rule, a region access error fault identification is output.

[0008] Further, S3 adjusts the memory size limit parameter of the address mapping, and replaces the storage area identification bit of the physical address, specifically: For address size out-of-limit fault identification, the memory size limit signal is used to adjust the memory size limit parameter value of the address mapping. For region access error fault identification, the storage area identification bit of the physical address is directly replaced with the identifier of the preset safe address region.

[0009] Based on the above-mentioned memory fault management method based on the NPU processor architecture integrated circuit, S2 further includes, after detecting the fault signal, taking the physical address corresponding to the fault signal as a node, and forcibly repositioning all physical addresses after the physical address to the preset safe address region.

[0010] Based on the above-mentioned memory fault management method based on the NPU processor architecture integrated circuit, S2 detects the validity of the bus handshake protocol, and if the effective signal value and the ready signal value corresponding to the protocol are both 1, the protocol is valid.

[0011] Based on the above-mentioned memory fault management method based on the NPU processor architecture integrated circuit, S2 further includes, if the fault detection switch signal value is 0, after the buffered processing of the sorted physical address or the original virtual address and the matching bus signal, transmitting the same to the target storage end.

[0012] Based on the above-mentioned memory fault management method based on the NPU processor architecture integrated circuit, S3 further includes: when no fault signal is detected, stopping the reverse transmission control signal, and restoring the original memory size limit parameter of the address mapping and the storage area determination result.

[0013] The application also provides a memory fault management system based on the NPU processor architecture integrated circuit, which comprises: An address mapping module: after outputting a virtual address according to a memory access request, combining the memory size limit parameter and the base address parameter of the address mapping, determining the storage area of the virtual address, and completing the conversion of the virtual address to the physical address according to a preset mapping rule; according to an enable signal, selecting to output the converted physical address or the original virtual address, and sorting the address access operation according to the receiving order; A fault detection module: based on the sorted physical address or the original virtual address and the matching bus signal, performing fault detection, and the operation is as follows: If the fault detection switch signal value is 1, the validity of the bus handshake protocol is detected. If the protocol is valid, the memory size of the sorted physical address and the storage area mapped by the physical address are detected, the fault type is identified, and the fault identification data is synchronously output. The regulation module generates a corresponding regulation signal according to the fault identification data, and reversely transmits the regulation signal to the address mapping module to adjust the memory size limit parameter of the address mapping and the storage area identification bit of the replaced physical address.

[0014] Based on the above-mentioned memory fault management system based on the NPU processor architecture integrated circuit, the fault detection module detects the sorted physical address memory size, the storage area of the mapped physical address, identifies the fault type, and synchronously outputs the fault identification data, specifically: determining whether the sorted physical address memory size exceeds the memory size limit parameter, and if the limit is exceeded, outputting an address size out-of-limit fault identification; determining whether the mapped physical address conforms to the preset area rule, and if the rule is violated, outputting an area access error fault identification.

[0015] Based on the above-mentioned memory fault management system based on the NPU processor architecture integrated circuit, the fault detection module further includes a security area orientation module, which, after detecting a fault signal, takes the physical address corresponding to the fault signal as a node, and forcibly relocates all physical addresses sorted after the physical address to a preset security address area.

[0016] Advantages The memory fault management method provided by the application first carries out multi-dimensional detection on the memory size, storage area and handshake protocol effectiveness of the physical address, which changes the passive transmission of abnormal signals in the traditional scheme. Then, according to the fault detection result, a control signal is reversely output to intervene the mapping logic, which effectively avoids the fault diffusion caused by continuous transmission of abnormal addresses, and when an address abnormality is detected, the subsequent physical address can be forcibly relocated to a preset security address area, providing reliable security bottom and improving the running stability. DETAILED DESCRIPTION

[0017] The following examples are intended to illustrate the application, but not to further limit the application.

[0018] Example 1 The embodiment provides a memory fault management method based on an NPU processor architecture integrated circuit, including: S1: After outputting a virtual address according to a memory access request, combining a memory size limit parameter and a base address parameter of address mapping, the virtual address is subjected to storage area judgment, and the conversion of the virtual address to a physical address is completed according to a preset mapping rule; according to an enable signal, the converted physical address or the original virtual address is selected and output, and the address access operation is sorted according to the receiving order.

[0019] The control signal of the virtual address to physical address mapping, namely the memory size limit parameter (limit_size) and the base address parameter (base_address), can divide the virtual address into two independent address segments at different positions, realize the isolation of the address space, and in the subsequent operation process, the virtual address greater than limit_size will be remapped by subtracting limit_size from the corresponding size of the address bit, and by adjusting the size of base_address, the entire virtual address segment can be "repositioned" in the physical address space.

[0020] In the conversion stage of the virtual address to the physical address, first, the address region of the virtual address is judged, the storage region to which the virtual address belongs is determined according to the preset region division rule, and then the mapping conversion of the virtual address to the corresponding physical address is completed according to the preset mapping rule. The converted physical address will be processed by two optional data selection, if the enable signal value is 1, the converted physical address will participate in sorting, otherwise the original virtual address will participate in sorting, the access operation is sorted according to the receiving order of the request, and the processed signal output.

[0021] S2: based on the sorted physical address or the original virtual address and the supporting bus signal, fault detection is performed, and the operation is as follows: If the fault detection switch signal value is 1, the validity of the bus handshake protocol is detected. If the protocol is valid, the memory size of the sorted physical address and the storage region of the physical address mapping are detected, the fault type is identified, and the fault identification data is synchronously output.

[0022] In the fault detection stage, first, the fault detection switch signal value is used for judgment, if the fault detection switch signal value is 0, the sorted physical address or the original virtual address and the supporting bus signal are buffered and then transmitted to the target storage end.

[0023] If the fault detection switch signal value is 1, the validity of the bus handshake protocol is detected.

[0024] Further, the validity of the bus handshake protocol is detected, that is, if the effective signal value and the ready signal value corresponding to the protocol are both 1, the protocol is valid.

[0025] Since there are many transaction signals on the AXI (Advanced eXtensible Interface) bus, only when the valid signal and the ready signal are pulled up at the same time, the transmission of address, data and other signals is officially effective. Therefore, the present application realizes the hierarchical design of filtering the valid signal first and then carrying out fault detection, which not only ensures the accuracy of fault detection, but also reduces the invalid operation amount in the fault detection stage, and improves the overall performance of NPU memory address transmission and access.

[0026] If the protocol is valid, the memory size of the sorted physical address is detected, the storage area of the physical address mapping is detected, the fault type is identified, the fault identification data is synchronized and output, and the fault identification data is synchronized with the input signal.

[0027] Specifically: Determine whether the memory size of the sorted physical address exceeds the memory size limit parameter, and output the address size overlimit (size_overlimit) fault identification if it exceeds the limit; Determine whether the mapped physical address meets the preset area rule, and output the region access error (region_access_fault) fault identification if it violates the rule.

[0028] In addition, after detecting the fault signal, the physical address corresponding to the fault signal is taken as a node, and all physical addresses sorted at the physical address are forcibly relocated to a preset safe address area.

[0029] The preset safe address area is an emergency data for storing fault processing; when an address exception is detected, the subsequent physical address is directed to the safe address area, avoiding the abnormal address accessing the calculation core cluster of the neural network processor (NPU), and protecting the hardware safety of the integrated circuit.

[0030] The application designs a safe area orientation mechanism under a fault scenario, which can forcibly relocate the subsequent physical address to the preset safe address area when an address exception is detected, provides reliable safety backup, and improves the running stability.

[0031] In the fault detection stage, the application carries out multi-dimensional detection on the memory size of the physical address, the storage area and the validity of the handshake protocol, can accurately identify address overlimit, region mapping error, protocol handshake failure and other abnormal scenarios, and output clear fault identification, so that the fault detection is accurate and convenient for error discovery and debugging.

[0032] S3: According to the fault identification data, generate corresponding control signal, reverse transmission to S1, adjust the memory size limit parameter of address mapping, replace the storage area identification bit of physical address.

[0033] In the control stage, for the address size overlimit fault identification, the memory size limit signal is used to adjust the memory size limit parameter value of address mapping to control the size of the subsequent physical address.

[0034] For the region access error fault identification, the storage area identification bit of the physical address is directly replaced with the identifier of the preset safe address area, so as to realize the backup rescue after the fault.

[0035] Further comprising: when no fault signal is detected, stopping the reverse transmission of the control signal, and restoring the original memory size limit parameter of the address mapping and the storage area determination result.

[0036] In the control stage, according to the fault detection result, the reverse output control signal intervenes the mapping logic, the memory size limit parameter value is adjusted to control the subsequent physical address size, and the replacement area identification bit is switched to the safe area, so that the fault diffusion caused by the continuous transmission of the abnormal address is effectively avoided.

[0037] Embodiment 2 Based on embodiment 1, the present embodiment provides a memory fault management system based on NPU processor architecture integrated circuit, which is adapted to the whole type network on chip (NoC, Network on Chip) architecture and AXI (Advanced eXtensible Interface) bus protocol, comprising: The address mapping module: after outputting the virtual address according to the memory access request, combining the memory size limit parameter and the base address parameter of the address mapping, the storage area of the virtual address is determined, and the conversion from the virtual address to the physical address is completed according to the preset mapping rule; according to the enable signal, the converted physical address or the original virtual address is selected and output, and the address access operation is sorted according to the receiving order.

[0038] Specifically, in the running process of the address mapping module, the master device in the NoC core module initiates the memory access request and outputs the virtual address, the control signal for mapping the virtual address to the physical address, i.e. the memory size limit parameter (limit_size) and the base address parameter (base_address) of each address segment, is input to the segment memory management unit core module, the segment memory management unit core module first judges the address region of the virtual address, determines the storage region to which the virtual address belongs according to the preset region division rule, and then completes the mapping conversion from the virtual address to the corresponding physical address according to the preset mapping rule. The converted physical address will pass through the two-way data selector, if the corresponding segment memory management unit core module enable signal value is 1, then the converted physical address will be sent to the segment memory management unit sorting module, otherwise the original virtual address will enter the segment memory management unit sorting module, the segment memory management unit sorting module sorts the access operation according to the receiving order of the request, and the processed signal is output from the segment memory management unit.

[0039] The fault detection module: based on the sorted physical address or the original virtual address and the matching bus signal, the fault detection is carried out, and the operation is as follows: If the fault detection switch signal value is 1, the validity of the bus handshake protocol is detected; If the protocol is valid, the memory size of the sorted physical address, the storage area of the physical address mapping are detected, the fault type is identified, and the fault identification data is output synchronously.

[0040] In the specific implementation process, the fault detection module is configured with a fault detection switch, which realizes two working modes in cooperation with the selector in the module. If the fault detection switch signal value is 0, the sorted physical address or the original virtual address and the matching bus signal directly pass through the fault detection module, enter the first-in first-out (FIFO) module buffer to avoid timing errors, and finally transmit to the target storage end.

[0041] If the fault detection switch signal value is 1, the AXI bus handshake protocol validity is detected first. On the premise that the protocol is valid, the memory size of the input physical address and the storage area information are further detected - if the memory size of the physical address exceeds the memory size limit parameter, the address size overlimit (size_overlimit) fault identification is output; if the mapped physical address is in the wrong area, the region access error (region_access_fault) fault identification is output, and the two types of fault identification will be transmitted synchronously with the input signal.

[0042] The fault detection module also includes a safe area orientation module, which, after detecting a fault signal, uses the physical address corresponding to the fault signal as a node, and all physical addresses sorted after the physical address are forcibly relocated to a preset safe address area.

[0043] The preset safe address area is a static random access memory (SRAM) on the chip in the NPU integrated circuit, which is specially used to store emergency data for fault handling; when an address exception is detected, the fault detection module directs the physical address to the SRAM area through a hardware circuit, avoiding the access of abnormal addresses to the computing core cluster of the NPU, and protecting the hardware safety of the integrated circuit.

[0044] The control module: according to the fault identification data, the corresponding control signal is generated, and is transmitted reversely to the address mapping module to adjust the memory size limit parameter of the address mapping and replace the storage area identification bit of the physical address.

[0045] The output signal of the fault detection module enters the control module, and the control module generates a corresponding control signal according to the fault identification data, which is reversely transmitted to the fragment memory management unit core module through a special two-way selector: Wherein size_overlimit will regulate the limit_size signal of the segment memory management unit core module, dynamically adjust the value to control the size of the subsequent physical address; region_access_fault will replace the region identification bit of the physical address in the segment memory management unit core module with the identifier of the preset safe address region, so as to realize the bottom salvage after the fault.

[0046] The memory fault management system provided by the application is composed of a fault detection logic circuit, a safe region switching circuit, a FIFO module and a control signal driving circuit; wherein the fault detection logic circuit realizes AXI protocol validity detection by using a combination logic circuit, the safe region switching circuit generates the regulation signal of the segment memory management unit core module by using a sequential logic circuit, cooperates with the FIFO module to avoid timing errors, realizes fault management while ensuring low latency of address transmission, and can be directly integrated in the on-chip storage control region of the NPU chip.

[0047] The above is only the preferred embodiment of the application, but the protection scope of the application is not limited to this, any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the application, which should be covered within the protection scope of the application.

Claims

1. A memory fault management method based on an NPU processor architecture integrated circuit, characterized in that, include: S1: After outputting the virtual address according to the memory access request, the storage area of ​​the virtual address is determined by combining the memory size limit parameter and base address parameter of the address mapping, and the conversion from virtual address to physical address is completed according to the preset mapping rule; the converted physical address or the original virtual address is selected to be output according to the enable signal, and the address access operation is sorted according to the receiving order. S2: Based on the sorted physical address or original virtual address and the corresponding bus signals, perform fault detection as follows: If the fault detection switch signal value is 1, then the validity of the bus handshake protocol is checked. If the protocol is valid, the sorted physical address memory size and the storage area mapped by the physical address are detected, the fault type is identified, and fault identification data is output synchronously. S3: Generate corresponding control signals based on fault identification data, transmit them in reverse to S1, adjust the memory size limit parameters of address mapping, and replace the storage area identifier bits of physical addresses.

2. The method for memory fault management based on NPU processor architecture integrated circuits according to claim 1, characterized in that, S2 describes the detection and sorting of physical address memory size and physical address mapped storage area, identifying fault types, and synchronously outputting fault identification data, specifically as follows: Determine whether the size of the sorted physical addresses exceeds the memory size limit parameter. If it does, output an address size exceedance fault flag. Determine whether the mapped physical address conforms to the preset zone rules. If it does not conform, output a zone access error fault flag.

3. The method for memory fault management based on NPU processor architecture integrated circuits according to claim 2, characterized in that, S3 describes adjusting the memory size limit parameters of the address mapping and replacing the storage area identifier bits of the physical address, specifically as follows: In response to the address size exceeding fault flag, the memory size limit parameter value of the address mapping is adjusted through the memory size limit signal; For the fault flag indicating an area access error, the storage area flag of the physical address is directly replaced with the identifier of the preset secure address area.

4. The method for memory fault management based on NPU processor architecture integrated circuits according to claim 1, characterized in that, S2 also includes, after detecting a fault signal, using the physical address corresponding to the fault signal as a node, forcibly relocating all physical addresses after the sorting of the physical addresses to a preset safe address area.

5. The method for memory fault management based on NPU processor architecture integrated circuits according to claim 1, characterized in that, The validity of the bus handshake protocol described in S2 is determined by the fact that if both the valid signal value and the ready signal value corresponding to the protocol are 1, then the protocol is valid.

6. The method for memory fault management based on NPU processor architecture integrated circuits according to claim 1, characterized in that, S2 also includes that if the fault detection switch signal value is 0, the sorted physical address or original virtual address and the associated bus signal are buffered and then transmitted to the target storage end.

7. The method for memory fault management based on NPU processor architecture integrated circuits according to claim 1, characterized in that, S3 also includes: when no fault signal is detected, stopping the reverse transmission of control signals and restoring the original memory size limit parameters and storage area determination results of the address mapping.

8. A memory fault management system based on an NPU processor architecture integrated circuit, characterized in that, include: Address mapping module: After outputting the virtual address according to the memory access request, it determines the storage area of ​​the virtual address by combining the memory size limit parameter and the base address parameter of the address mapping, and completes the conversion from virtual address to physical address according to the preset mapping rules; it selects to output the converted physical address or the original virtual address according to the enable signal, and sorts the address access operations according to the receiving order; Fault detection module: Based on the sorted physical address or original virtual address and the corresponding bus signals, fault detection is performed as follows: If the fault detection switch signal value is 1, then the validity of the bus handshake protocol is checked. If the protocol is valid, the sorted physical address memory size and the storage area mapped by the physical address are detected, the fault type is identified, and fault identification data is output synchronously. Control module: Generates corresponding control signals based on fault identification data, transmits them in reverse to the address mapping module, adjusts the memory size limit parameters of the address mapping, and replaces the storage area identifier bits of the physical address.

9. The NPU processor architecture-based integrated circuit memory fault management system according to claim 8, characterized in that, The fault detection module detects the sorted physical address memory size, the storage area mapped to the physical address, identifies the fault type, and synchronously outputs fault identification data, specifically as follows: Determine whether the size of the sorted physical addresses exceeds the memory size limit parameter. If it does, output an address size exceedance fault flag. Determine whether the mapped physical address conforms to the preset zone rules. If it does not conform, output a zone access error fault flag.

10. The NPU processor architecture-based integrated circuit memory fault management system according to claim 8, characterized in that, The fault detection module also includes a safe area orientation module, which, after detecting a fault signal, uses the physical address corresponding to the fault signal as a node and forces all physical addresses after the sorted physical address to be relocated to a preset safe address area.