Real arbitrary point waveform data processing method based on FPGA
By using an FPGA-based approach, waveform data is segmented using the burst read/write length M of the memory, and a flag bit is added to the cache unit. This solves the waveform distortion problem in arbitrary waveform output and achieves seamless connection and distortion-free restoration.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-12
- Publication Date
- 2026-03-27
AI Technical Summary
Existing arbitrary waveform generators tend to introduce noise and waveform distortion when outputting waveforms of unaligned lengths, making it difficult to achieve truly arbitrary point output.
By using an FPGA-based approach, the waveform data is segmented using the burst read/write length M of the memory, and a flag bit is added to the cache unit to ensure seamless data splicing and achieve true arbitrary point output.
It achieves seamless connection and distortion-free restoration of waveform data, eliminating waveform distortion caused by zero padding or truncation in traditional methods, and meeting users' requirements for arbitrary waveform length.
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Figure CN121743232A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of waveform measurement, in particular to a real arbitrary point number waveform data processing method based on FPGA. BACKGROUND
[0002] An arbitrary waveform generator is a key test equipment in electronic technology research and development. The existing products mainly adopt direct digital frequency synthesis (DDS) or traditional point-by-point output technology. Although the DDS technology is widely used, its essence is based on phase sampling interpolation or extraction, and the output is not the original real data in the memory, which is easy to cause detail loss and waveform distortion.
[0003] In contrast, the traditional point-by-point output technology can restore data in sequence, but is limited by the hardware storage mechanism (such as the burst read-write characteristics of DDR). The existing equipment usually requires that the total number of waveforms must be a specific fixed value or an integer multiple. When the user needs to output a waveform of a specific non-aligned length, data padding or truncation is often forced, which not only changes the frequency characteristics of the waveform, but also introduces discontinuous noise. Therefore, how to break through the hardware limitation to realize real arbitrary point number output without distortion is a technical problem to be solved at present.
[0004] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those skilled in the art.
[0005] CONTENT In view of at least one of the above technical problems, the present application provides a real arbitrary point number waveform data processing method based on FPGA to realize waveform data output of different point numbers without distortion, and to restore real waveform data.
[0006] The present application provides a real arbitrary point number waveform data processing method based on FPGA, the method comprising: S1, obtaining the total number N of waveform data, grouping the waveform data by M points to generate a plurality of segmented data, and calculating the remainder R of the last group of segmented data, wherein M is the burst read-write length of the memory, and R is the remainder of N divided by M; S2, for the segmented data of the last group of less than M points, filling and completing the first segmented data of the waveform data to make it meet the length of M points, and then writing the segmented data into the memory; S3, sequentially reading the segmented data from the memory and writing it into the first level cache unit, and adding an identification bit for each group of segmented data during the writing process; S4, reading the segmented data from the first level cache unit for processing: when detecting that the identification bit is in the unmarked state, removing the identification bit, and writing the set of segmented data into the second level cache unit; when detecting that the identification bit is in the marked state, removing the identification bit, retaining R valid points in the set of segmented data, and obtaining M-R points of the first set of segmented data of the waveform data of the next cycle, splicing the R valid points and the M-R points into a set of complete segmented data with M points, and writing into the second level cache unit; S5, reading the segmented data from the second level cache unit according to a preset sampling rate and outputting.
[0007] The method solves the contradiction between the fixed burst length limitation of the memory and the arbitrary waveform length requirement of the user, ensures that the tail data and the head data can be seamlessly connected when the waveform is played in a cycle, eliminates the flat waveform caused by zero padding or the phase mutation caused by truncation in the traditional method, and realizes real lossless restoration.
[0008] In some possible implementation manners, the filling and completion using the first set of segmented data of the waveform data in step S2 includes: The M-R points of the first set of segmented data of the waveform data are sequentially filled into positions of R+1 points to the Mth point of the last set of data.
[0009] In some possible implementation manners, an identification bit is added to each set of segmented data in the writing process in step S3, including: The bit width of the first level cache unit is configured as W+1 bits, and W is the total bit width of the M-point segmented data; The identification bit is attached to each set of segmented data; Among them, for the last set of segmented data, the identification bit is in the first logic level, and for other sets of segmented data, the identification bit is in the second logic level.
[0010] In some possible implementation manners, the R valid points and the M-R points are spliced into a set of complete segmented data with M points, including: After detecting that the identification bit is in the first logic level, M-R points of the completed waveform data are removed according to the remainder R; The first set of data of the next cycle waveform data is read, and the first M-R points of the first set of segmented data of the next cycle waveform data are intercepted; The retained R valid points and the first M-R points of the first set of segmented data of the next cycle waveform data are spliced to form new segmented data and written into the second level cache unit.
[0011] In some possible implementation manners, the memory is DDR3, and the burst read / write length M is 8.
[0012] In some possible implementation manners, the bit width of the points of the segmented data is 16 bits, the total bit width of M points of each group of the segmented data is 128 bits, and the bit width of the first-level cache unit is configured as 129 bits, where the 129th bit is an identification bit.
[0013] In some possible implementation manners, the first-level cache unit and the second-level cache unit are both FIFO memories.
[0014] In some possible implementation manners, when the first-level cache unit is not full, the segmented data is continuously read from the memory and written into the first-level cache unit; and when the first-level cache unit is not empty and the second-level cache unit is not full, the segmented data is continuously read from the first-level cache unit and written into the second-level cache unit.
[0015] In some possible implementation manners, the number N of points of the waveform data satisfies: 8≤N≤64 million points.
[0016] In some possible implementation manners, after step S5, the method further includes: The segmented data output from the second-level cache unit is sent to a digital-to-analog converter, and the digital-to-analog converter converts the segmented data into an analog voltage signal and outputs the analog voltage signal, where the readout clock of the second-level cache unit is synchronized with the sampling clock of the digital-to-analog converter.
[0017] The application will be further described below in conjunction with the accompanying drawings and embodiments. BRIEF DESCRIPTION OF DRAWINGS
[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the embodiments or the prior art will be briefly introduced as follows. Obviously, the accompanying drawings in the following description only represent some embodiments of the present application, and other accompanying drawings can be obtained by those skilled in the art without any creative effort on the basis of these accompanying drawings.
[0019] Figure 1 FIG. 1 is a structural schematic diagram of a waveform data processing apparatus provided by an embodiment of the present application; Figure 2 FIG. 2 is a flowchart of a real arbitrary point number waveform data processing method provided by an embodiment of the present application; DETAILED DESCRIPTION
[0020] In order to make the above objectives, characteristics and advantages of the present application more apparent and comprehensible, the specific embodiments of the present application will be described in detail below in conjunction with the accompanying drawings. In the following description, a large number of specific details are set forth in order to fully understand the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without departing from the connotations of the present application, so the present application is not limited by the specific embodiments disclosed below.
[0021] As Figure 1 shown, the embodiment provides a waveform data processing device, the device comprising a host computer 100, an FPGA and a memory 200, the host computer 100 being connected with the FPGA through a communication interface, the FPGA being connected with the memory 200 through a control bus, the FPGA being internally constructed with a processing logic module 320, a first-level cache unit 310 and a second-level cache unit 330, an input end of the first-level cache unit 310 being connected with the memory 200, an output end of the first-level cache unit 310 being connected with the processing logic module 320, an input end of the second-level cache unit 330 being connected with an output end of the processing logic module 320.
[0022] In some embodiments, the memory 200 is a DDR3 SDRAM, the burst mechanism of the DDR3 being 8 points, that is, 1 write read of the data of the DDR3 must be 8 points. The data processed by the DDR3 each time is 128 bits, that is, the bit width of each point of the data is 16 bits.
[0023] In some embodiments, the first-level cache unit 310 and the second-level cache unit 330 are both FIFO memories 200.
[0024] In some embodiments, the bit width of the first-level cache unit 310 is configured as 129 bits, wherein the 129th bit is an identification bit.
[0025] In some embodiments, the bit width of the second-level cache unit 330 is configured as 128 bits.
[0026] In some embodiments, when the first-level cache unit 310 is not full, the segmented data is continuously read from the memory 200 and written into the first-level cache unit 310. It can be understood that the FPGA monitors the writable flag of the first-level cache unit 310. As long as the first-level cache unit 310 is not full, the memory 200 continuously initiates a burst read request to fill the data.
[0027] In some embodiments, when the first-level cache unit 310 is not empty and the second-level cache unit 330 is not full, the segmented data is continuously read from the first-level cache unit 310 and written into the second-level cache unit 330. It can be understood that the FPGA monitors the writable flag of the second-level cache unit 330. As long as the second-level cache unit 330 is not full and the data of the first-level cache unit 310 is not empty, the second-level cache unit 330 reads the data from the first-level cache unit 310.
[0028] The first level cache unit 310 can absorb the discontinuity of the memory 200 reading in cooperation with the second level cache unit 330, and the second level cache unit 330 provides a stable data source for the subsequent DAC, and as long as the first level cache unit 310 is not empty and the second level cache unit 330 is not full, the output waveform is guaranteed not to be interrupted due to the instantaneous jitter of the memory 200.
[0029] As shown in Figure 2 The embodiment provides a real arbitrary point number waveform data processing method based on FPGA, and the method comprises the following steps: S1, obtaining the total point number N of the waveform data, grouping the waveform data by M points to generate a plurality of segmented data, and calculating the remainder R of the last group of segmented data, wherein M is the burst read-write length of the memory 200, and R is the remainder of N divided by M.
[0030] In step S1, the point number N of the waveform data satisfies: 8≤N≤64 million points, that is, the length N of the waveform data can be any integer in the range of 8pts to 64Mpts.
[0031] M is the burst read-write length of the memory 200, and it can be understood that the burst read-write length M is the burst mechanism of the memory 200. In the embodiment, M is 8.
[0032] In addition, the bit width of the segmented data is 16 bits. In the embodiment, the waveform data is grouped by M points, that is, the waveform data is grouped by 8 points, so the total bit width of each group of segmented data is 128 bits.
[0033] For example, the host computer 100 first parses the user waveform file to obtain the total point number N. And the burst read-write length M of the memory 200, calculate the remainder R. For example, if N=100, M=8, then R=4.
[0034] S2, for the last group of segmented data less than M points, fill the first segmented data of the waveform data to complete it to meet the length of M points, and then write the segmented data into the memory 200.
[0035] In step S2, when the last group of segmented data is less than M points, the host computer 100 fills the first segmented data of the waveform data to complete it to meet the length of M points, and then writes the segmented data into the memory 200.
[0036] Specifically, the first M-R points of the first group of segmented data of the waveform data are sequentially filled into the R+1 points to the Mth point of the last group of data.
[0037] For example, when the last group of segmented data only has 4 valid points, the host 100 will fill the first 4 points of the first group of segmented data of the waveform data to the second half of the last group of segmented data, and write the 8 points into the memory 200.
[0038] S3, sequentially reading the segmented data from the memory 200 and writing into the first-level cache unit 310, and adding an identification bit for each group of segmented data during the writing process; In step S3, when the segmented data is written from the memory 200 to the first-level cache unit 310, the FPGA adds an identification bit for each group of segmented data.
[0039] Specifically, the bit width of the first-level cache unit 310 is configured as W+1 bits, W being the total bit width of the M-point segmented data; the identification bit is attached to each group of segmented data; wherein for the last group of segmented data, the identification bit is located at the first logic level, and for other groups of segmented data, the identification bit is located at the second logic level.
[0040] As known from the foregoing, the bit width of the first-level cache unit 310 is 129 bits, wherein the bit width of the identification bit is 1 bit.
[0041] It can be understood that for the last group of segmented data, the identification bit is located at the first logic level, which is set to 1. For other groups of segmented data, the identification bit is located at the second logic level, which is set to 0. In this way, by expanding the 1-bit width and binding the identification bit in the segmented data, it is ensured that the processing logic module 320 can accurately identify which group of data needs special processing (i.e. splicing) with zero delay after the segmented data passes through the first-level cache unit 310.
[0042] S4, reading the segmented data from the first-level cache unit 310 for processing: when detecting that the identification bit is in the unmarked state, removing the identification bit and writing the group of segmented data into the second-level cache unit 330; when detecting that the identification bit is in the marked state, removing the identification bit, retaining R valid points in the group of segmented data, and obtaining the first M-R points of the first group of segmented data of the waveform data of the next cycle, splicing the R valid points and the M-R points into a group of complete M-point segmented data, and writing into the second-level cache unit 330; In step S4, the processing logic module 320 reads the segmented data from the first-level cache unit 310. When the identification bit of the segmented data is read as 0, the identification bit is removed, and then the segmented data after removing the identification bit is output to the second-level cache unit 330.
[0043] After detecting that the identification bit is 1, that is, the group of segmented data is the last group, the identification bit is removed, according to the remainder R, M-R points in the group of waveform data are removed; the first group of data of the next cycle waveform data is read, the first M-R points of the first group of segmented data of the next cycle waveform data are intercepted; the remaining R valid points are spliced with the first M-R points of the first group of segmented data of the next cycle waveform data to form new segmented data which is written into the second-level cache unit 330.
[0044] For example, when reading the identification bit of the segmented data is 1, that is, the group of segmented data is the last group, the processing logic module 320 identifies that the group has only the first 4 points valid. At this time, the identification bit is removed, and the first 4 points are retained, and the first group of segmented data of the next cycle waveform data is also obtained, and the first 4 points are intercepted. The processing logic module 320 splices the 4 valid points and the first 4 points of the first group of segmented data of the next cycle waveform data to form a group of complete segmented data with 8 points, which is written into the second-level cache unit 330.
[0045] S5, reading the segmented data from the second-level cache unit 330 according to a preset sampling rate and outputting.
[0046] The method solves the contradiction between the fixed burst length limitation of the memory 200 and the arbitrary waveform length requirement of the user, ensures that the tail data and the head data can be seamlessly connected when the waveform is played in a cycle, eliminates the flat waveform caused by zero padding or the phase mutation caused by truncation in the traditional method, and realizes real lossless restoration.
[0047] In some embodiments, after step S5, the method further includes: The segmented data output from the second-level cache unit 330 is sent to a digital-to-analog converter, and the digital-to-analog converter converts the segmented data into an analog voltage signal and outputs, wherein a read clock of the second-level cache unit 330 is synchronized with a sampling clock of the digital-to-analog converter.
[0048] In the description of the embodiments of the present application, unless otherwise specified, " / " represents the meaning of or, for example, A / B can represent A or B; "and / or" herein only describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can represent: A alone, A and B exist together, and B alone. In addition, in the description of the embodiments of the present application, "multiple" means two or more than two.
[0049] In the description of the specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" and the like means that the specific feature, structure, material or characteristic being described is included in at least one embodiment or example of the application. The illustrative descriptions of such terms does not mean that all embodiments or examples have to necessarily include, but can optionally include, the described specific feature, structure, material or characteristic. Moreover, the description of a specific feature, structure, material or characteristic in the specification does not mean that the described specific feature, structure, material or characteristic is essential or even an important feature, structure, material or characteristic of the application. In the description of the specification, the illustrative expressions "coupled" or "connected" or "linked" or the like are used to indicate either a direct connection between entities that are in physical or logical contact with each other, or an indirect connection or association through another intermediate medium that allows the entities to perform the same or similar functions as the directly connected entities. The illustrative expressions "coupled" or "connected" or "linked" or the like are not intended to exclude the presence of intermediate devices or material between the coupled or connected entities.
[0050] Furthermore, the terms "first", "second", "third", "fourth", "fifth", "sixth", "seventh", "eight", "ninth", "tenth", and the like, where used in the description, are used only to describe the different instances of the features, structures, materials or characteristics, and do not imply a relative importance or a specific order of the features, structures, materials or characteristics being described. Thus, a feature, structure, material or characteristic defined with "first", "second", "third", "fourth", "fifth", "sixth", "seventh", "eight", "ninth", "tenth", and the like, can include at least one of the feature, structure, material or characteristic, either explicitly or implicitly.
[0051] In the description of the specification, "coupled" or "connected" or "linked" or the like means either a direct connection between entities that are in physical or logical contact with each other, or an indirect connection or association through another intermediate medium that allows the entities to perform the same or similar functions as the directly connected entities. The illustrative expressions "coupled" or "connected" or "linked" or the like do not exclude the presence of intermediate devices or material between the coupled or connected entities.
[0052] In the detailed description of the specification, reference is made to the accompanying drawings that form a part thereof, in which like numerals refer to like components throughout the specification. The drawings are for purposes of illustrating the exemplary embodiments and are not necessarily drawn to scale with one another. It is to be understood that other embodiments can be utilized and structural or logical changes can be made without departing from the scope of the present application. Therefore, the following detailed description is not to be taken in a limiting sense as the scope of the application is defined by the appended claims and equivalents thereof.
[0053] Various operations can be described as multiple discrete actions or operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations can not be performed in the order of presentation. Operations described can be performed in a different order than the described embodiment. Various additional operations can be performed and / or described operations can be omitted in additional embodiments.
[0054] The above merely describes the preferred embodiments of the present application, and is not intended to limit the present application in any form. Any person skilled in the art, without departing from the technical scheme of the present application, can make many possible changes and modifications to the technical scheme of the present application, or modify equivalent embodiments with equivalent changes. Therefore, any equivalent changes made according to the shape, structure and principle of the present application, without departing from the technical scheme of the present application, shall be covered within the protection scope of the present application.
Claims
1. A method for processing real arbitrary-point waveform data based on FPGA, characterized in that, The method includes: S1. Obtain the total number of waveform data points N, divide the waveform data into multiple segments by M points, and calculate the remainder R of the last group of segmented data, where M is the burst read / write length of the memory and R is the remainder of N divided by M. S2. For the last group of segmented data with less than M points, fill in the first segment of the waveform data to make it meet the length of M points, and then write the segmented data into the memory. S3. Read segmented data sequentially from the memory and write it into the first-level cache unit. During the writing process, add an identifier bit to each segmented data. S4. Read the segmented data from the first-level cache unit and process it: When the flag bit is detected to be in a non-marked state, remove the flag bit and write the segmented data of that group into the second-level cache unit; When the flag bit is detected to be in a marked state, remove the flag bit, retain R valid points in the segmented data of that group, and obtain the first MR points of the first group of segmented data of the next cycle waveform data. Concatenate the R valid points with the MR points to form a complete segmented data with M points and write it into the second-level cache unit. S5. Read segmented data from the second-level buffer unit according to the preset sampling rate and output it.
2. The method for processing real arbitrary-point waveform data based on FPGA according to claim 1, characterized in that, Step S2, which involves filling in and completing the waveform data using the first segment of the waveform data, includes: The first MR points of the first group of waveform data segments are sequentially filled into the positions from the R+1 points to the Mth point of the last group of data.
3. The method for processing real arbitrary-point waveform data based on FPGA according to claim 1, characterized in that, In step S3, an identifier bit is added to each group of segmented data during the writing process, including: The bit width of the first-level cache unit is configured as W+1 bits, where W is the total bit width of the M point segmented data; The identifier bit is appended to each group of segmented data; Specifically, for the last group of segmented data, the identifier is set to the first logic level, and for the other groups of segmented data, the identifier is set to the second logic level.
4. The method for processing real arbitrary-point waveform data based on FPGA according to claim 3, characterized in that, The step of concatenating the R valid points with the MR points to form a complete set of segmented data with M points includes: After detecting that the flag bit is at the first logic level, remove the MR points that were padded in the waveform data according to the remainder R; Read the first set of data from the next cycle of waveform data, and extract the first MR points of the first segment of the next cycle of waveform data; The R valid points that are retained are concatenated with the first MR points of the first group of segmented data of the waveform data of the next cycle, and the new segmented data is written into the second-level buffer unit.
5. The method for processing real arbitrary-point waveform data based on FPGA according to claim 1, characterized in that, The memory is DDR3, and the burst read / write length M is 8.
6. The method for processing real arbitrary-point waveform data based on FPGA according to claim 5, characterized in that, The bit width of each segmented data point is 16 bits, the total bit width of each set of M segments is 128 bits, and the bit width of the first-level cache unit is configured to be 129 bits, wherein the 129th bit is the identifier bit.
7. The method for processing real arbitrary-point waveform data based on FPGA according to claim 1, characterized in that, Both the first-level cache unit and the second-level cache unit are FIFO memories.
8. The method for processing real arbitrary-point waveform data based on FPGA according to claim 7, characterized in that, When the first-level cache unit is not full, segmented data is continuously read from the memory and written to the first-level cache unit; when the first-level cache unit is not empty and the second-level cache unit is not full, segmented data is continuously read from the first-level cache unit and written to the second-level cache unit.
9. The method for processing real arbitrary-point waveform data based on FPGA according to claim 1, characterized in that, The number of points N in the waveform data satisfies: 8 ≤ N ≤ 64 megabits.
10. The method for processing real arbitrary-point waveform data based on FPGA according to claim 1, characterized in that, After step S5, the method further includes: The segmented data output from the second-level buffer unit is sent to the digital-to-analog converter (DAC), which converts the segmented data into an analog voltage signal output. The readout clock of the second-level buffer unit is synchronized with the sampling clock of the DAC.