Data processing method and device

Abstract

The invention provides a data processing method and device, and the method comprises the steps that a computing device reads a first task into a memory, the first task comprises a first matrix, the first matrix is a sparse matrix, and the first matrix is in an initial storage format in the memory; then, the computing device splits the first matrix into a plurality of sub-matrixes, and determines target storage formats corresponding to the plurality of sub-matrixes; the target storage format is determined according to the element distribution structure of the sub-matrix; finally, the computing device processes the first task according to the multiple sub-matrixes and the target storage formats corresponding to the multiple sub-matrixes, and a processing result corresponding to the first task is obtained. According to the method, the memory space occupied by the sub-matrix in the target storage format is small, so that when the sub-matrix is read into the cache, the cache hit rate of the sub-matrix in the cache is improved, and the processing efficiency of the first task is improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a data processing method and apparatus. Background Technology

[0002] In simulating complex fluid flows, chemical reactions, turbulent flows, heat transfer analysis, structural dynamics analysis, and electromagnetic field analysis, numerical simulations are generally required to address specific problems within the scenario. A key technique in numerical simulation is solving sparse linear equations. Specifically, a sparse linear equation system is like Ax = b, where A is a sparse matrix, and x and b are vectors. Solving this sparse linear equation system involves finding the unknown vector x based on the known sparse matrix A and vector b. Currently, when using iterative methods to solve sparse linear equation systems, the entire sparse matrix A and vector b can be loaded into memory first. Then, a portion of the sparse matrix A and a portion of the vector b can be loaded into a cache. Multiple iterations are then performed based on the cached sparse matrix A and vector b to finally solve for the unknown vector x.

[0003] In the process of solving sparse linear equations, how to improve the cache hit rate of sparse matrix A in the cache in order to improve the solution efficiency of sparse linear equations is a technical problem that urgently needs to be solved. Summary of the Invention

[0004] This application provides a data processing method and apparatus for improving the cache hit rate of sparse matrices in the cache during the process of solving sparse linear equations.

[0005] Firstly, this application provides a data processing method. The execution subject of this method is a computing device, a module within a computing device, or a chip within a computing device. Here, the computing device is used as the execution subject for example. The method includes: the computing device first reads a first task into memory. The first task includes a first matrix, which is a sparse matrix, and the first matrix is ​​stored in memory in an initial format. Then, the computing device splits the first matrix into multiple sub-matrices and determines the target storage format corresponding to each of the multiple sub-matrices. The target storage format is determined based on the element distribution structure of the sub-matrices. Finally, the computing device processes the first task according to the multiple sub-matrices and their respective target storage formats to obtain the processing result corresponding to the first task.

[0006] In the above method, the computing device does not directly process the first task using the first matrix in its original storage format. Instead, it splits the first matrix into multiple sub-matrices and determines the target storage format for each sub-matrix based on its element distribution structure. Since the target storage format for each sub-matrix is ​​the optimal storage format determined by fully considering its element distribution structure, using the target storage format helps save memory costs associated with the sub-matrixes. When the computing device processes the first task using sub-matrices in the target storage format, the smaller memory space occupied by these sub-matrices improves the cache hit rate when reading them into the cache, thereby increasing the processing efficiency of the first task.

[0007] In one possible design, the computing device splits the first matrix into multiple sub-matrices, including: the computing device determining the number P of processes handling the first task; P being an integer greater than 0; the computing device performing row partitioning on the first matrix according to the number of processes P, obtaining P reference matrices; and the computing device performing row partitioning and / or column partitioning on the P reference matrices respectively, obtaining multiple sub-matrices. In this design, after obtaining the first matrix, the computing device first performs row partitioning on the first matrix according to the number of processes P, obtaining P reference matrices, and then performs row partitioning and / or column partitioning on the P reference matrices respectively, obtaining multiple sub-matrices. This partitioning method can ensure that the number of sub-matrices corresponding to each process is relatively balanced, which facilitates subsequent processing of the first task by each process according to its corresponding sub-matrices, thus improving the processing efficiency of the first task.

[0008] In one possible design, multiple submatrices include a first submatrice; the computing device determines the target storage format corresponding to each of the multiple submatrices, including: the computing device determining the target storage format corresponding to the first submatrice based on the number of non-zero elements in the first submatrice. In this design, the computing device determines the target storage format corresponding to the submatrice based on the number of non-zero elements in the first submatrice. Submatrices using the target storage format occupy less memory space; therefore, when reading the submatrices into the cache, it is beneficial to improve the cache hit rate of the submatrices in the cache, thereby improving the processing efficiency of the first task.

[0009] In one possible design, the target storage format includes at least a first storage format, a second storage format, and a third storage format. The computing device determines the target storage format corresponding to the first submatrix based on the number of non-zero elements in the first submatrix, including: if the number of non-zero elements in the first submatrix is ​​less than or equal to the number of rows in the first submatrix, the computing device determines that the first submatrix corresponds to the first storage format; or, if the number of non-zero elements in the first submatrix is ​​greater than the number of rows in the first submatrix, and there are multiple row vectors or column vectors with the same number of non-zero elements in the first submatrix, the computing device determines that the first submatrix corresponds to the second storage format; if the number of non-zero elements is greater than 0; or, if the number of non-zero elements in the first submatrix is ​​greater than the number of rows in the first submatrix, and there are no multiple row vectors or column vectors with the same number of non-zero elements in the first submatrix, the computing device determines that the first submatrix corresponds to the third storage format. In this design, when the first submatrix has few non-zero elements, storing the first submatrix in the first storage format (e.g., COO format) saves memory and improves cache hit rate because the arrays for recording row and column numbers in the first storage format are determined by the number of non-zero elements. Conversely, when the first submatrix has a large number of non-zero elements and contains multiple row or column vectors with the same number of non-zero elements, storing the first submatrix in the second storage format (e.g., Ellpack format) saves memory and improves cache hit rate because the arrays in the second storage format are unaffected by the number of non-zero elements and require less space to fill the arrays representing the first submatrix. When the first submatrix contains a large number of non-zero elements, and there are no multiple row and column vectors with the same number of non-zero elements, storing the first submatrix in the third storage format (such as CSR or CSC format) is beneficial because the array used to record row offsets is determined by the number of rows in the first submatrix, or the array used to record column offsets is determined by the number of columns in the first submatrix, and is unaffected by the number of non-zero elements. Therefore, storing the first submatrix in the third storage format helps save memory usage and improves its cache hit rate.

[0010] In one possible design, the second storage format includes at least elliptic format and sliced ​​elliptic format. When the number of non-zero elements in the first submatrix is ​​greater than the number of rows in the first submatrix, and there are multiple row vectors or column vectors in the first submatrix with the same number of non-zero elements, the computing device determines that the first submatrix corresponds to the second storage format. This includes: when the number of non-zero elements in the first submatrix is ​​greater than the number of rows in the first submatrix, and the number of non-zero elements in the row vectors or column vectors in the first submatrix that include non-zero elements is the same, the computing device determines that the first submatrix corresponds to the elliptic format; or, when the number of non-zero elements in the first submatrix is ​​greater than the number of rows in the first submatrix, and there are multiple consecutive row vectors or column vectors in the first submatrix that have the same number of non-zero elements, the computing device determines that the first submatrix corresponds to the sliced ​​elliptic format. In this design, since the number of non-zero elements in the row vectors or column vectors in the first submatrix is ​​the same, and the Ellpack format does not require segmentation of the first submatrix, storing the first submatrix using the Ellpack format is more convenient. Furthermore, since the number of non-zero elements in the row or column vectors of the first submatrix is ​​the same for all of them, the Ellpack format eliminates the need to fill the array with zero elements to record the element values. This saves memory on the first submatrix and improves its cache hit rate. Because the first submatrix contains multiple consecutive row or column vectors with the same number of non-zero elements, and the Sliced-Ellpack format can segment these vectors, storing the first submatrix using the Sliced-Ellpack format is more efficient. Moreover, since the first submatrix contains multiple consecutive row or column vectors with the same number of non-zero elements, the Sliced-Ellpack format minimizes the need to fill the array with zero elements to record the element values, further saving memory on the first submatrix and improving its cache hit rate.

[0011] In one possible design, multiple submatrices include a first submatric; the target storage format includes at least a fourth storage format and a fifth storage format; the computing device determines the target storage format corresponding to each of the multiple submatrices, including: if the first submatric is a diagonal block, the computing device determines that the first submatric corresponds to the fourth storage format; if the first submatric is a non-diagonal block, the computing device determines that the first submatric corresponds to the fifth storage format. In this design, since the number of non-zero elements included in the diagonal block is relatively large, the computing device can determine that the first submatric corresponds to the fourth storage format (such as the CSR format) when the first submatric is a diagonal block. The array used to record row offset values ​​corresponding to the CSR format is determined based on the number of rows in the first submatric, and is not affected by the number of non-zero elements in the first submatric. Therefore, when the number of non-zero elements in the first submatric is relatively large, storing the first submatric according to the fourth storage format helps to save memory cost of the first submatric in memory, thereby improving the cache hit rate of the first submatric. Since off-diagonal blocks contain a relatively small number of non-zero elements, when the first submatrix is ​​an off-diagonal block, the computing device can use a fifth storage format (such as COO format) for the first submatrix. The array used to record row and column numbers in the COO format is determined based on the number of non-zero elements in the first submatrix. Therefore, storing the first submatrix in the fifth storage format when there are few non-zero elements helps save memory usage and improves cache hit rate. Furthermore, the aforementioned design determines the target storage format of the first submatrix directly based on whether it is a diagonal block, rather than on the number of non-zero elements, avoiding the need to count the number of non-zero elements and facilitating faster determination of the target storage format.

[0012] In one possible design, the computing device determines the target storage format corresponding to multiple sub-matrices, including: determining at least one first access count based on the multiple sub-matrices, where the first access count is the access count of a first matrix; and determining the target storage format corresponding to each of the multiple sub-matrices based on the at least one first access count. In this design, the computing device determines the target storage format corresponding to each of the multiple sub-matrices based on the first access count, and the determined target storage format corresponding to each of the multiple sub-matrices helps to reduce the first access count, thereby improving the cache hit rate of the sub-matrices in the cache.

[0013] In one possible design, the computing device processes a first task based on multiple sub-matrices and their respective target storage formats to obtain a processing result for the first task. This includes: the computing device converting the initial storage format of each of the multiple sub-matrices in memory to its corresponding target storage format; and the computing device processing the first task based on the converted sub-matrices to obtain the processing result for the first task. This design provides a specific method for processing a first task.

[0014] In one possible design, multiple submatrices include a first submatrice. The computing device converts the initial storage format of each submatric in memory to its corresponding target storage format, including: the computing device generating a first position record and a first element record for the target storage format of the first submatric, where the first position record records the position of an element in the first submatric, and the first element record records the value of an element in the first submatric; the computing device processes the first task based on the multiple submatrices converted to the target storage format to obtain a processing result for the first task, which may include: processing the first task based on the first position record and the first element record to obtain a processing result for the first task. This design provides a specific method for processing the first task.

[0015] In one possible design, the above method further includes: the computing device reading a second task into memory, the second task including a second matrix, the second matrix being a sparse matrix, the second matrix having an initial storage format in memory, and the element distribution structure of the second matrix being the same as that of the first matrix; the computing device splitting the second matrix to obtain multiple sub-matrices in the second matrix, the splitting method of the second matrix being the same as that of the first matrix; the computing device converting the initial storage format of the multiple sub-matrices in the second matrix in memory to their respective target storage formats according to the target storage formats corresponding to the multiple sub-matrices in the first matrix; the target storage formats of the multiple sub-matrices in the second matrix corresponding to the target storage formats of the multiple sub-matrices in the first matrix; and the computing device processing the second task based on the multiple sub-matrices in the second matrix converted to the target storage formats to obtain the processing result corresponding to the second task. In this design, the computing device splits the second matrix according to the splitting method of the first matrix, without needing to calculate how to split the second matrix into multiple sub-matrices. In addition, the computing device converts the initial storage format of the multiple sub-matrices in the second matrix in memory to their respective target storage formats according to the target storage formats corresponding to the multiple sub-matrices in the first matrix. Without needing to calculate to determine the target storage format of the multiple sub-matrices in the second matrix, it is beneficial to improve the efficiency of converting the second sub-matrices to their corresponding target storage formats, thereby improving the processing efficiency of the second task.

[0016] In one possible design, a first matrix contains multiple submatrices, each including a first submatrice, and a second matrix contains multiple submatrices, each including a second submatrice. The first and second submatrices correspond to each other. The computing device converts the initial storage format of the multiple submatrices in the second matrix in memory to their respective target storage formats, based on the target storage formats corresponding to the multiple submatrices in the first matrix. This includes: the computing device determining a first position record corresponding to the first submatric as a second position record corresponding to the second submatric; the second position record being used to record the position of an element in the second submatric; and the computing device updating the first element record corresponding to the first submatric with elements from the second submatric to obtain a second element record corresponding to the second submatric, where the second element record is used to record the value of an element in the second submatric. In this design, the computing device can directly use the first position record as the second position record without generating a second position record. Furthermore, the computing device only needs to generate the second element record, which effectively improves the efficiency of converting the second submatric to its corresponding target storage format.

[0017] The computing device processes the second task based on multiple sub-matrices in the second matrix converted to the target storage format, and obtains the processing result corresponding to the second task. This includes: the computing device processes the second task based on the second position record and the second element record, and obtains the processing result corresponding to the second task. This design provides a specific method for processing the second task.

[0018] In one possible design, the first storage format includes a coordinate format, the second storage format includes an ellipse type format, and the third storage format includes at least a compressed sparse row format and a compressed sparse column format.

[0019] In one possible design, the fourth storage format includes a compressed sparse line format, and the fifth storage format includes a coordinate format.

[0020] Secondly, this application also provides a data processing apparatus, which includes methods for performing the methods provided in the first aspect above. The data processing apparatus includes: a reading module, a splitting module, a determining module, and a processing module.

[0021] The reading module is used to read the first task into memory. The first task includes a first matrix, which is a sparse matrix and is stored in memory in its initial format.

[0022] The splitting module is used to split the first matrix into multiple sub-matrices;

[0023] The determination module is used to determine the target storage format for each of the multiple sub-matrices; the target storage format is determined based on the element distribution structure of the sub-matrices.

[0024] The processing module is used to process the first task according to multiple sub-matrices and their respective target storage formats, and obtain the processing result of the first task.

[0025] In one possible design, the splitting module is specifically used for: determining the number P of processes handling the first task; P being an integer greater than 0; splitting the first matrix into rows based on the number of processes P to obtain P reference matrices; and splitting the P reference matrices into rows and / or columns respectively to obtain multiple sub-matrices.

[0026] In one possible design, multiple submatrices include a first submatrix; the determining module is specifically used to: determine the target storage format corresponding to the first submatrix based on the number of non-zero elements in the first submatrix.

[0027] In one possible design, the target storage format includes at least a first storage format, a second storage format, and a third storage format. The determining module is specifically used to: determine the first storage format corresponding to the first submatrix when the number of non-zero elements in the first submatrix is ​​less than or equal to the number of rows in the first submatrix; or, determine the second storage format corresponding to the first submatrix when the number of non-zero elements in the first submatrix is ​​greater than the number of rows in the first submatrix, and there are multiple row vectors or column vectors with the same number of non-zero elements in the first submatrix; or, determine the third storage format corresponding to the first submatrix when the number of non-zero elements in the first submatrix is ​​greater than 0; or, determine the third storage format corresponding to the first submatrix when the number of non-zero elements in the first submatrix is ​​greater than the number of rows in the first submatrix, and there are no multiple row vectors or column vectors with the same number of non-zero elements in the first submatrix.

[0028] In one possible design, the second storage format includes at least an elliptic format and a sliced ​​elliptic format; the determining module is specifically used to: determine the elliptic format corresponding to the first submatrix when the number of non-zero elements in the first submatrix is ​​greater than the number of rows in the first submatrix, and the number of non-zero elements corresponding to row vectors or column vectors containing non-zero elements in the first submatrix is ​​the same; or, determine the sliced ​​elliptic format corresponding to the first submatrix when the number of non-zero elements in the first submatrix is ​​greater than the number of rows in the first submatrix, and the number of non-zero elements corresponding to multiple consecutive row vectors or column vectors in the first submatrix is ​​the same.

[0029] In one possible design, multiple submatrices include a first submatric; the target storage format includes at least a fourth storage format and a fifth storage format; the determining module is specifically used to: determine the fourth storage format corresponding to the first submatric when the first submatric is a diagonal block; and determine the fifth storage format corresponding to the first submatric when the first submatric is a non-diagonal block.

[0030] In one possible design, the determining module is specifically used for: determining at least one first access count based on multiple submatrices, wherein the first access count is the access count of the first matrix; and determining the target storage format corresponding to each of the multiple submatrices based on at least one first access count.

[0031] In one possible design, the processing module is specifically used to: convert the initial storage format of the multiple sub-matrices in memory to their respective target storage formats according to the target storage formats corresponding to the multiple sub-matrices; and process the first task according to the multiple sub-matrices converted to the target storage formats to obtain the processing result corresponding to the first task.

[0032] In one possible design, multiple submatrices include a first submatric; the processing module is specifically used to: generate a first position record and a first element record of the target storage format corresponding to the first submatric based on the first submatric and the target storage format corresponding to the first submatric, wherein the first position record is used to record the position of the element in the first submatric and the first element record is used to record the value of the element in the first submatric; the processing module is specifically used to: process the first task based on the first position record and the first element record to obtain the processing result corresponding to the first task.

[0033] In one possible design, the reading module is also used to read the second task into memory. The second task includes a second matrix, which is a sparse matrix. The second matrix is ​​stored in memory in an initial format, and the element distribution structure of the second matrix is ​​the same as that of the first matrix.

[0034] The processing module is also used to split the second matrix to obtain multiple sub-matrices in the second matrix; the splitting method of the second matrix is ​​the same as that of the first matrix; according to the target storage format corresponding to the multiple sub-matrices in the first matrix, the initial storage format of the multiple sub-matrices in the second matrix in memory is converted to their respective target storage formats; the target storage formats of the multiple sub-matrices in the second matrix correspond to the target storage formats of the multiple sub-matrices in the first matrix; based on the multiple sub-matrices in the second matrix converted to the target storage format, the second task is processed to obtain the processing result corresponding to the second task.

[0035] In one possible design, the first matrix contains multiple submatrices including the first submatrix, and the second matrix contains multiple submatrices including the second submatrix; the first submatrix corresponds to the second submatrix; the processing module is specifically used to: determine the first position record corresponding to the first submatrix as the second position record corresponding to the second submatrix; the second position record is used to record the position of the element in the second submatrix; update the first element record corresponding to the first submatrix with the element in the second submatrix to obtain the second element record corresponding to the second submatrix, the second element record is used to record the value of the element in the second submatrix;

[0036] The processing module is specifically used to: process the second task based on the second position record and the second element record, and obtain the processing result corresponding to the second task.

[0037] Thirdly, this application also provides a computer program product containing instructions that, when executed by a computing system, cause the computing system to perform the method provided in the first aspect above.

[0038] Fourthly, this application also provides a computer-readable storage medium including computer program instructions, which, when executed by a computing system, enable the computing system to perform the method provided in the first aspect above.

[0039] Fifthly, this application also provides a computing device, including a processor and a memory, wherein the memory stores computer-executable instructions; the processor is used to execute the computer-executable instructions stored in the memory, and the processor performs the method provided in the first aspect above.

[0040] Sixthly, this application also provides a chip containing instructions that, when executed by a computing system, cause the computing system to perform the method provided in the first aspect above.

[0041] In a seventh aspect, this application provides a chip system containing instructions that, when executed by a computing system, cause the computing system to perform the method provided in the first aspect above. This chip system may be composed of chips or may include chips and other discrete devices. Attached Figure Description

[0042] Figure 1(a) is a schematic diagram of a CSR format provided in an embodiment of this application;

[0043] Figure 1(b) is a schematic diagram of a CSC format structure provided in an embodiment of this application;

[0044] Figure 2(a) is a schematic diagram of the structure of an Ellpack format provided in an embodiment of this application;

[0045] Figure 2(b) is a schematic diagram of the structure of a Sliced-Ellpack format provided in an embodiment of this application;

[0046] Figure 3 A schematic diagram of a computing device provided in an embodiment of this application;

[0047] Figure 4 A flowchart illustrating a data processing method provided in an embodiment of this application;

[0048] Figure 5 A flowchart illustrating a method for splitting a first matrix provided in an embodiment of this application;

[0049] Figure 6 This is a schematic diagram of a structure for splitting a first matrix, provided in an embodiment of this application.

[0050] Figure 7 A flowchart illustrating a method for splitting a first reference matrix provided in an embodiment of this application;

[0051] Figure 8 A flowchart illustrating a method for determining the target storage format corresponding to a submatrix, provided in an embodiment of this application;

[0052] Figure 9A flowchart illustrating a method for determining the target storage format corresponding to a submatrix, provided in an embodiment of this application;

[0053] Figure 10 A flowchart illustrating a method for determining at least one first access count, provided as an embodiment of this application;

[0054] Figure 11 A flowchart illustrating a method for obtaining the processing result corresponding to a first task, provided in an embodiment of this application;

[0055] Figure 12 A flowchart illustrating a data processing method provided in an embodiment of this application;

[0056] Figure 13 A flowchart illustrating a method for transforming a second submatrix provided in an embodiment of this application;

[0057] Figure 14 This is a schematic diagram of the structure of a data processing device provided in an embodiment of this application. Detailed Implementation

[0058] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. The terms "first," "second," and corresponding reference numerals in the specification, claims, and drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate; this is merely a way of distinguishing objects with the same attributes in the embodiments of this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, so that a process, method, system, product, or apparatus that comprises a series of units is not necessarily limited to those units, but may include other units not explicitly listed or inherent to these processes, methods, products, or apparatuses.

[0059] The following explanations of some terms used in the embodiments of this application are provided to facilitate understanding by those skilled in the art.

[0060] I. Row Vectors

[0061] A row vector is a 1×m matrix, where m is any positive integer, for example: x = [x1 x2…xm].

[0062] II. Column Vectors

[0063] A column vector is an n×1 matrix, where n is any positive integer, for example:

[0064] III. Matrix Size / Scale

[0065] An m×n matrix is ​​a rectangular array consisting of m rows and n columns of elements. For example:

[0066]

[0067] In a matrix, each number that makes up the matrix is ​​called an element of the matrix. For example, A 11 A 12 , ..., Amn are all elements of matrix A. The subscript (or coordinate) of an element indicates its position in the matrix; it can be the row number (or row coordinate) or column number (or column coordinate). For example, A 11 This indicates that the element is located in the first row and first column of matrix A. 21 This indicates that the element is located in the second row and first column of matrix A. Additionally, subscripts can have different representations, such as A... 11 It can also be written as A1, 1, A 21 It can also be written as A2, 1, etc., and similar examples will not be repeated below.

[0068] IV. Diagonal Matrix

[0069] A diagonal matrix is ​​a matrix whose only diagonal elements are non-zero. Alternatively, a square matrix is ​​called a diagonal matrix if all elements except those on the main diagonal are zero. For example:

[0070]

[0071] This can be abbreviated as A = diag{A 11 A 22 ,…,Ann}.

[0072] V. Sparse matrix / Dense matrix

[0073] Matrices are classified into sparse and dense matrices based on the proportion of non-zero elements. A dense matrix contains mostly non-zero elements, while a sparse matrix contains mostly zero elements. Sparsity reflects the proportion of non-zero elements in a sparse matrix; higher sparsity indicates a lower proportion of non-zero elements. Below is an example of a sparse matrix:

[0074] 0 7 0 0 0 0 0 7 6 3 0 4 0 4 3 0 0 0 4 2 0 0 0 0 0 0 0 0 3 2 5 0 0 0 0 1

[0075] Large matrices require significant memory for storage, while sparse matrices contain mostly zeros. Therefore, when storing and manipulating sparse matrices in a computer, the elements are typically encoded using sparse codes. Sparse codes only include information about non-zero elements, saving memory overhead when manipulating the sparse matrix. Common sparse encoding formats include: coordinate (COO) format, compressed sparse row (CSR) format, compressed sparse column (CSC) format, ellipse (Ellpack) format, and sliced-Ellpack format.

[0076] (1) COO format: Sparse matrices are represented by triples, which include the element value, row number, and column number. The row and column numbers are used to identify the position of the element. A simple sparse matrix is ​​shown below for illustration.

[0077] 1 0 0 0 0 6 3 0 0

[0078] For this sparse matrix, the information can be stored in the format (values, row, column) as follows:

[0079] (1, 1, 1): The element has a value of 1 and an index of (1, 1).

[0080] (3, 3, 1): The element has a value of 3 and an index of (3, 1).

[0081] (6, 2, 3): The element has a value of 6 and an index of (2, 3).

[0082] Of course, the above information can also be stored in other formats, such as (row, column, values), etc., without any specific limitation.

[0083] (2) CSR Format: The sparse matrix is ​​represented by three arrays, which are used to record row offsets, column numbers, and element values, respectively. The array recording element values ​​stores the values ​​of non-zero elements in the sparse matrix. The array recording column numbers uses the i-th column number to identify the column number of the i-th element in the array recording element values. The array recording row offsets uses the j-th row offset to record the number of non-zero elements in the first j-1 rows of the sparse matrix. The difference between the CSR format and the COO format is that the CSR format uses row offsets instead of row numbers. Figure 1(a) illustrates an example of a CSR format.

[0084] (3) CSC format: The sparse matrix is ​​represented by three arrays, which are used to record column offsets, column numbers, and element values, respectively. The array for recording element values ​​records the values ​​of non-zero elements in the sparse matrix. The array for recording column numbers identifies the column number of the i-th element in the array for recording element values. The array for recording column offsets records the number of non-zero elements in the first j-1 columns of the sparse matrix. The difference between the CSC format and the COO format is that the CSC format uses column offsets instead of column numbers. Figure 1(b) illustrates an example of a CSC format.

[0085] (4) Ellpack format: The sparse matrix is ​​represented by three arrays, which are used to record the first quantity, row number, and element value, respectively. The first quantity array records the number of non-zero elements in the row vector with the most non-zero elements in the sparse matrix. The column number array includes the column numbers of the non-zero elements in each row vector. If the number of non-zero elements in a row vector is less than the first quantity, the column number of the last non-zero element in that row vector is used to fill the first quantity. The element value array includes the element value of the non-zero elements in each row vector. If the number of non-zero elements in a row vector is less than the first quantity, zero elements are used to fill the first quantity. Figure 2(a) illustrates an example of the Ellpack format.

[0086] (5) Sliced-Ellpack format: A sparse matrix is ​​represented by a slice count and three arrays. The slice count records the number of matrices resulting from the sparse matrix being sliced. The three arrays record the slice count, row number, and element value, respectively. Each sliced ​​matrix is ​​recorded according to the Ellpack format, thus obtaining these three arrays. Figure 2(b) illustrates an example of the Sliced-Ellpack format.

[0087] The above describes five compression formats for sparse matrices. In contrast, matrices in uncompressed formats are generally called dense matrices. Dense matrices only include the numerical values ​​of the matrix elements and do not store the coordinates of the elements.

[0088] VI. Sparse Linear Equations

[0089] A sparse linear system of equations can be represented in matrix form as: Ax = b. Here, A can be an m×n sparse matrix. x is an n×1 vector to be solved, and b is the right-hand side term, which can be an m×1 vector.

[0090] Solving sparse linear equation systems can be done using either matrix factorization or iterative methods. Iterative methods include steepest descent, Newton's method, quasi-Newton method, generalized minimal residual, and conjugate gradient.

[0091] Taking the conjugate gradient method as an example, the solution process of sparse linear equations is explained in detail.

[0092] 1) Initialize the vector x to be solved to obtain the initial vector x0;

[0093] 2) Based on the right-hand side terms b and x0, determine the initial iteration residual r0 = bA * x0 and the initial iteration direction p0 = r0;

[0094] 3) Iterate and update the initial direction p0, initial residual r0, and initial vector x0 to be solved to obtain the iteration direction p. i+1 Iteration residual r i+1 The vector to be solved x i+1 ;

[0095] x i+1 =x i +c1*p i

[0096] r i+1 =r i -c1*A*p i

[0097]

[0098] Where, x i+1 Let x represent the vector to be solved in the (i+1)th iteration. i Let r represent the vector to be solved in the i-th iteration. i+1 Let r represent the iterative residual corresponding to the (i+1)th iteration. i p represents the iterative residual corresponding to the i-th iteration. i+1 p represents the iteration direction corresponding to the (i+1)th iteration. i This indicates the iteration direction corresponding to the i-th iteration. Let c1 and c2 represent the direction update amount corresponding to the i-th iteration, A be a sparse matrix, i be the iteration number i be the value taken in [0, num], and num be a positive integer.

[0099] 4) The solution vector x under the condition that the iteration stopping condition is met.i+1 This is the vector to be solved in the end.

[0100] As can be seen from the solution process of the above sparse linear equation system, in calculating the iterative residual r i+1 When it is necessary to calculate A*p i That is, sparse matrix A and vector p i The multiplication operation can also be called sparse matrix-vector multiplication (SPMV).

[0101] Currently, when solving the sparse linear equation system Ax = b using the iterative method, the sparse matrix A and vector b can be loaded into memory first. Then, a portion of the sparse matrix A and vector b used in the iterative calculation can be loaded into a cache, and a portion of the sparse matrix A and vector b can be retrieved from the cache for the aforementioned iterative calculation. Generally, the sparse matrix A can be stored in memory according to any sparse encoding format. When the sparse matrix A is stored in memory according to different sparse encoding formats, the cache hit rate of loading the sparse matrix A into the cache will also be different.

[0102] For example, an example of a sparse matrix A is as follows:

[0103] 1 0 0 2 3 0 0 4 5 0 0 6 7 0 0 8

[0104] When the sparse matrix A is stored in memory in CSR format, as shown in Figure 1(a), after loading the arrays corresponding to sparse matrix A for recording row offsets and the arrays for recording element values ​​into the cache, assuming that the current cache has only one free space, it is impossible to load the entire array for recording column numbers into the cache. Therefore, the first column number 1 is loaded into the cache first. When loading the second column number 4 into the cache, since 4 is not in the cache, a first cache miss occurs, and the second column number 4 is loaded into the cache, overwriting the first column number 1. When loading the third column number 1 into the cache, since 1 is not in the cache, a second cache miss occurs, and the third column number 1 is loaded into the cache, overwriting the second column number 4. When loading the fourth column number 4 into the cache, since 4 is not in the cache, a third cache miss occurs, and the fourth column number 4 is loaded into the cache, overwriting the third column number 1. When loading the fifth column (column number 1) into the cache, a fourth cache miss occurs because column 1 is not in the cache. The fifth column (column number 1) is then loaded into the cache, overwriting the fourth column (column number 4). Similarly, when loading the sixth column (column number 4) into the cache, a fifth cache miss occurs because column 4 is not in the cache. The sixth column (column number 4) is then loaded into the cache, overwriting the fifth column (column number 1). When loading the seventh column (column number 1) into the cache, a sixth cache miss occurs because column 1 is not in the cache. The seventh column (column number 1) is then loaded into the cache, overwriting the sixth column (column number 4). Finally, when loading the eighth column (column number 4) into the cache, a seventh cache miss occurs because column 4 is not in the cache. The eighth column (column number 4) is then loaded into the cache, overwriting the seventh column (column number 1). From the above cache loading process, it can be seen that when the sparse matrix A is stored in memory in CSR format, there are a total of 7 cache misses.

[0105] When the sparse matrix A is stored in memory in CSC format, as shown in Figure 1(b), after loading the arrays corresponding to sparse matrix A for recording column offsets and the arrays for recording element values ​​into the cache, assuming that the current cache has only one free space, it is impossible to load the entire array for recording column numbers into the cache. Therefore, the first column number 1 is loaded into the cache first. When loading the second column number 1 into the cache, since 1 is already in the cache, there is no need to load the second column number 1 into the cache. When loading the third column number 1 into the cache, since 1 is already in the cache, there is no need to load the third column number 1 into the cache. When loading the fourth column number 1 into the cache, since 1 is already in the cache, there is no need to load the fourth column number 1 into the cache. When loading the fifth column number 4 into the cache, since 4 is not in the cache, a first cache miss occurs, and the fifth column number 4 is loaded into the cache, overwriting the first column number 1. When loading the sixth column number 4 into the cache, since 4 is already in the cache, there is no need to load the sixth column number 4 into the cache. When loading the seventh column (4) into the cache, since 4 is already in the cache, there's no need to load the seventh column (4) into the cache. Similarly, when loading the eighth column (4) into the cache, since 4 is already in the cache, there's no need to load the eighth column (4) into the cache. From the above cache loading process, it can be seen that when the sparse matrix A is stored in memory in CSC format, there is a total of one cache miss.

[0106] Therefore, in the process of solving sparse linear equations, how to improve the cache hit rate of sparse matrix A in the cache in order to improve the solution efficiency of sparse linear equations is a technical problem that urgently needs to be solved.

[0107] The technical solutions provided in the embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0108] Figure 3 This is a schematic diagram of a computing device 300 provided in this application. The computing device 300 includes a processor 301, a memory 302, and a communication interface 304. Optionally, the computing device 300 may also include a matrix arithmetic unit 306. The processor 301, memory 302, matrix arithmetic unit 306, and communication interface 304 can be interconnected via a communication line 305. The communication line 305 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The communication line 305 can be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, Figure 3 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0109] The processor 301 may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), an artificial intelligence (AI) chip, a system-on-chip (SoC), a complex programmable logic device (CPLD), a graphics processing unit (GPU), a neural network processing unit (NPU), a tensor processing unit (TPU), a deep learning processing unit (DPU), a microprocessor, or one or more integrated circuits used to control the execution of programs according to the present application.

[0110] Please note, Figure 3 Only one processor 301 is shown in this embodiment. In practical applications, there can be multiple processors 301. These multiple processors 301 may include multiple processors of the same type or multiple processors of different types. For example, the multiple processors 301 may include multiple CPUs. Alternatively, the multiple processors 301 may include at least one CPU and at least one GPU. Each CPU may have one or more CPU cores. This embodiment does not limit the number of processors 301 or the number of CPU cores.

[0111] Specifically, the processor 301 is used to process data access requests from outside the computing device 300 (such as other computing devices), and also to process requests generated internally by the computing device 300. For example, the data access request may be a write data request, which includes a first matrix, which may be a sparse matrix. After receiving the write data request, the processor 301 can execute the data processing method provided in this embodiment to process the first matrix and store the processed data in the memory 302. Alternatively, the request may be a read data request, which requests to read matrix data. The matrix data may include part or all of the first matrix. After receiving the read data request, the processor 301 reads the matrix data from the memory 302.

[0112] In addition to the above, processor 301 is also used for other data calculations or processing, such as matrix operations, etc., without specific limitations. Optionally, the aforementioned matrix operations can also be assigned to matrix operation unit 306 for execution. In some cases, when processor 301 has multiple cores, or computing device 300 includes multiple processors 301, or computing device 300 includes multiple matrix operation units 306, multiple cores, multiple processors 301, or multiple matrix operation units 306 can execute matrix operations in parallel, which will not be discussed in detail here.

[0113] The matrix operator 306 can be a GPU, NPU, TPU, DPU, etc., and is not limited here. The matrix operator 306 can be used to process matrix operations, as described above, and will not be repeated here.

[0114] Communication interface 304 uses any transceiver-like device for communicating with other devices or communication networks, such as Ethernet, radio access network (RAN), wireless local area network (WLAN), wired access network, etc. For example, it can be used to obtain read data requests, write data requests, matrix data, etc.

[0115] Memory 302 is used to store data and computer-executable program code. Data includes, but is not limited to, data from the first matrix. The executable program code may include program code for the data processing method provided in the embodiments of this application. Processor 301 executes the executable program code to implement the data processing method provided in this embodiment. That is, memory 302 stores computer execution instructions for executing the solution of this application, and the processor 301 controls the execution. Processor 301 is used to execute the computer execution instructions stored in memory 302 to implement the data processing method provided in the above embodiments of this application.

[0116] The memory 302 can exist independently and be connected to the processor via communication line 305. Alternatively, the memory 302 can be integrated with the processor. Specifically, the memory 302 can include RAM or a hard disk. RAM refers to the internal storage that directly exchanges data with the processor 301. It can read and write data at any time and at a very fast speed, serving as temporary data storage for the operating system or other running programs. Unlike RAM, the hard disk reads and writes data more slowly and is typically used for persistent data storage. In some application scenarios, the processor 301 can temporarily store the data of the first matrix in RAM. When the total amount of data in RAM reaches a certain threshold, the processor 301 sends the data stored in RAM to the hard disk for persistent storage. This data can be obtained from external devices, input by the user, or generated by the computing device 300; there are no specific limitations. Alternatively, the processor 301 can read data from RAM. If a memory cache miss occurs, the processor 301 reads the data from the hard disk into RAM and then reads the data from RAM again.

[0117] The memory includes at least two types of storage, such as random access memory (RAM) and read-only memory (ROM). For example, RAM can be dynamic random access memory (DRAM) or storage class memory (SCM). Memory can also include other types of RAM, such as static random access memory (SRAM). For read-only memory, examples include programmable read-only memory (PROM) and erasable programmable read-only memory (EPROM). Additionally, the memory can be a dual in-line memory module (DIMM), i.e., a module composed of DRAM. In practical applications, the computing device 300 can be configured with multiple memory modules of different types. This embodiment does not limit the number or type of memory.

[0118] A hard drive can specifically be a disk or other type of storage medium, such as a solid-state drive (SSD), a hard disk drive (HDD), a shingled magnetic recording hard disk, a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed discs, laser discs, optical discs, universal optical discs, Blu-ray discs, etc.), a disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer, but is not limited thereto.

[0119] It should be noted that, Figure 3 The structure of the computing device 300 shown is merely an example. In practical applications, the computing device 300 may have more or fewer components. For example, the computing device 300 may also include input / output devices such as a keyboard, mouse, and display screen. This application embodiment does not limit this.

[0120] Next, let's apply it to... Figure 3 Taking the computing device shown as an example, the data processing method provided in the embodiments of this application will be described in detail.

[0121] Figure 4 This is a flowchart illustrating the data processing method provided in the embodiments of this application. The method can be executed by a computing device with data processing capabilities (such as computing device 300), a module within that computing device, or a chip within that computing device, such as processor 301. For ease of explanation, the following description uses computing device 300 as an example. Figure 4 As shown, the method includes:

[0122] S401, the computing device reads the first task into memory.

[0123] In this embodiment, the first task can be solving a sparse linear system of equations Ax = b. The first task includes a first matrix A and a right-hand side term b, where the first matrix A can be an m×n sparse matrix, and the right-hand side term b can be an m×1 vector. The first task is used to determine the vector x to be solved using an iterative method based on the first matrix A and the right-hand side term b.

[0124] In this embodiment, the first matrix A can be stored in memory in an initial storage format, such as COO, CSR, CSC, Ellpack, Sliced-Ellpack, etc., without limitation. The right-hand item b can be stored in memory in the same or a different format than the first matrix A, without limitation.

[0125] S402, the computing device splits the first matrix into multiple sub-matrices and determines the target storage format corresponding to each of the multiple sub-matrices.

[0126] In the above S402, the computing device can, as shown in... Figure 5 The steps shown below split the first matrix into multiple submatrices.

[0127] S501, The computing device determines the number P of processes to handle the first task, where P is an integer greater than 0.

[0128] In this embodiment of the application, the number P of processes corresponding to the first task can be set by the user or determined by the computing device.

[0129] When the number of processes P corresponding to the first task is determined by the computing device, the computing device can directly use the first preset value as the number of processes P corresponding to the first task, or it can determine the number of processes P based on the size of the first matrix in the first task. For example, the more rows and / or columns the first matrix has, the larger the number of processes P will be; the fewer rows and / or columns the first matrix has, the smaller the number of processes P will be.

[0130] S502, the computing device performs row splitting on the first matrix according to the number of processes P, to obtain P reference matrices.

[0131] In this embodiment of the application, the computing device may perform row splitting on the first matrix through any one of the following implementations A1, A2, or A3.

[0132] In implementation method A1, a user can send a splitting request to a computing device. The splitting request may include the number of processes P and the row numbers in the first matrix corresponding to the P processes. Accordingly, the computing device receives the splitting request, obtains the number of processes P and the row numbers in the first matrix corresponding to the P processes from the splitting request, determines the P processes based on the number of processes P, and then performs row splitting on the first matrix according to the row numbers in the first matrix corresponding to the P processes to obtain P reference matrices.

[0133] For example, if the user inputs 3 processes, the row numbers in the first matrix corresponding to these 3 processes are 1 and 2, 3 and 4, and 5 and 6, respectively. Figure 6As shown, the computing device determines three processes based on the number of processes (3): process 1, process 2, and process 3. Then, the computing device performs row splitting on the first matrix based on row numbers 1 and 2 corresponding to process 1 to obtain reference matrix 1; the computing device performs row splitting on the first matrix based on row numbers 3 and 4 corresponding to process 2 to obtain reference matrix 2; and the computing device performs row splitting on the first matrix based on row numbers 5 and 6 corresponding to process 3 to obtain reference matrix 3.

[0134] In implementation method A2, the user sends a split request to the computing device, wherein the split request may include the number of processes P. Accordingly, the computing device receives the split request, obtains the number of processes P from the split request, determines P processes based on the number of processes P, and determines the reference matrices corresponding to the P processes from the first matrix, thereby obtaining P reference matrices.

[0135] In the above-described embodiment A2, after determining P processes based on the number of processes P, the computing device can select at least one consecutive row vector from the first matrix as a reference matrix corresponding to a process.

[0136] In implementation method A3, the computing device determines the number of processes P, and determines P processes based on the number of processes P. It then determines the reference matrices corresponding to the P processes from the first matrix to obtain P reference matrices.

[0137] In the above-described embodiment A3, the computing device may directly use the first preset value as the number of processes P, or it may determine the number of processes P based on the size of the first matrix; there is no limitation on this.

[0138] In the above-described embodiment A3, after determining P processes based on the number of processes P, the computing device can select at least one consecutive row vector from the first matrix as a reference matrix corresponding to a process.

[0139] It should be understood that, among the P reference matrices determined by any one of embodiments A1, A2, or A3, the number of rows in each reference matrix may be the same or different, and this is not limited here. The number of columns in each reference matrix is ​​the same, and the number of columns in each reference matrix is ​​the same as the number of columns in the first matrix.

[0140] S503, the computing device performs row splitting and / or column splitting on the P reference matrices respectively to obtain multiple sub-matrices.

[0141] In the above Figure 5In the steps shown, after obtaining the first matrix, the computing device first performs row partitioning on the first matrix according to the number of processes P, obtaining P reference matrices. Then, it performs row partitioning and / or column partitioning on the P reference matrices respectively, obtaining multiple sub-matrices. This partitioning method can ensure that the number of sub-matrices corresponding to each process is relatively balanced, which facilitates subsequent processing of the first task by each process according to its corresponding sub-matrices, and helps to improve the processing efficiency of the first task.

[0142] In the above S503, the computing device can perform row splitting and / or column splitting on the P reference matrices through any one of the following embodiments B1, B2 or B3 to obtain multiple sub-matrices.

[0143] In implementation method B1, the computing device performs row splitting and / or column splitting on the P reference matrices according to the element distribution structure of each reference matrix in the P reference matrices to obtain multiple sub-matrices.

[0144] In this embodiment of the application, for the first reference matrix among P reference matrices, where the first reference matrix is ​​any one of the P reference matrices, it can be adopted as follows: Figure 7 The following steps are shown for row splitting and / or column splitting.

[0145] S701, the computing device performs column splitting on the first reference matrix to obtain diagonal blocks and off-diagonal blocks.

[0146] In this embodiment of the application, since the element distribution structure of the diagonal blocks and off-diagonal blocks is different, that is, the number of non-zero elements included in the diagonal blocks is relatively large and the number of non-zero elements included in the off-diagonal blocks is relatively small, the computing device can split the first reference matrix into diagonal blocks and off-diagonal blocks.

[0147] When the first matrix A is an m×n sparse matrix, the first reference matrix can be an m1×n matrix, where m1 is less than m. That is, the number of columns in the first reference matrix is ​​the same as the number of columns in the first matrix, and the number of rows in the first reference matrix is ​​less than or equal to the number of rows in the first matrix. The computing device performs column splitting on the first reference matrix, which yields an m1×n1 diagonal block and an m1×n2 off-diagonal block, where n1 and n2 are both less than n, and n1 + n2 equals n, and m1 equals n1.

[0148] It should be understood that the number of rows in the diagonal block matrix is ​​equal to the number of rows in the first reference matrix, and the number of columns in the diagonal block matrix is ​​less than or equal to the number of columns in the first reference matrix. The diagonal block is a square matrix. In the embodiments of this application, different element distribution structures of the first matrix A result in different element distribution structures of the obtained diagonal blocks. Therefore, for different first matrices A, the obtained diagonal blocks may be diagonal matrices or off-diagonal matrices.

[0149] It should be understood that the number of rows in the off-diagonal block matrix is ​​equal to the number of rows in the first reference matrix, and the number of columns in the off-diagonal block matrix is ​​less than or equal to the number of columns in the first reference matrix.

[0150] In this embodiment of the application, the computing device can treat both the diagonal and off-diagonal blocks obtained in S701 as sub-matrices, without having to perform the steps in S702 to split the diagonal blocks obtained in S701, and without having to perform the steps in S703 to split the off-diagonal blocks obtained in S701.

[0151] Optionally, Figure 7 The steps may also include S702 and S703.

[0152] S702, the computing device performs row splitting and / or column splitting on the diagonal blocks in the first reference matrix to obtain at least one submatrix.

[0153] In the above S702, the computing device can perform row splitting and / or column splitting of the diagonal block through any of the following embodiments C1 or C2.

[0154] In implementation C1, the computing device performs row splitting and / or column splitting on the diagonal blocks according to the element distribution structure of the diagonal blocks in the first reference matrix to obtain at least one submatrix. In implementation C1, the computing device can allocate as many non-zero elements in the diagonal blocks as possible to a submatrix, and also allocate as many zero elements in the diagonal blocks as possible to a submatrix, which is beneficial for more accurately determining the target storage format corresponding to the submatrix.

[0155] In implementation C2, the computing device performs random row and / or column splitting on the diagonal blocks of the first reference matrix to obtain at least one submatrix. Implementation C2 improves the diversity of diagonal block splitting.

[0156] It should be understood that in S702 above, the submatrices split from the diagonal blocks in the first reference matrix can all be set as diagonal blocks, or they can be set as diagonal blocks or off-diagonal blocks according to the position of the submatrices in the first matrix.

[0157] S703, the computing device performs row splitting and / or column splitting on the off-diagonal blocks in the first reference matrix to obtain at least one submatrix.

[0158] In the above S703, the computing device can perform row splitting and / or column splitting on the off-diagonal blocks through any of the following embodiments D1 or D2.

[0159] In implementation D1, the computing device performs row and / or column splitting on the off-diagonal blocks according to the element distribution structure of the off-diagonal blocks in the first reference matrix to obtain at least one sub-matrix. In implementation D1, the computing device can allocate as many non-zero elements and zero elements as possible from the off-diagonal blocks into a sub-matrix, which is beneficial for more accurately determining the target storage format corresponding to the sub-matrix.

[0160] In implementation D2, the computing device performs random row and / or column splitting on the off-diagonal blocks of the first reference matrix to obtain at least one submatrix. Implementation D2 improves the diversity of off-diagonal block splitting.

[0161] It should be understood that in S703 above, the submatrices split from the off-diagonal blocks of the first reference matrix can all be set as off-diagonal blocks.

[0162] The submatrix obtained through implementation method B1 includes non-zero elements as much as possible, or includes zero elements as much as possible, which is beneficial for more accurately determining the target storage format corresponding to the submatrix in the subsequent process.

[0163] In implementation method B2, the computing device can perform row splitting and / or column splitting on the P reference matrices according to user-defined splitting rules to obtain multiple sub-matrices.

[0164] In one possible implementation, the user can send a splitting rule to the computing device; accordingly, the computing device receives the splitting rule and splits the P reference matrices according to the splitting rule to obtain multiple sub-matrices.

[0165] It should be understood that the splitting rules may include the row and column numbers corresponding to each submatrix. Alternatively, the splitting rules may include splitting instruction information, which instructs the computing device to split the reference matrix according to the element distribution structure of the reference matrix.

[0166] Through the above implementation method B2, the computing device can split the reference matrix according to the user-defined splitting rules, which is beneficial to improving the interactivity with the user.

[0167] In implementation method B3, the computing device can perform random row splitting and / or column splitting on the P reference matrices respectively to obtain multiple sub-matrices.

[0168] Through the above implementation method B3, the computing device can randomly split the reference matrix, which is beneficial to achieving splitting diversity.

[0169] In S402 above, the computing device can determine the target storage format corresponding to the multiple sub-matrices through any one of the embodiments E1, E2, E3 or E4, wherein the target storage format corresponding to the sub-matrices can be determined according to the element distribution structure of the sub-matrices.

[0170] In implementation method E1, for the first submatrix among multiple submatrixes, where the first submatrix is ​​any one of the multiple submatrixes, the computing device can determine the target storage format corresponding to the first submatrix based on the number of non-zero elements in the first submatrix.

[0171] The above-described implementation method E1 may include, for example: Figure 8 The following steps are shown.

[0172] S801, the computing device determines the number of non-zero elements in the first submatrix.

[0173] S802, if the number of non-zero elements in the first submatrix is ​​less than or equal to the number of rows in the first submatrix, the computing device determines that the first submatrix corresponds to the first storage format.

[0174] In this embodiment of the application, the first storage format may be COO format.

[0175] In the above S802, since the number of non-zero elements in the first submatrix is ​​relatively small, and the array used to record row and column numbers in the COO format is determined according to the number of non-zero elements in the first submatrix, storing the first submatrix in the COO format when there are relatively few non-zero elements in the first submatrix is ​​beneficial to saving the memory cost of the first submatrix in memory, and thus improving the cache hit rate of the first submatrix.

[0176] S803, if the number of non-zero elements in the first submatrix is ​​greater than the number of rows in the first submatrix, and there are multiple row vectors or column vectors in the first submatrix with the same number of non-zero elements, the computing device determines that the first submatrix corresponds to the second storage format; wherein the number of non-zero elements is greater than 0.

[0177] In this embodiment of the application, the second storage format can be an Ellpack type format, wherein the Ellpack type format includes at least the Ellpack format and the Sliced-Ellpack format.

[0178] In one possible implementation, the first submatrix is ​​determined to be in Ellpack format if the number of non-zero elements in the first submatrix is ​​greater than the number of rows in the first submatrix, and the number of non-zero elements in the row or column vectors of the first submatrix that contain non-zero elements is the same. Since the number of non-zero elements in the row or column vectors of the first submatrix is ​​the same, and the Ellpack format does not require splitting the first submatrix, storing the first submatrix using the Ellpack format is more convenient. Furthermore, because the number of non-zero elements in the row or column vectors of the first submatrix is ​​the same, using the Ellpack format eliminates the need to fill the array with zero elements to record element values, saving memory on the first submatrix and thus improving its cache hit rate.

[0179] For example, the first submatrix is ​​as follows:

[0180] 1 0 0 2 3 0 0 4 5 0 0 6 7 0 0 8

[0181] The number of non-zero elements in the first submatrix is ​​8, and the number of rows in the first submatrix is ​​4, which satisfies the condition that the number of non-zero elements in the first submatrix (8) is greater than the number of rows in the first submatrix (4).

[0182] The first submatrix contains four row vectors with non-zero elements: [1,0,0,2], [3,0,0,4], [5,0,0,6], and [7,0,0,8]. Each row vector has two non-zero elements, satisfying the condition that the row vectors in the first submatrix that contain non-zero elements all have the same number of non-zero elements.

[0183] Therefore, the first submatrix mentioned above corresponds to the Ellpack format.

[0184] In one possible implementation, if the number of non-zero elements in the first submatrix is ​​greater than the number of rows in the first submatrix, and multiple consecutive row or column vectors in the first submatrix have the same number of non-zero elements, then the first submatrix is ​​determined to be in Sliced-Ellpack format. Since multiple consecutive row or column vectors in the first submatrix have the same number of non-zero elements, and the Sliced-Ellpack format can segment row or column vectors with the same number of non-zero elements, storing the first submatrix in Sliced-Ellpack format is more reasonable. Furthermore, because multiple consecutive row or column vectors in the first submatrix have the same number of non-zero elements, using Sliced-Ellpack format can minimize the use of zero elements to fill the array used to record element values, which helps save memory costs for the first submatrix in memory, thereby improving the cache hit rate of the first submatrix.

[0185] It should be understood that when the first submatrix can correspond to either the Ellpack format or the Sliced-Ellpack format, the computing device can choose either the Ellpack format or the Sliced-Ellpack format as the target storage format for the first submatrix, or it can preferentially choose the Ellpack format as the target storage format for the first submatrix.

[0186] For example, the first submatrix is ​​as follows:

[0187] 1 0 0 2 3 0 0 4 5 0 0 6 7 0 0 8

[0188] The number of non-zero elements in the first submatrix is ​​8, and the number of rows in the first submatrix is ​​4, which satisfies the condition that the number of non-zero elements in the first submatrix (8) is greater than the number of rows in the first submatrix (4).

[0189] The first submatrix contains four consecutive row vectors with non-zero elements: [1,0,0,2], [3,0,0,4], [5,0,0,6], and [7,0,0,8]. Each row vector contains two non-zero elements, satisfying the condition that the first submatrix contains multiple consecutive row vectors with the same number of non-zero elements.

[0190] Therefore, the first submatrix mentioned above corresponds to the Sliced-Ellpack format.

[0191] It should be understood that if the first submatrix can correspond to either Ellpack or Sliced-Ellpack format, either Ellpack or Sliced-Ellpack format can be chosen as the target storage format for the first submatrix, without any limitation.

[0192] In S803 above, since the first submatrix has a large number of non-zero elements and contains multiple row or column vectors with the same number of non-zero elements, storing the first submatrix in Ellpack format is beneficial in saving memory usage and thus improving cache hit rate. This is because the number of non-zero elements in the first submatrix is ​​not affected by the number of non-zero elements, and using Ellpack format reduces the amount of space needed to represent the first submatrix.

[0193] S804, if the number of non-zero elements in the first submatrix is ​​greater than the number of rows in the first submatrix, and there are no multiple row vectors and column vectors with the same number of non-zero elements in the first submatrix, the computing device determines that the first submatrix corresponds to the third storage format.

[0194] In the embodiments of this application, the third storage format includes at least CSR format, CSC format, etc., and is not limited thereto.

[0195] In S804 above, since the first submatrix has a relatively large number of non-zero elements, and there are no multiple row vectors and column vectors with the same number of non-zero elements, the array used to record row offset values ​​in the CSR format is determined by the number of rows in the first submatrix, and the array used to record column offset values ​​in the CSC format is determined by the number of columns in the first submatrix; neither is affected by the number of non-zero elements in the first submatrix. Therefore, when the first submatrix has a relatively large number of non-zero elements, and there are no multiple row vectors and column vectors with the same number of non-zero elements, storing the first submatrix in CSR or CSC format helps save memory usage and thus improves the cache hit rate of the first submatrix.

[0196] For example, the first submatrix is ​​as follows:

[0197] 1 0 0 0 3 4 0 0 5 6 6 0 7 7 7 8

[0198] The number of non-zero elements in the first submatrix is ​​8, and the number of rows in the first submatrix is ​​4, which satisfies the condition that the number of non-zero elements in the first submatrix (8) is greater than the number of rows in the first submatrix (4).

[0199] The first submatrix contains four row vectors with non-zero elements: [1,0,0,0], [3,4,0,0], [5,6,6,0], and [7,7,7,8]. The number of non-zero elements in these four row vectors are 1, 2, 3, and 4, respectively, which satisfies the condition that there are no multiple row vectors with the same number of non-zero elements in the first submatrix.

[0200] The first submatrix contains four column vectors with non-zero elements: [1,3,5,7], [0,4,6,7], [0,0,6,7], and [0,0,0,8]. The number of non-zero elements in these four column vectors are 4, 3, 2, and 1, respectively, which satisfies the condition that there are no multiple column vectors with the same number of non-zero elements in the first submatrix.

[0201] Therefore, the first submatrix mentioned above corresponds to the third storage format.

[0202] In the above implementation method E1, when there are relatively few non-zero elements in the first submatrix, since the array used to record row and column numbers corresponding to the first storage format (such as COO format) is determined according to the number of non-zero elements in the first submatrix, storing the first submatrix according to the first storage format is beneficial to saving the memory cost of the first submatrix in memory, and thus beneficial to improving the cache hit rate of the first submatrix.

[0203] When the first submatrix has a large number of non-zero elements and contains multiple row or column vectors with the same number of non-zero elements, storing the first submatrix in the second storage format (such as the Ellpack type format) is beneficial because the array corresponding to the second storage format is not affected by the number of non-zero elements in the first submatrix, and the second storage format can fill less of the array used to represent the first submatrix. Therefore, storing the first submatrix in the second storage format is beneficial to saving memory cost of the first submatrix in memory, and thus improving the cache hit rate of the first submatrix.

[0204] When the first submatrix contains a large number of non-zero elements, and there are no multiple row and column vectors with the same number of non-zero elements, storing the first submatrix in the third storage format (such as CSR or CSC format) is beneficial because the array used to record row offsets is determined by the number of rows in the first submatrix, or the array used to record column offsets is determined by the number of columns in the first submatrix, and is unaffected by the number of non-zero elements. Therefore, storing the first submatrix in the third storage format helps save memory usage and improves its cache hit rate.

[0205] In implementation method E2, the computing device can determine the target storage format corresponding to each of the multiple sub-matrices according to user-defined storage format rules.

[0206] In one possible implementation, the user can send storage format rules to the computing device; accordingly, the computing device receives the storage format rules and determines the target storage format corresponding to each of the multiple sub-matrices based on the storage format rules.

[0207] It should be understood that the storage format rules may include the target storage format corresponding to each submatrix. Alternatively, the storage format rules may include storage format indication information, wherein the storage format indication information is used to instruct the computing device to determine the target storage format corresponding to the submatrix according to the element distribution structure of the submatrix, or the storage format indication information is used to instruct the computing device to determine the target storage format corresponding to the submatrix based on the number of non-zero elements in the submatrix.

[0208] In the above-described implementation E2, the computing device determines the target storage format corresponding to each of the multiple sub-matrices according to the user-defined storage format rules, which helps to improve the interactivity with the user.

[0209] In implementation method E3, for the first submatrix among multiple submatrixes, where the first submatrix is ​​any one of the multiple submatrixes, if the first submatrix is ​​a diagonal block, the first submatrix is ​​determined to correspond to a fourth storage format; if the first submatrix is ​​a non-diagonal block, the first submatrix is ​​determined to correspond to a fifth storage format.

[0210] In one possible implementation, the fourth storage format is CSR format and the fifth storage format is COO format.

[0211] In the above-described embodiment E3, since the number of non-zero elements included in the diagonal block is relatively large, the computing device can determine the CSR format corresponding to the first submatrix when the first submatrix is ​​a diagonal block. The array used to record row offset values ​​corresponding to the CSR format is determined based on the number of rows in the first submatrix, and is not affected by the number of non-zero elements in the first submatrix. Therefore, when the number of non-zero elements in the first submatrix is ​​relatively large, storing the first submatrix in the CSR format helps to save memory costs in memory, thereby improving the cache hit rate of the first submatrix.

[0212] In the above-described embodiment E3, since the number of non-zero elements included in the off-diagonal block is relatively small, when the first submatrix is ​​an off-diagonal block, the computing device can use the COO format corresponding to the first submatrix. The array used to record row and column numbers corresponding to the COO format is determined based on the number of non-zero elements in the first submatrix. Therefore, when there are few non-zero elements in the first submatrix, storing the first submatrix in the COO format helps to save memory costs in memory, thereby improving the cache hit rate of the first submatrix.

[0213] Furthermore, implementation E3 determines the target storage format of the first submatrix directly based on whether the first submatrix is ​​a diagonal block, rather than based on the number of non-zero elements in the first submatrix. This avoids counting the number of non-zero elements in the first submatrix and facilitates the rapid determination of the target storage format of the first submatrix.

[0214] Implementation method E4 includes, for example: Figure 9 The following steps are shown.

[0215] S901, the computing device determines at least one first access number based on multiple sub-matrices.

[0216] In the above S901, the computing device can, as shown in... Figure 10 The steps shown determine at least one first access number based on multiple submatrices.

[0217] S1001, the computing device determines at least one candidate storage format corresponding to each of the plurality of submatrices.

[0218] In the embodiments of this application, candidate storage formats may include COO format, CSR format, CSC format, Ellpack format, Sliced-Ellpack format, etc.

[0219] S1002, the computing device determines at least one combination method based on at least one candidate storage format corresponding to each submatrix, wherein each combination method includes a candidate storage format corresponding to multiple submatrixes.

[0220] In the embodiments of this application, since each submatrix can select any candidate storage format, the computing device can combine at least one candidate storage format corresponding to each submatrix to obtain at least one combination method.

[0221] For example, the first matrix is ​​split into two sub-matrices, sub-matrices 1 and 2. Sub-matrices 1 correspond to five candidate storage formats: COO, CSR, CSC, Ellpack, and Sliced-Ellpack. Sub-matrices 2 also correspond to five candidate storage formats: COO, CSR, CSC, Ellpack, and Sliced-Ellpack. Based on these five candidate storage formats for sub-matrices 1 and 2, the computing device can determine 5*5 possible combinations.

[0222] S1003, the computing device determines the first access count corresponding to at least one combination method.

[0223] In the embodiments of this application, when the submatrix corresponds to different candidate storage formats, the number of times the first matrix is ​​accessed is also different, that is, the number of first accesses is different.

[0224] One possible implementation is that the first access count can be determined as follows: the computing device determines the arrays corresponding to each submatrix to represent the submatrix, and the sum of the lengths of the arrays corresponding to each submatrix is ​​taken as the first access count.

[0225] Optionally, the computing device can also determine the second access count corresponding to at least one combination. When the submatrix corresponds to different candidate storage formats, the access count of the iteration direction p during the iteration process is also different, that is, the second access count is different.

[0226] One possible implementation is that the second access count can be determined as follows: the computing device determines the arrays corresponding to each submatrix for representing the column numbers of the elements in the submatrix, and the sum of the lengths of the arrays corresponding to each submatrix for representing the column numbers of the elements in the submatrix is ​​taken as the second access count.

[0227] For example, the first matrix is ​​split into two sub-matrices, sub-matrices 1 and 2. Sub-matrices 1 correspond to five candidate storage formats: COO, CSR, CSC, Ellpack, and Sliced-Ellpack. Sub-matrices 2 also correspond to five candidate storage formats: COO, CSR, CSC, Ellpack, and Sliced-Ellpack. Based on these five candidate storage formats for sub-matrices 1 and 2, the computing device can determine 5*5 possible combinations.

[0228] Taking the combination of submatrix 1 corresponding to CSR format and submatrix 2 corresponding to CSC format as an example, submatrix 1 and its corresponding CSR format can be seen in Figure 1(a), and submatrix 2 and its corresponding CSC format can be seen in Figure 1(b). Submatrix 1 is represented by 3 arrays, and the sum of the lengths of the arrays corresponding to submatrix 1 is 21 (i.e., 5+8+8). Submatrix 2 is represented by 3 arrays, and the sum of the lengths of the arrays corresponding to submatrix 2 is 21 (i.e., 5+8+8). Therefore, the first access count for this combination of submatrix 1 corresponding to CSR format and submatrix 2 corresponding to CSC format is 42 (i.e., 21+21). The length of the array used to represent the element column number in submatrix 1 is 8, and the length of the array used to represent the element column number in submatrix 2 is 8. Therefore, the second access count for this combination of submatrix 1 corresponding to CSR format and submatrix 2 corresponding to CSC format is 16 (8+8).

[0229] pass Figure 10 The steps shown enable the computing device to quickly and accurately determine at least one first access count.

[0230] S902, the computing device determines the target storage format corresponding to the multiple sub-matrices based on at least one first access number.

[0231] In one possible implementation, the computing device can select the combination corresponding to the smallest first access count from at least one first access count as the target storage format corresponding to the multiple submatrices respectively.

[0232] In one possible implementation, the computing device can select the combination corresponding to the smallest second access count from at least one second access count as the target storage format corresponding to the multiple submatrices respectively.

[0233] In one possible implementation, the computing device can add at least one first access count and at least one second access count to obtain at least one total access count. Then, the computing device can select the combination with the smallest total access count from the at least one total access count as the target storage format corresponding to the multiple sub-matrices respectively.

[0234] In the above-described implementation E4, the computing device determines the target storage format corresponding to each of the multiple sub-matrices based on the first access count. The determined target storage format corresponding to each of the multiple sub-matrices helps to reduce the first access count, thereby improving the cache hit rate of the sub-matrices in the cache.

[0235] It should be understood that in any of the above embodiments E1, E2, E3 or E4, the target storage format corresponding to each submatrix can be determined by the processor 301 in the computing device 300. In order to speed up the execution efficiency, the target storage format of each corresponding submatrix can also be determined by P processes respectively, which is not limited here.

[0236] S403, the computing device processes the first task according to the multiple sub-matrices and the target storage format corresponding to the multiple sub-matrices, and obtains the processing result corresponding to the first task.

[0237] In the above S403, the computing device can, as shown in... Figure 11 The following steps are shown to obtain the processing result corresponding to the first task.

[0238] S1101, the computing device converts the initial storage format of the multiple sub-matrices in memory to their respective target storage formats according to the target storage formats corresponding to the multiple sub-matrices.

[0239] In one possible implementation, the multiple submatrices include a first submatric, which is any one of the multiple submatrices. The computing device can perform the following steps on the first submatric: the computing device generates a first position record and a first element record of the target storage format corresponding to the first submatric based on the first submatric and the target storage format corresponding to the first submatric. The first position record is used to record the position of the element in the first submatric, and the first element record is used to record the value of the element in the first submatric.

[0240] For example, the first submatrix can be referenced from the matrix shown in Figure 1(a). The computing device reads the first submatrix into memory. Since the original storage format of the first submatrix is ​​CSR format, the computing device reads the three arrays corresponding to the first submatrix (i.e., the array for recording row offset values, the array for recording column numbers, and the array for recording element values) into memory. If the computing device determines that the target storage format corresponding to the first submatrix is ​​CSC format, as shown in Figure 1(b), then the computing device generates the first position record and the first element record in CSC format corresponding to the first submatrix. The first position record includes an array for recording row offset values ​​and an array for recording column numbers, and the first element record includes an array for recording the values ​​of the elements.

[0241] S1102, the computing device processes the first task based on multiple sub-matrices converted to the target storage format, and obtains the processing result corresponding to the first task.

[0242] In one possible implementation, the computing device can process the sparse linear equation system solution task in the first task based on multiple sub-matrices converted to the target storage format and the right-hand side terms, and obtain the solution result.

[0243] In one possible implementation, the multiple submatrices include a first submatrice, which is any one of the multiple submatrices. The computing device can obtain the processing result corresponding to the first task in the following way: the computing device processes the sparse linear equation system solution task in the first task according to the first position record, the first element record, and the right-hand side of the first submatric, and obtains the solution result.

[0244] It should be understood that S1102 can be executed by the processor 301 in the computing device 300; to speed up the execution efficiency, it can also be executed by P processes in the processor 301; to further speed up the execution efficiency, it can also be executed by the matrix operation unit 306 in the computing device 300, which is not limited here.

[0245] Figure 11 A specific method for handling the first task is provided.

[0246] exist Figure 4In the steps shown, the computing device does not directly process the first task using the first matrix in its original storage format. Instead, it splits the first matrix into multiple sub-matrices and determines the target storage format for each sub-matrix based on its element distribution structure. Since the target storage format for each sub-matrix is ​​the optimal storage format determined by fully considering its element distribution structure, using the target storage format helps save memory overhead. When the computing device processes the first task using sub-matrices in the target storage format, the smaller memory space occupied by these sub-matrices improves the cache hit rate, thereby increasing the processing efficiency of the first task.

[0247] Optionally, after the computing device finishes processing the first task, it can also acquire a second task. Figure 12 This is a flowchart illustrating the data processing method provided in the embodiments of this application. Figure 12 The data processing method shown is used to perform the second task.

[0248] S1201, the computing device reads the second task into memory.

[0249] In this embodiment, the second task can be solving a sparse linear system of equations A'x = b'. The second task includes a second matrix A' and a right-hand side b', wherein the second matrix A' has the same size as the first matrix A, both being m×n sparse matrices, and the right-hand side b' in the second task has the same size as the right-hand side b' in the first task, both being m×1 vectors. The second task is used to determine the vector x to be solved using an iterative method based on the second matrix A' and the right-hand side b'.

[0250] In this embodiment, the second matrix A' can be stored in memory in an initial format, such as COO, CSR, CSC, Ellpack, Sliced-Ellpack, etc., which is not limited here. The initial storage format of the second matrix A' and the first matrix A can be the same or different, which is not limited here.

[0251] Furthermore, the second matrix A' has the same element distribution structure as the first matrix A, meaning that elements exist at the same positions in both the second matrix A' and the first matrix A. However, the values ​​of the elements at the same positions in the second matrix A' and the first matrix A are different.

[0252] For example, the first matrix A is as follows:

[0253] 1 0 0 2 3 0 0 4 5 0 0 6 7 0 0 8

[0254] The second matrix A' is as follows:

[0255] 2 0 0 2 4 0 0 4 6 0 0 6 8 0 0 8

[0256] As can be seen from the examples of the first matrix A and the second matrix A' above, the element distribution structure of the first matrix A and the second matrix A' is the same, that is, A in the first matrix A 11 A 14 A 21 A 24 A 31 A 34 A 41 A 44 With the second matrix A', A' 11 A' 14 A' 21 A' 24 A' 31 A' 34 A' 41 A' 44 Both contain elements, but at the same position A 11 With A' 11 The elements have different values, and the same position A 21 With A' 21 The elements have different values, and the same position A 31 With A' 31 The elements have different values, and the same position A 41 With A' 41 The values ​​of the elements are different.

[0257] S1202, the computing device splits the second matrix to obtain multiple sub-matrices in the second matrix.

[0258] In this embodiment of the application, since the element distribution structure of the second matrix A' is the same as that of the first matrix A, the splitting method of the second matrix is ​​the same as that of the first matrix, and there is no need to calculate how to split the second matrix into multiple sub-matrices.

[0259] The multiple submatrices in the second matrix obtained through S1202 correspond one-to-one with the multiple submatrices in the first matrix. Specifically, the multiple submatrices in the first matrix include the first submatrices, and the multiple submatrices in the second matrix include the second submatrices. When the first submatrices and the second submatrices correspond, the row numbers of the first submatrices in the first matrix are the same as the row numbers of the second submatrices in the second matrix, the column numbers of the first submatrices in the first matrix are the same as the column numbers of the second submatrices in the second matrix, and the element distribution structures of the first submatrices and the second submatrices are the same.

[0260] S1203, the computing device converts the initial storage format of the multiple sub-matrices in the second matrix in memory to their respective target storage formats according to the target storage formats corresponding to the multiple sub-matrices in the first matrix.

[0261] In this embodiment of the application, since the element distribution structure of the second matrix A' is the same as that of the first matrix A, the target storage format of the multiple sub-matrices in the second matrix corresponds to the target storage format of the multiple sub-matrices in the first matrix, and it is not necessary to determine the target storage format of the multiple sub-matrices in the second matrix by calculation.

[0262] In S1203 above, the first matrix includes a plurality of submatrices comprising a first submatrix, and the second matrix includes a plurality of submatrices comprising a second submatrix, wherein the first submatrix corresponds to the second submatrix, and the computing device can, as shown in the example... Figure 13 The steps shown convert the initial storage format of the second submatrix in memory to the target storage format corresponding to the second submatrix.

[0263] S1301, the computing device determines the first position record corresponding to the first submatrix as the second position record corresponding to the second submatrix.

[0264] In this embodiment of the application, the second position record is used to record the position of the element in the second submatrix. The second position record does not need to be generated, and the computing device can directly use the first position record as the second position record.

[0265] S1302, the computing device updates the first element record corresponding to the first submatrix using the elements in the second submatrix, and obtains the second element record corresponding to the second submatrix.

[0266] In this embodiment of the application, the second element record is used to record the numerical values ​​of the elements in the second submatrix.

[0267] exist Figure 13 In the steps shown, the computing device can directly use the first position record as the second position record without generating the second position record. Furthermore, the computing device only needs to generate the second element record, which can effectively improve the efficiency of converting the second submatrix to the corresponding target storage format.

[0268] S1204, the computing device processes the second task based on multiple sub-matrices in the second matrix converted to the target storage format, and obtains the processing result corresponding to the second task.

[0269] In one possible implementation, the computing device can process the sparse linear equation system solution task in the second task based on multiple sub-matrices in the second matrix converted to the target storage format and the right-hand side terms in the second task, and obtain the solution result.

[0270] In one possible implementation, the second matrix includes multiple submatrices, and the computing device can obtain the processing result corresponding to the second task in the following way: the computing device processes the sparse linear equation system solution task in the second task based on the second position record and second element record corresponding to the second submatrix and the right-hand side term in the second task, and obtains the solution result.

[0271] exist Figure 12 In the steps shown, the computing device splits the second matrix according to the splitting method of the first matrix, without needing to calculate how to split the second matrix into multiple sub-matrices. In addition, the computing device converts the initial storage format of the multiple sub-matrices in the second matrix in memory to their respective target storage formats according to the target storage formats corresponding to the multiple sub-matrices in the first matrix. Without needing to calculate to determine the target storage format of the multiple sub-matrices in the second matrix, it is beneficial to improve the efficiency of converting the second sub-matrices to the corresponding target storage formats, thereby improving the processing efficiency of the second task.

[0272] Based on the above embodiments, this application also provides a data processing apparatus, which is used in... Figure 3 The computing device shown is used to implement Figure 4 The illustrated embodiment provides a data processing method. See also... Figure 14 As shown, the data processing device includes: a reading module 1401, a splitting module 1402, a determining module 1403, and a processing module 1404. Wherein:

[0273] The reading module 1401 is used to read the first task into memory. The first task includes a first matrix, which is a sparse matrix and is in the initial storage format in memory.

[0274] The splitting module 1402 is used to split the first matrix into multiple sub-matrices;

[0275] The determination module 1403 is used to determine the target storage format corresponding to each of the multiple sub-matrices; the target storage format is determined based on the element distribution structure of the sub-matrices.

[0276] The processing module 1404 is used to process the first task according to the multiple sub-matrices and the target storage format corresponding to the multiple sub-matrices, and obtain the processing result corresponding to the first task.

[0277] In one possible implementation, the splitting module 1402 is specifically used to: determine the number P of processes handling the first task; P is an integer greater than 0; split the first matrix into rows according to the number of processes P to obtain P reference matrices; and split the P reference matrices into rows and / or columns respectively to obtain multiple sub-matrices.

[0278] In one possible implementation, multiple submatrices include a first submatrix; the determining module 1403 is specifically used to: determine the target storage format corresponding to the first submatrix based on the number of non-zero elements in the first submatrix.

[0279] In one possible implementation, the target storage format includes at least a first storage format, a second storage format, and a third storage format; the determining module 1403 is specifically used to: determine the first storage format corresponding to the first submatrix when the number of non-zero elements in the first submatrix is ​​less than or equal to the number of rows in the first submatrix; or, determine the second storage format corresponding to the first submatrix when the number of non-zero elements in the first submatrix is ​​greater than the number of rows in the first submatrix, and there are multiple row vectors or column vectors with the same number of non-zero elements in the first submatrix; or, determine the third storage format corresponding to the first submatrix when the number of non-zero elements in the first submatrix is ​​greater than the number of rows in the first submatrix, and there are no multiple row vectors or column vectors with the same number of non-zero elements in the first submatrix.

[0280] In one possible implementation, the second storage format includes at least an elliptical format and a sliced ​​elliptical format; the determining module 1403 is specifically used to: determine the elliptical format corresponding to the first submatrix when the number of non-zero elements in the first submatrix is ​​greater than the number of rows in the first submatrix, and the number of non-zero elements corresponding to row vectors or column vectors including non-zero elements in the first submatrix is ​​the same; or, determine the sliced ​​elliptical format corresponding to the first submatrix when the number of non-zero elements in the first submatrix is ​​greater than the number of rows in the first submatrix, and the number of non-zero elements corresponding to multiple consecutive row vectors or column vectors in the first submatrix is ​​the same.

[0281] In one possible implementation, the multiple submatrices include a first submatric; the target storage format includes at least a fourth storage format and a fifth storage format; the determining module 1403 is specifically used to: determine the fourth storage format corresponding to the first submatric when the first submatric is a diagonal block; and determine the fifth storage format corresponding to the first submatric when the first submatric is a non-diagonal block.

[0282] In one possible implementation, the determining module 1403 is specifically used to: determine at least one first access count based on multiple submatrices, wherein the first access count is the access count of the first matrix; and determine the target storage format corresponding to each of the multiple submatrices based on at least one first access count.

[0283] In one possible implementation, the processing module 1404 is specifically used to: convert the initial storage format of the multiple sub-matrices in memory to their respective target storage formats according to the target storage formats corresponding to the multiple sub-matrices; and process the first task according to the multiple sub-matrices converted to the target storage formats to obtain the processing result corresponding to the first task.

[0284] In one possible implementation, the multiple submatrices include a first submatric; the processing module 1404 is specifically used to: generate a first position record and a first element record of the target storage format corresponding to the first submatric based on the first submatric and the target storage format corresponding to the first submatric, wherein the first position record is used to record the position of the element in the first submatric and the first element record is used to record the value of the element in the first submatric; the processing module 1404 is specifically used to: process the first task based on the first position record and the first element record to obtain the processing result corresponding to the first task.

[0285] In one possible implementation, the reading module 1401 is also used to read the second task into memory. The second task includes a second matrix, which is a sparse matrix. The second matrix is ​​in an initial storage format in memory, and the element distribution structure of the second matrix is ​​the same as that of the first matrix.

[0286] The processing module 1404 is further configured to split the second matrix to obtain multiple sub-matrices in the second matrix; the splitting method of the second matrix is ​​the same as that of the first matrix; according to the target storage format corresponding to the multiple sub-matrices in the first matrix, the initial storage format of the multiple sub-matrices in the second matrix in memory is converted to their respective target storage formats; the target storage formats of the multiple sub-matrices in the second matrix correspond to the target storage formats of the multiple sub-matrices in the first matrix; based on the multiple sub-matrices in the second matrix converted to the target storage formats, the second task is processed to obtain the processing result corresponding to the second task.

[0287] In one possible implementation, the first matrix includes multiple submatrices, and the second matrix includes multiple submatrices, each including a second submatric; the first submatrices correspond to the second submatrices; the processing module 1404 is specifically used to: determine the first position record corresponding to the first submatric as the second position record corresponding to the second submatric; the second position record is used to record the position of the element in the second submatric; update the first element record corresponding to the first submatric with the element in the second submatric to obtain the second element record corresponding to the second submatric, the second element record being used to record the value of the element in the second submatric;

[0288] The processing module 1404 is specifically used to: process the second task based on the second position record and the second element record, and obtain the processing result corresponding to the second task.

[0289] In this embodiment, the reading module, splitting module, determining module, and processing module can all be implemented in software or in hardware. For example, the implementation of the reading module will be described below. Similarly, the implementation of the splitting module, determining module, and processing module can refer to the implementation of the reading module.

[0290] As an example of a software functional unit, a reading module may include code running on a computing instance. A computing instance may include at least one of a physical host (computing device), a virtual machine, or a container. Furthermore, the aforementioned computing instance may be one or more. For example, a reading module may include code running on multiple hosts / virtual machines / containers. It should be noted that the multiple hosts / virtual machines / containers used to run the code may be distributed within the same region or in different regions. Further, the multiple hosts / virtual machines / containers used to run the code may be distributed within the same availability zone (AZ) or in different AZs, each AZ comprising one or more geographically proximate data centers. Typically, a region may include multiple AZs.

[0291] Similarly, multiple hosts / virtual machines / containers used to run this code can be distributed within the same Virtual Private Cloud (VPC) or across multiple VPCs. Typically, a VPC is set up within a region. Communication between two VPCs within the same region, as well as between VPCs in different regions, requires a communication gateway to be set up within each VPC to enable interconnection between VPCs.

[0292] As an example of a hardware functional unit, a reading module may include at least one computing device, such as a server. Alternatively, a reading module may also be a device implemented using an application-specific integrated circuit (ASIC) or a programmable logic device (PLD). The aforementioned PLD may be implemented using a complex programmable logical device (CPLD), a field-programmable gate array (FPGA), generic array logic (GAL), or any combination thereof.

[0293] The multiple computing devices included in the read module can be distributed within the same region or in different regions. Similarly, the multiple computing devices included in the read module can be distributed within the same Availability Zone (AZ) or in different AZs. Likewise, the multiple computing devices included in the read module can be distributed within the same Virtual Private Cloud (VPC) or multiple VPCs. These multiple computing devices can be any combination of computing devices such as servers, ASICs, PLDs, CPLDs, FPGAs, and GALs.

[0294] It should be noted that, in other embodiments, the reading module is used to read the first task into memory. The first task includes a first matrix, which is a sparse matrix, and the first matrix is ​​stored in memory in an initial format. The splitting module is used to split the first matrix into multiple sub-matrices. The determining module is used to determine the target storage format corresponding to each of the multiple sub-matrices. The target storage format is determined based on the element distribution structure of the sub-matrices. The processing module is used to process the first task based on the multiple sub-matrices and the target storage formats corresponding to the multiple sub-matrices, and obtain the processing result corresponding to the first task.

[0295] The steps implemented by the reading module, splitting module, determining module, and processing module can be specified as needed. By implementing different steps in the data processing method through the reading module, splitting module, determining module, and processing module, the full functionality of the data processing device can be achieved.

[0296] This application also provides a computing device, which includes a processor and a memory, wherein the memory stores computer-executable instructions; the processor is used to execute the computer-executable instructions stored in the memory, and the processor can execute data processing methods.

[0297] This application also provides a computer program product containing instructions. The computer program product may be a software or program product containing instructions, capable of running on a computing system or stored on any usable medium. When the computer program product is run on at least one computing system, it causes the at least one computing system to perform a data processing method.

[0298] This application also provides a computer-readable storage medium. The computer-readable storage medium can be any available medium that a computing system can store, or a data storage device such as a data center containing one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state drive). The computer-readable storage medium includes instructions that instruct the computing system to perform a data processing method.

[0299] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the protection scope of the technical solutions of the embodiments of the present invention.

[0300] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0301] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more blocks of the flowchart illustrations and / or one or more blocks of the block diagrams.

[0302] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams.

[0303] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.

[0304] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A data processing method, characterized in that, include: The first task is read into memory. The first task includes a first matrix, which is a sparse matrix and is stored in memory in its initial format. The first matrix is ​​split into multiple sub-matrices, and the target storage format corresponding to each of the multiple sub-matrices is determined; The target storage format is determined based on the element distribution structure of the submatrix; The first task is processed according to the plurality of sub-matrices and the target storage format corresponding to the plurality of sub-matrices, and the processing result corresponding to the first task is obtained.

2. The method as described in claim 1, characterized in that, The step of splitting the first matrix into multiple sub-matrices includes: Determine the number P of processes to handle the first task; P is an integer greater than 0. Based on the number of processes P, the first matrix is ​​row-splitted to obtain P reference matrices; The P reference matrices are split into rows and / or columns respectively to obtain the multiple sub-matrices.

3. The method as described in any one of claims 1-2, characterized in that, The plurality of submatrices includes the first submatrix; Determining the target storage format corresponding to each of the plurality of sub-matrices includes: The target storage format corresponding to the first submatrix is ​​determined based on the number of non-zero elements in the first submatrix.

4. The method as described in claim 3, characterized in that, The target storage format includes at least a first storage format, a second storage format, and a third storage format; The step of determining the target storage format corresponding to the first submatrix based on the number of non-zero elements in the first submatrix includes: If the number of non-zero elements in the first submatrix is ​​less than or equal to the number of rows in the first submatrix, then the first submatrix corresponds to the first storage format; or... If the number of non-zero elements in the first submatrix is ​​greater than the number of rows in the first submatrix, and there are multiple row vectors or column vectors with the same number of non-zero elements in the first submatrix, then the first submatrix corresponds to the second storage format; the number of non-zero elements is greater than 0; or... If the number of non-zero elements in the first submatrix is ​​greater than the number of rows in the first submatrix, and there are no multiple row vectors and column vectors with the same number of non-zero elements in the first submatrix, then the first submatrix is ​​determined to correspond to the third storage format.

5. The method as described in claim 4, characterized in that, The second storage format includes at least elliptic format and sliced ​​elliptic format; The step of determining the second storage format corresponding to the first submatrix when the number of non-zero elements in the first submatrix is ​​greater than the number of rows in the first submatrix, and when there are multiple row vectors or column vectors with the same number of non-zero elements in the first submatrix, includes: If the number of non-zero elements in the first submatrix is ​​greater than the number of rows in the first submatrix, and the number of non-zero elements in the row vectors or column vectors of the first submatrix that include non-zero elements is the same, then the first submatrix is ​​determined to correspond to the elliptic format; or, If the number of non-zero elements in the first submatrix is ​​greater than the number of rows in the first submatrix, and there are multiple consecutive row vectors or column vectors in the first submatrix with the same number of non-zero elements, then the first submatrix is ​​determined to correspond to the slice ellipse format.

6. The method according to any one of claims 1-2, characterized in that, The plurality of submatrices includes a first submatrix; the target storage format includes at least a fourth storage format and a fifth storage format; Determining the target storage format corresponding to each of the plurality of sub-matrices includes: When the first submatrix is ​​a diagonal block, the first submatrix is ​​determined to correspond to the fourth storage format; If the first submatrix is ​​a non-diagonal block, then the first submatrix is ​​determined to correspond to the fifth storage format.

7. The method as described in any one of claims 1-2, characterized in that, Determining the target storage format corresponding to each of the plurality of sub-matrices includes: Based on the plurality of submatrices, at least one first access count is determined, wherein the first access count is the access count of the first matrix; Based on the at least one first access count, the target storage format corresponding to each of the plurality of sub-matrices is determined.

8. The method according to any one of claims 1-7, characterized in that, The step of processing the first task according to the plurality of sub-matrices and the target storage format corresponding to the plurality of sub-matrices respectively, and obtaining the processing result corresponding to the first task, includes: Based on the target storage format corresponding to each of the multiple sub-matrices, the initial storage format of each of the multiple sub-matrices in the memory is converted to their respective target storage formats. Based on multiple sub-matrices converted to the target storage format, the first task is processed to obtain the processing result corresponding to the first task.

9. The method as described in claim 8, characterized in that, The plurality of submatrices includes the first submatrix; The step of converting the initial storage format of the multiple sub-matrices in memory to their respective target storage formats according to the target storage formats corresponding to the multiple sub-matrices includes: Based on the first submatrix and the target storage format corresponding to the first submatrix, a first position record and a first element record of the target storage format corresponding to the first submatrix are generated. The first position record is used to record the position of the element in the first submatrix, and the first element record is used to record the value of the element in the first submatrix. The step of processing the first task based on multiple sub-matrices converted to the target storage format to obtain the processing result corresponding to the first task includes: Based on the first position record and the first element record, the first task is processed to obtain the processing result corresponding to the first task.

10. The method according to any one of claims 1-9, characterized in that, Also includes: The second task is read into memory. The second task includes a second matrix, which is a sparse matrix. The second matrix is ​​stored in memory in the initial storage format. The element distribution structure of the second matrix is ​​the same as that of the first matrix. The second matrix is ​​split to obtain multiple sub-matrices; The second matrix is ​​split in the same way as the first matrix; Based on the target storage formats corresponding to the multiple sub-matrices in the first matrix, the initial storage format of the multiple sub-matrices in the second matrix in the memory is converted to their respective target storage formats. The target storage format of multiple submatrices in the second matrix corresponds to the target storage format of multiple submatrices in the first matrix; The second task is processed based on multiple sub-matrices in the second matrix converted to the target storage format to obtain the processing result corresponding to the second task.

11. The method as described in claim 10, characterized in that, The first matrix includes a first submatrix among its multiple submatrixes, and the second matrix includes a second submatrix among its multiple submatrixes; the first submatrix corresponds to the second submatrix. The step of converting the initial storage format of the multiple sub-matrices in the second matrix in memory to their respective target storage formats according to the target storage formats corresponding to the multiple sub-matrices in the first matrix includes: The first position record corresponding to the first submatrix is ​​determined as the second position record corresponding to the second submatrix; the second position record is used to record the position of the element in the second submatrix. The first element record corresponding to the first submatrix is ​​updated using the elements in the second submatrix to obtain the second element record corresponding to the second submatrix. The second element record is used to record the value of the element in the second submatrix. The step of processing the second task based on multiple sub-matrices in the second matrix converted to the target storage format to obtain the processing result corresponding to the second task includes: Based on the second position record and the second element record, the second task is processed to obtain the processing result corresponding to the second task.

12. A data processing apparatus, characterized in that, include: The reading module is used to read the first task into memory. The first task includes a first matrix, which is a sparse matrix and is in an initial storage format in memory. A splitting module is used to split the first matrix into multiple sub-matrices; A determining module is used to determine the target storage format corresponding to the plurality of sub-matrices respectively; The target storage format is determined based on the element distribution structure of the submatrix; The processing module is used to process the first task according to the plurality of sub-matrices and the target storage format corresponding to the plurality of sub-matrices respectively, and obtain the processing result corresponding to the first task.

13. A computing device, characterized in that, The device includes a processor and a memory; the memory stores computer-executable instructions; the processor executes the computer-executable instructions stored in the memory to cause the computing device to perform the method as described in any one of claims 1-11.

14. A computer program product containing instructions, characterized in that, When the instruction is executed by the computing system, it causes the computing system to perform the method as described in any one of claims 1-11.

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