Configurable neuron circuit and control method
By designing configurable neuron circuits and utilizing pattern selection modules and circuit reuse techniques, the problems of complex and large-area structures in existing neuron circuits are solved, and simplified circuit structures and complex behavioral patterns that support multiple neuron models are realized.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-26
- Publication Date
- 2026-03-27
AI Technical Summary
Most existing neuron circuits only support a single neuron model or involve stacking multiple models, resulting in complex structures and large footprints.
Design a configurable neuron circuit that includes a mode selection module, a calculation module, a comparison module, and a pulse generation module. Switch between two neuron models can be achieved through circuit reuse, simplifying the circuit structure.
It enables support for two neuron models with a lower circuit area, simplifies the circuit structure, and allows for more complex behavioral patterns.
Smart Images
Figure CN121745178A_ABST
Abstract
Description
[Technical Field]
[0001] This invention relates to the field of neuronal circuit technology, and in particular to a configurable neuronal circuit and control method. [Background Technology]
[0002] Inspired by the biological brain, spiking neural networks (SNNs) are third-generation neural network models. Compared to traditional artificial neural networks and convolutional neural networks, SNNs use discrete pulse signals to transmit information, thus better mimicking the workings of biological nervous systems, which contributes to brain science research. Because of the sparsity of pulses in SNNs, and the fact that the network only responds when a pulse occurs, they can effectively reduce power consumption compared to traditional neural networks. Furthermore, due to the independent activity of neurons within the network, the computational nature of SNNs is naturally suited for parallel computing.
[0003] Dedicated neural network acceleration circuits can effectively leverage the low power consumption and high parallelism advantages of spiking neural networks. The neuron computation circuit, as a crucial component, is responsible for mimicking neuron behavior, updating membrane potentials, and generating corresponding pulses within the acceleration circuit. Currently, there are various neuron models with computational complexity, ranging from simple to complex, including LIF neurons, Izhikevich neurons, and HH neurons. However, most existing dedicated neuron circuit designs can only support one neuron model. Some neuron circuits that support two models are constructed by stacking different neuron circuits, resulting in complex structures and large footprints. [Summary of the Invention]
[0004] This invention provides a configurable neuron circuit and control method, aiming to solve the technical problems in related technologies, such as the complex structure and large area occupied by neuron circuits that only support a single neuron model or support two neuron models.
[0005] In a first aspect, embodiments of the present invention provide a configurable neuron circuit, comprising:
[0006] The mode selection module selects the corresponding target working mode based on the received neuron configuration signal, wherein the target working mode includes LIF working mode or Izhikevich working mode.
[0007] The calculation module, connected to the mode selection module, is used to update the membrane potential according to the target working mode selected by the mode selection module and the received pulse information of the presynaptic neuron, and obtain the membrane potential update result.
[0008] A comparison module, connected to the calculation module, is used to compare the membrane potential update result with a preset threshold and determine whether the current neuron will generate a pulse based on the comparison result;
[0009] The pulse generation module, connected to the comparison module, is used to generate a pulse signal and an AER encoding packet when the comparison module determines that the current neuron will generate a pulse, and output updated membrane potential information.
[0010] In one embodiment, optionally, the computing module includes a first computing unit, a second computing unit, a third computing unit, and a fourth computing unit, each computing unit including: a control subunit, a data allocation subunit, and a computing subunit;
[0011] The control subunit is used to generate a first clock pulse signal of a first preset period length based on the received pulse information of the presynaptic neuron and the target working mode, so as to control the data allocation subunit and the calculation subunit.
[0012] The data allocation subunit is connected to the control subunit and the computing subunit, and is used to allocate corresponding computing tasks to the computing subunit.
[0013] The calculation subunit is connected to the control subunit and the data allocation subunit, and is used to perform data calculation and membrane potential accumulation to obtain the corresponding membrane potential update result.
[0014] In one embodiment, optionally, when the target operating mode is LIF operating mode, the data allocation subunits and calculation subunits corresponding to the first computing unit, second computing unit, third computing unit, and fourth computing unit have the same function, and each data allocation subunit is used for:
[0015] Assign prominent weight values, membrane potential leakage values, and membrane potential information from the previous time step to the calculation subunit, and assign calculation tasks to calculate the membrane potential information for the current time step.
[0016] Each computational subunit is used for:
[0017] Calculate the membrane potential information for the current time step based on the computational task;
[0018] Update the membrane potential information at the current time step to obtain the corresponding membrane potential update result.
[0019] In one embodiment, optionally, when the target working mode is the Izhikevich working mode, the data allocation subunit and the computing subunit corresponding to the first computing unit, the second computing unit, the third computing unit and the fourth computing unit have different functions;
[0020] The first allocation subunit corresponding to the first calculation unit is used for:
[0021] Assign synaptic weight values, membrane potential information from the previous time step, first intermediate calculation result, second calculation result, and third calculation result to the first calculation subunit corresponding to the first calculation unit, and assign a first calculation task to calculate the membrane potential information of the current time step.
[0022] The second allocation subunit corresponding to the second calculation unit is used for:
[0023] Assign the membrane potential information of the previous time step and the second intermediate calculation result to the second calculation subunit corresponding to the second calculation unit, and assign the second calculation task to calculate the second calculation result;
[0024] The third allocation subunit corresponding to the third calculation unit is used for:
[0025] Assign the membrane potential information of the previous time step, the membrane recovery variable of the previous time step, and the third intermediate calculation result to the third calculation subunit corresponding to the third calculation unit, and assign the third calculation task to calculate the third calculation result;
[0026] The fourth allocation subunit corresponding to the fourth calculation unit is used for:
[0027] Assign the membrane potential information of the previous time step, the membrane recovery variable of the previous time step, and the fourth intermediate calculation result to the fourth calculation unit corresponding to the fourth calculation unit, and assign the fourth calculation task to calculate the membrane recovery variable of the current time step.
[0028] In one embodiment, optionally, when the target operating mode is the Izhikevich operating mode, the first computing subunit is used to:
[0029] The first intermediate calculation result and the membrane potential information at the current time step are calculated based on the first calculation task.
[0030] The second calculation subunit is used for:
[0031] Calculate the second intermediate calculation result and the second calculation result according to the second calculation task;
[0032] The third computing subunit is used for:
[0033] Calculate the third intermediate calculation result and the third calculation result based on the third calculation task;
[0034] The fourth calculation subunit is used for:
[0035] The fourth intermediate calculation result and the membrane recovery variable at the current time step are calculated based on the fourth calculation task.
[0036] In one embodiment, optionally, it also includes: an arbitration circuit;
[0037] When the target operating mode is LIF operating mode, the arbitration circuit is used for:
[0038] Arbitrate the corresponding membrane potential update results obtained from each calculation subunit and sort them according to the receiving order of each membrane potential update result;
[0039] Based on the sorting results, the update results of each membrane potential are compared with the preset threshold in sequence.
[0040] When the target operating mode is the Izhikevich operating mode, the arbitration circuit is used for:
[0041] The first calculation unit is controlled to compare the update results of each membrane potential with the preset threshold.
[0042] In one embodiment, optionally, the comparison module includes: a control unit, a first register, and a comparison unit;
[0043] The control unit is connected to the arbitration circuit and is used to generate a second clock pulse signal with a second preset period length based on the received membrane potential update result, so as to control the comparison unit and the pulse generation module.
[0044] The first register, connected to the arbitration circuit, is used to store the received membrane potential update result;
[0045] The comparison unit is connected to the register and is used to compare the membrane potential update result in the register with a preset threshold to obtain a comparison result.
[0046] In one embodiment, optionally, the pulse generation module includes: a second register area;
[0047] The second register is used for:
[0048] When it is determined that the current neuron will generate a pulse, obtain the address of the source neuron and the address of the destination neuron;
[0049] Based on the source neuron address and the target neuron address, a pulse signal and an AER encoded packet are generated, and the updated membrane potential information is output.
[0050] In one embodiment, optionally, the mode selection module is specifically used for:
[0051] When the received neuron configuration signal is at the first level, the corresponding target working mode is selected as the LIF working mode;
[0052] When the received neuron configuration signal is at the second level, the corresponding target working mode is selected as the Izhikevich working mode.
[0053] Secondly, embodiments of the present invention provide a control method for a configurable neuron circuit, comprising:
[0054] Based on the received neuron configuration signal, a corresponding target working mode is selected, wherein the target working mode includes LIF working mode or Izhikevich working mode;
[0055] Based on the selected target working mode and the received pulse information from the presynaptic neuron, the corresponding membrane potential is updated to obtain the membrane potential update result.
[0056] The membrane potential update result is compared with a preset threshold, and it is determined whether the current neuron will generate a pulse based on the comparison result;
[0057] When it is determined that the current neuron will generate a pulse, a pulse signal and an AER-encoded packet are generated, and the updated membrane potential information is output.
[0058] The configurable neuron circuit of this invention includes: a mode selection module, which selects a corresponding target operating mode based on a received neuron configuration signal, wherein the target operating mode includes a LIF operating mode or an Izhikevich operating mode; a calculation module, connected to the mode selection module, which updates the membrane potential according to the target operating mode selected by the mode selection module and the received pulse information of the presynaptic neuron, to obtain a membrane potential update result; a comparison module, connected to the calculation module, which compares the membrane potential update result with a preset threshold and determines whether the current neuron will generate a pulse based on the comparison result; and a pulse generation module, connected to the comparison module, which generates a pulse signal and an AER encoded packet when the comparison module determines that the current neuron will generate a pulse, and outputs the updated membrane potential information. In this invention, by reusing circuits, two neuron models can be selected. Compared with the method of stacking two neuron model circuits separately, this achieves a lower circuit area and simplifies the circuit structure. Furthermore, compared with traditional neuron circuits that only support one neuron model, it can achieve more complex behavioral patterns. [Attached Image Description]
[0059] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0060] Figure 1 A schematic diagram of the circuit structure of a configurable neuron circuit according to an embodiment of the present invention is shown.
[0061] Figure 2 A schematic diagram of the specific circuit structure of a configurable neuron circuit according to an embodiment of the present invention is shown.
[0062] Figure 3 A schematic diagram of the circuit structure of a computing unit in a configurable neuron circuit according to an embodiment of the present invention is shown.
[0063] Figure 4 A schematic diagram of the circuit structure of a pulse generation module in a configurable neuron circuit according to an embodiment of the present invention is shown.
[0064] Figure 5 A flowchart illustrating a control method for a configurable neuron circuit according to an embodiment of the present invention is shown.
Detailed Implementation Methods
[0065] To better understand the technical solution of the present invention, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0066] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.
[0067] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.
[0068] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.
[0069] Please see Figure 1 , Figure 1 A schematic block diagram of a configurable neuron circuit according to an embodiment of the present invention is shown. This configurable neuron circuit is used to solve the technical problems existing in related technologies, such as the complex structure and large area occupied by neuron circuits that only support a single neuron model or support two neuron models.
[0070] like Figure 1 As shown, a configurable neuron circuit according to an embodiment of the present invention includes:
[0071] The mode selection module 11 selects the corresponding target working mode according to the received neuron configuration signal, wherein the target working mode includes LIF working mode or Izhikevich working mode.
[0072] The calculation module 12 is connected to the mode selection module 11 and is used to update the membrane potential according to the target working mode selected by the mode selection module 11 and the received pulse information of the presynaptic neuron, so as to obtain the membrane potential update result.
[0073] The comparison module 13, connected to the calculation module 12, is used to compare the membrane potential update result with a preset threshold and determine whether the current neuron will generate a pulse based on the comparison result.
[0074] The pulse generation module 14 is connected to the comparison module 13 and is used to generate a pulse signal and an AER encoding packet when the comparison module 13 determines that the current neuron will generate a pulse, and output the updated membrane potential information.
[0075] In this embodiment, by reusing circuits, two neuron models can be selected. Compared with the method of stacking two neuron model circuits separately, it can achieve a lower circuit area and simplify the circuit structure. At the same time, compared with the traditional neuron circuit that only supports one neuron model, it can achieve more complex behavioral patterns.
[0076] like Figure 2 As shown, in one embodiment, optionally, the computing module 12 includes a first computing unit 121, a second computing unit 122, a third computing unit 123, and a fourth computing unit 124.
[0077] Among them, such as Figure 3 As shown, each computing unit includes: a control subunit 31, a data allocation subunit 32, and a computing subunit 33;
[0078] The control subunit 31 is used to generate a first clock pulse signal of a first preset period length according to the received pulse information of the presynaptic neuron and the target working mode, so as to control the data allocation subunit and the calculation subunit.
[0079] The data allocation subunit 32 is connected to the control subunit 31 and the calculation subunit 33, and is used to allocate corresponding calculation tasks to the calculation subunit.
[0080] The calculation subunit 33 is connected to the control subunit 31 and the data allocation subunit 32, and is used to perform data calculation and membrane potential accumulation to obtain the corresponding membrane potential update result.
[0081] In one embodiment, optionally, when the target operating mode is LIF operating mode, the data allocation subunits and calculation subunits corresponding to the first computing unit 121, the second computing unit 122, the third computing unit 123, and the fourth computing unit 124 have the same function, and each data allocation subunit 32 is used for:
[0082] Assign prominent weight values, membrane potential leakage values, and membrane potential information from the previous time step to the calculation subunit, and assign calculation tasks to calculate the membrane potential information for the current time step.
[0083] Each computational subunit is used for:
[0084] Calculate the membrane potential information for the current time step based on the computational task;
[0085] Update the membrane potential information at the current time step to obtain the corresponding membrane potential update result.
[0086] In this embodiment, for LIF operating mode, the circuit is implemented as a LIF neuron model. Its specific function is to receive pulse information from the presynaptic neuron, combine it with the corresponding synaptic weights and the membrane potential information from the previous time step, and update the membrane potential information for the current time step. Four computational units act as independent LIF neuron computational units, each performing the membrane potential update; that is, this circuit can be divided into four independent LIF neurons. The logical functions of all four computational units can be implemented by accumulators. In LIF operating mode, each unit accumulates the synaptic weights, leakage values, and the membrane potential from the previous time step.
[0087] In one embodiment, optionally, when the target working mode is the Izhikevich working mode, the data allocation subunit and the calculation subunit corresponding to the first calculation unit 121, the second calculation unit 122, the third calculation unit 123 and the fourth calculation unit 124 have different functions.
[0088] The first allocation subunit corresponding to the first calculation unit 121 is used for:
[0089] Assign synaptic weight values, membrane potential information from the previous time step, first intermediate calculation result, second calculation result, and third calculation result to the first calculation subunit corresponding to the first calculation unit 121, and assign a first calculation task to calculate the membrane potential information of the current time step.
[0090] The second allocation subunit corresponding to the second calculation unit 122 is used for:
[0091] Assign the membrane potential information of the previous time step and the second intermediate calculation result to the second calculation subunit corresponding to the second calculation unit 122, and assign the second calculation task to calculate the second calculation result.
[0092] The third allocation subunit corresponding to the third calculation unit 123 is used for:
[0093] Assign the membrane potential information of the previous time step, the membrane recovery variable of the previous time step, and the third intermediate calculation result to the third calculation subunit corresponding to the third calculation unit 123, and assign the third calculation task to calculate the third calculation result.
[0094] The fourth allocation subunit corresponding to the fourth calculation unit 124 is used for:
[0095] The membrane potential information of the previous time step, the membrane recovery variable of the previous time step, and the fourth intermediate calculation result are assigned to the fourth calculation unit corresponding to the fourth calculation unit 124, and the fourth calculation task of calculating the membrane recovery variable of the current time step is assigned.
[0096] In one embodiment, optionally, when the target operating mode is the Izhikevich operating mode, the first computing subunit is used to:
[0097] The first intermediate calculation result and the membrane potential information at the current time step are calculated based on the first calculation task.
[0098] The second calculation subunit is used for:
[0099] Calculate the second intermediate calculation result and the second calculation result according to the second calculation task;
[0100] The third computing subunit is used for:
[0101] Calculate the third intermediate calculation result and the third calculation result based on the third calculation task;
[0102] The fourth calculation subunit is used for:
[0103] The fourth intermediate calculation result and the membrane recovery variable at the current time step are calculated based on the fourth calculation task.
[0104] In this embodiment, for the Izhikevich operating mode, the circuit is implemented as an IZH neuron model. Its specific function is to receive pulse information from the presynaptic neuron, combine it with the corresponding synaptic weights to obtain the input current value of the postsynaptic neuron, and then combine it with the membrane potential information and membrane recovery variable information from the previous time step to update the membrane potential information and membrane recovery variable information for the current time step. Specifically, the first to third calculation units calculate partial results of the IZH neuron membrane potential update, which are then accumulated to obtain the final membrane potential update result. The fourth calculation unit calculates the membrane recovery variable update result. Therefore, this circuit is an independent Izhikevich neuron.
[0105] In the Izhikevich working mode, the four computational units perform different functions due to different data allocations, each completing a portion of the computation. The first computational unit 0 accumulates the membrane potential and weight values based on the impulse firing status of the previous stage neurons, and subsequently adds the calculation results from the second and third computational units 1 and 2. The second computational unit 1 performs multiplication using an accumulation method, calculating v. 2 The value of . Calculation Unit 2 of the third calculation unit calculates (2) 2 +2)v[n]-u[n]+(2 7 +2 3 +2 2 The value of ) is calculated in the fourth calculation unit 3, which calculates u[n+1], i.e., calculates 2. -8 v[n]+(1-2 -6 +2 -8 The value of u[n].
[0106] like Figure 2 As shown, in one embodiment, optionally, an arbitration circuit 21 may also be included;
[0107] When the target operating mode is LIF operating mode, the arbitration circuit 21 is used for:
[0108] Arbitrate the corresponding membrane potential update results obtained from each calculation subunit and sort them according to the receiving order of each membrane potential update result;
[0109] Based on the sorting results, the update results of each membrane potential are compared with the preset threshold in sequence.
[0110] In this embodiment, in LIF operating mode, each of the four computational units generates a valid block_complete signal (active high) after completing its membrane potential update calculation. Since in this operating mode, a circuit module contains four computational units, one comparison module, and one pulse generation module, the subsequent comparison and pulse generation modules are shared by all four computational units. When multiple computational units simultaneously generate valid block_complete (computation end flag) signals, i.e., simultaneously access the comparison and pulse generation modules, a conflict occurs. To avoid this problem, an arbitration circuit is used to arbitrate the block_complete signals. Only one valid block_complete signal is allowed to be responded to by the subsequent comparison and pulse generation modules at a time; other valid block_complete signals wait until the subsequent circuit responds to the previous block_complete signal. Specifically, the arbitration circuit responds to the earliest arriving valid block_complete signal and pulls the corresponding port's arbitration response (gnt) signal high. During this period, it does not respond to subsequent block_complete signals. The pulled-up gnt signal then pulls down the corresponding block_complete signal. Afterward, the arbitrator can respond to subsequent block_complete signals and repeat the above process.
[0111] When the target operating mode is the Izhikevich operating mode, the arbitration circuit 41 is used for:
[0112] The first calculation unit is controlled to compare the update results of each membrane potential with the preset threshold.
[0113] In the above embodiment, in LIF operating mode, the membrane potential updates of the four LIF neurons are arbitrated by a subsequent arbitration circuit and sequentially compared with threshold values by a comparator circuit to determine whether the current neuron will generate a pulse. If a pulse is generated, a subsequent pulse generation unit generates a pulse signal and an Address-Event-Representation (AER) encoded packet, and simultaneously outputs the updated membrane potential. Specifically, if a pulse is generated, the membrane potential is reset; if no pulse is generated, the membrane potential is updated by subtracting the potential leakage value.
[0114] In Izhikevich mode, the membrane potential update of this neuron is compared with a threshold by a subsequent comparator circuit to determine whether the neuron will generate a pulse. If a pulse is generated, the subsequent pulse generation unit generates a pulse signal and an Address-Event-Representation (AER) encoded packet, and simultaneously outputs the updated membrane potential and membrane recovery variable. If a pulse is generated, the membrane potential and membrane recovery variable are reset; if no pulse is generated, the updated values are retained.
[0115] like Figure 2 In one embodiment, optionally, the comparison module 13 includes: a control unit 131, a first register 132, and a comparison unit 133;
[0116] The control unit 131 is connected to the arbitration circuit 41 and is used to generate a second clock pulse signal with a second preset period length based on the received membrane potential update result, so as to control the comparison unit and the pulse generation module.
[0117] The first register 132 is connected to the arbitration circuit 41 and is used to store the received membrane potential update result;
[0118] The comparison unit 133 is connected to the first register 132 and is used to compare the membrane potential update result in the first register 132 with a preset threshold to obtain a comparison result.
[0119] In this embodiment, the control unit generates a clock pulse signal of a certain period length upon receiving a valid input signal, which is then used for other control and calculation logic. The register stores the membrane potential update results, facilitating subsequent comparison by the comparison unit between the membrane potential update results and a preset threshold.
[0120] like Figure 4 As shown, in one embodiment, optionally, the pulse generation module 14 includes: a second register 41;
[0121] The second register is used for:
[0122] When it is determined that the current neuron will generate a pulse, obtain the address of the source neuron and the address of the destination neuron;
[0123] Based on the source neuron address and the target neuron address, a pulse signal and an AER encoded packet are generated, and the updated membrane potential information is output.
[0124] In one embodiment, optionally, the mode selection module 11 is specifically used for:
[0125] When the received neuron configuration signal is at the first level, the corresponding target working mode is selected as the LIF working mode;
[0126] When the received neuron configuration signal is at the second level, the corresponding target working mode is selected as the Izhikevich working mode.
[0127] In this embodiment, the neuron circuit's operating mode control signal is neuron_config. When this signal is high, the circuit is in Izhikevich operating mode, and its function is to implement the Izhikevich neuron model; when this signal is low, the circuit is in LIF operating mode, and its function is to implement the LIF neuron model. Furthermore, for a single circuit unit, one Izhikevich neuron model or four LIF neuron models can be implemented.
[0128] Figure 5 A flowchart illustrating a control method for a configurable neuron circuit according to an embodiment of the present invention is shown.
[0129] Secondly, embodiments of the present invention provide a control method for a configurable neuron circuit, comprising:
[0130] Step S501: Select the corresponding target working mode according to the received neuron configuration signal, wherein the target working mode includes LIF working mode or Izhikevich working mode.
[0131] Step S502: Update the membrane potential according to the selected target working mode and the received pulse information of the presynaptic neuron to obtain the membrane potential update result.
[0132] Step S503: Compare the membrane potential update result with a preset threshold, and determine whether the current neuron will generate a pulse based on the comparison result;
[0133] Step S504: When it is determined that the current neuron will generate a pulse, a pulse signal and an AER encoding packet are generated, and the updated membrane potential information is output.
[0134] In one embodiment, optionally, step S502 includes:
[0135] Based on the received pulse information from the presynaptic neuron and the target operating mode, a first clock pulse signal with a first preset cycle length is generated to control multiple computing units.
[0136] Data calculations and membrane potential accumulation are performed by multiple computing units to obtain the corresponding membrane potential update results.
[0137] In one embodiment, optionally, when the target operating mode is LIF operating mode, step S502 includes:
[0138] Synaptic weight values, membrane potential leakage values, and membrane potential information from the previous time step are allocated through multiple computing units.
[0139] Based on the assigned synaptic weights, membrane potential leakage values, and membrane potential information from the previous time step, the membrane potential information for the current time step is calculated to obtain the corresponding membrane potential update result.
[0140] In one embodiment, optionally, when the target operating mode is the Izhikevich operating mode, step S502 includes:
[0141] Based on the received pulse information from the presynaptic neuron and the membrane potential and membrane recovery variable information from the previous time step, the membrane potential and membrane recovery variable information for the current time step are calculated and updated through multiple computing units.
[0142] In one embodiment, optionally, selecting a corresponding target operating mode based on the received neuron configuration signal includes:
[0143] When the received neuron configuration signal is at the first level, the corresponding target working mode is selected as the LIF working mode;
[0144] When the received neuron configuration signal is at the second level, the corresponding target working mode is selected as the Izhikevich working mode.
[0145] In one embodiment, optionally, upon determining that the current neuron will generate a pulse, a pulse signal and an AER-encoded packet are generated, and updated membrane potential information is output, including:
[0146] When it is determined that the current neuron will generate a pulse, obtain the address of the source neuron and the address of the destination neuron;
[0147] Based on the source neuron address and the target neuron address, a pulse signal and an AER encoded packet are generated, and the updated membrane potential information is output.
[0148] It is understood that the configuration of the mode selection circuit, arbitration circuit, data distribution unit and computing unit, as well as the selection of each component, can be selected and set according to the actual scenario of production design, and this embodiment does not impose specific limitations.
[0149] It should be noted that the circuit function of the configurable neural circuit provided in this embodiment is mainly realized through the circuit connection relationship between various circuit modules, and does not depend on the program module in a particular circuit module. Furthermore, the various circuit modules in the configurable neural circuit can be implemented using analog circuits or digital circuits, and for circuit modules that can be implanted with program modules, their module functions can be implemented using program modules provided by existing technologies.
[0150] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.
[0151] It should be understood that although the terms "first," "second," etc., may be used to describe the setting modules in the embodiments of the present invention, these setting modules should not be limited to these terms. These terms are only used to distinguish the setting modules from each other. For example, without departing from the scope of the embodiments of the present invention, the first setting module may also be referred to as the second setting module, and similarly, the second setting module may also be referred to as the first setting module.
[0152] Depending on the context, the word "if" as used here can be interpreted as "when," "when," "in response to determination," or "in response to detection." Similarly, depending on the context, the phrase "if determination" or "if detection (of the stated condition or event)" can be interpreted as "when determination," "in response to determination," "when detection (of the stated condition or event)," or "in response to detection (of the stated condition or event)."
[0153] In the embodiments provided by this invention, it should be understood that the disclosed systems, methods, and approaches can be implemented in other ways. For example, the system embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between systems or modules may be electrical, mechanical, or other forms.
[0154] Furthermore, the functional modules in the various embodiments of the present invention can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The integrated module can be implemented in hardware or in the form of hardware plus software functional modules.
[0155] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.
Claims
1. A configurable neuron circuit, comprising: The method comprises the following steps: a mode selection module selects a corresponding target working mode according to a received neuron configuration signal, wherein the target working mode comprises a LIF working mode or an Izhikevich working mode; a calculation module connected to the mode selection module is used for performing corresponding membrane potential updating according to the target working mode selected by the mode selection module and received presynaptic neuron pulse information, to obtain a membrane potential updating result; a comparison module connected to the calculation module is used for comparing the membrane potential updating result with a preset threshold value, and determining whether the current neuron will generate a pulse according to a comparison result; a pulse generation module connected to the comparison module is used for generating a pulse signal and an AER encoding group packet, and outputting updated membrane potential information when the comparison module determines that the current neuron will generate a pulse.
2. The configurable neuron circuit of claim 1, wherein, The calculation module comprises a first calculation unit, a second calculation unit, a third calculation unit and a fourth calculation unit, each of which comprises a control subunit, a data distribution subunit and a calculation subunit; The control subunit is used for generating a first clock pulse signal of a first preset period length according to the received presynaptic neuron pulse information and the target working mode, to control the data distribution subunit and the calculation subunit; The data distribution subunit connected to the control subunit and the calculation subunit is used for distributing corresponding calculation tasks to the calculation subunit; The calculation subunit connected to the control subunit and the data distribution subunit is used for performing data calculation and membrane potential accumulation, to obtain a corresponding membrane potential updating result.
3. The configurable neuron circuit of claim 2, wherein, When the target working mode is the LIF working mode, the functions of the data distribution subunits and the calculation subunits corresponding to the first calculation unit, the second calculation unit, the third calculation unit and the fourth calculation unit are the same, and each data distribution subunit is used for: distributing a synaptic weight value, a membrane potential leakage value and membrane potential information of a previous time step to the calculation subunit, and distributing a calculation task of calculating membrane potential information of a current time step; each calculation subunit is used for: calculating the membrane potential information of the current time step according to the calculation task; updating the membrane potential information of the current time step, to obtain a corresponding membrane potential updating result.
4. The configurable neuron circuit of claim 2, wherein, When the target working mode is the Izhikevich working mode, the functions of the data distribution subunits and the calculation subunits corresponding to the first calculation unit, the second calculation unit, the third calculation unit and the fourth calculation unit are different; the first distribution subunit corresponding to the first calculation unit is used for: distributing a synaptic weight value, membrane potential information of a previous time step, a first intermediate calculation result, a second calculation result and a third calculation result to the first calculation subunit corresponding to the first calculation unit, and distributing a first calculation task of calculating membrane potential information of a current time step; the second distribution subunit corresponding to the second calculation unit is used for: distributing membrane potential information of a previous time step and a second intermediate calculation result to the second calculation subunit corresponding to the second calculation unit, and distributing a second calculation task of calculating a second calculation result; The third distribution subunit corresponding to the third calculation unit is configured to: distribute the membrane potential information of the previous time step, the membrane recovery variable of the previous time step, and the third intermediate calculation result to the third calculation subunit corresponding to the third calculation unit, and distribute the third calculation task of calculating the third calculation result; The fourth distribution subunit corresponding to the fourth calculation unit is configured to: distribute the membrane potential information of the previous time step, the membrane recovery variable of the previous time step, and the fourth intermediate calculation result to the fourth calculation unit corresponding to the fourth calculation unit, and distribute the fourth calculation task of calculating the membrane recovery variable of the current time step.
5. The configurable neuron circuit of claim 4, wherein, When the target working mode is the Izhikevich working mode, the first calculation subunit is configured to: calculate the first intermediate calculation result and the membrane potential information of the current time step according to the first calculation task; The second calculation subunit is configured to: calculate the second intermediate calculation result and the second calculation result according to the second calculation task; The third calculation subunit is configured to: calculate the third intermediate calculation result and the third calculation result according to the third calculation task; The fourth calculation subunit is configured to: calculate the fourth intermediate calculation result and the membrane recovery variable of the current time step according to the fourth calculation task.
6. A configurable neuron circuit according to claim 3 or 5, characterized in that, Further comprising: an arbitration circuit; When the target working mode is the LIF working mode, the arbitration circuit is configured to: arbitrate the corresponding membrane potential update results obtained by each calculation subunit, and sort the membrane potential update results according to the receiving order of the membrane potential update results; according to the sorting result, control the membrane potential update results to be compared with the preset threshold value in sequence; When the target working mode is the Izhikevich working mode, the arbitration circuit is configured to: control the first calculation unit to compare each membrane potential update result with the preset threshold value.
7. The configurable neuron circuit of claim 6, wherein, The comparison module comprises a control unit, a first register, and a comparison unit; The control unit is connected to the arbitration circuit and is configured to generate a second clock pulse signal with a second preset period length according to the received membrane potential update result, so as to control the comparison unit and the pulse generation module; The first register is connected to the arbitration circuit and is configured to store the received membrane potential update result; The comparison unit is connected to the first register and is configured to compare the membrane potential update result in the first register with the preset threshold value to obtain a comparison result.
8. The configurable neuron circuit of claim 1, wherein, The pulse generation module comprises a second register; The second register is configured to: when it is determined that the current neuron will generate a pulse, obtain a source neuron address and a destination neuron address; generate a pulse signal and an AER encoding packet according to the source neuron address and the destination neuron address, and output the updated membrane potential information.
9. The configurable neuron circuit of claim 1, wherein, The mode selection module is specifically configured to: when the received neuron configuration signal is a first level, select the corresponding target working mode as the LIF working mode; when the received neuron configuration signal is a second level, select the corresponding target working mode as the Izhikevich working mode.
10. A control method of a configurable neuron circuit, characterized by, According to the received neuron configuration signal, a corresponding target working mode is selected, wherein the target working mode includes an LIF working mode or an Izhikevich working mode; According to the selected target working mode and the received pulse information of the presynaptic neuron, a corresponding membrane potential update is performed to obtain a membrane potential update result; The membrane potential update result is compared with a preset threshold, and it is determined whether the current neuron will generate a pulse according to the comparison result; When it is determined that the current neuron will generate a pulse, a pulse signal and an AER encoding group package are generated, and the updated membrane potential information is output.