Low-noise arbitrary waveform generating device and method for superconducting quantum computing

Abstract

The invention provides a low-noise arbitrary waveform generation device and method for superconducting quantum computing, which adopts a hardware architecture in which a bottom plate integrated with a medium-speed waveform generation circuit is combined with a high-speed daughter card, so that the expansibility and the application range of the device are improved; the radio frequency direct acquisition circuit design is applied to the high-speed daughter card, and the unique power management module and the device overall ground plane configuration scheme and other innovative noise suppression technologies are introduced into the bottom plate, so that the system noise is remarkably reduced, and the signal-to-noise ratio and the measurement precision of signals are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of signal generation, in particular to a low-noise arbitrary waveform generation device and method, which is especially suitable for superconducting quantum computing applications. BACKGROUND

[0002] In the fields of electronic testing, communication, scientific research, etc., especially in quantum computing, it is necessary to use a waveform generator to accurately prepare various quantum states. Therefore, an arbitrary waveform generation device is one of the important equipment for quantum computing.

[0003] In traditional quantum computing, IQ mixing technology is used to generate the required waveforms. In IQ mixing technology, the input signal is divided into orthogonal I (in-phase) and Q (quadrature) signals for processing, which can achieve precise control of the signal phase and amplitude; by adjusting the phase difference of the I and Q signals, signal rotation, translation and frequency conversion operations can be easily realized, thus providing a flexible means for complex signal processing in quantum computing.

[0004] However, IQ mixing technology also has some defects, mainly as follows:

[0005] (1) Complex implementation circuit structure. In the implementation circuit based on IQ mixing technology, additional hardware devices such as mixers and local oscillator sources are needed, which increases the complexity of the quantum computing system, making it difficult to achieve high integration and multi-channel waveform output.

[0006] (2) Sideband leakage. Sideband leakage may occur during IQ mixing, i.e., the phenomenon that unwanted sideband signals (upper or lower sidebands) are not fully suppressed and leak into the output signal. Sideband leakage can cause inaccurate manipulation of quantum bits and affect the results of quantum computing. For example, in the radio frequency manipulation of quantum bits, if there is sideband leakage, it may introduce additional noise or interfere with the state of the quantum bits.

[0007] (3) Local oscillator leakage. In the IQ mixer, the local oscillator signal may appear at the output of the mixer under unexpected circumstances, and this output signal contains a strong local oscillator frequency component. In a quantum computing system, this local oscillator leakage can cause inaccurate manipulation of quantum bits and affect the results of quantum computing. For example, in the radio frequency manipulation of quantum bits, if there is local oscillator leakage, it may introduce additional noise or interfere with the state of the quantum bits, causing signal distortion and misjudgment, affecting the results of quantum computing.

[0008] In recent years, quantum computing systems have developed rapidly and are developing towards the scale of thousands of bits, which puts higher requirements on the integration and low noise of arbitrary waveform generating devices. The traditional IQ mixing technology cannot meet the current needs due to the complex circuit structure, sideband leakage and local oscillator leakage, which leads to low signal-to-noise ratio. Therefore, it has become a key task with great importance and practical value to develop an arbitrary waveform generating device with high integration, multi-channel output, ultra-low noise and high-speed arbitrary waveform generation capability. SUMMARY

[0009] In view of the above problems existing in the prior art, the present application provides a low-noise arbitrary waveform generating device and method for superconducting quantum computing, wherein a hardware architecture combining an integrated medium-speed waveform generating circuit bottom plate and a high-speed daughter card is adopted to improve the scalability and application range of the device; by applying innovative noise suppression technologies such as radio frequency direct sampling circuit design in the high-speed daughter card, introducing a unique power management module in the bottom plate and overall ground plane configuration scheme of the device, the system noise is significantly reduced, and the signal-to-noise ratio and measurement accuracy of the signal are improved.

[0010] Specifically, the first aspect of the present application relates to a low-noise arbitrary waveform generating device for superconducting quantum computing, comprising a bottom plate and a plurality of daughter cards.

[0011] The bottom plate is integrated with a control module and a plurality of medium-speed arbitrary waveform generating circuits.

[0012] The daughter card is integrated with a high-speed arbitrary waveform generating circuit.

[0013] The control module is configured to control the medium-speed arbitrary waveform generating circuit and / or the high-speed arbitrary waveform generating circuit to generate a waveform signal according to control data.

[0014] Further, the high-speed arbitrary waveform generating circuit comprises a high-speed digital-to-analog converter and a high-rolloff low-pass filter circuit.

[0015] Further, the low-noise arbitrary waveform generating device of the present application can further comprise a power management module integrated on the bottom plate.

[0016] The power management module comprises a DCDC switching power supply and a common-mode filter.

[0017] The DCDC switching power supply is configured to generate an internal power supply signal based on an external power supply signal.

[0018] The common-mode filter is configured to filter the internal power supply signal.

[0019] Furthermore, the base plate is provided with a first ground plane for the DC-DC switching power supply, a second ground plane for the common-mode filter, and a third ground plane for the medium-speed arbitrary waveform generation circuit, and the daughter card is provided with a fourth ground plane for the high-speed arbitrary waveform generation circuit.

[0020] The first ground plane, the second ground plane, the third ground plane, and the fourth ground plane are isolated from each other.

[0021] Preferably, the first ground plane is a PGND plane, the second ground plane is a PGND plane or a GND plane, and the third and fourth ground planes are AGND planes.

[0022] Preferably, the daughter card integrates a low-dropout linear regulator, which is configured to provide operating voltage to the high-speed arbitrary waveform generation circuit based on the internal power signal; and / or, the baseboard integrates a low-dropout linear regulator, which is configured to provide operating voltage to the medium-speed arbitrary waveform generation circuit based on the internal power signal.

[0023] Furthermore, the control module includes a communication interface and an FPGA unit;

[0024] The communication interface is configured for data communication between the host computer and the FPGA unit;

[0025] The FPGA unit is configured to control the medium-speed arbitrary waveform generation circuit and / or the high-speed arbitrary waveform generation circuit to generate waveform signals according to the control data.

[0026] Furthermore, the medium-speed arbitrary waveform generation circuit includes a digital-to-analog converter.

[0027] Preferably, the data frame for controlling the data includes an instruction portion for instructing the operation of the arbitrary waveform generation circuit and waveform parameters, and the waveform data itself.

[0028] The second aspect of the present invention relates to a low-noise arbitrary waveform generation method for superconducting quantum computing based on the above-described low-noise arbitrary waveform generation device, which includes a control data generation step, a control data parsing step, and a waveform signal generation step.

[0029] In the control data generation step, the host computer generates control data, which includes an instruction part and a waveform data part.

[0030] In the control data parsing step, the control module parses the control data and determines an arbitrary waveform generation circuit related to the waveform data based on the instruction portion;

[0031] In the waveform signal generation step, an arbitrary waveform generation circuit generates a waveform signal based on the waveform data portion. Attached Figure Description

[0032] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0033] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 A preferred example of the low-noise arbitrary waveform generator for superconducting quantum computing of the present invention is shown schematically.

[0035] Figure 2 A preferred example of the power management module and ground plane configuration in the low-noise arbitrary waveform generator of the present invention is illustrated schematically. Detailed Implementation

[0036] In the following description, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided by way of example in order to fully convey the spirit of the invention to those skilled in the art. Therefore, the invention is not limited to the embodiments disclosed herein.

[0037] Figure 1 A preferred example of the low-noise arbitrary waveform generator for superconducting quantum computing of the present invention is shown schematically.

[0038] like Figure 1 As shown, the low-noise arbitrary waveform generator of the present invention may include a base plate 11 and multiple daughter cards, such as high-speed daughter card 1 and high-speed daughter card 2. Those skilled in the art will understand that the high-speed daughter cards here can be adapted to use with the base plate 11.

[0039] The base plate 11 can integrate multiple medium-speed arbitrary waveform generation circuits, such as arbitrary waveform generation circuit 16 and arbitrary waveform generation circuit 17.

[0040] The daughter card can integrate multiple high-speed arbitrary waveform generation circuits. For example, high-speed daughter card 1 integrates high-speed arbitrary waveform generation circuits 12 and 13, and high-speed daughter card 2 integrates high-speed arbitrary waveform generation circuits 14 and 15.

[0041] In this invention, the high-speed arbitrary waveform generation circuit can have an operating frequency of 4GHz-8GHz, and the medium-speed arbitrary waveform generation circuit can have an operating frequency of DC-700MHz.

[0042] In this invention, the high-speed arbitrary waveform generation circuit adopts a direct RF sampling circuit design, which includes a high sampling rate digital-to-analog converter (DAC) and a low insertion loss, high roll-off low-pass filter circuit. Therefore, compared with the traditional IQ mixing design, the high-speed arbitrary waveform generation circuit of this invention has the ability to directly filter out high-order harmonics, can generate high signal-to-noise ratio signals required for quantum bit manipulation, and has a simpler circuit structure. It also solves the local oscillator leakage and sideband leakage problems caused by IQ mixing signals.

[0043] In a preferred embodiment of the present invention, only one high-speed output channel is provided for each high-speed arbitrary waveform generation circuit.

[0044] The medium-speed arbitrary waveform generation circuit is also implemented using a DAC chip and necessary filtering and shaping circuits.

[0045] In a preferred embodiment of the invention, for a medium-speed arbitrary waveform generation circuit, multiple (e.g., four) medium-speed output channels can be configured based on a single DAC chip, thereby improving resource utilization and reducing costs, and providing a rich array of output channels with less hardware configuration.

[0046] See also Figure 1 The base plate 11 can also integrate a control module, which can control the medium-speed arbitrary waveform generation circuit and the high-speed arbitrary waveform generation circuit on the high-speed daughter card to generate and output the required waveform signal according to control data provided by, for example, the host computer.

[0047] exist Figure 1 In one example, the control module may include, for example, a high-speed communication interface and a programmable logic array (FPGA) unit.

[0048] (High-speed) communication interfaces can be used to enable data communication between external devices (such as a host computer) and the FPGA unit. For example, it can receive control data sent by the host computer and transmit it to the FPGA unit.

[0049] The FPGA unit can control the medium-speed and / or high-speed arbitrary waveform generation circuit to generate corresponding waveform signals based on the received control data.

[0050] In this invention, the host computer can achieve data communication between the two by sending data frames of a specific format to any waveform generator.

[0051] In a preferred example, the data frame may include a frame header, an instruction portion, a waveform data portion, a checksum, and a frame trailer.

[0052] The frame header can contain information such as the start identifier of the data frame, the frame length, and the frame type, which are used to identify the start and type of the data frame.

[0053] The instruction section can include control commands and parameter settings.

[0054] Control commands can be used to instruct any waveform generation circuit to perform specific operations, such as waveform selection, frequency setting, and amplitude adjustment. As an example, the FPGA unit can determine whether to send waveform data to a high-speed output channel or a medium-speed output channel based on the channel address in the control command.

[0055] The parameter settings can be used to specify specific parameters of the waveform, such as frequency, amplitude, and phase.

[0056] The waveform data portion may contain the waveform data itself. In this invention, the waveform data can be pre-stored waveform samples or waveform data generated in real time. Depending on the complexity and accuracy requirements of the waveform, the waveform data portion can occupy most of the space in the data frame. An 8-checksum can be used to verify the integrity and accuracy of the data frame. During data frame transmission, data loss or errors may occur; the checksum can help detect and address these problems promptly.

[0057] The frame tail can contain an end marker for the data frame, used to indicate the end of the data frame.

[0058] Therefore, when the FPGA unit receives control data, it can parse and process the control data, generate corresponding waveform data according to the control command requirements, and distribute it to the corresponding high-speed or medium-speed output channel.

[0059] In high-speed / medium-speed arbitrary waveform generation circuits, the DAC chip corresponding to the selected output channel converts the digital signal into an analog signal and performs signal conditioning through a filtering and shaping circuit.

[0060] To reduce noise in high-speed and medium-speed arbitrary waveform generation circuits, this invention not only employs a direct RF sampling circuit design in the high-speed arbitrary waveform generation circuit, but also adaptably introduces other noise suppression schemes into the arbitrary waveform generation device.

[0061] Figure 2 The diagram schematically illustrates a preferred example of the power management module and ground plane configuration in the arbitrary waveform generator of the present invention, thereby allowing for further suppression of device noise by means of a unique power management module and ground plane configuration scheme.

[0062] The power management module can be integrated on the baseboard 11 to generate an internal power signal based on an external power signal (such as a 12V power supply signal) to drive various chips / circuits in the arbitrary waveform generator, such as the control module, high-speed daughter card and medium-speed arbitrary waveform generator circuit.

[0063] exist Figure 2 In the preferred example shown, a power filtering circuit can also be provided at the power input of the base plate 11 (which is used to receive, for example, an external power signal of 12V) to filter the external power signal before it enters the power management module, thereby reducing noise at the source.

[0064] See also Figure 2 The power management module of the present invention may include multiple DC-DC switching power supplies and multiple common-mode filters.

[0065] Since the arbitrary waveform generator of the present invention contains a variety of different chips, such as FPGA chips, DAC chips in high-speed / medium-speed arbitrary waveform generation circuits, etc., different chips require different operating voltages, and the same chip may also require multiple voltages. Therefore, a DC-DC switching power supply can be used to generate various internal power signals using external power signals, thereby providing the required operating voltage for the corresponding circuits / chips.

[0066] Considering the noise sensitivity of analog devices such as DAC chips and filtering / shaping circuits, the internal power supply signal directly output by the DC-DC switching power supply has significant ripple and switching noise. Therefore, a common-mode filter can be placed after the DC-DC switching power supply to filter the internal power supply signal before it is provided to these analog devices, thereby reducing the impact of the DC-DC switching power supply on circuits such as medium-speed / high-speed arbitrary waveform generators. Furthermore, when using a DC-DC switching power supply to provide the internal power supply signal to a medium-speed / high-speed arbitrary waveform generator circuit, the DC-DC switching power supply can be configured to reduce the voltage of the internal power supply signal to a voltage slightly higher than the target voltage.

[0067] For digital circuits that are not sensitive to noise, such as FPGA chips, a DC-DC switching power supply can be used to directly power them.

[0068] See also Figure 2 To achieve noise suppression, a low-dropout linear regulator (LDO) can be integrated on the baseboard 11 to adjust the voltage of the internal power supply signal to the voltage required by each chip / circuit in the medium-speed arbitrary waveform generation circuit, thereby generating the corresponding operating voltage. Simultaneously, a low-dropout linear regulator (LDO) can also be integrated on the high-speed daughter card to adjust the voltage of the internal power supply signal to the voltage required by each chip / circuit in the high-speed arbitrary waveform generation circuit, thereby generating the corresponding operating voltage.

[0069] Furthermore, the inventors noted that, in addition to the power supply, the ground plane also constitutes a noise conduction path. To reduce the impact of noise on the arbitrary waveform generation circuit through the ground plane, this invention also incorporates noise suppression design in the ground plane configuration of the arbitrary waveform generation device; that is, a unique segmentation and isolation design is implemented for the ground planes of the base plate and the high-speed daughter card.

[0070] like Figure 2 As shown, in the ground plane configuration of the present invention, the ground plane of the base plate 11 is divided into a first ground plane for the DC-DC switching power supply, a second ground plane for the common-mode filter, and a third ground plane for the medium-speed arbitrary waveform generation circuit. At the same time, the ground plane of the high-speed daughter card is divided into a fourth ground plane for the high-speed arbitrary waveform generation circuit, so that the first ground plane, the second ground plane, the third ground plane and the fourth ground plane are isolated from each other.

[0071] In addition, the first ground plane is specifically set as the PGND plane, the second ground plane is set as the PGND plane or GND plane, and the third and fourth ground planes are set as the AGND plane. This makes all DC-DC switching power supplies after the external power signal passes through the power filter PGND1 plane, the common mode filter PGND2 plane or GND plane, and the LDO of the high-speed daughter card and the LDO of the baseboard are all on a relatively clean AGND plane, thereby effectively eliminating the conduction path of noise on the ground plane and reducing the impact of noise on arbitrary waveform generation circuits through the ground plane.

[0072] In summary, the arbitrary waveform generator of the present invention adopts a hardware architecture that combines a baseboard and a high-speed daughter card, which allows multiple high-speed (4-8GHz) arbitrary waveform generator circuits and multiple medium-speed (DC-700MHz) arbitrary waveform generator circuits to be conveniently implemented on a single board. Through this combination of high and medium speeds, the device can cover a wider range of application scenarios, and is particularly suitable for the needs of quantum technology to control high-speed and medium-speed arbitrary waveforms.

[0073] Meanwhile, designing the high-speed arbitrary waveform generation circuit (high-speed output channel) as a separate daughter card not only reduces interference from factors such as switching power supply noise on the high-speed arbitrary waveform generation circuit, but also allows for easy expansion of the output channel to meet the needs of various multi-channel scenarios.

[0074] Furthermore, this invention innovatively introduces noise suppression technologies such as a power management module combined with an LDO and a unique ground plane segmentation configuration, significantly reducing system noise and improving signal-to-noise ratio and measurement accuracy. Specifically, by utilizing a DC-DC switching power supply and a common-mode filter to implement the power management module, and by using an LDO to distribute operating voltage to each chip, power utilization efficiency can be effectively improved and common-mode noise in the power system can be suppressed, while maintaining output voltage stability.

[0075] By employing a direct RF sampling circuit design in the high-speed arbitrary waveform generation circuit, high-order harmonics can be directly filtered out, generating a high signal-to-noise ratio signal required for quantum bit control. The circuit structure is simpler and can also solve the problems of local oscillator leakage and sideband leakage caused by IQ mixing signals.

[0076] Therefore, the arbitrary waveform generator of the present invention can achieve the currently urgently needed performance such as high integration, ultra-low noise, easy expansion, multi-channel output and high-speed arbitrary waveform generation capability, so as to be well suited for scenarios such as quantum computing control that have the requirements of high-speed and medium-speed arbitrary waveforms and multi-channel requirements.

[0077] Meanwhile, the highly integrated design of the arbitrary waveform generator of the present invention can significantly reduce the size and weight of the device, improve the installation flexibility of the device, and the modular design makes the device easy to maintain and upgrade, extending the service life of the device and reducing long-term operating costs.

[0078] Based on the arbitrary waveform generator described above, this invention also proposes a low-noise arbitrary waveform generation method that is particularly suitable for superconducting quantum computing.

[0079] The arbitrary waveform generation method of the present invention may include a control data generation step, a control data parsing step, and a waveform signal generation step.

[0080] After the device starts working, the host computer can construct data frames to generate control data according to requirements in the control data generation step, and send it to the arbitrary waveform generator through the high-speed communication interface.

[0081] After receiving a data frame, the arbitrary waveform generator can use the control module to parse the data frame of the control data in the control data parsing step, confirm the validity and accuracy of the data frame, determine the arbitrary waveform generation circuit related to the waveform data part according to the channel address of the instruction part, decide whether to send the waveform data to the high-speed output channel or the medium-speed output channel, extract the waveform data part, and output the waveform data part to the corresponding channel.

[0082] Subsequently, the arbitrary waveform generation circuit can generate a corresponding waveform signal based on the received waveform data portion during the waveform signal generation step.

[0083] Finally, after completing the waveform output, the arbitrary waveform generator can send a confirmation message to the host computer through a feedback mechanism to indicate that the waveform output has been completed.

[0084] Although the present invention has been described above with reference to the accompanying drawings and specific embodiments, those skilled in the art will readily recognize that the above embodiments are merely exemplary and used to illustrate the principles of the present invention. They do not limit the scope of the present invention. Those skilled in the art can make various combinations, modifications and equivalent substitutions to the above embodiments without departing from the spirit and scope of the present invention.

Claims

1. A low-noise arbitrary waveform generation device for superconducting quantum computing, comprising a backplane and a plurality of daughter cards; a control module and a plurality of medium-speed arbitrary waveform generation circuits are integrated on the backplane; a high-speed arbitrary waveform generation circuit is integrated on the daughter card; the control module is configured to control the medium-speed arbitrary waveform generation circuits and / or the high-speed arbitrary waveform generation circuit to generate waveform signals according to control data.

2. The low noise arbitrary waveform generation device of claim 1, wherein, the high-speed arbitrary waveform generation circuit comprises a high-speed digital-to-analog converter and a high-rolloff low-pass filter circuit. 3.The low-noise arbitrary waveform generation device of claim 1, further comprising a power management module integrated on the backplane; the power management module comprises a DC / DC switching power supply and a common-mode filter; the DC / DC switching power supply is configured to generate an internal power supply signal based on an external power supply signal; the common-mode filter is configured to filter the internal power supply signal.

4. The low noise arbitrary waveform generation device of claim 3, wherein, a first ground plane for the DC / DC switching power supply, a second ground plane for the common-mode filter, and a third ground plane for the medium-speed arbitrary waveform generation circuits are provided on the backplane, and a fourth ground plane for the high-speed arbitrary waveform generation circuit is provided on the daughter card; the first, second, third, and fourth ground planes are isolated from each other.

5. The low noise arbitrary waveform generation device of claim 4, wherein, the first ground plane is a PGND plane, the second ground plane is a PGND plane or a GND plane, and the third and fourth ground planes are AGND planes. 6.The low-noise arbitrary waveform generation device of claim 3, wherein a low-dropout linear regulator is integrated on the daughter card and configured to provide an operating voltage for the high-speed arbitrary waveform generation circuit based on the internal power supply signal; and / or a low-dropout linear regulator is integrated on the backplane and configured to provide an operating voltage for the medium-speed arbitrary waveform generation circuits based on the internal power supply signal.

7. The low noise arbitrary waveform generation device of any one of claims 1-6, wherein, the control module comprises a communication interface and an FPGA unit; the communication interface is configured to communicate data between a host computer and the FPGA unit; the FPGA unit is configured to control the medium-speed arbitrary waveform generation circuits and / or the high-speed arbitrary waveform generation circuit to generate waveform signals according to the control data.

8. The low noise arbitrary waveform generation device of claim 1, wherein, the medium-speed arbitrary waveform generation circuit comprises a digital-to-analog converter.

9. The low noise arbitrary waveform generation device of claim 1, wherein, a data frame for control data comprises an instruction part for indicating operation of an arbitrary waveform generation circuit and waveform parameters, and waveform data itself. 10.A low-noise arbitrary waveform generation method for superconducting quantum computing based on the low-noise arbitrary waveform generation device of any one of claims 1-9, comprising a control data generation step, a control data analysis step, and a waveform signal generation step; in the control data generation step, control data is generated by a host computer, comprising an instruction part and a waveform data part; in the control data analysis step, the control data is analyzed by a control module, and an arbitrary waveform generation circuit related to the waveform data part is determined according to the instruction part; in the waveform signal generation step, a waveform signal is generated by an arbitrary waveform generation circuit according to the waveform data part.

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