Semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device includes: a first word line on a first surface of a substrate; a second word line on a second surface of the substrate; and a first cell and a second cell adjacent to each other along the second direction on the substrate. Each of the first cell and the second cell includes a first inverter and a second inverter, a first pass transistor connecting the first inverter with a bit line, and a second pass transistor connecting the second inverter with a complementary bit line. The first word line is connected to a gate of the first pass transistor of the first cell and a gate of the second pass transistor of the first cell. The second word line is connected to a gate of the first pass transistor of the second cell and a gate of the second pass transistor of the second cell.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0129801, filed on September 25, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to a semiconductor device, and more specifically, to a semiconductor device including a static random access memory (SRAM) device. Background Technology

[0004] Semiconductor devices allow for miniaturization, multifunctionality, and / or low manufacturing costs. Semiconductor devices include semiconductor memory devices for storing logic data, semiconductor logic devices for processing logic data, and hybrid semiconductor devices that include memory elements and logic elements.

[0005] The demand for improved characteristics in semiconductor devices is increasing. For example, there is a need for increased reliability, higher speed, and greater versatility. To meet these requirements, the structures in semiconductor devices have become increasingly complex and highly integrated. Consequently, delays occur when transmitting electrical signals through wiring. Summary of the Invention

[0006] One or more embodiments provide a semiconductor device with improved performance.

[0007] The purposes of this disclosure are not limited to those mentioned above, and other purposes not mentioned herein will be clearly understood by those skilled in the art from the following description.

[0008] According to one aspect of an embodiment, a semiconductor device includes: a substrate including a first surface and a second surface opposite to each other; a first word line extending along a first direction on the first surface; a second word line extending along the first direction on the second surface; a bit line and a complementary bit line extending parallel to each other along a second direction intersecting the first direction on the substrate; and a first cell and a second cell adjacent to each other on the substrate along the second direction. Each of the first cell and the second cell includes a latch circuit, the latch circuit including a first inverter and a second inverter, a first transfer transistor connecting the output node of the first inverter to the bit line, and a second transfer transistor connecting the output node of the second inverter to the complementary bit line. The first word line is connected to the gate of the first transfer transistor of the first cell and the gate of the second transfer transistor of the first cell. The second word line is connected to the gate of the first transfer transistor of the second cell and the gate of the second transfer transistor of the second cell.

[0009] According to another aspect of an embodiment, a semiconductor device includes a substrate including a first surface and a second surface opposite to each other, a plurality of unit static random access memory (SRAM) cells arranged in a matrix on the first surface along a first direction and a second direction crossing each other, a first word line extending along the first direction on the first surface, and a second word line extending along the first direction on the second surface. The plurality of unit SRAM cells includes first unit SRAM cells arranged in a first row and second unit SRAM cells arranged in a second row, each of the first row and the second row extending along the first direction. The first word line is commonly connected to the first unit SRAM cells of the first row. The second word line is commonly connected to the second unit SRAM cells of the second row.

[0010] According to another aspect of an embodiment, a semiconductor device includes: a first unit and a second unit adjacent to each other along a first direction; a substrate including a first surface and a second surface opposite to each other; first to fourth active patterns arranged sequentially along a second direction intersecting the first direction, each of the first to fourth active patterns extending along the first direction on the first surface; a first gate structure extending along the second direction in the first unit to intersect the first active pattern; a second gate structure extending along the second direction in the first unit to intersect the third and fourth active patterns; a third gate structure extending along the second direction in the first unit to intersect the first and second active patterns; a fourth gate structure extending along the second direction in the first unit to intersect the fourth active pattern; a first source / drain contact connecting the first active pattern with the second active pattern and the second gate structure between the first and third gate structures and between the second and third gate structures; a second source / drain contact connecting the third active pattern with the fourth active pattern and the third gate structure between the second and third gate structures and between the second and fourth gate structures; a fifth gate structure extending along the second direction in the second unit to intersect the first active pattern; a sixth gate structure extending along the second direction in the second unit to intersect the third and fourth active patterns; a seventh gate structure extending along the second direction in the second unit to intersect the first and second active patterns; an eighth gate structure extending along the second direction in the second unit to intersect the fourth active pattern; a third source / drain contact connecting the first active pattern with the second active pattern and the sixth gate structure between the fifth and seventh gate structures and between the sixth and seventh gate structures; a fourth source / drain contact connecting the third active pattern with the fourth active pattern and the seventh gate structure between the sixth and seventh gate structures and between the sixth and eighth gate structures; a first front wiring pattern extending along the second direction on the first surface and connected to the first and fourth gate structures; and a first back wiring pattern extending along the second direction on the second surface and connected to the fifth and eighth gate structures. BRIEF DESCRIPTION OF DRAWINGS

[0011] The above and other aspects and features will become more apparent from the following description of embodiments taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a block diagram illustrating a semiconductor device according to some embodiments.

[0013] Figure 2 is a circuit diagram illustrating a semiconductor device according to some embodiments.

[0014] Figure 3 is a layout view illustrating a semiconductor device according to some embodiments.

[0015] Figure 4 is a schematic cross-sectional view taken along line A-A of Figure 3

[0016] Figure 5 is a schematic cross-sectional view taken along line B-B of Figure 3

[0017] Figure 6 is a schematic cross-sectional view taken along line C-C of Figure 3

[0018] Figure 7 is a schematic cross-sectional view taken along line D-D of Figure 3

[0019] Figure 8 is a schematic cross-sectional view taken along line E-E of Figure 3

[0020] Figure 9 to Figure 11 is a layout view illustrating a semiconductor device according to some embodiments.

[0021] Figure 12 is a layout view illustrating a semiconductor device according to some embodiments.

[0022] Figure 13 is a schematic cross-sectional view taken along line F-F of Figure 12

[0023] Figure 14 is a schematic cross-sectional view taken along line G-G of Figure 12

[0024] Figure 15 is a circuit view illustrating a semiconductor device according to some embodiments.

[0025] Figure 16 is a layout view illustrating a semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0026] ​​​​​​​Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Like reference numerals are used to refer to like elements throughout the specification and a repeated description is omitted. It will be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on another element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" another element or layer, there are no intervening elements or layers present. Embodiments described herein are example embodiments, thus the present disclosure is not limited thereto and can be implemented in various other forms. Each of the embodiments provided in the following description are not mutually exclusive, with reference to one or more features associated with another example or another embodiment also provided herein or not provided herein but consistent with the present disclosure. It is to be understood that the terms first, second, etc. can be used herein to describe various elements, but the elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, for example, a first element, a first component, or a first part discussed below could be termed a second element, a second component, or a second part without departing from the teachings of the present disclosure.

[0027] Figure 1 is a block diagram illustrating a semiconductor device according to some embodiments.

[0028] Referring to Figure 1 A semiconductor device according to some embodiments includes a plurality of unit static random access memory (SRAM) cells MC, a first word line WL1, a second word line WL2, a bit line BL, and a complementary bit line / BL.

[0029] The plurality of unit SRAM cells MC can be arranged two-dimensionally. For example, the plurality of unit SRAM cells MC can be arranged in a matrix form along a first direction X and a second direction Y that cross each other.

[0030] The plurality of unit SRAM cells MC can include a first row R1 and a second row R2. Each of the first row R1 and the second row R2 can include a row of unit SRAM cells MC arranged along the first direction X. The first row R1 and the second row R2 can be arranged along the second direction Y. In some embodiments, the first row R1 and the second row R2 can be alternately arranged along the second direction Y. In this regard, the semiconductor device can include a plurality of first word lines WL1 and a plurality of second word lines WL2 alternately disposed along the second direction Y.

[0031] Each of the first word line WL1 and the second word line WL2 can extend in the first direction X. The first word line WL1 can be commonly connected to the unit SRAM cells MC of the first row R1. The second word line WL2 can be commonly connected to the unit SRAM cells MC of the second row R2. In some embodiments, the first word line WL1 and the second word line WL2 can be alternately arranged along the second direction Y.

[0032] The bit line BL and the complementary bit line / BL can extend in parallel in the second direction Y. One bit line BL and one complementary bit line / BL adjacent to each other can form a pair. A pair of the bit line BL and the complementary bit line / BL can extend in the second direction Y, and thus can be commonly connected to the unit SRAM cells MC of a column of the plurality of unit SRAM cells MC arranged along the second direction Y. For example, a pair of the bit line BL and the complementary bit line / BL can be commonly connected to the first row R1 and the second row R2.

[0033] Figure 2 is a circuit diagram illustrating a semiconductor device according to some embodiments.

[0034] Referring to Figure 1 and Figure 2 , a semiconductor device according to some embodiments includes a first cell MC1 and a second cell MC2 adjacent to each other.

[0035] Each of the first cell MC1 and the second cell MC2 can correspond to one of a plurality of unit SRAM cells MC. The first cell MC1 and the second cell MC2 can be adjacent to each other in the second direction Y. The first cell MC1 can be one of the plurality of unit SRAM cells MC in the first row R1. The second cell MC2 can be one of the plurality of unit SRAM cells MC in the second row R2.

[0036] Each of the first cell MC1 and the second cell MC2 can include a pair of inverters INV1 and INV2 connected in parallel between a power supply node V DD and a ground node V SS , and a first pass transistor PS1 and a second pass transistor PS2 connected to an output node of the inverters INV1 and INV2.

[0037] To configure one latch circuit, an input node of the first inverter INV1 can be connected to an output node of the second inverter INV2, and an input node of the second inverter INV2 can be connected to an output node of the first inverter INV1.

[0038] The first inverter INV1 can include a first transistor T1 and a second transistor T2 connected in series between the power supply node V DD and the ground node V SSa first pull-down transistor PD1 between the first pull-up transistor PU1 and the ground node VSS. The second inverter INV2 can include a second pull-up transistor PU2 and a second pull-down transistor PD2 connected in series between the power supply node VDD and the ground node VSS. Each of the first pull-up transistor PU1 and the second pull-up transistor PU2 can be a P-type field effect transistor (PFET), and each of the first pull-down transistor PD1 and the second pull-down transistor PD2 can be an N-type field effect transistor (NFET). DD between the first pull-up transistor PU1 and the ground node VSS SS between the first pull-up transistor PU1 and the ground node VSS

[0039] The first pass transistor PS1 can connect the bit line BL to an output node of the first inverter INV1. The second pass transistor PS2 can connect the complementary bit line / BL to an output node of the second inverter INV2.

[0040] The first word line WL1 can be connected to a gate of the first pass transistor PS1 of the first cell MC1 and a gate of the second pass transistor PS2 of the first cell MC1. The second word line WL2 can be connected to a gate of the first pass transistor PS1 of the second cell MC2 and a gate of the second pass transistor PS2 of the second cell MC2.

[0041] Figure 3 is a layout diagram illustrating a semiconductor device according to some embodiments. Figure 4 is a schematic cross-sectional view taken along line A-A of Figure 3 . Figure 5 is a schematic cross-sectional view taken along line B-B of Figure 3 . Figure 6 is a schematic cross-sectional view taken along line C-C of Figure 3 .

[0042] Figure 7 is a schematic cross-sectional view taken along line D-D of Figure 3 . Figure 8 is a schematic cross-sectional view taken along line E-E of Figure 3 .

[0043] Referring to Figure 1 to Figure 8 , a semiconductor device according to some embodiments includes a device region DR, a front region FR, and a back region BR.

[0044] The device region DR can include the first and second cells MC1 and MC2 formed on the substrate 100. The first and second cells MC1 and MC2 can be adjacent to each other in the second direction Y. The device region DR can include the substrate 100, the field insulating film 105, the first to fourth active patterns AP1 to AP4, the first to eighth gate structures GS1 to GS8, the first to fourth source / drain regions 161 to 164, the first to tenth source / drain contacts 170 to 179, the first and second interlayer insulating films ID1 and ID2.

[0045] The substrate 100 can be bulk silicon or silicon-on-insulator (SOI). Alternatively, the substrate 100 can be a silicon substrate, or can include another material such as silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. The substrate 100 can be formed by etching a portion of a base substrate, or can be an epitaxial layer formed on a base substrate.

[0046] In some embodiments, the substrate 100 can be an insulating substrate including an insulating material. For example, the substrate 100 can include at least one of silicon oxide, silicon oxynitride, and combinations thereof, although embodiments are not limited thereto. For example, the substrate 100 can include a silicon oxide film.

[0047] The substrate 100 can include a first surface 100a and a second surface 100b opposite to each other. In the following description, the first surface 100a can also be referred to as a front surface of the substrate 100, and the second surface 100b can also be referred to as a back surface of the substrate 100.

[0048] The first to fourth active patterns AP1 to AP4 can be formed on the first surface 100a. The first to fourth active patterns AP1 to AP4 can be arranged in order along the first direction X. The first to fourth active patterns AP1 to AP4 can be longer in the second direction and can be spaced apart from each other in the first direction X. The first to fourth active patterns AP1 to AP4 can extend over the first and second cells MC1 and MC2, respectively.

[0049] Each of the first to fourth active patterns AP1 to AP4 can include silicon (Si) or germanium (Ge), which is an elemental semiconductor material. Alternatively, each of the first to fourth active patterns AP1 to AP4 can include a compound semiconductor, such as a Group IV-IV compound semiconductor or a Group III-V compound semiconductor. The Group IV-IV compound semiconductor can be a binary compound or a ternary compound including at least two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or a compound including at least two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn) doped with a Group IV element. The Group III-V compound semiconductor can be, for example, one of binary, ternary, and quaternary compounds formed by combining at least one of aluminum (Al), gallium (Ga), and indium (In) as a Group III element with at least one of phosphorus (P), arsenic (As), and antimony (Sb) as a Group V element.

[0050] In some embodiments, the first active pattern AP1 and the fourth active pattern AP4 can be used as channel regions of NFETs, and the second active pattern AP2 and the third active pattern AP3 can be used as channel regions of PFETs.

[0051] In some embodiments, each of the first to fourth active patterns AP1 to AP4 can include a plurality of bridge patterns 111 to 113 located on the substrate 100. The plurality of bridge patterns 111 to 113 can be sequentially stacked along a vertical direction (e.g., a third direction Z crossing the first direction X and the second direction Y), and thus can be spaced apart from each other. The first to fourth active patterns AP1 to AP4 can be used as channel regions of a multi-bridge channel field effect transistor including a multi-bridge channel. The number of bridge patterns 111 to 113 included in each of the first to fourth active patterns AP1 to AP4 is provided by way of example, and embodiments are not limited to the illustrated example.

[0052] In some embodiments, a fin pattern 110 can be formed between the substrate 100 and the bridge patterns 111 to 113. The fin pattern 110 can protrude from the first surface 100a of the substrate 100 and extend along the second direction Y, and in some embodiments, the fin pattern 110 can be an insulating pattern including an insulating material.

[0053] In some embodiments, the second active pattern AP2 of the first cell MC1 can be separated from the second active pattern AP2 of the second cell MC2. For example, a separation pattern AC can be formed between the second active pattern AP2 of the first cell MC1 and the second active pattern AP2 of the second cell MC2. The separation pattern AC can extend in the first direction X at the boundary between the first cell MC1 and the second cell MC2 to separate the second active pattern AP2 of the first cell MC1 from the second active pattern AP2 of the second cell MC2.

[0054] The separation pattern AC can include an insulating material, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbon nitride, silicon oxycarbonitride, and combinations thereof, but embodiments are not limited thereto.

[0055] In some embodiments, the first to fourth active patterns AP1 to AP4 can be arranged in a planar symmetric relationship with respect to a boundary surface (e.g., the XZ plane) between the first cell MC1 and the second cell MC2.

[0056] A field insulating film 105 can be formed on the substrate 100. In some embodiments, the field insulating film 105 can cover at least a portion of one side of the fin pattern 110. The field insulating film 105 can include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof, but embodiments are not limited thereto.

[0057] First to eighth gate structures GS1 to GS8 can be formed on the substrate 100 and the field insulating film 105. Each of the first to eighth gate structures GS1 to GS8 can extend longer in the first direction X. The first to eighth gate structures GS1 to GS8 can cross the first to fourth active patterns AP1 to AP4. For example, the bridge patterns 111 to 113 can extend in the second direction Y to pass through the first to eighth gate structures GS1 to GS8. The first to fourth gate structures GS1 to GS4 can be provided in the first cell MC1. The fifth to eighth gate structures GS5 to GS8 can be provided in the second cell MC2.

[0058] The first gate structure GS1 can cross the first active pattern AP1. The first gate structure GS1 can be provided as a gate of a first pass transistor PS1 of the first cell MC1. That is, a region of the first active pattern AP1 that crosses the first gate structure GS1 can be provided as a channel region of the first pass transistor PS1 of the first cell MC1.

[0059] The second gate structure GS2 can be spaced apart from the first gate structure GS1 in the first direction X. The second gate structure GS2 can cross the third active pattern AP3 and the fourth active pattern AP4. The second gate structure GS2 can be provided as a gate of a second inverter INV2 of the first cell MC1. For example, a region of the third active pattern AP3 crossing the second gate structure GS2 can be provided as a channel region of a second pull-up transistor PU2 of the first cell MC1, and a region of the fourth active pattern AP4 crossing the second gate structure GS2 can be provided as a channel region of a second pull-down transistor PD2 of the first cell MC1.

[0060] The third gate structure GS3 can be spaced apart from the first gate structure GS1 and the second gate structure GS2 in the second direction Y. The third gate structure GS3 can cross the first active pattern AP1 and the second active pattern AP2. The third gate structure GS3 can be provided as a gate of a first inverter INV1 of the first cell MC1. For example, a region of the first active pattern AP1 crossing the third gate structure GS3 can be provided as a channel region of a first pull-down transistor PD1 of the first cell MC1, and a region of the second active pattern AP2 crossing the third gate structure GS3 can be provided as a channel region of a first pull-up transistor PU1 of the first cell MC1.

[0061] The fourth gate structure GS4 can be spaced apart from the third gate structure GS3 in the first direction X. The fourth gate structure GS4 can cross the fourth active pattern AP4. The fourth gate structure GS4 can be provided as a gate of a second pass transistor PS2 of the first cell MC1. That is, a region of the fourth active pattern AP4 crossing the fourth gate structure GS4 can be provided as a channel region of the second pass transistor PS2 of the first cell MC1.

[0062] The fifth gate structure GS5 can cross the first active pattern AP1. The fifth gate structure GS5 can be provided as a gate of a first pass transistor PS1 of the second cell MC2. That is, a region of the first active pattern AP1 crossing the fifth gate structure GS5 can be provided as a channel region of the first pass transistor PS1 of the second cell MC2.

[0063] The sixth gate structure GS6 can be spaced apart from the fifth gate structure GS5 in the first direction X. The sixth gate structure GS6 can cross the third active pattern AP3 and the fourth active pattern AP4. The sixth gate structure GS6 can be provided as a gate of a second inverter INV2 of the second cell MC2. For example, a region of the third active pattern AP3 crossing the sixth gate structure GS6 can be provided as a channel region of a second pull-up transistor PU2 of the second cell MC2, and a region of the fourth active pattern AP4 crossing the sixth gate structure GS6 can be provided as a channel region of a second pull-down transistor PD2 of the second cell MC2.

[0064] The seventh gate structure GS7 can be spaced apart from the fifth gate structure GS5 and the sixth gate structure GS6 in the second direction Y. The seventh gate structure GS7 can cross the first active pattern AP1 and the second active pattern AP2. The seventh gate structure GS7 can be provided as a gate of a first inverter INV1 of the second cell MC2. For example, a region of the first active pattern AP1 crossing the seventh gate structure GS7 can be provided as a channel region of a first pull-down transistor PD1 of the second cell MC2, and a region of the second active pattern AP2 crossing the seventh gate structure GS7 can be provided as a channel region of a first pull-up transistor PU1 of the second cell MC2.

[0065] The eighth gate structure GS8 can be spaced apart from the seventh gate structure GS7 in the first direction X. The eighth gate structure GS8 can cross the fourth active pattern AP4. The eighth gate structure GS8 can be provided as a gate of a second pass transistor PS2 of the second cell MC2. That is, a region of the fourth active pattern AP4 crossing the eighth gate structure GS8 can be provided as a channel region of the second pass transistor PS2 of the second cell MC2.

[0066] In some embodiments, a width of each of the first cell MC1 and the second cell MC2 in the second direction Y can be about 2 contacted poly pitches (CPP). In this case, the CPP refers to a unit arrangement spacing between gate structures arranged along the second direction Y. For example, 1 CPP can be defined as a sum of a spacing between gate structures (e.g., the first gate structure GS1 and the third gate structure GS3) adjacent to each other in the second direction Y and a width of one of the gate structures (e.g., the first gate structure GS1). Alternatively, for example, 1 CPP can be defined as a spacing between a center line of one gate structure (e.g., the first gate structure GS1) and a center line of another gate structure (e.g., the third gate structure GS3) adjacent thereto along the second direction Y, the center lines extending in the first direction X.

[0067] Each of the first to eighth gate structures GS1 to GS8 can include a gate dielectric film 120, a gate electrode 130, a gate spacer 140, and a gate capping layer 150.

[0068] The gate dielectric film 120 can be interposed between each of the first to fourth active patterns AP1 to AP4 and the gate electrode 130. The gate dielectric film 120 can be interposed between the field insulating film 105 and the gate electrode 130. In some embodiments, the gate dielectric film 120 can be interposed between the fin pattern 110 and the gate electrode 130.

[0069] The gate dielectric film 120 can include, for example, at least one of silicon oxide, silicon oxynitride, silicon nitride, and a high dielectric constant material (i.e., a high-k dielectric) having a dielectric constant greater than that of silicon oxide. The high dielectric constant material can include, for example, hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), titanium oxide (TiO2), strontium titanium oxide (SrTiO3), lanthanum aluminum oxide (LaAlO3), yttrium oxide (Y2O3), hafnium oxynitride (HfON), zirconium oxynitride (ZrON), lanthanum oxynitride (La2ON), aluminum oxynitride (Al2ON), titanium oxynitride (TiON), strontium titanium oxynitride (SrTiON), lanthanum aluminum oxynitride (LaAlON), yttrium oxynitride (Y2ON), or a combination thereof, but embodiments are not limited thereto. x N y ), zirconium oxynitride (ZrO x N y ), lanthanum oxynitride (La2O x N y ), aluminum oxynitride (Al2O x N y ), titanium oxynitride (TiO x N y ), strontium titanium oxynitride (SrTiO x N y ), lanthanum aluminum oxynitride (LaAlO x N y ), yttrium oxynitride (Y2O x N y ), or a combination thereof, but embodiments are not limited thereto.

[0070] In some embodiments, the gate dielectric film 120 can include an interface film 122 and a high-k dielectric film 124 sequentially stacked on the first to fourth active patterns AP1 to AP4.

[0071] The interface film 122 can surround a periphery of each of the bridge patterns 111 to 113. For example, the interface film 122 can conformingly extend along the periphery of each of the bridge patterns 111 to 113. The interface film 122 can extend along a surface of the fin pattern 110 exposed from the field insulating film 105. In some embodiments, the interface film 122 can include an oxide film formed by oxidizing a surface of each of the bridge patterns 111 to 113. For example, when each of the bridge patterns 111 to 113 is a silicon (Si) pattern, the interface film 122 can include a silicon oxide film.

[0072] The high-k dielectric film 124 can surround a periphery of the interface film 122. In some embodiments, a portion of the high-k dielectric film 124 can be interposed between the gate electrode 130 and the gate spacer 140. For example, the high-k dielectric film 124 can conformingly extend along the periphery of the interface film 122 and a contour of the inner side of the gate spacer 140. Further, the high-k dielectric film 124 can further extend along an upper surface of the field insulating film 105. The high-k dielectric film 124 can include a high dielectric constant material having a dielectric constant greater than that of silicon oxide.

[0073] The gate electrode 130 can be longer in the first direction X to cross the first to fourth active patterns AP1 to AP4. Each of the bridge patterns 111 to 113 can extend in the second direction Y to pass through the gate electrode 130. The gate electrode 130 can include a conductive material, for example, at least one of TiN, WN, TaN, Ru, TiC, TaC, Ti, Ag, Al, TiAl, TiAlN, TiAlC, TaCN, TaSiN, Mn, Zr, W, and combinations thereof, although embodiments are not limited thereto. The gate electrode 130 can be formed by a replacement process, although embodiments are not limited thereto.

[0074] The gate electrode 130 is illustrated as a single layer only, although embodiments are not limited thereto. For example, the gate electrode 130 can be a multi-layer formed by stacking a plurality of conductive layers. For example, the gate electrode 130 can include a work function adjusting layer for adjusting a work function and a filling conductive layer for filling a space formed by the work function adjusting layer. The work function adjusting layer can include, for example, at least one of TiN, TaN, TiC, TaC, TiAlC, and combinations thereof. The filling conductive layer can include, for example, W or Al.

[0075] The gate spacer 140 can extend along a side of the gate electrode 130. Each of the bridge patterns 111 to 113 can extend in the second direction Y to pass through the gate spacer 140. The gate spacer 140 can include an insulating material, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbon nitride, silicon boron carbon oxynitride, and combinations thereof, although embodiments are not limited thereto.

[0076] The gate capping layer 150 can extend along the upper surface of the gate electrode 130. The gate capping layer 150 can include an insulating material, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbon nitride, silicon carbon oxynitride, and a combination thereof, but embodiments are not limited thereto.

[0077] In some embodiments, each of the first to eighth gate structures GS1 to GS8 can further include an inner spacer 145. The inner spacer 145 can be formed on one side of the gate electrode 130 between the bridge patterns 111 to 113. The inner spacer 145 can be formed on one side of the gate electrode 130 between the fin pattern 110 and the bridge patterns 111 to 113. The inner spacer 145 can include an insulating material, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbon nitride, silicon carbon oxynitride, and a combination thereof, but embodiments are not limited thereto.

[0078] In some embodiments, the first to eighth gate structures GS1 to GS8 can be separated by a cut pattern GC. For example, the cut pattern GC can extend along the second direction Y between the first and second active patterns AP1 and AP2 to separate the first gate structure GS1 from the second gate structure GS2 and separate the fifth gate structure GS5 from the sixth gate structure GS6. For example, the cut pattern GC can extend along the second direction Y between the third and fourth active patterns AP3 and AP4 in the first memory cell MC1 to separate the third gate structure GS3 from the fourth gate structure GS4. For example, the cut pattern GC can extend along the second direction Y between the third and fourth active patterns AP3 and AP4 in the second cell MC2 to separate the seventh gate structure GS7 from the eighth gate structure GS8.

[0079] The cut pattern GC can include an insulating material, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbon nitride, silicon carbon oxynitride, and a combination thereof, but embodiments are not limited thereto.

[0080] In some embodiments, the first to eighth gate structures GS1 to GS8 can be arranged in a planar symmetric relationship with respect to a boundary surface (e.g., the XZ plane) between the first and second cells MC1 and MC2.

[0081] The first to fourth source / drain regions 161 to 164 can be formed in the first to fourth active patterns AP1 to AP4, respectively. In this specification, the first to fourth source / drain regions 161 to 164 can be described as elements included in the first to fourth active patterns AP1 to AP4, or can be described as separate elements different from the first to fourth active patterns AP1 to AP4.

[0082] For example, the first active pattern AP1 can include the first source / drain region 161. The first source / drain region 161 can be formed at side surfaces of the first, third, fifth, and seventh gate structures GS1, GS3, GS5, and GS7 in the first active pattern AP1.

[0083] For example, the second active pattern AP2 can include the second source / drain region 162. The second source / drain region 162 can be formed at side surfaces of the second, third, sixth, and seventh gate structures GS2, GS3, GS6, and GS7 in the second active pattern AP2.

[0084] For example, the third active pattern AP3 can include the third source / drain region 163. The third source / drain region 163 can be formed at side surfaces of the second, third, sixth, and seventh gate structures GS2, GS3, GS6, and GS7 in the third active pattern AP3.

[0085] For example, the fourth active pattern AP4 can include the fourth source / drain region 164. The fourth source / drain region 164 can be formed at side surfaces of the second, fourth, sixth, and eighth gate structures GS2, GS4, GS6, and GS8 in the fourth active pattern AP4.

[0086] Each of the bridge patterns 111 to 113 can be connected to the first to fourth source / drain regions 161 to 164 by passing through the gate electrode 130 and the gate spacer 140. The first to fourth source / drain regions 161 to 164 can be separated from the gate electrode 130 by the gate dielectric film 120, the gate spacer 140, and / or the inner spacer 145.

[0087] In some embodiments, each of the first to fourth source / drain regions 161 to 164 can include an epitaxial layer doped with impurities. For example, each of the first to fourth source / drain regions 161 to 164 can include an epitaxial pattern grown from the first to fourth active patterns AP1 to AP4 by an epitaxial growth method.

[0088] When the first active pattern AP1 and the fourth active pattern AP4 are channel regions of NFETs, the first source / drain region 161 and the fourth source / drain region 164 can include an N-type impurity (e.g., P, Sb, or As) or an impurity for preventing diffusion of the N-type impurity.

[0089] When the second active pattern AP2 and the third active pattern AP3 are channel regions of PFETs, each of the second source / drain region 162 and the third source / drain region 163 can include a P-type impurity (e.g., B, In, Ga, or Al) or an impurity for preventing diffusion of the P-type impurity.

[0090] The first source / drain contact 170 through the tenth source / drain contact 179 can be connected to the first source / drain region 161 through the fourth source / drain region 164. Accordingly, the first source / drain contact 170 through the tenth source / drain contact 179 can be electrically connected to the first active pattern AP1 through the fourth active pattern AP4. The shape and arrangement of the first source / drain contact 170 through the tenth source / drain contact 179 are provided as an example, and embodiments are not limited to the illustrated example.

[0091] The first source / drain contact 170 can be connected to the first active pattern AP1. For example, the first source / drain contact 170 can contact the first source / drain region 161 between the first gate structure GS1 and the fifth gate structure GS5. In some embodiments, the first source / drain contact 170 can be disposed at a boundary between the first cell MC1 and the second cell MC2. The first cell MC1 and the second cell MC2 can share the first source / drain contact 170.

[0092] The second source / drain contact 171 can be interposed between the first gate structure GS1 and the third gate structure GS3, and between the second gate structure GS2 and the third gate structure GS3. The second source / drain contact 171 can connect the first active pattern AP1 with the second active pattern AP2. For example, the second source / drain contact 171 can extend in the first direction X to contact the first source / drain region 161 and the second source / drain region 162.

[0093] The second source / drain contact 171 can be electrically connected to the second gate structure GS2. For example, a first shared contact SC1 can be formed on the second gate structure GS2 and the second source / drain contact 171. The first shared contact SC1 can extend in the second direction Y to connect the gate electrode 130 of the second gate structure GS2 with the second source / drain contact 171. The output node (i.e., the second source / drain contact 171) of the first inverter INV1 of the first cell MC1 can be connected to the input node (i.e., the second gate structure GS2) of the second inverter INV2 of the first cell MC1 through the first shared contact SC1.

[0094] The third source / drain contact 172 can be connected to the second active pattern AP2. For example, the third source / drain contact 172 can be in contact with the second source / drain region 162 on one side of the third gate structure GS3. The third gate structure GS3 can be interposed between the second source / drain contact 171 and the third source / drain contact 172.

[0095] The fourth source / drain contact 173 can be interposed between the second gate structure GS2 and the third gate structure GS3, and between the second gate structure GS2 and the fourth gate structure GS4. The fourth source / drain contact 173 can connect the third active pattern AP3 with the fourth active pattern AP4. For example, the fourth source / drain contact 173 can extend in the first direction X to contact the third source / drain region 163 and the fourth source / drain region 164.

[0096] The fourth source / drain contact 173 can be electrically connected to the third gate structure GS3. For example, a second shared contact SC2 can be formed on the third gate structure GS3 and the fourth source / drain contact 173. The second shared contact SC2 can extend in the second direction Y to connect the gate electrode 130 of the third gate structure GS3 with the fourth source / drain contact 173. The output node (i.e., the fourth source / drain contact 173) of the second inverter INV2 of the first cell MC1 can be connected to the input node (i.e., the third gate structure GS3) of the first inverter INV1 of the first cell MC1 through the second shared contact SC2.

[0097] The fifth source / drain contact 174 can be connected to the fourth active pattern AP4. For example, the fifth source / drain contact 174 can be in contact with the fourth source / drain region 164 on one side of the fourth gate structure GS4. The fourth gate structure GS4 can be interposed between the fourth source / drain contact 173 and the fifth source / drain contact 174.

[0098] The sixth source / drain contact 175 can be connected to the third active pattern AP3. For example, the sixth source / drain contact 175 can contact the third source / drain region 163 between the second gate structure GS2 and the sixth gate structure GS6. In some embodiments, the sixth source / drain contact 175 can be disposed at a boundary between the first cell MC1 and the second cell MC2. The first cell MC1 and the second cell MC2 can share the sixth source / drain contact 175.

[0099] The seventh source / drain contact 176 can be interposed between the fifth gate structure GS5 and the seventh gate structure GS7, and between the sixth gate structure GS6 and the seventh gate structure GS7. The seventh source / drain contact 176 can connect the first active pattern AP1 with the second active pattern AP2. For example, the seventh source / drain contact 176 can extend in the first direction X to contact both the first source / drain region 161 and the second source / drain region 162.

[0100] The seventh source / drain contact 176 can be electrically connected to the sixth gate structure GS6. For example, a third shared contact SC3 can be formed on the sixth gate structure GS6 and the seventh source / drain contact 176. The third shared contact SC3 can extend in the second direction Y to connect the gate electrode 130 of the sixth gate structure GS6 with the seventh source / drain contact 176. An output node (i.e., the seventh source / drain contact 176) of the first inverter INV1 of the second cell MC2 can be connected to an input node (i.e., the sixth gate structure GS6) of the second inverter INV2 of the second cell MC2 through the third shared contact SC3.

[0101] The eighth source / drain contact 177 can be connected to the second active pattern AP2. For example, the eighth source / drain contact 177 can contact the second source / drain region 162 on a side of the seventh gate structure GS7. The seventh gate structure GS7 can be interposed between the seventh source / drain contact 176 and the eighth source / drain contact 177.

[0102] The ninth source / drain contact 178 can be interposed between the sixth gate structure GS6 and the seventh gate structure GS7, and between the sixth gate structure GS6 and the eighth gate structure GS8. The ninth source / drain contact 178 can connect the third active pattern AP3 with the fourth active pattern AP4. For example, the ninth source / drain contact 178 can extend in the first direction X to contact the third source / drain region 163 and the fourth source / drain region 164.

[0103] The ninth source / drain contact 178 can be electrically connected to the seventh gate structure GS7. For example, a fourth shared contact SC4 can be formed on the seventh gate structure GS7 and the ninth source / drain contact 178. The fourth shared contact SC4 can extend in the second direction Y to connect the gate electrode 130 of the seventh gate structure GS7 with the ninth source / drain contact 178. The output node of the second inverter INV2 of the second cell MC2 (i.e., the ninth source / drain contact 178) can be connected to the input node of the first inverter INV1 of the second cell MC2 (i.e., the seventh gate structure GS7) through the fourth shared contact SC4.

[0104] The tenth source / drain contact 179 can be connected to the fourth active pattern AP4. For example, the tenth source / drain contact 179 can be in contact with the fourth source / drain region 164 on one side of the eighth gate structure GS8. The eighth gate structure GS8 can be interposed between the ninth source / drain contact 178 and the tenth source / drain contact 179.

[0105] The first interlayer insulating film ID1 can fill spaces on sides of the first to eighth gate structures GS1 to GS8. For example, the first interlayer insulating film ID1 can cover the first to fourth source / drain regions 161 to 164. The second interlayer insulating film ID2 can be formed on the first to eighth gate structures GS1 to GS8 and the first interlayer insulating film ID1.

[0106] Each of the first and second interlayer insulating films ID1 and ID2 can include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, silicon boron oxycarbonitride, and a low dielectric constant material (i.e., low-k dielectric) having a lower dielectric constant than that of silicon oxide, but embodiments are not limited thereto.

[0107] The front region FR can be formed on the first surface 100a of the substrate 100. The front region FR can include a first-stage front wiring FM1 and a second-stage front wiring FM2. For example, an inter-wiring insulating layer 200 can be formed on the second interlayer insulating film ID2. The first-stage front wiring FM1 and the second-stage front wiring FM2 can be formed in the inter-wiring insulating layer 200 to form an electrical path.

[0108] The first-level front surface wiring FM1 and the second-level front surface wiring FM2 can be sequentially stacked on the first surface 100a of the substrate 100. That is, the second-level front surface wiring FM2 can be provided at a higher level than the first-level front surface wiring FM1. In the front region FR, "provided at a higher level" means "provided further away from the substrate 100 in the third direction Z". For example, in the third direction Z, the second-level front surface wiring FM2 can be spaced further away from the first surface 100a than the first-level front surface wiring FM1.

[0109] In some embodiments, the first-level front surface wiring FM1 can include a first front surface wiring pattern 211 to a fifth front surface wiring pattern 215. The first front surface wiring pattern 211 to the fifth front surface wiring pattern 215 can be provided at the same level. The first front surface wiring pattern 211 to the fifth front surface wiring pattern 215 can be sequentially arranged along the first direction X. Each of the first front surface wiring pattern 211 to the fifth front surface wiring pattern 215 can extend longer in the second direction Y.

[0110] The first front surface wiring pattern 211 can be connected to the first gate structure GS1. For example, a first gate contact 191 can be formed which contacts the gate electrode 130 of the first gate structure GS1 by passing through the second interlayer insulating film ID2 and the gate capping layer 150. The first front surface wiring pattern 211 can be connected to the first gate structure GS1 through the first gate contact 191.

[0111] The second front surface wiring pattern 212 can be connected to the first source / drain contact 170. For example, a first contact via 180 can be formed which contacts the first source / drain contact 170 by passing through the second interlayer insulating film ID2. The second front surface wiring pattern 212 can be connected to the first source / drain contact 170 through the first contact via 180.

[0112] In some embodiments, the second front surface wiring pattern 212 can extend longer in the second direction Y beyond the first cell MC1 and the second cell MC2. The second front surface wiring pattern 212 can be provided as a bit line BL and can be commonly connected to the first pass transistor PS1 of the first cell MC1 and the first pass transistor PS1 of the second cell MC2.

[0113] The third front side wiring pattern 213 can be connected to the third source / drain contact 172, the sixth source / drain contact 175, and the eighth source / drain contact 177. For example, a second contact via 182 that contacts the third source / drain contact 172 by passing through the second interlayer insulating film ID2 can be formed, a third contact via 185 that contacts the sixth source / drain contact 175 by passing through the second interlayer insulating film ID2 can be formed, and a fourth contact via 187 that contacts the eighth source / drain contact 177 by passing through the second interlayer insulating film ID2 can be formed. The third front side wiring pattern 213 can be connected to the third source / drain contact 172 through the second contact via 182, can be connected to the sixth source / drain contact 175 through the third contact via 185, and can be connected to the eighth source / drain contact 177 through the fourth contact via 187.

[0114] In some embodiments, the third front side wiring pattern 213 can extend longer in the second direction Y beyond the first cell MC1 and the second cell MC2. The third front side wiring pattern 213 can be provided as a first power supply line for applying a first power supply voltage (e.g., VDD) to the first pull-up transistor PU1 and the second pull-up transistor PU2. DD ) to the first pull-up transistor PU1 and the second pull-up transistor PU2.

[0115] The fourth front side wiring pattern 214 can be connected to the fifth source / drain contact 174 and the tenth source / drain contact 179. For example, a fifth contact via 184 that contacts the fifth source / drain contact 174 by passing through the second interlayer insulating film ID2 can be formed, and a sixth contact via 189 that contacts the tenth source / drain contact 179 by passing through the second interlayer insulating film ID2 can be formed. The fourth front side wiring pattern 214 can be connected to the fifth source / drain contact 174 through the fifth contact via 184, and can be connected to the tenth source / drain contact 179 through the sixth contact via 189.

[0116] In some embodiments, the fourth front side wiring pattern 214 can extend longer in the second direction Y beyond the first cell MC1 and the second cell MC2. The fourth front side wiring pattern 214 can be provided as a complementary bit line / BL, and can be commonly connected to the second transfer transistor PS2 of the first cell MC1 and the second transfer transistor PS2 of the second cell MC2.

[0117] The fifth front surface wiring pattern 215 can be connected to the fourth gate structure GS4. For example, a second gate contact 194 can be formed that contacts the gate electrode 130 of the fourth gate structure GS4 through the second interlayer insulating film ID2 and the gate capping layer 150. The fifth front surface wiring pattern 215 can be connected to the gate electrode 130 of the fourth gate structure GS4 through the second gate contact 194.

[0118] In some embodiments, the second-stage front surface wiring FM2 can include a sixth front surface wiring pattern 230. The sixth front surface wiring pattern 230 can extend longer in the first direction X.

[0119] The sixth front surface wiring pattern 230 can be connected to the first front surface wiring pattern 211 and the fifth front surface wiring pattern 215. For example, a first front surface via pattern 221 connecting the first front surface wiring pattern 211 and the sixth front surface wiring pattern 230 can be formed, and a second front surface via pattern 225 connecting the fifth front surface wiring pattern 215 and the sixth front surface wiring pattern 230 can be formed.

[0120] In some embodiments, the sixth front surface wiring pattern 230 can extend longer in the first direction X beyond the first cell MC1 and the second cell MC2. The sixth front surface wiring pattern 230 can be provided as the first word line WL1, and can be commonly connected to the gate of the first pass transistor PS1 of the first cell MC1 (i.e., the first gate structure GS1) and the gate of the second pass transistor PS2 of the first cell MC1 (i.e., the fourth gate structure GS4).

[0121] In some embodiments, the sixth front surface wiring pattern 230 can be formed above the first cell MC1 and the second cell MC2. For example, the sixth front surface wiring pattern 230 can overlap both the first cell MC1 and the second cell MC2 in the third direction Z.

[0122] In some embodiments, the width W1 of the sixth front surface wiring pattern 230 can be greater than or equal to about 2CPP and less than about 4CPP. For example, the width W1 of the sixth front surface wiring pattern 230 can be about 2CPP to about 3.5CPP, or about 2CPP to about 3CPP.

[0123] A back surface region BR can be formed on the second surface 100b of the substrate 100. The back surface region BR can include a first-stage back surface wiring BM1 and a second-stage back surface wiring BM2. For example, a back surface wiring interlayer insulating film 300 can be on the second surface 100b of the substrate 100. The first-stage back surface wiring BM1 and the second-stage back surface wiring BM2 can be formed in the back surface wiring interlayer insulating film 300 to form an electrical path.

[0124] The first back surface wiring BM1 and the second back surface wiring BM2 can be sequentially stacked on the second surface 100b of the substrate 100. That is, the second back surface wiring BM2 can be provided at a higher level than the first back surface wiring BM1. In the back surface region BR, “provided at a higher level” means “provided further away from the substrate 100 in the vertical direction (hereinafter, referred to as a third direction Z)”. For example, in the third direction Z, the second back surface wiring BM2 can be spaced further apart from the second surface 100b than the first back surface wiring BM1.

[0125] In some embodiments, the first back surface wiring BM1 can include a first back surface wiring pattern 310 to a fourth back surface wiring pattern 313. The first back surface wiring pattern 310 to the fourth back surface wiring pattern 313 can be provided at the same level.

[0126] The first back surface wiring pattern 310 can be connected to the fifth gate structure GS5 and the eighth gate structure GS8. For example, a first back surface gate contact 395 can be formed that contacts the gate electrode 130 of the fifth gate structure GS5 by passing through the substrate 100 and the gate dielectric film 120. Further, a second back surface gate contact 398 can be formed that contacts the gate electrode 130 of the eighth gate structure GS8 by passing through the substrate 100 and the gate dielectric film 120. The first back surface wiring pattern 310 can be connected to the fifth gate structure GS5 through the first back surface gate contact 395, and can be connected to the eighth gate structure GS8 through the second back surface gate contact 398.

[0127] In some embodiments, the first back surface gate contact 395 can not overlap the first active pattern AP1 in the third direction Z. For example, the first back surface gate contact 395 can contact the gate electrode 130 of the fifth gate structure GS5 by passing through the substrate 100, the field insulating film 105, and the gate dielectric film 120.

[0128] In some embodiments, the second back surface gate contact 398 can not overlap the fourth active pattern AP4 in the third direction Z. For example, the second back surface gate contact 398 can contact the gate electrode 130 of the eighth gate structure GS8 by passing through the substrate 100, the field insulating film 105, and the gate dielectric film 120.

[0129] In some embodiments, the first back surface wiring pattern 310 can extend longer in the first direction X beyond the first cell MC1 and the second cell MC2. The first back surface wiring pattern 310 can be provided as the second word line WL2, and can be commonly connected to the gate of the first transfer transistor PS1 of the second cell MC2 (i.e., the fifth gate structure GS5) and the gate of the second transfer transistor PS2 of the second cell MC2 (i.e., the eighth gate structure GS8).

[0130] In some embodiments, the first backside wiring pattern 310 can be formed on the first cell MC1 and the second cell MC2. For example, the first backside wiring pattern 310 can overlap both the first cell MC1 and the second cell MC2 in the third direction Z.

[0131] In some embodiments, at least a portion of the first backside wiring pattern 310 can overlap at least a portion of the sixth frontside wiring pattern 230 in the third direction Z. In this regard, the first cell MC1 and the second cell MC2 can be provided between the sixth frontside wiring pattern 230 and the first backside wiring pattern 310.

[0132] In some embodiments, a maximum width W2m of the first backside wiring pattern 310 can be greater than or equal to about 2CPP and less than about 4CPP. For example, the maximum width W2m of the first backside wiring pattern 310 can be about 2CPP to about 3.5CPP, or about 2CPP to about 3CPP.

[0133] In some embodiments, the first backside wiring pattern 310 can include a first portion 310a, a second portion 310b, and a third portion 310c. The first portion 310a can extend in the first direction X. The second portion 310b can extend in the first direction X and can be connected to one side of the first portion 310a. The third portion 310c can extend in the first direction X and can be connected to another side of the first portion 310a. The second portion 310b and the third portion 310c can be spaced apart from each other in the second direction Y.

[0134] The first portion 310a of the first backside wiring pattern 310 can be connected to the fifth gate structure GS5. For example, the first backside gate contact 395 can directly connect the first portion 310a with the fifth gate structure GS5.

[0135] The third portion 310c of the first backside wiring pattern 310 can be connected to the eighth gate structure GS8. For example, the second backside gate contact 398 can directly connect the third portion 310c with the eighth gate structure GS8.

[0136] In some embodiments, a width W2a of the first portion 310a can be about 1CPP to about 3CPP, or about 1.5CPP to about 2.5CPP, or about 1.5CPP to about 2CPP.

[0137] In some embodiments, the width W2b of the second portion 310b and the width W2c of the third portion 310c can be about 0.5CPP to about 1.5CPP, or about 0.7CPP to about 1.3CPP, or about 0.8CPP to about 1.2CPP. The width W2b of the second portion 310b and the width W2c of the third portion 310c are shown to be the same as each other, but embodiments are not limited thereto, and the width W2b of the second portion 310b and the width W2c of the third portion 310c can be different from each other.

[0138] The second backside wiring pattern 311 can be connected to the first active pattern AP1. For example, a first backside source / drain contact 371 can be formed on one side of the third gate structure GS3 in contact with the first source / drain region 161. The first backside source / drain contact 371 can connect the second backside wiring pattern 311 with the first source / drain region 161 by passing through the substrate 100 and the fin pattern 110. The third gate structure GS3 can be interposed between the second source / drain contact 171 and the first backside source / drain contact 371.

[0139] The third backside wiring pattern 312 can be connected to the first active pattern AP1. For example, a second backside source / drain contact 373 can be formed on one side of the seventh gate structure GS7 in contact with the first source / drain region 161. The second backside source / drain contact 373 can connect the third backside wiring pattern 312 with the first source / drain region 161 by passing through the substrate 100 and the fin pattern 110. The seventh gate structure GS7 can be interposed between the seventh source / drain contact 176 and the second backside source / drain contact 373.

[0140] The fourth backside wiring pattern 313 can be connected to the fourth active pattern AP4. For example, a third backside source / drain contact 372 can be formed between the second gate structure GS2 and the sixth gate structure GS6 in contact with the fourth source / drain region 164. The third backside source / drain contact 372 can connect the fourth backside wiring pattern 313 with the fourth source / drain region 164 by passing through the substrate 100 and the fin pattern 110.

[0141] In some embodiments, the first portion 310a of the first backside wiring pattern 310 can be interposed between the second backside wiring pattern 311 and the third backside wiring pattern 312. Each of the second backside wiring pattern 311 and the third backside wiring pattern 312 can be spaced apart from the first portion 310a in the second direction Y. Further, the second backside wiring pattern 311 can be spaced apart from the second portion 310b in the first direction X, and the third backside wiring pattern 312 can be spaced apart from the third portion 310c in the first direction X.

[0142] In some embodiments, the fourth back surface wiring pattern 313 can be interposed between the second portion 310b of the first back surface wiring pattern 310 and the third portion 310c of the first back surface wiring pattern 310. Each of the second portion 310b and the third portion 310c can be spaced apart from the fourth back surface wiring pattern 313 in the second direction Y.

[0143] In some embodiments, the second stage back surface wiring BM2 can include a fifth back surface wiring pattern 330.

[0144] The fifth back surface wiring pattern 330 can be connected to the second back surface wiring pattern 311 to the fourth back surface wiring pattern 313. For example, a first back surface via pattern 321 connecting the second back surface wiring pattern 311 and the fifth back surface wiring pattern 330 can be formed, a second back surface via pattern 322 connecting the third back surface wiring pattern 312 and the fifth back surface wiring pattern 330 can be formed, and a third back surface via pattern 323 connecting the fourth back surface wiring pattern 313 and the fifth back surface wiring pattern 330 can be formed.

[0145] The fifth back surface wiring pattern 330 can be provided to apply a second power supply voltage (e.g., Vss) different from a first power supply voltage (e.g., Vdd) to a second power supply line of the first pull-down transistor PD1 and the second pull-down transistor PD2. DD ) different from a first power supply voltage (e.g., V SS ) to a second power supply line of the first pull-down transistor PD1 and the second pull-down transistor PD2.

[0146] In some embodiments, the fifth back surface wiring pattern 330 can include a first extension portion 330a and a second extension portion 330b crossing each other. For example, the first extension portion 330a can be longer in the second direction Y, and the second extension portion 330b can be longer in the first direction X.

[0147] The first extension portion 330a of the fifth back surface wiring pattern 330 can be connected to the second back surface wiring pattern 311 and the third back surface wiring pattern 312. For example, the first back surface via pattern 321 can directly connect the first extension portion 330a and the second back surface wiring pattern 311, and the second back surface via pattern 322 can directly connect the first extension portion 330a and the third back surface wiring pattern 312.

[0148] The second extension portion 330b of the fifth back surface wiring pattern 330 can be connected to the fourth back surface wiring pattern 313. For example, the third back surface via pattern 323 can directly connect the second extension portion 330b and the fourth back surface wiring pattern 313.

[0149] As the integration density of semiconductor devices increases, in order to increase the density in the same area and implement more semiconductor devices, individual circuit patterns become increasingly fine. Therefore, there is a problem that a delay occurs in the transmission of an electrical signal through a wiring. For example, in a row in a cell array of a static random access memory (SRAM) device in which unit cells are arranged in the form of a matrix, one word line can be provided per unit cell. In this case, the width of the word line can be limited to less than the width of one unit cell (e.g., 2CPP), and as the size of the unit cell decreases, the word line signal delay is exacerbated.

[0150] In a semiconductor device according to some embodiments, a delay of an electrical signal can be reduced by using a backside power delivery network (BSPDN). In detail, as described above, in a semiconductor device according to some embodiments, a first word line WL1 (e.g., a sixth front side wiring pattern 230) can be disposed on a front side (i.e., a first surface 100a) of a substrate 100 and connected to a first cell MC1, and a second word line WL2 (e.g., a first backside wiring pattern 310) can be disposed on a backside (i.e., a second surface 100b) of the substrate 100 and connected to a second cell MC2. Therefore, each of the width of the first word line WL1 and the width of the second word line WL2 can not be limited to the width of one unit cell (e.g., 2CPP), and can be provided with a relatively wide width (e.g., about 2CPP or more). Therefore, a semiconductor device having improved performance by reducing a word line signal delay can be provided.

[0151] Figure 9 to Figure 11 FIGS. 1 to 3 are various layout diagrams illustrating a semiconductor device according to some embodiments. For ease of description, those redundant portions described above with reference to Figure 1 to Figure 8 FIGS. 1 to 3 will be briefly described or omitted.

[0152] Referring to Figure 1 , Figure 2 and Figure 9 , in the semiconductor device of the present disclosure, the front side region FR further includes a third level front side wiring FM3.

[0153] The third level front side wiring FM3 can be arranged at a higher level than the second level front side wiring FM2. The third level front side wiring FM3 can include a seventh front side wiring pattern 251 and an eighth front side wiring pattern 252. The seventh front side wiring pattern 251 and the eighth front side wiring pattern 252 can be disposed at the same level. The seventh front side wiring pattern 251 and the eighth front side wiring pattern 252 can be sequentially arranged along the first direction X. Each of the seventh front side wiring pattern 251 and the eighth front side wiring pattern 252 can extend longer in the second direction Y.

[0154] The seventh front side wiring pattern 251 can be connected to the second front side wiring pattern 212. For example, the second-stage front side wiring line FM2 can further include a first connection pattern 231 disposed at the same level as the sixth front side wiring pattern 230. The first connection pattern 231 can be connected to the second front side wiring pattern 212. Further, a third front side via pattern 241 connecting the first connection pattern 231 with the seventh front side wiring pattern 251 can be formed.

[0155] In some embodiments, the seventh front side wiring pattern 251 can extend longer in the second direction Y, beyond the first cell MC1 and the second cell MC2. The seventh front side wiring pattern 251 can provide a relatively wide bit line BL with respect to the second front side wiring pattern 212.

[0156] The eighth front side wiring pattern 252 can be connected to the fourth front side wiring pattern 214. For example, the second-stage front side wiring line FM2 can further include a second connection pattern 232 disposed at the same level as the sixth front side wiring pattern 230. The second connection pattern 232 can be connected to the fourth front side wiring pattern 214. Further, a fourth front side via pattern 242 connecting the second connection pattern 232 with the eighth front side wiring pattern 252 can be formed.

[0157] In some embodiments, the eighth front side wiring pattern 252 can extend longer in the second direction Y, beyond the first cell MC1 and the second cell MC2. The eighth front side wiring pattern 252 can provide a complementary bit line / BL having a relatively wide width compared to the fourth front side wiring pattern 214. The sixth front side wiring pattern 230 can also be connected to an upper stage to provide a first word line WL1 having a wider width.

[0158] Referring to Figure 1 , Figure 2 and Figure 10 In a semiconductor device according to some embodiments, the second-stage back side wiring BM2 includes a sixth back side wiring pattern 331 and a seventh back side wiring pattern 332.

[0159] The sixth back side wiring pattern 331 and the seventh back side wiring pattern 332 can be arranged along the first direction X. Each of the sixth back side wiring pattern 331 and the seventh back side wiring pattern 332 can extend longer in the second direction Y.

[0160] The sixth back surface wiring pattern 331 can be connected to the second back surface wiring pattern 311 and the third back surface wiring pattern 312. For example, the first back surface via pattern 321 can connect the second back surface wiring pattern 311 with the sixth back surface wiring pattern 331, and the second back surface via pattern 322 can connect the third back surface wiring pattern 312 with the sixth back surface wiring pattern 331. In some embodiments, the sixth back surface wiring pattern 331 can extend longer in the second direction Y, beyond the first cell MC1 and the second cell MC2.

[0161] The seventh back surface wiring pattern 332 can be connected to the fourth back surface wiring pattern 313. For example, the third back surface via pattern 323 can connect the fourth back surface wiring pattern 313 with the seventh back surface wiring pattern 332. In some embodiments, the seventh back surface wiring pattern 332 can extend longer in the second direction Y, beyond the first cell MC1 and the second cell MC2.

[0162] Each of the sixth back surface wiring pattern 331 and the seventh back surface wiring pattern 332 can be provided as a second power line for applying a second power supply voltage (e.g., V SS ).

[0163] Referring to Figure 1 , Figure 2 and Figure 11 , in the semiconductor device according to some embodiments, the first-stage back surface wiring BM1 includes an eighth back surface wiring pattern to a tenth back surface wiring pattern 316, 314 and 315, and the second-stage back surface wiring BM2 includes an eleventh back surface wiring pattern 333.

[0164] The eighth back surface wiring pattern 316 can be connected to the first back surface source / drain contact 371, the second back surface source / drain contact 373 and the third back surface source / drain contact 372. The eighth back surface wiring pattern 316 can be provided as a second power line for applying a second power supply voltage (e.g., V SS ).

[0165] In some embodiments, the eighth back surface wiring pattern 316 can include a fourth portion 316a, a fifth portion 316b, a sixth portion 316c and a seventh portion 316d. Each of the fourth portion 316a and the fifth portion 316b can extend in the first direction X. The fourth portion 316a and the fifth portion 316b can be spaced apart from each other in the second direction Y. The sixth portion 316c can extend in the second direction Y to connect the fourth portion 316a with the fifth portion 316b. The seventh portion 316d can extend in the first direction X from the sixth portion 316c. The sixth portion 316c can be connected between the fourth portion 316a and the seventh portion 316d, and between the fifth portion 316b and the seventh portion 316d.

[0166] The fourth portion 316a of the eighth backside wiring pattern 316 can be connected to the first backside source / drain contact 371. The fifth portion 316b of the eighth backside wiring pattern 316 can be connected to the second backside source / drain contact 373. The seventh portion 316d of the eighth backside wiring pattern 316 can be connected to the third backside source / drain contact 372.

[0167] The ninth backside wiring pattern 314 can be connected to the fifth gate structure GS5. For example, the first backside gate contact 395 can directly connect the ninth backside wiring pattern 314 with the fifth gate structure GS5.

[0168] In some embodiments, the ninth backside wiring pattern 314 can be interposed between the fourth portion 316a and the fifth portion 316b. Each of the fourth portion 316a and the fifth portion 316b can be spaced apart from the ninth backside wiring pattern 314 in the second direction Y. Further, the ninth backside wiring pattern 314 can be spaced apart from the sixth portion 316c in the first direction X.

[0169] The tenth backside wiring pattern 315 can be connected to the eighth gate structure GS8. For example, the second backside gate contact 398 can directly connect the tenth backside wiring pattern 315 with the eighth gate structure GS8.

[0170] In some embodiments, the tenth backside wiring pattern 315 can be spaced apart from the seventh portion 316d in the second direction Y. Further, the tenth backside wiring pattern 315 can be spaced apart from the sixth portion 316c in the first direction X.

[0171] The eleventh backside wiring pattern 333 can be connected to the ninth backside wiring pattern 314 and the tenth backside wiring pattern 315. For example, the fourth backside via pattern 324 connecting the ninth backside wiring pattern 314 with the eleventh backside wiring pattern 333 can be formed, and the fifth backside via pattern 325 connecting the tenth backside wiring pattern 315 with the eleventh backside wiring pattern 333 can be formed.

[0172] In some embodiments, the eleventh backside wiring pattern 333 can be elongated in the first direction X beyond the first cell MC1 and the second cell MC2. The eleventh backside wiring pattern 333 can be provided as the second word line WL2, and commonly connected to the gate of the first pass transistor PS1 of the second cell MC2 (i.e., the fifth gate structure GS5) and the gate of the second pass transistor PS2 of the second cell MC2 (i.e., the eighth gate structure GS8).

[0173] In some embodiments, the eleventh backside wiring pattern 333 can be formed on the first cell MC1 and the second cell MC2. For example, the eleventh backside wiring pattern 333 can overlap both the first cell MC1 and the second cell MC2 in the third direction Z.

[0174] In some embodiments, at least a portion of the eleventh backside wiring pattern 333 can overlap at least a portion of the sixth frontside wiring pattern 230 in the third direction Z.

[0175] In some embodiments, a width W3 of the eleventh backside wiring pattern 333 can be greater than or equal to about 2CPP and less than about 4CPP. For example, the width W3 of the eleventh backside wiring pattern 333 can be about 2CPP to about 3.5CPP, or about 2CPP to about 3CPP.

[0176] Figure 12 is a layout diagram illustrating a semiconductor device according to some embodiments. Figure 13 is a schematic cross-sectional view taken along Figure 12 line F-F of Figure 14 is a schematic cross-sectional view taken along Figure 12 line G-G of Figure 1 to Figure 8 For ease of description, redundant portions described above with reference to

[0177] Referring to Figure 1 , Figure 2 and Figure 12 to Figure 14 , in a semiconductor device according to some embodiments, the first backside gate contact 395 overlaps the first active pattern AP1 in the third direction Z, and the second backside gate contact 398 overlaps the fourth active pattern AP4 in the third direction Z.

[0178] For example, the first backside gate contact 395 can contact the gate electrode 130 of the fifth gate structure GS5 by passing through the fin pattern 110 under the first active pattern AP1. For example, the second backside gate contact 398 can contact the gate electrode 130 of the eighth gate structure GS8 by passing through the fin pattern 110 under the fourth active pattern AP4.

[0179] In some embodiments, a sacrificial pattern 115 can be formed in the fin pattern 110. The sacrificial pattern 115 can be formed in the fin pattern 110 under the first gate structure GS1 to the eighth gate structure GS8.

[0180] The sacrificial pattern 115 can include an insulating material, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbon nitride, silicon oxycarbonitride, and combinations thereof, but embodiments are not limited thereto.

[0181] In some embodiments, the sacrificial pattern 115 can include a material having etch selectivity with respect to the fin pattern 110. For example, the fin pattern 110 can include a silicon oxide layer, and the sacrificial pattern 115 can include a silicon nitride layer. In some embodiments, the first back gate contact 395 and the second back gate contact 398 can be in contact with the gate electrode 130 by passing through a portion of the sacrificial pattern 115.

[0182] In some embodiments, the substrate 100 described with reference to Figure 4 to Figure 8 may be omitted. For example, the substrate 100 can be removed in a thinning process for implementing the backside region BR. In this case, in this specification, the fin pattern 110 and / or the sacrificial pattern 115 can also be referred to as a substrate for providing the device region DR.

[0183] Figure 15 is a circuit diagram illustrating a semiconductor device according to some embodiments. For ease of description, redundant portions described above with reference to Figure 1 to Figure 14 may be briefly described or omitted.

[0184] with reference to Figure 1 and Figure 15 , the semiconductor device according to some embodiments includes first to fourth cells MC1 to MC4 adjacent to each other.

[0185] Each of the first to fourth cells MC1 to MC4 can correspond to one of a plurality of unit SRAM cells MC. The first cell MC1 and the second cell MC2 are adjacent to each other in a second direction Y. The first cell MC1 and the third cell MC3 are adjacent to each other in a first direction X. The second cell MC2 and the fourth cell MC4 are adjacent to each other in the first direction X, and the third cell MC3 and the fourth cell MC4 are adjacent to each other in the second direction Y.

[0186] Each of the first to fourth cells MC1 to MC4 can include a pair of inverters INV1 and INV2 connected in parallel between a power supply node V DD and a ground node V SS , and first and second pass transistors PS1 and PS2 connected to an output node of each of the inverters INV1 and INV2. Since each of the first to fourth cells MC1 to MC4 is the same as described above with reference to Figure 2 , a detailed description thereof will be omitted below.

[0187] In some embodiments, the first cell MC1 and the third cell MC3 can share the first word line WL1, and the second cell MC2 and the fourth cell MC4 can share the second word line WL2. For example, gates of the pass transistors PS1 and PS2 of the first cell MC1 and gates of the pass transistors PS1 and PS2 of the third cell MC3 can be commonly connected to one first word line WL1. For example, gates of the pass transistors PS1 and PS2 of the second cell MC2 and gates of the pass transistors PS1 and PS2 of the fourth cell MC4 can be commonly connected to one second word line WL2.

[0188] In some embodiments, the first cell MC1 and the second cell MC2 can share one bit line BL and one complementary bit line / BL, and the third cell MC3 and the fourth cell MC4 can share another bit line BL and another complementary bit line / BL. For example, the first pass transistor PS1 of the first cell MC1 and the first pass transistor PS1 of the second cell MC2 can be commonly connected to one bit line BL, and the second pass transistor PS2 of the first cell MC1 and the second pass transistor PS2 of the second cell MC2 can be commonly connected to one complementary bit line / BL. For example, the first pass transistor PS1 of the third cell MC3 and the first pass transistor PS1 of the fourth cell MC4 can be commonly connected to another bit line BL, and the second pass transistor PS2 of the third cell MC3 and the second pass transistor PS2 of the fourth cell MC4 can be commonly connected to another complementary bit line / BL.

[0189] Figure 16 is a layout diagram illustrating a semiconductor device according to some embodiments.

[0190] Referring to Figure 1 , Figure 2 , Figure 15 and Figure 16 , a semiconductor device according to some embodiments includes first to fourth cells MC1 to MC4.

[0191] The first cell MC1 and the second cell MC2 can correspond to the first cell MC1 and the second cell MC2 described with reference to Figure 1 to Figure 14 For ease of description, Figure 16 the first cell MC1 and the second cell MC2 of Figure 3 are the same as the first cell MC1 and the second cell MC2 of

[0192] The first and third units MC1 and MC3 can be arranged in a planar symmetric relationship with respect to a boundary surface (e.g., the YZ plane) between the first and third units MC1 and MC3. The second and fourth units MC2 and MC4 can be arranged in a planar symmetric relationship with respect to a boundary surface (e.g., the YZ plane) between the second and fourth units MC2 and MC4.

[0193] The second and fourth front side wiring patterns 212 and 214 can be arranged repeatedly in the first direction X. One second front side wiring pattern 212 can extend in the second direction Y and be provided as one bit line BL commonly connected to the first and second units MC1 and MC2. Another second front side wiring pattern 212 can extend in the second direction Y and be provided as another bit line BL commonly connected to the third and fourth units MC3 and MC4. One fourth front side wiring pattern 214 can extend in the second direction Y and be provided as one complementary bit line / BL commonly connected to the first and second units MC1 and MC2. Another fourth front side wiring pattern 214 can extend in the second direction Y and be provided as another complementary bit line / BL commonly connected to the third and fourth units MC3 and MC4.

[0194] The third front side wiring patterns 213 can be arranged repeatedly in the first direction X. One third front side wiring pattern 213 can extend in the second direction Y and be provided as a first power line for applying a first power voltage (e.g., V DD ) to the first and second units MC1 and MC2. Another third front side wiring pattern 213 can extend in the second direction Y and be provided as a first power line for applying a first power voltage (e.g., V DD ) to the third and fourth units MC3 and MC4.

[0195] The sixth front side wiring pattern 230 can extend in the first direction X and be provided as one first word line WL1 commonly connected to the first and third units MC1 and MC3. For example, the sixth front side wiring pattern 230 can be shared by the first and third units MC1 and MC3 through the first and fifth front side wiring patterns 211 and 215. In some embodiments, the first and third units MC1 and MC3 can share the fifth front side wiring pattern 215.

[0196] The first back side wiring pattern 310 can extend in the first direction X and be provided as one second word line WL2 commonly connected to the second and fourth units MC2 and MC4.

[0197] The fifth back side wiring pattern 330 can be provided as a second power line for applying a second power voltage (e.g., V SS) applied to the first to fourth cells MC1 to MC4. For example, the fifth back surface wiring pattern 330 can be shared by the first to fourth cells MC1 to MC4 through the second to fourth back surface wiring patterns 311 to 313. In some embodiments, the first to fourth cells MC1 to MC4 can share the fourth back surface wiring pattern 313.

[0198] While aspects of embodiments have been particularly shown and described, it will be understood that various changes can be made without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device comprising: a substrate including a first surface and a second surface opposite to each other; a first word line extending along a first direction on the first surface; a second word line extending along the first direction on the second surface; a bit line and a complementary bit line extending in parallel along a second direction intersecting the first direction on the substrate; and a first cell and a second cell adjacent to each other along the second direction on the substrate, wherein each of the first cell and the second cell includes a latch circuit including a first inverter and a second inverter, a first pass transistor connecting an output node of the first inverter with the bit line, and a second pass transistor connecting an output node of the second inverter with the complementary bit line, wherein the first word line is connected to a gate of the first pass transistor of the first cell and a gate of the second pass transistor of the first cell, and wherein the second word line is connected to a gate of the first pass transistor of the second cell and a gate of the second pass transistor of the second cell. the first word line overlaps the first cell and the second cell along a third direction intersecting the first direction and the second direction.

2. The semiconductor device according to claim 1, wherein the second word line overlaps the first cell and the second cell along a third direction intersecting the first direction and the second direction.

3. The semiconductor device according to claim 1, wherein the second word line includes a first portion extending along the first direction, a second portion extending along the first direction from one side of the first portion, and a third portion extending along the first direction from the other side of the first portion and spaced apart from the second portion along the second direction.

4. The semiconductor device according to claim 1, wherein a first power line and a second power line on the substrate, the first power line and the second power line configured to provide different voltages, 5. The semiconductor device according to claim 1, further comprising: wherein the first inverter and the second inverter are connected in parallel between the first power line and the second power line. the first power line is on the first surface, and the second power line is on the second surface.

6. The semiconductor device according to claim 5, wherein the bit line and the complementary bit line are arranged at the same level as the first power line along a third direction intersecting the first direction and the second direction.

7. The semiconductor device according to claim 6, wherein the second word line is arranged at a different level from the second power line along a third direction intersecting the first direction and the second direction.

8. The semiconductor device according to claim 6, wherein the second power line includes a first extension portion extending along the second direction and a second extension portion extending along the first direction.

9. The semiconductor device according to claim 6, wherein 10. A semiconductor device comprising: a substrate including a first surface and a second surface opposite to each other; a plurality of unit static random access memory cells arranged in a matrix along a first direction and a second direction intersecting each other on the first surface; a first word line extending along the first direction on the first surface; and a second word line extending along the first direction on the second surface, ​ ​ The plurality of unit SRAM cells includes first unit SRAM cells arranged in a first row and second unit SRAM cells arranged in a second row, each of the first row and the second row extending along the first direction, The first word line is commonly connected to the first unit SRAM cells of the first row, and The second word line is commonly connected to the second unit SRAM cells of the second row.

11. The semiconductor device according to claim 10, wherein The first row is one of a plurality of first rows, the second row is one of a plurality of second rows, and the plurality of first rows and the plurality of second rows are alternately arranged along the second direction.

12. The semiconductor device according to claim 10, wherein The first word line and the second word line overlap each other along a third direction intersecting the first direction and the second direction.

13. The semiconductor device of claim 10, further comprising: Bit lines and complementary bit lines extending in parallel along the second direction on the first surface, Each of the bit lines and the complementary bit lines is commonly connected to the first row and the second row.

14. The semiconductor device according to claim 13, wherein Each of the plurality of unit SRAM cells includes a latch circuit including a first inverter and a second inverter, a first pass transistor connecting an output node of the first inverter with the bit line, and a second pass transistor connecting an output node of the second inverter with the complementary bit line, The first word line is connected to gates of the first pass transistors in the plurality of unit SRAM cells in the first row and gates of the second pass transistors in the plurality of unit SRAM cells in the first row, and The second word line is connected to gates of the first pass transistors in the plurality of unit SRAM cells in the second row and gates of the second pass transistors in the plurality of unit SRAM cells in the second row.

15. A semiconductor device comprising: a first unit and a second unit adjacent to each other along a first direction; a substrate including a first surface and a second surface opposite to each other; first to fourth active patterns sequentially arranged along a second direction intersecting the first direction, each of the first to fourth active patterns extending along the first direction on the first surface; a first gate structure extending along the second direction in the first unit intersecting the first active pattern; a second gate structure extending along the second direction in the first unit intersecting the third active pattern and the fourth active pattern; a third gate structure extending along the second direction in the first unit intersecting the first active pattern and the second active pattern; a fourth gate structure extending along the second direction in the first unit intersecting the fourth active pattern; a first source / drain contact connecting the first active pattern to the second active pattern and the second gate structure between the first gate structure and the third gate structure; a second source / drain contact connecting the third active pattern to the fourth active pattern and the third gate structure between the second gate structure and the third gate structure and between the second gate structure and the fourth gate structure; a fifth gate structure intersecting the first active pattern along the second direction in the second cell; a sixth gate structure intersecting the third active pattern and the fourth active pattern along the second direction in the second cell; a seventh gate structure intersecting the first active pattern and the second active pattern along the second direction in the second cell; an eighth gate structure intersecting the fourth active pattern along the second direction in the second cell; a third source / drain contact connecting the first active pattern to the second active pattern and the sixth gate structure between the fifth gate structure and the seventh gate structure and between the sixth gate structure and the seventh gate structure; a fourth source / drain contact connecting the third active pattern to the fourth active pattern and the seventh gate structure between the sixth gate structure and the seventh gate structure and between the sixth gate structure and the eighth gate structure; a first front side wiring pattern extending along the second direction on the first surface and connected to the first gate structure and the fourth gate structure; and a first back side wiring pattern extending along the second direction on the second surface and connected to the fifth gate structure and the eighth gate structure.

16. The semiconductor device of claim 15, further comprising: a fifth source / drain contact connected to the first active pattern between the first gate structure and the fifth gate structure; a sixth source / drain contact connected to the fourth active pattern, the fourth gate structure interposed between the second source / drain contact and the sixth source / drain contact; a seventh source / drain contact connected to the fourth active pattern, the eighth gate structure interposed between the fourth source / drain contact and the seventh source / drain contact; a second front side wiring pattern extending along the first direction on the first surface and connected to the fifth source / drain contact; and a third front side wiring pattern extending along the first direction on the first surface and connected to the sixth source / drain contact and the seventh source / drain contact. A width of the first front side wiring pattern is greater than or equal to 2 contact multi-pitches and less than 4 contact multi-pitches.

18. The semiconductor device of claim 15, further comprising:

17. The semiconductor device according to claim 15, wherein ​ ​ a first backside gate contact through the substrate, the first backside gate contact connecting the first backside wiring pattern with the fifth gate structure; and a second backside gate contact through the substrate, the second backside gate contact connecting the first backside wiring pattern with the eighth gate structure.

19. The semiconductor device according to claim 18, wherein the first backside wiring pattern comprises a first portion extending along the second direction, a second portion extending along the second direction from one side of the first portion, and a third portion extending along the second direction from another side of the first portion and spaced apart from the second portion in the first direction, wherein the first backside gate contact connects the first portion with the fifth gate structure, and wherein the second backside gate contact connects the third portion with the eighth gate structure.

20. The semiconductor device according to claim 15, wherein a maximum width of the first backside wiring pattern is greater than or equal to 2 contact multi-pitches and less than 4 contact multi-pitches.

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