Nonvolatile static random access memory cell

Abstract

The invention provides a nonvolatile static random access memory unit which can be applied to the technical field of nonvolatile static random access memory. The non-volatile static random access memory cell includes: a static random access memory circuit having a cross-coupled inverter structure, the static random access memory circuit including a memory node and an inverted memory node; a first control transistor electrically connected between the first data line and the first node; a second control transistor electrically connected between the storage node and the first node; and a plurality of first resistive random access memory devices electrically connected between the first node and the corresponding RRAM bit lines, respectively.

Description

Technical Field

[0001] This disclosure relates to the field of non-volatile static random access memory technology, and more specifically to a non-volatile static random access memory unit. Background Technology

[0002] With the trend of integrated circuit storage technology upgrading towards larger capacity, higher integration, and lower power consumption, data throughput is growing exponentially, placing stringent requirements on the storage density of NVSRAM (Non-Volatile Static Random Access Memory) cells. In related technologies, NVSRAM cells use a single control transistor to drive multiple variable resistive memories for writing, reading, backup, and power-loss data recovery, achieving increased storage capacity without significantly increasing cell area.

[0003] However, in related technologies, RRAM (Resistive Random-Access Memory) devices and SRAM (Static Random-Access Memory) circuits in NVSRAM share control signals, which leads to conflicts in the operation between RRAM devices and SRAM circuits.

[0004] In the process of realizing the concept of this disclosure, it was found that at least the following problems exist in the related technology: the operation of RRAM devices and SRAM circuits is difficult to be compatible. Summary of the Invention

[0005] In view of the above problems, this disclosure provides a non-volatile static random access memory unit.

[0006] According to a first aspect of this disclosure, a non-volatile static random access memory (SRAM) is provided, the non-volatile SRAM comprising:

[0007] A static random access memory circuit with a cross-coupled inverter structure includes a memory node and an inverting memory node;

[0008] The first control transistor is electrically connected between the first data line and the first node;

[0009] A second control transistor is electrically connected between the memory node and the first node; and

[0010] Multiple first resistive random access memory devices are electrically connected between the first node and the corresponding resistive random access memory bit lines.

[0011] According to embodiments of this disclosure, the non-volatile static random access memory unit further includes:

[0012] A third control transistor is electrically connected between the inverting memory node and the second node; and

[0013] The second resistive random access memory device is electrically connected between the second node and the reference resistive random access memory bit line.

[0014] According to embodiments of this disclosure, the static random access memory circuit includes:

[0015] A first pull-up transistor and a first pull-down transistor are connected to form a first inverter, wherein the node between the first pull-up transistor and the first pull-down transistor constitutes the memory node;

[0016] The second pull-up transistor, the second pull-down transistor, and the third pull-down transistor are connected to form a second inverter, wherein the first inverter and the second inverter are cross-coupled, and the node between the second pull-up transistor and the second pull-down transistor constitutes the inverted memory node.

[0017] A first transmission transistor electrically connected between a static random access memory bit line and the memory node; and

[0018] A second transmission transistor is electrically connected between the complementary static random access memory bit line and the inverting memory node.

[0019] According to embodiments of this disclosure, the non-volatile static random access memory unit is configured as follows:

[0020] The first control transistor is turned on and the second control transistor is turned off by a corresponding control signal, and a selected resistive random access memory (RRAM) device is selected from the plurality of first RRAM devices by a corresponding resistive random access memory bit line to receive data from the first data line via the first control transistor and store the data; or

[0021] The first control transistor is turned off and the second control transistor is turned on by a corresponding control signal, and a selected resistive random access memory device among the plurality of first resistive random access memory devices is selected by a corresponding resistive random access memory bit line to receive data from the memory node via the second control transistor and store the data.

[0022] According to embodiments of this disclosure, the non-volatile static random access memory unit is configured as follows:

[0023] By sequentially applying low and high levels to the resistive random access memory bit lines, the data in the memory node is stored in the selected resistive random access memory device.

[0024] According to embodiments of this disclosure, the non-volatile static random access memory unit further includes:

[0025] A transistor is connected between the node between the second pull-down transistor and the third pull-down transistor and the control signal line, and the control terminal is electrically connected to the inverting memory node.

[0026] According to embodiments of this disclosure, the non-volatile static random access memory unit is configured as follows:

[0027] Set the second resistive random access memory device;

[0028] By turning on the first transmission transistor and the second control transistor and turning off the first control transistor through the corresponding control signals, a first level is applied to the static random access memory bit line and a second level is applied to the selected resistive random access memory bit line, forming a conduction path through the first transmission transistor, the second control transistor and the selected resistive random access memory device corresponding to the selected resistive random access memory bit line, and causing a first voltage on the memory node.

[0029] The second transmission transistor and the third control transistor are turned on by corresponding control signals, the first level is applied to the complementary static random access memory bit line and the second level is applied to the reference resistive random access memory bit line, forming a conduction path through the second transmission transistor, the third control transistor and the second resistive random access memory device, and causing a second voltage on the inverting memory node, wherein the resistance between the inverting memory node and the reference resistive random access memory line is made to have a resistance value between the set state and the reset state of the selected resistive random access memory device through the third control transistor;

[0030] By turning off the first transmission transistor, the second transmission transistor, the second control transistor, and the third control transistor through corresponding control signals, the data on the selected resistive random access memory device is restored to the memory node based on the difference between the first voltage and the second voltage.

[0031] According to an embodiment of this disclosure, a first control signal is applied to the control terminal of the second control transistor to turn on the second control transistor, and a second control signal is applied to the control terminal of the third control transistor to turn on the third control transistor, wherein the level of the second control signal is lower than the level of the first control signal, so that the resistance between the inverting memory node and the reference resistive random access memory line has a resistance value between the set state and the reset state of the selected resistive random access memory device.

[0032] According to embodiments of this disclosure, the non-volatile static random access memory unit is configured as follows:

[0033] The third control transistor is turned on by a corresponding control signal, and a low level and a high level are sequentially applied to the reference resistive random access memory bit line to back up the data stored in the memory node to the second resistive random access memory device.

[0034] According to embodiments of this disclosure, the non-volatile static random access memory unit is configured as follows:

[0035] A high level is applied to the static random access memory bit line and a low level is applied to the reference resistive random access memory bit line. The first transmission transistor and the third control transistor are turned on by the corresponding control signal, and the data backed up in the second resistive random access memory device is restored to the memory node.

[0036] According to embodiments of this disclosure, the SRAM circuit and the first RRAM device are decoupled via a first control transistor and a second control transistor. When the first RRAM device and the SRAM circuit can operate simultaneously, voltage fluctuations generated during the operation of the SRAM circuit will not interfere with the resistive stability of the first RRAM device, and signals generated by the operation of the first RRAM device will not affect the devices in the SRAM circuit. This effectively reduces operational conflicts caused by the SRAM circuit and the first RRAM device sharing the same control signal. This configuration allows the SRAM circuit and the first RRAM device to work together efficiently, improving the stability and reliability of the non-volatile static random access memory (SRAM) cells. It eliminates the need for additional complex isolation circuits to reduce mutual interference between the SRAM circuit and the first RRAM device during operation, enhancing the area advantage of an array composed of multiple first RRAM devices. Attached Figure Description

[0037] The foregoing contents, as well as other objects, features, and advantages of this disclosure, will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0038] Figure 1A schematic diagram illustrating the structure of a non-volatile static random access memory cell according to an embodiment of the present disclosure is shown.

[0039] Figure 2 This illustration schematically shows another non-volatile static random access memory cell structure according to an embodiment of the present disclosure;

[0040] Figure 3 A schematic diagram of an SRAM circuit structure according to an embodiment of the present disclosure is shown; and

[0041] Figure 4 A schematic diagram of another SRAM circuit structure according to an embodiment of the present disclosure is shown. Detailed Implementation

[0042] The embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the present disclosure for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0043] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0044] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0045] When using expressions such as "at least one of A, B and C", they should generally be interpreted in accordance with the meaning that is commonly understood by those skilled in the art (e.g., "a system having at least one of A, B and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B and C, etc.).

[0046] In realizing the inventive concept of this disclosure, the area occupied by each bit of NVSRAM cell is too large, and the storage capacity per unit chip area is difficult to meet the large-capacity storage requirements of hundreds of megabits or even gigabits. High-density storage has become the core bottleneck restricting the large-scale application of NVSRAM cells.

[0047] In NVSRAM cells based on RRAM devices, the RRAM devices are the non-volatile storage component. Improving the storage density of an NVSRAM cell requires increasing the density of the RRAM devices. Specifically, the density of the RRAM devices can be increased through multi-value storage, three-dimensional resistive switching storage, or a 1TnR array storage method (one CMOS (Complementary Metal Oxide Semiconductor) paired with n RRAM devices for data storage).

[0048] Multi-value storage increases the density of RRAM devices by allowing a single non-volatile element to carry 2 bits or more of data. However, RRAM devices suffer from poor multi-resistive-state stability, are prone to resistive-state confusion due to process variations, significantly reduce reliability, and have poor scalability.

[0049] Three-dimensional resistive random access memory (RRAM) increases the density of RRAM devices by stacking them in a three-dimensional manner. However, this method suffers from problems such as difficult inter-layer interconnection processes, severe crosstalk between upper and lower layer devices, and low process compatibility with CMOS. The mass production cost is three to five times higher than that of planar structures, making it difficult to meet the low-cost requirements of consumer and industrial applications.

[0050] In 1TnR array memory, CMOS offers high process compatibility, strong reliability, and high scalability. RRAM devices, as non-volatile core components, possess nanometer-scale dimensions, nanosecond-level switching speeds, and 10... 12 The advantages of the above-mentioned write / erase cycles are significant. By driving multiple RRAM devices with a single control transistor for writing, reading, backup, and power-down data recovery, storage capacity can be increased without significantly increasing cell area. For example, a 1T4R array storage method can achieve a storage density of 4 bits per cell without overcoming the technical barriers of three-dimensional processes, and is compatible with CMOS processes, making mass production costs controllable.

[0051] However, in the 1TnR array storage method, the RRAM devices and SRAM circuits in the NVSRAM cell share control signals, making it difficult for the RRAM devices and SRAM circuits to operate in harmony. In view of this, the embodiments of this disclosure provide a non-volatile static random access memory cell that can effectively make the operation between RRAM devices and SRAM circuits compatible, thereby improving the stability and reliability of the NVSRAM cell.

[0052] Figure 1 A schematic diagram of a non-volatile static random access memory cell structure according to an embodiment of the present disclosure is shown.

[0053] like Figure 1 As shown, according to an embodiment of the present disclosure, the NVSRAM cell includes an SRAM circuit 101 with a cross-coupled inverter structure, including a storage node Q and an inverting storage node QB; a first control transistor N9 is electrically connected between a first data line CSL and a first node, a second control transistor N8 is electrically connected between the storage node Q and the first node, and a plurality of first RRAM devices Rn are electrically connected between the first node and the corresponding RRAM bit line BLN.

[0054] According to embodiments of this disclosure, the aforementioned storage node Q is used to store data (0 or 1). When the SRAM circuit 101 performs read or write operations on data, the inverting storage node QB provides a voltage difference to storage node Q, causing the state of the data stored in storage node Q to flip (from 0 to 1 or from 1 to 0). The aforementioned first control transistor N9 and second control transistor N8 are both N-type MOS transistors. The aforementioned RRAM bit line BLN is used to provide voltage to the first RRAM device Rn. When the second control transistor N8 is turned on, the path from the first RRAM device Rn to storage node Q via the second control transistor N8 is turned on. The aforementioned first data line CSL is used to provide data to the first control transistor N9. When the first control transistor N9 is turned on, the first data line CSL is turned on via the first control transistor N9 to the first RRAM device Rn.

[0055] The on / off states of the first control transistor N9 and the second control transistor N8 are controlled by different control signals, decoupling the SRAM circuit 101 and the first RRAM device Rn. When the first control transistor N9 is on and the second control transistor N8 is off, or when the first control transistor N9 is off and the second control transistor N8 is on, the first RRAM device Rn and the SRAM circuit 101 can operate simultaneously, reducing the possibility of mutual conflict.

[0056] According to the non-volatile static random access memory (SRAM) cell provided in this disclosure, the SRAM circuit 101 and the first RRAM device Rn are decoupled through a first control transistor N9 and a second control transistor N8. When the first RRAM device Rn and the SRAM circuit 101 can operate simultaneously, the voltage fluctuations generated by the SRAM circuit 101 during operation will not interfere with the resistance stability of the first RRAM device Rn, and the signals generated by the operation of the first RRAM device Rn will not affect the devices in the SRAM circuit 101. This effectively reduces the operational conflicts caused by the SRAM circuit 101 and the first RRAM device sharing the same control signal. This configuration allows the SRAM circuit 101 and the first RRAM device Rn to work together efficiently, improving the stability and reliability of the non-volatile static random access memory cell. It eliminates the need for additional complex isolation circuits to reduce the mutual influence between the SRAM circuit 101 and the first RRAM device Rn during operation, enhancing the area advantage of the array composed of multiple first RRAM devices Rn.

[0057] Figure 2 The schematic diagram illustrates another non-volatile static random access memory cell structure according to an embodiment of the present disclosure.

[0058] like Figure 2 As shown, according to an embodiment of the present disclosure, the NVSRAM cell further includes: a third control transistor N7 electrically connected between the inverting memory node QB and the second node, and a second RRAM device R2 electrically connected between the second node and the reference RRAM bit line CTRL.

[0059] According to embodiments of this disclosure, the third control transistor N7 is an N-type MOS transistor. The reference RRAM bit line CTRL is used to provide voltage to the second RRAM device R2. When the third control transistor N7 is turned on, the path from the second RRAM device R2 to the memory node Q via the third control transistor N7 and the inverting memory node QB is turned on. By adjusting the voltage at the control terminal of the third control transistor N7, the resistance value of the second RRAM device R2 can be adjusted, thereby controlling the voltage of the inverting memory node QB to create a voltage difference between the inverting memory node QB and the memory node Q.

[0060] According to embodiments of this disclosure, by adjusting the resistance value of the second RRAM device R2, the voltage division state between the inverting memory node QB and the memory node Q is adjusted, providing a reference for the level at the memory node Q, ensuring the reliability of data transmission between the inverting memory nodes QB, and thus improving the stability of the NVSRAM cell operation.

[0061] Figure 3 A schematic diagram of an SRAM circuit structure according to an embodiment of the present disclosure is shown. Figure 3As shown, according to an embodiment of this disclosure, the SRAM circuit 101 includes: a first pull-up transistor P1 and a first pull-down transistor N1 connected to form a first inverter 301, wherein the node between the first pull-up transistor P1 and the first pull-down transistor N1 constitutes a storage node Q; a second pull-up transistor P2, a second pull-down transistor N2, and a third pull-down transistor N3 connected to form a second inverter 302, wherein the first inverter 301 and the second inverter 302 are cross-coupled, and the node between the second pull-up transistor P2 and the second pull-down transistor N2 constitutes an inverted storage node QB; a first transfer transistor N4 electrically connected between the SRAM bit line BL and the storage node Q; and a second transfer transistor N5 electrically connected between the complementary SRAM bit line BLB and the inverted storage node QB.

[0062] like Figure 3 As shown, according to an embodiment of this disclosure, the first inverter 301 and the second inverter 302 constitute the cross-coupled inverter structure of the NVSRAM cell. The first pull-up transistor P1 and the second pull-up transistor P2 are P-type MOS transistors. The first transfer transistor N4, the second transfer transistor N5, the first pull-down transistor N1, the second pull-down transistor N2, and the third pull-down transistor N3 are all N-type MOS transistors. Both the SRAM bit line BL and the complementary SRAM bit line BLB can provide data, and the data levels provided by the SRAM bit line BL and the complementary SRAM bit line BLB are complementary. When the data level provided by the SRAM bit line BL is high (data is 1), the data level provided by the complementary SRAM bit line BLB is low (data is 0). When the data level provided by the SRAM bit line BL is low (data is 0), the data level provided by the complementary SRAM bit line BLB is high (data is 1). When the first transmission transistor N4 is turned on, the SRAM bit line BL is turned on via the first transmission transistor N4 to the memory node Q. When the second transmission transistor N5 is turned on, the complementary SRAM bit line BLB is turned on via the second transmission transistor N5 to the inverted memory node QB.

[0063] According to embodiments of this disclosure, a self-locking structure is formed by the cooperation of the first pull-up transistor P1, the second pull-up transistor P2, the first pull-down transistor N1, the second pull-down transistor N2, and the third pull-down transistor N3, ensuring data recovery even after power failure. The cross-coupled inverter structure formed by the first inverter 301 and the second inverter 302 has a positive feedback mechanism, ensuring stable data retention even under external interference, eliminating the need for periodic refresh. When external interference causes voltage fluctuations in memory node Q or the inverted memory node QB, the positive feedback mechanism quickly pulls the voltage of memory node Q or the inverted memory node QB back to a stable state, enhancing the NVSRAM cell's noise suppression capability. This configuration effectively improves the reliability of the NVSRAM cell.

[0064] like Figure 3 As shown, according to an embodiment of this disclosure, the NVSRAM cell is configured to: turn on the first control transistor N9 and turn off the second control transistor N8 via a corresponding control signal, and select a selected RRAM device from a plurality of first RRAM devices Rn via a corresponding RRAM bit line BLN to receive and store data from the first data line CSL via the first control transistor N9. Alternatively, the first control transistor N9 is turned off and the second control transistor N8 is turned on via a corresponding control signal, and a selected RRAM device from a plurality of first RRAM devices Rn is selected via the corresponding RRAM bit line BLN to receive and store data from the storage node Q via the second control transistor N8. Specifically, applying a low level and a high level sequentially to the RRAM bit line BLN stores data from the storage node Q into the selected RRAM device.

[0065] According to embodiments of this disclosure, the high-density storage mode of the first RRAM device Rn is illustrated below. A high-level control signal is provided to the first control transistor N9 and a low-level control signal is provided to the second control transistor N8, causing the first control transistor N9 to be turned on and the second control transistor N8 to be turned off. When the data provided by the first data line CSL is 1 (high level), the selected RRAM device is set, i.e., the data 1 is accepted and stored. When the data provided by the first data line CSL is 0 (low level), the selected RRAM device is reset, i.e., the data 0 is accepted and stored.

[0066] The following example illustrates another high-density storage mode for the first RRAM device Rn. By providing a low-level control signal to the first control transistor N9 and a high-level control signal to the second control transistor N8, the first control transistor N9 is turned off and the second control transistor N8 is turned on. When the data provided by the SRAM bit line BL is 1 (high level), the storage node Q receives and stores this data 1. Then, a low level is first applied to the RRAM bit line BLN connected to the selected RRAM device. Oxygen ions migrate in the selected RRAM device, forming conductive filaments. The selected RRAM device transitions from a high-resistance state to a low-resistance state. Then, a high level is applied to the selected RRAM device, reversing the electric field direction in the selected RRAM device, causing the conductive filaments to break. The selected RRAM device transitions from a low-resistance state to a high-resistance state, and the selected RRAM device receives and stores this data 1 (the selected RRAM is set).

[0067] When the data provided by the SRAM bit line BL is 0 (low level), the storage node Q receives and stores the data 0. Then, a low level is first applied to the RRAM bit line BLN connected to the selected RRAM device. Oxygen ions in the selected RRAM device migrate and form conductive filaments. The selected RRAM device changes from a high-resistance state to a low-resistance state. Then, a high level is applied to the selected RRAM device. The electric field direction in the selected RRAM device reverses, the conductive filaments break, and the selected RRAM device changes from a low-resistance state to a high-resistance state. The selected RRAM device receives and stores the data 0 (the selected RRAM is reset).

[0068] The following example illustrates the data write modes of the SRAM circuit 101. For example... Figure 3 As shown, the first transmission transistor N4 and the second transmission transistor N5 are turned on by the corresponding control signals, and the data stored on the SRAM bit line BL is written into the storage node Q.

[0069] According to embodiments of this disclosure, data is stored using two high-density storage modes of the first RRAM device Rn. These two modes can be performed independently or simultaneously with the operation of the SRAM circuit 101 (data write mode and data read mode of the SRAM circuit 101) without affecting the operation of the SRAM circuit 101. This reduces the conflict between voltage fluctuations generated when the first RRAM device Rn stores data and signals generated when the SRAM circuit 101 operates, further ensuring the stability of the NVSRAM cell.

[0070] Figure 4 A schematic diagram of another SRAM circuit structure according to an embodiment of the present disclosure is shown. Figure 4As shown, according to an embodiment of this disclosure, the NVSRAM cell further includes: a transistor N6, connected between the node between the second pull-down transistor N2 and the third pull-down transistor N3 and the control signal line FBL, and the control terminal is electrically connected to the inverting memory node QB.

[0071] According to embodiments of this disclosure, transistor N6, the second pull-down transistor N2, and the third pull-down transistor N3 form a half-Schmitt structure. The following example illustrates the data reading process of the RRAM device R2. When memory node Q has stored the first data (data is 0) and the inverting memory node QB has stored the second data (data is 1), the SRAM bit line BL provides a high level. A corresponding control signal turns on the first transmission transistor N4, and memory node Q is de-energized to 0V, allowing the SRAM bit line BL to read the data from memory node Q. However, at the instant the first transmission transistor N4 turns on, a path is formed through the SRAM bit line BL, the first transmission transistor N4, memory node Q, the first pull-down transistor N1, and ground, causing the voltage of memory node Q to rise rapidly. This, in turn, gradually turns on the second pull-down transistor N2 and the third pull-down transistor N3, causing the voltage of the inverting memory node QB to drop. This can lead to memory node Q mistakenly flipping to 1 and the inverting memory node QB mistakenly flipping to 0, thereby corrupting the data originally stored in memory node Q and resulting in a data reading error. Therefore, a high level needs to be applied to the control signal line FBL (input terminal of transistor N6). Based on the half-Schmitt structure formed between transistor N6, the second pull-down transistor N2, and the third pull-down transistor N3, the conduction thresholds of the second pull-down transistor N2 and the third pull-down transistor N3 are pulled high, causing the second pull-down transistor N2 and the third pull-down transistor N3 to be turned off. This reduces the error rate of memory node Q and inverting memory node QB, effectively reducing the risk of data corruption during data reading and improving the stability of data reading.

[0072] The following example illustrates the data read modes of the SRAM circuit 101. For example... Figure 4 As shown, the first transmission transistor N4 is turned on by the corresponding control signal, a high level is applied to the control signal line FBL (the input terminal of transistor N6), a high level is applied to the SRAM bit line BL, and the data in the storage node Q is stored in the SRAM bit line BL.

[0073] According to embodiments of this disclosure, the conduction of the second pull-down transistor N2 and the third pull-down transistor N3 is delayed by the half-Schmitt structure formed between transistor N6, the second pull-down transistor N2 and the third pull-down transistor N3, thereby stabilizing the voltage of the storage node Q and the inverting storage node QB, reducing the error flip rate of the storage node Q and the inverting storage node QB, and thus ensuring the stability and reliability of the data read operation of the SRAM circuit 101 in the NVSRAM cell.

[0074] like Figure 4 As shown, according to an embodiment of this disclosure, the NVSRAM cell is configured to: set the second RRAM device R2; turn on the first transfer transistor N4 and the second control transistor N8 and turn off the first control transistor N9 by corresponding control signals, apply a first level to the SRAM bit line BL and apply a second level to the selected RRAM bit line BLN, forming a conduction path through the first transfer transistor N4, the second control transistor N8 and the selected RRAM device corresponding to the selected RRAM bit line BLN, and causing a first voltage at the storage node Q; turn on the second transfer transistor N5 and the third control transistor N7 by corresponding control signals, and apply a first voltage to the complementary SRAM bit line BLB. A first voltage level is applied and a second voltage level is applied to the reference RRAM bit line CTRL, forming a conduction path through the second transfer transistor N5, the third control transistor N7, and the second RRAM device R2, resulting in a second voltage at the inverting memory node QB. The third control transistor N7 causes the resistance between the inverting memory node QB and the reference RRAM line to have a resistance value between the set and reset states of the selected RRAM device. The first transfer transistor N4, the second transfer transistor N5, the second control transistor N8, and the third control transistor N7 are turned off by corresponding control signals. Based on the difference between the first and second voltages, the data on the selected RRAM device is restored to the memory node Q.

[0075] According to embodiments of this disclosure, an example of a high-density data recovery mode for an NVSRAM cell is described below. A difference is created between the resistance between the inverting memory node QB and the reference RRAM line and the resistance between the second control transistor N8 and the RRAM bit line BLN. This creates a voltage difference (the difference between a first voltage and a second voltage) between memory node Q and inverting memory node QB. The path from the selected RRAM device to memory node Q via the second control transistor N8 is then turned on, allowing data stored in the selected RRAM device to be recovered to memory node Q along this path.

[0076] According to embodiments of this disclosure, the resistance between the inverting memory node QB and the reference RRAM line is used as a reference. This creates a voltage difference between memory node Q and the inverting memory node QB. This accelerates the turn-on speed of the selected RRAM device via the second control transistor N8 to memory node Q, thereby enabling faster data recovery to memory node Q and improving the efficiency and reliability of data recovery.

[0077] like Figure 4As shown, according to an embodiment of this disclosure, a first control signal is applied to the control terminal of the second control transistor N8 to turn on the second control transistor N8, and a second control signal is applied to the control terminal of the third control transistor N7 to turn on the third control transistor N7. The level of the second control signal is lower than the level of the first control signal, so that the resistance between the inverting memory node QB and the reference RRAM line has a resistance value between the set state and the reset state of the selected RRAM device.

[0078] According to embodiments of this disclosure, the second control signal is the gate voltage of the second control transistor N8, and the third control voltage is the gate voltage of the third control transistor N7. By lowering the level of the third control signal and raising the voltage of the second control signal, the resistance between the inverting memory node QB and the reference RRAM line is compensated, so that the second RRAM device R2 is between a high-resistance state and a low-resistance state.

[0079] According to embodiments of this disclosure, by placing the second RRAM device R2 between a high-resistance state and a low-resistance state, the selected RRAM device can be turned on more stably via the second control transistor N8 to the storage node Q, reducing the risk of voltage flip-flops in the storage node Q and improving the stability and reliability of restoring data to the storage node Q.

[0080] like Figure 4 As shown, according to an embodiment of this disclosure, the NVSRAM cell is configured to: turn on the third control transistor N7 through a corresponding control signal, and sequentially apply a low level and a high level to the reference RRAM bit line CTRL, thereby backing up the data stored in the storage node Q to the second RRAM device R2.

[0081] According to an embodiment of this disclosure, the backup mode of the second RRAM device R2 is illustrated below. A high-level control signal is provided to the third control transistor N7 to turn it on. When the data provided by the reference RRAM bit line CTRL is 1 (high level), a low level is first applied to the reference RRAM bit line CTRL to which the second RRAM device R2 is connected. Oxygen ions in the second RRAM device R2 migrate, forming conductive filaments. The second RRAM device R2 transitions from a high-resistance state to a low-resistance state. Then, a high level is applied to the second RRAM device R2, reversing the electric field direction in the second RRAM device R2. The conductive filaments break, and the second RRAM device R2 transitions from a low-resistance state to a high-resistance state. The second RRAM device R2 receives and stores the data 1 (the second RRAM is set).

[0082] When the data provided by the reference RRAM bit line CTRL is 0 (low level), a low level is first applied to the reference RRAM bit line CTRL connected to the second RRAM device R2. Oxygen ions in the second RRAM device R2 migrate and form conductive filaments. The second RRAM device R2 changes from a high-resistance state to a low-resistance state. Then, a high level is applied to the second RRAM device R2. The direction of the electric field in the second RRAM device R2 is reversed, the conductive filaments break, and the second RRAM device R2 changes from a low-resistance state to a high-resistance state. The second RRAM device R2 receives the data 0 and stores it (the second RRAM is reset).

[0083] According to embodiments of this disclosure, backing up the data in storage node Q using the second RRAM device R2 can reduce the probability of data loss after power failure of the NVSRAM cell and improve the security of data in the NVSRAM cell.

[0084] like Figure 4 As shown, according to an embodiment of this disclosure, the NVSRAM cell is configured to: apply a high level to the SRAM bit line BL and a low level to the reference RRAM bit line CTRL, turn on the first transmission transistor N4 and the third control transistor N7 through corresponding control signals, and restore the data backed up in the second RRAM device R2 to the storage node Q.

[0085] According to embodiments of this disclosure, the backup and recovery mode of the second RRAM device R2 is illustrated below. A high-level control signal is provided to the first transmission transistor N4 and the third control transistor N7 to turn them on. After the NVSRAM cell is powered off and then powered on again, the storage node Q automatically returns to a low-level state. When the second RRAM device R2 transitions from a low-resistance state to a high-resistance state, the storage node Q receives and stores the backup data 0 from the second RRAM device R2. When the second RRAM device R2 transitions from a high-resistance state to a low-resistance state, the storage node Q receives and stores the backup data 1 from the second RRAM device R2.

[0086] According to embodiments of this disclosure, after the NVSRAM cell is powered on again, the data in the second RRAM device R2 is transmitted back to the storage node Q of the SRAM circuit 101, which increases the probability of data retrieval after the NVSRAM cell is powered off and ensures the security and integrity of the data in the NVSRAM cell.

[0087] Those skilled in the art will understand that the features described in the various embodiments of this disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments of this disclosure can be combined and / or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0088] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A non-volatile static random access memory unit, characterized in that, The non-volatile static random access memory unit includes: A static random access memory circuit with a cross-coupled inverter structure includes a memory node and an inverting memory node; The first control transistor is electrically connected between the first data line and the first node; A second control transistor is electrically connected between the memory node and the first node; and Multiple first resistive random access memory devices are electrically connected between the first node and the corresponding resistive random access memory bit lines.

2. The non-volatile static random access memory unit according to claim 1, characterized in that, The non-volatile static random access memory unit further includes: A third control transistor is electrically connected between the inverting memory node and the second node; and The second resistive random access memory device is electrically connected between the second node and the reference resistive random access memory bit line.

3. The non-volatile static random access memory unit according to claim 2, characterized in that, The static random access memory circuit includes: A first pull-up transistor and a first pull-down transistor are connected to form a first inverter, wherein the node between the first pull-up transistor and the first pull-down transistor constitutes the memory node; The second pull-up transistor, the second pull-down transistor, and the third pull-down transistor are connected to form a second inverter, wherein the first inverter and the second inverter are cross-coupled, and the node between the second pull-up transistor and the second pull-down transistor constitutes the inverted memory node. A first transmission transistor electrically connected between a static random access memory bit line and the memory node; and A second transmission transistor is electrically connected between the complementary static random access memory bit line and the inverting memory node.

4. The non-volatile static random access memory unit according to claim 1, characterized in that, The non-volatile static random access memory unit is configured as follows: The first control transistor is turned on and the second control transistor is turned off by a corresponding control signal, and a selected resistive random access memory device among the plurality of first resistive random access memory devices is selected by a corresponding resistive random access memory bit line to receive data from the first data line via the first control transistor and store the data. or The first control transistor is turned off and the second control transistor is turned on by a corresponding control signal, and a selected resistive random access memory device among the plurality of first resistive random access memory devices is selected by a corresponding resistive random access memory bit line to receive data from the memory node via the second control transistor and store the data.

5. The non-volatile static random access memory unit according to claim 4, characterized in that, The non-volatile static random access memory unit is configured as follows: By sequentially applying low and high levels to the resistive random access memory bit lines, the data in the memory node is stored in the selected resistive random access memory device.

6. The non-volatile static random access memory unit according to claim 3, characterized in that, The non-volatile static random access memory unit further includes: A transistor is connected between the node between the second pull-down transistor and the third pull-down transistor and the control signal line, and the control terminal is electrically connected to the inverting memory node.

7. The non-volatile static random access memory unit according to claim 3, characterized in that, The non-volatile static random access memory unit is configured as follows: Set the second resistive random access memory device; By turning on the first transmission transistor and the second control transistor and turning off the first control transistor through the corresponding control signals, a first level is applied to the static random access memory bit line and a second level is applied to the selected resistive random access memory bit line, forming a conduction path through the first transmission transistor, the second control transistor and the selected resistive random access memory device corresponding to the selected resistive random access memory bit line, and causing a first voltage on the memory node. The second transmission transistor and the third control transistor are turned on by corresponding control signals, the first level is applied to the complementary static random access memory bit line and the second level is applied to the reference resistive random access memory bit line, forming a conduction path through the second transmission transistor, the third control transistor and the second resistive random access memory device, and causing a second voltage on the inverting memory node, wherein the resistance between the inverting memory node and the reference resistive random access memory line is made to have a resistance value between the set state and the reset state of the selected resistive random access memory device through the third control transistor; By turning off the first transmission transistor, the second transmission transistor, the second control transistor, and the third control transistor through corresponding control signals, the data on the selected resistive random access memory device is restored to the memory node based on the difference between the first voltage and the second voltage.

8. The non-volatile static random access memory unit according to claim 7, characterized in that, A first control signal is applied to the control terminal of the second control transistor to turn on the second control transistor, and a second control signal is applied to the control terminal of the third control transistor to turn on the third control transistor, wherein the level of the second control signal is lower than the level of the first control signal, so that the resistance between the inverting memory node and the reference resistive random access memory line has a resistance value between the set state and the reset state of the selected resistive random access memory device.

9. The non-volatile static random access memory unit according to claim 3, characterized in that, The non-volatile static random access memory unit is configured as follows: The third control transistor is turned on by a corresponding control signal, and a low level and a high level are sequentially applied to the reference resistive random access memory bit line to back up the data stored in the memory node to the second resistive random access memory device.

10. The non-volatile static random access memory unit according to claim 9, characterized in that, The non-volatile static random access memory unit is configured as follows: A high level is applied to the static random access memory bit line and a low level is applied to the reference resistive random access memory bit line. The first transmission transistor and the third control transistor are turned on by the corresponding control signal, and the data backed up in the second resistive random access memory device is restored to the memory node.

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