Semiconductor device

Abstract

The invention relates to a semiconductor device. A semiconductor device may include: a cell memory bank in which a plurality of normal data storage regions and a plurality of ECC data storage regions are disposed in a three-dimensional matrix on a plurality of stacked layers, the plurality of normal data storage regions and the plurality of ECC data storage regions corresponding to different numbers of bit lines; and a peripheral layer electrically connected to the cell bank and located below a layer of the cell bank, in which the peripheral layer includes an internal circuit configured to control the cell bank, the internal circuit including a plurality of test circuits, the plurality of test circuits are configured to identify whether all data output from the plurality of normal data storage regions and the plurality of ECC data storage regions are identical to each other.

Description

Cross-references to related applications

[0001] This patent application claims priority to Korean Patent Application No. 10-2024-0131449, filed on September 27, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] Embodiments of this disclosure relate to integrated circuit technology, and more specifically, to semiconductor devices. Background Technology

[0003] Recently, with the reduction in size, power consumption, performance improvement, and diversification of electronic devices, various electronic devices (such as computers and portable communication devices) require semiconductor devices capable of storing information. Semiconductor devices can be broadly classified into volatile memory devices and non-volatile memory devices. Volatile memory devices retain data only when powered on. Non-volatile memory devices retain data even when no power is supplied.

[0004] In order to reduce the size of semiconductor devices and increase their data storage capacity, semiconductor devices have been developed that allow many memory cells to be integrated in the same area by reducing the width of metal lines in a two-dimensional (2D) plane.

[0005] However, as the manufacturing equipment, investment costs, and development cycles increase exponentially as the width of metal lines in a 2D plane decreases, technologies are being developed to realize semiconductor devices with three-dimensional (3D) structures. Summary of the Invention

[0006] In one embodiment of this disclosure, a semiconductor device may include: a cell bank, wherein a plurality of normal data storage regions and a plurality of ECC data storage regions are arranged in a three-dimensional matrix on a plurality of stacked layers, the plurality of normal data storage regions and the plurality of ECC data storage regions corresponding to different numbers of bit lines; and a peripheral layer electrically connected to the cell bank and located below the layers of the cell bank, wherein the peripheral layer includes internal circuitry configured to control the cell bank, the internal circuitry including a plurality of test circuits configured to identify whether all data output from the plurality of normal data storage regions and the plurality of ECC data storage regions are identical to each other.

[0007] In one embodiment of this disclosure, a semiconductor device may include: a memory bank including a plurality of normal data storage regions and at least one ECC data storage region, the normal data storage regions corresponding to a plurality of bit lines, and the ECC data storage region corresponding to a fewer number of bit lines compared to each of the plurality of normal data storage regions; and a test circuit configured to identify whether all data output from the plurality of normal data storage regions and data output from the ECC data storage region are identical to each other based on a column address of a selected bit line, wherein the test circuit: identifies whether the data output from the normal data storage region and the data output from the ECC data storage region are identical to each other when a bit line included in the ECC data storage region is selected based on a column address; and identifies whether the data output from the normal data storage region is identical to each other when a bit line included in the ECC data storage region is not selected based on a column address.

[0008] In one embodiment of this disclosure, a semiconductor device may include: a memory bank including first to sixteenth normal data storage regions and first to fourth ECC data storage regions; a first test circuit configured to identify, based on the most significant bit of a column address, whether data output from the first to eighth normal data storage regions is identical to each other, or whether data output from the first to eighth normal data storage regions and data output from the first and second ECC data storage regions are identical to each other; and a second test circuit configured to: identify, based on the most significant bit of a column address, whether data output from the ninth to sixteenth normal data storage regions is identical to each other, or whether data output from the ninth to sixteenth normal data storage regions and data output from the third and fourth ECC data storage regions are identical to each other. Attached Figure Description

[0009] Figure 1 This is a diagram illustrating a memory cell with a 2D structure included in a semiconductor device according to embodiments of the present disclosure.

[0010] Figures 2 to 4 This is a diagram used to describe the 3D structure of a storage medium according to embodiments of the present disclosure.

[0011] Figure 5 This is a diagram illustrating the configuration of a semiconductor device according to embodiments of the present disclosure.

[0012] Figure 6 This is a diagram illustrating a test circuit for a semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 7 This is a diagram illustrating a detailed configuration of a test circuit included in a semiconductor device according to embodiments of the present disclosure. Detailed Implementation

[0014] Hereinafter, embodiments based on the technical essence of this disclosure will be described with reference to the accompanying drawings.

[0015] Embodiments of this disclosure provide a semiconductor device capable of normal operation even in a three-dimensional (3D) structure.

[0016] It is possible to improve the reliability of semiconductor devices with 3D structures.

[0017] A semiconductor device can be configured to store data and output the stored data. In this case, the semiconductor device may include memory cells in which data is stored. Memory cells may be coupled to bit lines and word lines. For example, the semiconductor device may include multiple memory cells coupled to multiple bit lines and multiple word lines, respectively. For example, the semiconductor device may be configured such that a memory cell connecting a selected bit line among multiple bit lines and a selected word line among multiple word lines is designated. In this case, the semiconductor device may be configured to store data in the designated memory cell and output the stored data.

[0018] Semiconductor devices can test whether memory cells are storing data correctly. They can also perform repair operations on memory cells where data is not being stored correctly.

[0019] For example, a semiconductor device may include multiple memory banks. Each of the multiple memory banks may include multiple data storage areas. Each of the multiple data storage areas may include a predetermined number of memory cells.

[0020] A semiconductor device can identify a memory bank among multiple memory banks that includes memory cells where data is not stored correctly, and can repair a memory bank including abnormal memory cells by using another memory bank. In this case, to identify a memory cell where data is not stored correctly, the semiconductor device can perform a test to store the same data in all memory cells of the memory bank, output the data stored in all memory cells, and compare the data. When the data stored in all memory cells during the test is the same as each other, the semiconductor device can determine that the memory bank is normal; and when at least one piece of data stored in all memory cells during the test is different, the semiconductor device can determine that the memory bank includes at least one abnormal memory cell. A semiconductor device according to embodiments of this disclosure can be configured to identify a memory bank including memory cells where data is not stored correctly.

[0021] Figure 1 This is a diagram illustrating a memory cell with a two-dimensional (2D) structure included in a semiconductor device according to embodiments of the present disclosure. Figure 1 In this example, a storage unit comprising seventeen data storage areas can be shown as an embodiment.

[0022] refer to Figure 1 A storage unit with a 2D structure may include first to seventeenth data storage areas H0 to H15 and an ECC. In this case, some of the first to seventeenth data storage areas H0 to H15 and the ECC (e.g., H0 to H15) may be areas for storing normal data, while the remaining ECC may be areas for storing ECC data required for error correction codes (ECC).

[0023] In one embodiment, the first to seventeenth data storage areas H0 to H15 and the ECC can be arranged along a first direction X. For example, the first to sixteenth data storage areas H0 to H15, which store normal data, can be arranged sequentially along the first direction X. In this case, the seventeenth data storage area ECC, which stores ECC data, can be located between the eighth data storage area H7 (not shown) and the ninth data storage area H8 (not shown).

[0024] Each of the first to seventeenth data storage areas H0 to H15 and the ECC can include 64k word lines (64k WL) and 512 bit lines (512 BL). In this case, k can refer to the decimal number 1024, and 64k can refer to 64 * 1024. Furthermore, a storage cell can be connected to the intersection of a word line and a bit line. Therefore, the number of word lines and the number of bit lines can correspond to the data storage capacity.

[0025] Each of the 64k word lines in the 64k WL can be configured to extend and form in the first direction X.

[0026] Each of the 512 bit lines in the 512 BL can be configured to extend and form in the second direction Y. The first direction X and the second direction Y can be mutually intersecting directions.

[0027] A storage unit with a 2D structure as described above can store the same data in the first to seventeenth data storage areas H0 to H15 and ECC, can output the data stored in the first to seventeenth data storage areas H0 to H15 and ECC, can compare the output data, and can determine that the storage unit includes at least one storage cell where the data was not stored correctly when at least one piece of data is different.

[0028] Figures 2 to 4 This is a diagram used to describe the 3D structure of a storage medium according to embodiments of the present disclosure.

[0029] Figure 2 This is a diagram used to compare and describe normal data storage areas with 2D structures and normal data storage areas with 3D structures. In this context, Figure 2 It can be shown Figure 1 The first data storage area H0 is used as an example.

[0030] See Figure 2 A data storage region H0 with a 2D structure can have a planar structure defined in a first direction X and a second direction Y. A normal data storage region H0 with a 3D structure can have a structure in which the planar structures defined in the first direction X and the second direction Y are stacked in a third direction Z. In this case, the third direction Z can be a direction orthogonal to the plane defined in the first direction X and the second direction Y.

[0031] For example, a data storage region H0 with a 2D structure may include 64k word lines (64k WL) and 512 bit lines (512 BL). A normal data storage region H0 with a 3D structure may also include 64k word lines (64k WL) and 512 bit lines (512 BL). In this case, the normal data storage region H0 with a 3D structure may be a structure stacked with 64 layers. Each of the 64 layers may include 1k word lines (1k WL) and 512 bit lines (512 BL).

[0032] Therefore, a data storage area H0 with a 2D structure and a normal data storage area H0 with a 3D structure can have the same data storage capacity because the data storage area H0 with a 2D structure and the normal data storage area H0 with a 3D structure include the same number of word lines and the same number of bit lines.

[0033] Figure 3 This is a diagram used to compare and describe ECC data storage areas with 2D and 3D structures. In this context, Figure 3 It can be shown Figure 1 The seventeenth data storage area, ECC, is used as an example. In this case, the data storage area ECC with a 2D structure and the ECC data storage areas ECC 1 / 4, ECC 2 / 4, ECC 3 / 4, and ECC 4 / 4, which all have a 3D structure, can all be areas that store the ECC data required for using error correction codes (ECC).

[0034] refer to Figure 3A data storage region ECC with a 2D structure can have a planar structure defined in a first direction X and a second direction Y. Each of the first to fourth ECC data storage regions ECC 1 / 4, ECC 2 / 4, ECC 3 / 4, and ECC 4 / 4, all having a 3D structure, can have a structure where the planar structures defined in the first direction X and the second direction Y are stacked in a third direction Z. In this case, the third direction Z can be a direction orthogonal to the plane defined in the first direction X and the second direction Y. For example, a data storage region ECC with a 2D structure can include 64k word lines (64k WL) and 512 bit lines (512 BL). Each of the first to fourth ECC data storage regions ECC 1 / 4, ECC 2 / 4, ECC 3 / 4, and ECC 4 / 4, all having a 3D structure, can have a structure with 64 stacked layers. Each of the 64 layers can include 1k word lines (1k WL) and 128 bit lines (128 BL). Therefore, the total number of word lines in the first to fourth ECC data storage areas ECC 1 / 4, ECC 2 / 4, ECC 3 / 4 and ECC 4 / 4, which all have a 3D structure, can be 64k (i.e., 64k WL), and the total number of bit lines can be 512 (i.e., 512 BL).

[0035] Therefore, since the total number of word lines and bit lines in the first to fourth ECC data storage areas ECC 1 / 4, ECC 2 / 4, ECC 3 / 4 and ECC 4 / 4 are the same as the total number of word lines and bit lines in the ECC data storage area with 2D structure, the first to fourth ECC data storage areas ECC 1 / 4, ECC 2 / 4, ECC 3 / 4 and ECC 4 / 4, which all have 3D structure, can have the same data storage capacity.

[0036] Figure 4 It is a diagram used to describe a storage unit with a 3D structure, whose data storage capacity is related to... Figure 2 The memory bank shown is the same as the one with a 2D structure. Figure 4 It is through the use of Figure 2 The normal data storage area H0 with a 3D structure shown in the figure and Figure 3The diagram shown illustrates a 3D-structured storage unit constructed from first to fourth normal data storage regions ECC 1 / 4, ECC 2 / 4, ECC 3 / 4, and ECC 4 / 4. In this embodiment, the 3D-structured storage unit may include a structure in which data storage regions H0 to H15, ECC 1 / 4, ECC 2 / 4, ECC 3 / 4, and ECC 4 / 4 are arranged in a matrix on a plane defined by a first direction X and a second direction Y, and this matrix arrangement is stacked in a third direction Z. That is, data storage regions H0 to H15, ECC 1 / 4, ECC 2 / 4, ECC 3 / 4, and ECC 4 / 4 are arranged in a 3D matrix on a stacked layer.

[0037] refer to Figure 4 A storage unit may include first to sixteenth normal data storage areas H0 to H15 for storing normal data and first to fourth ECC data storage areas ECC 1 / 4, ECC 2 / 4, ECC 3 / 4 and ECC4 / 4 for storing ECC data.

[0038] The first to fourth normal data storage areas H0, H1, H2, and H3 can be arranged along the first direction X. In this case, the first ECC data storage area ECC 1 / 4 can be located between the second normal data storage area H1 and the third normal data storage area H2. That is, the first normal data storage area H0, the second normal data storage area H1, the first ECC data storage area ECC 1 / 4, the third normal data storage area H2, and the fourth normal data storage area H3 can be arranged sequentially along the first direction X.

[0039] The fifth to eighth normal data storage areas H4, H5, H6, and H7 can be arranged along the first direction X. In this case, the second ECC data storage area ECC 2 / 4 can be arranged between the sixth normal data storage area H5 and the seventh normal data storage area H6. That is, the fifth normal data storage area H4, the sixth normal data storage area H5, the second ECC data storage area ECC 2 / 4, the seventh normal data storage area H6, and the eighth normal data storage area H7 can be arranged sequentially along the first direction X. Furthermore, the fifth normal data storage area H4 can be arranged adjacent to the first normal data storage area H0 in the second direction Y. The sixth normal data storage area H5 can be arranged adjacent to the second normal data storage area H1 in the second direction Y. The second ECC data storage area ECC 2 / 4 can be arranged adjacent to the first ECC data storage area ECC 1 / 4 in the second direction Y. The seventh normal data storage area H6 can be arranged adjacent to the third normal data storage area H2 in the second direction Y. The eighth normal data storage area H7 can be arranged adjacent to the fourth normal data storage area H3 in the second direction Y.

[0040] The ninth to twelfth normal data storage areas H8, H9, H10, and H11 can be located in the first direction X. In this case, the third ECC data storage area ECC 3 / 4 can be located between the tenth normal data storage area H9 and the eleventh normal data storage area H10. That is, the ninth normal data storage area H10, the tenth normal data storage area H11, the third ECC data storage area ECC 3 / 4, the eleventh normal data storage area H10, and the twelfth normal data storage area H11 can be arranged sequentially along the first direction X. Furthermore, the ninth normal data storage area H8 can be located adjacent to the fifth normal data storage area H4 in the second direction Y. The tenth normal data storage area H9 can be located adjacent to the sixth normal data storage area H5 in the second direction Y. The third ECC data storage area ECC 3 / 4 can be located adjacent to the second ECC data storage area ECC 2 / 4 in the second direction Y. The eleventh normal data storage area H10 can be located adjacent to the seventh normal data storage area H6 in the second direction Y. The twelfth normal data storage area H11 can be set to be adjacent to the eighth normal data storage area H7 in the second direction Y.

[0041] The thirteenth to sixteenth normal data storage areas H12, H13, H14, and H15 can be arranged along the first direction X. In this case, the fourth ECC data storage area ECC 4 / 4 can be arranged between the fourteenth normal data storage area H13 and the fifteenth normal data storage area H14. That is, the thirteenth normal data storage area H12, the fourteenth normal data storage area H13, the fourth ECC data storage area ECC 4 / 4, the fifteenth normal data storage area H14, and the sixteenth normal data storage area H15 can be arranged sequentially along the first direction X. Furthermore, the thirteenth normal data storage area H12 can be arranged adjacent to the ninth normal data storage area H8 in the second direction Y. The fourteenth normal data storage area H13 can be arranged adjacent to the tenth normal data storage area H9 in the second direction Y. The fourth ECC data storage area ECC 4 / 4 can be arranged adjacent to the third ECC data storage area ECC 3 / 4 in the second direction Y. The fifteenth normal data storage area H14 can be arranged adjacent to the eleventh normal data storage area H10 in the second direction Y. The sixteenth normal data storage area H15 can be set to be adjacent to the twelfth normal data storage area H11 in the second direction Y.

[0042] Figure 1 The memory bank with a 2D structure shown may include the first to seventeenth data storage areas H0 to H15 and ECC, each with 64k word lines (64k WL) and 512 bit lines (512 BL). Figure 4 The 3D-structured memory bank shown may include first to sixteenth normal data storage areas H0 to H15, each with 64k word lines and 512 bit lines, and first to fourth ECC data storage areas ECC 1 / 4, ECC 2 / 4, ECC 3 / 4, and ECC 4 / 4, each with 64k word lines and 128 bit lines. The total number of word lines and bit lines in the first to fourth ECC data storage areas ECC 1 / 4, ECC 2 / 4, ECC 3 / 4, and ECC 4 / 4 may be the same as the total number of word lines and bit lines in a single data storage area (e.g., the first data storage area H0) with a 2D structure.

[0043] therefore, Figure 1 The memory cell with a 2D structure shown is Figure 4 The memory banks with 3D structures shown can have the same data storage capacity because they have the same number of word lines and the same number of bit lines.

[0044] Each of the first to sixteenth normal data storage areas H0 to H15 includes 512 bit lines 512 BL, which can be configured such that at least one of the 512 bit lines 512 BL is selected based on a column address (not shown).

[0045] Furthermore, the 512 bit lines (i.e., 128+128+128+128=512) contained in the first to fourth ECC data storage areas ECC 1 / 4, ECC 2 / 4, ECC 3 / 4, and ECC 4 / 4 can be configured such that at least one of the 512 bit lines is selected based on a column address (not shown). Therefore, at least one of the first to fourth ECC data storage areas ECC 1 / 4, ECC 2 / 4, ECC 3 / 4, and ECC 4 / 4 may include a bit line selected based on a column address. For example, the first ECC data storage area ECC 1 / 4 may include at least one bit line selected by a column address. The second ECC data storage area, ECC 2 / 4, among the first to fourth ECC data storage areas ECC 1 / 4, ECC 2 / 4, ECC 3 / 4, and ECC 4 / 4, may include at least one bit line selected by a column address. The third ECC data storage area, ECC 3 / 4, among the first to fourth ECC data storage areas ECC 1 / 4, ECC 2 / 4, ECC 3 / 4, and ECC 4 / 4, may include at least one bit line selected by a column address. The fourth ECC data storage area, ECC 4 / 4, among the first to fourth ECC data storage areas ECC 1 / 4, ECC 2 / 4, ECC 3 / 4, and ECC 4 / 4, may include at least one bit line selected by a column address.

[0046] Therefore, each of the first to sixteenth normal data storage areas H0 to H15 and the first to fourth ECC data storage areas ECC 1 / 4, ECC 2 / 4, ECC 3 / 4, and ECC 4 / 4 may include at least one bit line selected based on the same column address from the 512 bit lines 512 BL. Therefore, each of the first to sixteenth normal data storage areas H0 to H15 may include a bit line selected based on the same column address. Only one of the first to fourth ECC data storage areas ECC 1 / 4, ECC 2 / 4, ECC 3 / 4, and ECC 4 / 4 may include the selected bit line.

[0047] Each of the first to sixteenth normal data storage areas H0 to H15 can have a larger data storage capacity than each of the first to fourth ECC data storage areas ECC 1 / 4, ECC 2 / 4, ECC 3 / 4, and ECC 4 / 4, because each of the first to sixteenth normal data storage areas H0 to H15 has a larger number of bit lines than each of the first to fourth ECC data storage areas ECC1 / 4, ECC 2 / 4, ECC 3 / 4, and ECC 4 / 4. Therefore, the first to sixteenth normal data storage areas H0 to H15 can be referred to as large unit areas, and the first to fourth ECC data storage areas can be referred to as small unit areas.

[0048] Figure 5 This is a diagram used to describe the configuration of a semiconductor device according to embodiments of the present disclosure. Figure 5 It is shown Figure 4 The diagram shown illustrates a memory bank including storage cells, referred to as a cell memory bank, and a region including the internal circuitry of the control unit memory bank, referred to as a peri-bank (i.e., peripheral layer). The cell memory bank and the peri-bank can be electrically connected via hybrid bonding.

[0049] refer to Figure 5 The semiconductor device according to embodiments of the present disclosure may include a cell memory and a peripheral body.

[0050] The description of the cell memory is based on a reference. Figure 4 The given description will replace it.

[0051] The peripheral body can be electrically connected to the cell memory. The peripheral body can be configured to be adjacent to the cell memory in a third direction Z. For example, the peripheral body can be located below the cell memory and electrically connected to the cell memory.

[0052] Peripherals may include the internal circuitry of the control unit memory. For example, peripherals may include a column decoder (YDEC), a word line driver (WDRV), a sense amplifier (IOSA), an ECC circuit (ECC), and test circuits (Test Circuit_UP and Test Circuit_DN). The column decoder (YDEC) can selectively drive the bit lines of the cell memory based on column addresses (not shown). The word line driver (WDRV) can selectively drive the word lines of the cell memory based on row addresses (not shown). The sense amplifier (IOSA) can sense data stored in the memory cells of the cell memory. The ECC circuit (ECC) can correct errors in the data sensed from the memory cells of the cell memory (i.e., errors in the data output after a read operation has begun). The test circuits (TestCircuit_UP and Test Circuit_DN) can be used when the semiconductor device is being tested. For example, the test circuits (TestCircuit_UP and Test Circuit_DN) can test whether the memory cells of the cell memory are storing data correctly.

[0053] Generally speaking, semiconductor devices, including memory cells, perform redundancy operations, which involve testing whether the memory cells can store data properly and replacing defective memory cells with normal ones based on the test results.

[0054] According to embodiments of this disclosure, a semiconductor device including a cell memory with a 3D structure can also perform redundancy operations, namely, testing whether the memory cells of the cell memory are storing data correctly, and replacing defective memory cells with normal memory cells based on the test results. In this case, test circuits Test Circuit_UP and Test Circuit_DN can be used.

[0055] For example, a test to identify whether a storage cell is storing data correctly can include an operation to identify whether all the data stored in a storage cell is the same after a write operation is performed that stores data with the same level in all the storage cells contained in the cell storage.

[0056] Test Circuit_UP and Test Circuit_DN can be circuits used to identify whether all data sensed from the storage unit is the same.

[0057] Figure 6 This is a diagram illustrating a test circuit for a semiconductor device according to embodiments of the present disclosure.

[0058] refer to Figure 6According to embodiments of the present disclosure, the test circuits Test Circuit_UP and TestCircuit_DN of the semiconductor device may include a first test circuit Test Circuit_UP 10 and a second test circuit Test Circuit_DN 20.

[0059] The first test circuit 10 can identify whether all the data output from some memory cells of the cell memory bank are the same.

[0060] The second test circuit 20 can identify whether all the data output from the other memory cells of the cell memory bank are the same.

[0061] The first test circuit 10 can be located below the area where the fifth to eighth normal data storage areas H4 to H7 and the second ECC data storage area ECC 2 / 4 are located. The second test circuit 20 can be located below the area where the ninth to twelfth normal data storage areas H8 to H11 and the third ECC data storage area ECC 3 / 4 are located.

[0062] The first test circuit 10 can be configured to identify whether all data output from the first to eighth normal data storage areas H0 to H7 and the first and second ECC data storage areas ECC 1 / 4 and ECC 2 / 4 included in the cell memory are identical. Furthermore, the second test circuit 20 can be configured to identify whether all data output from the ninth to sixteenth normal data storage areas H9 to H15 and the third and fourth ECC data storage areas ECC 3 / 4 and ECC 4 / 4 included in the cell memory are identical. Both the first test circuit 10 and the second test circuit 20 are positioned below the data storage area under test to minimize the length of the conductors.

[0063] Figure 7 This is a diagram illustrating a detailed configuration of a test circuit included in a semiconductor device according to embodiments of the present disclosure. Figure 7 It can be shown Figure 6 The diagram shows the first test circuit 10 and the second test circuit 20.

[0064] See Figure 7 The first test circuit 10 and the second test circuit 20 may respectively include selection circuits MUX0 and MUX1 and data comparison circuits XOR0 and XOR1.

[0065] The first test circuit 10 can be configured to identify whether all data output from the first to eighth normal data storage areas H0 to H7 and the first and second ECC data storage areas ECC 1 / 4 and ECC 2 / 4 included in the cell memory are the same.

[0066] The first test circuit 10 may include a multiplexer (i.e., a selection circuit) MUX0 as the selection circuit MUX0, and an XOR gate (i.e., a data comparison circuit) XOR0 as the data comparison circuit XOR0.

[0067] Address based on the highest column address (i.e., the highest bit of the column address) <9> The multiplexer MUX0 can provide the XOR gate XOR0 with one of the data H7<0:7> output from the eighth normal data storage area H7 and the data ECC_UP<0:7> output from the first and second ECC data storage areas ECC 1 / 4 and ECC 2 / 4. For example, when the highest column address is... <9> When the value is high (1), the multiplexer MUX0 can provide the data H7<0:7> output from the eighth normal data storage area H7 to the XOR gate XOR0. When the highest column address... <9> When the level is low (0), the multiplexer MUX0 can provide the data ECC_UP<0:7> output from the first and second ECC data storage areas ECC 1 / 4 and ECC 2 / 4 to the XOR gate XOR0.

[0068] The XOR gate XOR0 can identify whether all data H0<0:7>, H1<0:7>, H2<0:7>, H3<0:7>, H4<0:7>, H5<0:7>, H6<0:7>, and H7<0:7> output from the first to eighth normal data storage areas H0 to H7 have the same data value as the data output from the multiplexer MUX0. For example, when all input data have the same value, the XOR gate XOR0 can output a test result signal Test_UP at a low level 0. When any input data has a different data value, the XOR gate XOR0 can output a test result signal Test_UP at a high level 1. In this case, the data output from the first normal data storage area H0 can be H0<0:7>. The data output from the second normal data storage area H1 can be H1<0:7>. The data output from the third normal data storage area H2 can be H2<0:7>. The data output from the fourth normal data storage area H3 can be H3<0:7>. Data output from the fifth normal data storage area H4 can be H4<0:7>. Data output from the sixth normal data storage area H5 can be H5<0:7>. Data output from the seventh normal data storage area H6 can be H6<0:7>. Data output from the eighth normal data storage area H7 can be H7<0:7>. Furthermore, data output from either the first or second ECC data storage areas ECC 1 / 4 and ECC 2 / 4 can be ECC_UP<0:7>.

[0069] The second test circuit 20 may include a multiplexer (i.e., a selection circuit) MUX1 as the selection circuit MUX1 and an XOR gate (i.e., a data comparison circuit) XOR1 as the data comparison circuit XOR1.

[0070] Based on the highest column address (Address) <9> The multiplexer MUX1 can provide the XOR gate XOR1 with one of the data H8<0:7> output from the ninth normal data storage area H8 and the data ECC_DN<0:7> output from the third and fourth ECC data storage areas ECC 3 / 4 and ECC 4 / 4. For example, when the highest column address is... <9> When the value is high (1), multiplexer MUX1 provides the data ECC_DN<0:7> output from the third and fourth ECC data storage areas ECC 3 / 4 and ECC 4 / 4 to XOR gate XOR1. When the highest column address... <9> When the level is low (0), the multiplexer MUX1 provides the data H8<0:7> output from the ninth normal data storage area H8 to the XOR gate XOR1.

[0071] The XOR gate XOR1 can identify whether all data output from the ninth to sixteenth normal data storage areas H8 to H15 (H8<0:7>, H9<0:7>, H10<0:7>, H11<0:7>, H12<0:7>, H13<0:7>, H14<0:7>, and H15<0:7>) and the data output from the multiplexer MUX1 have the same data value. For example, when all input data have the same value, the XOR gate XOR1 can output a test result signal Test_UP at a low level (0). When any of the input data has a different data value, the XOR gate XOR1 can output a test result signal Test_UP at a high level (1). In this case, the data output from the ninth normal data storage area H8 can be H8<0:7>. The data output from the tenth normal data storage area H9 can be H9<0:7>. The data output from the eleventh normal data storage area H10 can be H10<0:7>. Data output from the twelfth normal data storage area H11 can be H11<0:7>. Data output from the thirteenth normal data storage area H12 can be H12<0:7>. Data output from the fourteenth normal data storage area H13 can be H13<0:7>. Data output from the fifteenth normal data storage area H14 can be H14<0:7>. Data output from the sixteenth normal data storage area H15 can be H15<0:7>. Furthermore, data output from either the third or fourth ECC data storage areas ECC 3 / 4 and ECC 4 / 4 can be ECC_DN<0:7>.

[0072] In this case, the data H0<0:7> to H15<0:7> output from the first to the sixteenth normal data storage areas H0 to H15 respectively can be data output from storage cells connected to bit lines selected by the same column address. One of the data ECC_UP<0:7> and ECC_DN<0:7> can be output from the first to the fourth ECC data storage areas ECC 1 / 4, ECC 2 / 4, ECC 3 / 4, and ECC 4 / 4 relative to the same column address.

[0073] More specifically, each of the first to sixteenth normal data storage areas H0 to H15 may include one of 512 bit lines selected by a column address capable of selecting one of the 512 bit lines. Therefore, each of the first to sixteenth normal data storage areas H0 to H15 can output data from the storage cell connected to the selected bit line. However, the first to fourth ECC data storage areas ECC 1 / 4, ECC 2 / 4, ECC 3 / 4, and ECC 4 / 4 can select one of a total of 512 bit lines by a column address capable of selecting one of the 512 bit lines. Therefore, only one of the first to fourth ECC data storage areas ECC 1 / 4, ECC 2 / 4, ECC 3 / 4, and ECC 4 / 4 may include the selected bit line. Therefore, the data output from the first to fourth ECC data storage areas ECC 1 / 4, ECC 2 / 4, ECC 3 / 4 and ECC 4 / 4 via column address can be data ECC_UP<0:7> output from the first and second ECC data storage areas ECC 1 / 4 and ECC 2 / 4 or data ECC_DN<0:7> output from the third and fourth ECC data storage areas ECC3 / 4 and ECC 4 / 4.

[0074] Therefore, the data output from the first to fourth ECC data storage areas ECC 1 / 4, ECC 2 / 4, ECC 3 / 4, and ECC 4 / 4 by selecting one of the column addresses of the 512 bit lines can be either ECC_UP<0:7> or ECC_DN<0:7>. The other of ECC_UP<0:7> and ECC_DN<0:7> may not be data output from the storage unit.

[0075] The first and second ECC data storage areas, ECC 1 / 4 and ECC 2 / 4, may include the upper 256 bit lines of the 512 bit lines included in the first through fourth ECC data storage areas, ECC 1 / 4, ECC 2 / 4, ECC 3 / 4, and ECC 4 / 4. The third and fourth ECC data storage areas, ECC 3 / 4 and ECC 4 / 4, may include the lower 256 bit lines of the 512 bit lines included in the first through fourth ECC data storage areas, ECC 1 / 4, ECC 2 / 4, ECC 3 / 4, and ECC 4 / 4. In this case, the most significant bit of the column address can be used to determine whether the selected bit line is one of the upper 256 bit lines or one of the lower 256 bit lines.

[0076] Therefore, by identifying whether the selected bit line is contained in the first and second ECC data storage areas ECC 1 / 4 and ECC 2 / 4 or in the third and fourth ECC data storage areas ECC 3 / 4 and ECC 4 / 4, it is possible to identify, based on the most significant bit of the column address, which of the data ECC_UP<0:7> and ECC_DN<0:7> output from the first to fourth ECC data storage areas ECC 1 / 4, ECC 2 / 4, ECC 3 / 4 and ECC 4 / 4 corresponds to the data output from the storage cell.

[0077] like Figure 7 As shown, the first test circuit 10 is configured to identify whether the data output from the first to seventh normal data storage areas H0 to H6 is the same as the data output from the first and second ECC data storage areas ECC 1 / 4 and ECC 2 / 4. The second test circuit 20 is configured to identify whether the data output from the eighth to sixteenth normal data storage areas H7 to H15 is the same as the data output from the third and fourth ECC data storage areas ECC 3 / 4 and ECC 4 / 4.

[0078] Each of the first to sixteenth normal data storage areas H0 to H15 can output data H0<0:7> to H15<0:7> from a memory cell connected to a selected bit line based on a column address that can select one of the 512 bit lines. However, only one of the data ECC_UP<0:7> and ECC_DN<0:7> can be output from the memory cell because only one of the first to fourth ECC data storage areas ECC 1 / 4, ECC 2 / 4, ECC 3 / 4, and ECC 4 / 4 can include a selected bit line based on a column address that can select one of the 512 bit lines. Therefore, each of the first test circuit 10 and the second test circuit 20 includes multiplexers MUX0 and MUX1 and XOR gates XOR0 and XOR1, respectively. Based on the most significant bit of the column address (e.g., column address Address) <9> The most significant bit), one of the first and second test circuits 10 and 20 can be configured to identify whether the data output from the normal data storage area and the data output from the ECC data storage area are the same as each other, and the other of the first and second test circuits 10 and 20 can be configured to identify whether the data output from the normal data storage area is the same as each other.

[0079] More specifically, for example, the first test circuit 10 and the second test circuit 20 can operate as follows.

[0080] When the highest column address Address <9> When the level is low, multiplexer MUX0 can select and output the data ECC_UP<0:7> of the first ECC data storage area ECC 1 / 4 and the second ECC storage area ECC 2 / 4, while multiplexer MUX1 can select and output the data H8<0:7> of the ninth normal data storage area H8.

[0081] Therefore, the first test circuit 10 can output the test result signal Test_UP by identifying whether all data H0<0:7>, H1<0:7>, H2<0:7>, H3<0:7>, H4<0:7>, H5<0:7>, H6<0:7>, and H7<0:7> output from the first to eighth normal data storage areas H0 to H7, and the data ECC_UP<0:7> output from the first and second ECC data storage areas ECC 1 / 4 and ECC 2 / 4 are the same as each other. Furthermore, the second test circuit 20 can output the test result signal Test_DN by identifying whether all data H8<0:7>, H9<0:7>, H10<0:7>, H11<0:7>, H12<0:7>, H13<0:7>, H14<0:7>, and H15<0:7> output from the ninth to sixteenth normal data storage areas H8 to H15 are the same as each other. In this case, the XOR gate XOR1 of the second test circuit 20 can receive data H8<0:7>, H9<0:7>, H10<0:7>, H11<0:7>, H12<0:7>, H13<0:7>, H14<0:7> and H15<0:7> output from the ninth to sixteenth normal data storage areas H8 to H15, as well as data H8<0:7> output from the multiplexer MUX1.

[0082] When the highest column address Address <9> When the level is high, multiplexer MUX0 can output data H7<0:7> from the eighth normal data storage area H7, while multiplexer MUX1 can output data ECC_DN<0:7> from the third and fourth ECC data storage areas ECC 3 / 4 and ECC 4 / 4.

[0083] Therefore, the first test circuit 10 can output the test result signal Test_UP by identifying whether all data H0<0:7>, H1<0:7>, H2<0:7>, H3<0:7>, H4<0:7>, H5<0:7>, H6<0:7>, and H7<0:7> output from the first to eighth normal data storage areas H0 to H7 are the same. In this case, the XOR gate XOR0 of the first test circuit 10 can receive the data H0<0:7>, H1<0:7>, H2<0:7>, H3<0:7>, H4<0:7>, H5<0:7>, H6<0:7>, and H7<0:7> output from the first to eighth normal data storage areas H0 to H7, as well as the data H7<0:7> output from the multiplexer MUX0.

[0084] In addition, the second test circuit 20 can output the test result signal Test_DN by identifying whether all data H8<0:7>, H9<0:7>, H10<0:7>, H11<0:7>, H12<0:7>, H13<0:7>, H14<0:7>, and H15<0:7> output from the ninth to the sixteenth normal data storage areas H8 to H15 are the same as the data ECC_DN<0:7> output from the third and fourth ECC data storage areas ECC 3 / 4 and ECC 4 / 4.

[0085] The memory bank of a semiconductor device according to embodiments of the present disclosure is configured to include first to fourth ECC data storage regions ECC 1 / 4, ECC 2 / 4, ECC 3 / 4, and ECC 4 / 4, comprising 512 bit lines divided into four groups of 128 bit lines each. Furthermore, the most significant bit of the column address (e.g., the most significant bit of the column address) used to select the 512 bit lines can be the column address that distinguishes between the upper 256 bit lines and the lower 256 bit lines. Therefore, in embodiments of the present disclosure, examples of using the most significant column address as a selection control signal for multiplexers MUX0 and MUX1 have been described to distinguish between the selection of bit lines included in the first and second ECC data storage regions ECC 1 / 4 and ECC 2 / 4, which include the upper 256 bit lines, and the selection of bit lines included in the third and fourth ECC data storage regions ECC 3 / 4 and ECC 4 / 4, which include the lower 256 bit lines.

[0086] Although embodiments of the technical essence of this disclosure have been described above with reference to the accompanying drawings, these embodiments are provided merely to illustrate embodiments based on the concepts of this disclosure, and this disclosure is not limited to these embodiments. Those skilled in the art to which this disclosure pertains can substitute, modify, and change these embodiments in various ways without departing from the technical spirit of this disclosure as set forth in the claims. Such substitutions, modifications, and changes are said to fall within the scope of this disclosure. Furthermore, embodiments can be combined to form other embodiments.

Claims

1. A semiconductor device, comprising: A unit storage unit, wherein multiple normal data storage areas and multiple ECC data storage areas are arranged in a three-dimensional matrix on multiple stacked layers, the multiple normal data storage areas and the multiple ECC data storage areas corresponding to different numbers of bit lines; and An outer layer, electrically connected to the cell memory and located below the cell memory, The peripheral layer includes internal circuitry that controls the unit storage. The internal circuitry includes multiple test circuits that identify whether all data output from the multiple normal data storage areas and the multiple ECC data storage areas are identical to each other.

2. The semiconductor device according to claim 1, wherein, The number of bit lines corresponding to each of the plurality of normal data storage areas is the same as the total number of bit lines corresponding to the plurality of ECC data storage areas.

3. The semiconductor device according to claim 2, wherein, The plurality of test circuits include: A first test circuit receives data from some normal data storage areas within the plurality of normal data storage areas and some ECC data storage areas within the plurality of ECC data storage areas; and The second test circuit receives data from the remainder of the plurality of normal data storage areas and the remainder of the plurality of ECC data storage areas.

4. The semiconductor device according to claim 3, wherein, The outer layer causes the first test circuit to be disposed below some of the normal data storage areas and some of the ECC data storage areas in the plurality of normal data storage areas, and the second test circuit to be disposed below the remaining portions of the plurality of normal data storage areas and the remaining portions of the plurality of ECC data storage areas.

5. The semiconductor device according to claim 3, wherein: The first test circuit identifies whether the data output from the normal data storage area and the ECC data storage area are the same based on column address; as well as The second test circuit identifies whether the data output from the normal data storage area are the same as each other based on the column address.

6. The semiconductor device according to claim 5, wherein, The first test circuit and the second test circuit perform identification based on the most significant bit of the column address.

7. The semiconductor device according to claim 6, wherein, Each of the first test circuit and the second test circuit includes: A multiplexer that, based on the most significant bit of the column address, selects one of data output from the normal data storage area and data output from the ECC data storage area; and An XOR gate identifies whether all data output from the multiplexer and data output from the normal data storage area are the same.

8. A semiconductor device, comprising: The storage unit includes a plurality of normal data storage areas and at least one ECC data storage area, the normal data storage areas corresponding to a plurality of bit lines, and the ECC data storage area corresponding to a smaller number of bit lines compared to each of the plurality of normal data storage areas; as well as The test circuit identifies whether all data output from the plurality of normal data storage areas and data output from the ECC data storage area are the same as each other based on the column address of a selected bit line. The test circuit: when the bit lines included in the ECC data storage area are selected based on the column address, it identifies whether the data output from the normal data storage area and the data output from the ECC data storage area are the same; and when the bit lines included in the ECC data storage area are not selected based on the column address, it identifies whether the data output from the normal data storage area are the same.

9. The semiconductor device according to claim 8, wherein, The test circuit includes: A multiplexer that, based on the most significant bit of the column address, outputs one of the data output from the normal data storage area and the data output from the ECC data storage area; and An XOR gate identifies whether all data output from the normal data storage area and the output of the multiplexer are the same.

10. A semiconductor device, comprising: The storage unit includes a first normal data storage area to a sixteenth normal data storage area and a first ECC data storage area to a fourth ECC data storage area; A first test circuit, which: based on the most significant bit of the column address, identifies whether the data output from the first normal data storage area to the eighth normal data storage area is the same as each other, or identifies whether the data output from the first normal data storage area to the eighth normal data storage area and the data output from the first ECC data storage area and the second ECC data storage area are the same as each other; and The second test circuit identifies, based on the most significant bit of the column address, whether the data output from the ninth normal data storage area to the sixteenth normal data storage area are the same as each other, or identifies whether the data output from the ninth normal data storage area to the sixteenth normal data storage area and the data output from the third ECC data storage area and the fourth ECC data storage area are the same as each other.

11. The semiconductor device of claim 10, wherein, First test circuit: When the most significant bit of the column address is at the first level, it is determined whether the data output from the first normal data storage area to the eighth normal data storage area is the same as each other; as well as When the most significant bit of the column address is at the second level, it is determined whether the data output from the first normal data storage area to the eighth normal data storage area and the data output from the first ECC data storage area and the second ECC data storage area are the same as each other.

12. The semiconductor device of claim 11, wherein, Second test circuit: When the most significant bit of the column address is at the first level, it is determined whether the data output from the ninth normal data storage area to the sixteenth normal data storage area and the data output from the third ECC data storage area and the fourth ECC data storage area are the same as each other; as well as When the most significant bit of the column address is at the second level, it is determined whether the data output from the ninth normal data storage area to the sixteenth normal data storage area are the same as each other.

13. The semiconductor device of claim 11, wherein, The first test circuit includes: The selection circuit, based on the most significant bit of the column address, outputs the data from the eighth normal data storage area or the data from the first ECC data storage area and the second ECC data storage area; and A data comparison circuit identifies whether the data output from the first normal data storage area to the eighth normal data storage area and the data output from the selection circuit are the same as each other.

14. The semiconductor device of claim 13, wherein: The selection circuit includes a multiplexer that uses the most significant bit of the column address as a selection control signal, and The data comparison circuit includes an XOR gate.

15. The semiconductor device according to claim 12, wherein, The second test circuit includes: The selection circuit, based on the most significant bit of the column address, outputs the data from the ninth normal data storage area or the data from the third and fourth ECC data storage areas; and A data comparison circuit identifies whether the data output from the ninth to the sixteenth normal data storage areas and the data output from the selection circuit are the same as each other.

16. The semiconductor device of claim 15, wherein: The selection circuit includes a multiplexer that uses the most significant bit of the column address as a selection control signal, and The data comparison circuit includes an XOR gate.

17. The semiconductor device of claim 10, wherein: Each of the first to the sixteenth normal data storage areas corresponds to 512 bit lines, and Each of the first to fourth ECC data storage areas corresponds to 128 bit lines.

18. The semiconductor device according to claim 17, wherein, The most significant bit of the column address distinguishes the first and second ECC data storage areas from the third and fourth ECC data storage areas.

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