Memory device and program operation thereof

Abstract

In certain aspects, a memory device includes memory strings, each including a first drain select gate (DSG) transistor; an insulating structure disposed between two adjacent sets of memory strings and electrically isolating the first DSG transistors of the two adjacent sets of memory strings; a first DSG line, each coupled to the first DSG transistor in a corresponding one of the two adjacent sets of the memory string; and a peripheral circuit coupled to the memory string through the first DSG lines, and configured to, in operation, apply a negative voltage to an unselected first DSG line among the first DSG lines, the unselected first DSG line is coupled to the first DSG transistor in an unselected set of two adjacent sets of the memory string.

Description

Technical Field

[0001] This disclosure relates to memory devices and methods of operating thereof. Background Technology

[0002] Flash memory is a low-cost, high-density, non-volatile solid-state storage medium that can be electrically erased and reprogrammed. Flash memory includes NOR flash memory and NAND flash memory. Flash memory can perform various operations, such as reading, programming (writing), and erasing. For NAND flash memory, erasure operations can be performed at the block level, and programming or reading operations can be performed at the page level. Summary of the Invention

[0003] In one aspect, a memory device includes: a memory string, each memory string including a first drain-select-gate (DSG) transistor; an insulating structure disposed between two adjacent sets of the memory string and electrically isolating the first DSG transistors in the two adjacent sets of the memory string; first DSG lines, each coupled to a first DSG transistor in a corresponding set of the two adjacent sets of the memory string; and peripheral circuitry coupled to the memory string via the first DSG lines and configured to: in operation, apply a negative voltage to an unselected first DSG line of the first DSG lines, wherein the unselected first DSG line is coupled to a first DSG transistor in an unselected set of the two adjacent sets of the memory string.

[0004] In some embodiments, the insulation structure extends laterally in a straight or serpentine pattern and extends vertically through the first DSG line.

[0005] In some embodiments, each of the memory strings further includes a memory cell, and the memory device further includes word lines coupled to the memory cells of the memory strings. In some embodiments, the operation includes a programming operation, and the peripheral circuitry is further configured to: during the programming operation, while the negative voltage is applied to the unselected first DSG line, apply a programming voltage to a select word line among the word lines to program a selected memory cell among the memory cells coupled to the select word line.

[0006] In some embodiments, each of the memory strings further includes a memory cell, and the memory device further includes a word line coupled to the memory cell of the memory string. In some embodiments, the operation includes a read operation or a verification operation, and the peripheral circuitry is further configured to: during the read operation or the verification operation, while the negative voltage is applied to the unselected first DSG line, apply a read / verify voltage to a select word line among the word lines to read or verify a selected memory cell among the memory cells coupled to the select word line.

[0007] In some embodiments, each of the memory strings further includes a second DSG transistor, and the memory device further includes a second DSG line coupled to the second DSG transistor of the memory string. In some embodiments, the peripheral circuitry is also configured to apply a first positive voltage to the second DSG line during the application of the negative voltage to the unselected first DSG line to turn on the second DSG transistor.

[0008] In some embodiments, each of the memory strings further includes a third DSG transistor, and the memory device further includes a third DSG line coupled to the third DSG transistor of the memory string, wherein the third DSG line is closer to the insulating structure in the vertical direction than the second DSG line. In some embodiments, the peripheral circuitry is further configured to apply a second positive voltage, less than the first positive voltage, to the third DSG line during the application of the negative voltage to the unselected first DSG line to turn on the third DSG transistor.

[0009] In some embodiments, the insulation structure extends vertically through the first DSG line and stops before reaching the second DSG line.

[0010] In some embodiments, the peripheral circuitry is further configured to: during the operation, apply a third positive voltage to select a first DSG line in the first DSG line, the select first DSG line being coupled to the first DSG transistor in the select set of the two adjacent sets of the memory string.

[0011] In some embodiments, the memory device further includes an additional first DSG line coupled to a first DSG transistor in an additional unselected set of the memory string, the additional unselected set being non-adjacent to the selected set in one of the two adjacent sets of the memory string. In some embodiments, the peripheral circuitry is also configured to apply a ground voltage to the additional first DSG line during operation.

[0012] In some embodiments, the memory device is a NAND flash memory device.

[0013] In another aspect, a method for operating a memory device is provided. The memory device includes: a memory string, each memory string including a first DSG transistor; an insulating structure disposed between two adjacent sets of the memory strings and electrically isolating the first DSG transistors in the two adjacent sets of the memory strings; and first DSG lines, each coupled to a first DSG transistor in a corresponding set of the two adjacent sets of the memory strings. In operation, a negative voltage is applied to an unselected first DSG line among the first DSG lines. The unselected first DSG line is coupled to a first DSG transistor in an unselected set of the two adjacent sets of the memory strings.

[0014] In some embodiments, the insulation structure extends laterally in a straight or serpentine pattern and extends vertically through the first DSG line.

[0015] In some embodiments, each of the memory strings further includes a memory cell, and the memory device further includes word lines coupled to the memory cells of the memory strings. In some embodiments, the operation includes a programming operation, in which a programming voltage is applied to a select word line among the word lines while the negative voltage is applied to the unselected first DSG line to program a selected memory cell among the memory cells coupled to the select word line.

[0016] In some embodiments, each of the memory strings further includes a memory cell, and the memory device further includes a word line coupled to the memory cell of the memory string. In some embodiments, the operation includes a read operation or a verification operation, and in the read operation or the verification operation, while the negative voltage is applied to the unselected first DSG line, a read / verify voltage is applied to a select word line among the word lines to read or verify a selected memory cell among the memory cells coupled to the select word line.

[0017] In some embodiments, each of the memory strings further includes a second DSG transistor, and the memory device further includes a second DSG line coupled to the second DSG transistor of the memory string. In some embodiments, while the negative voltage is applied to the unselected first DSG line, a first positive voltage is applied to the second DSG line to turn on the second DSG transistor.

[0018] In some embodiments, each of the memory strings further includes a third DSG transistor, and the memory device further includes a third DSG line coupled to the third DSG transistor of the memory string, and the third DSG line is closer to the insulating structure in the vertical direction than the second DSG line. In some embodiments, during the application of the negative voltage to the unselected first DSG line, a second positive voltage less than the first positive voltage is applied to the third DSG line to turn on the third DSG transistor.

[0019] In some embodiments, the insulation structure extends vertically through the first DSG line and stops before reaching the second DSG line.

[0020] In some implementations, during the operation, a third positive voltage is applied to the first DSG line, which is coupled to the first DSG transistor in the selection set of the two adjacent sets of the memory string.

[0021] In some embodiments, the memory device further includes an additional first DSG line coupled to the first DSG transistor in an additional unselected set of the memory string, the additional unselected set being non-adjacent to the selected set in one of the two adjacent sets of the memory string. In some embodiments, a ground voltage is applied to the additional first DSG line during operation.

[0022] In another aspect, a system includes: a memory device configured to store data; and a memory controller coupled to and configured to control the memory device. The memory device includes: a memory string, each memory string including a first DSG transistor; an insulating structure disposed between two adjacent sets of the memory strings and electrically isolating the first DSG transistors in the two adjacent sets of the memory strings; first DSG lines, each coupled to a first DSG transistor in a corresponding set of the two adjacent sets of the memory strings; and peripheral circuitry coupled to the memory strings via the first DSG lines and configured to: in operation, apply a negative voltage to an unselected first DSG line among the first DSG lines, wherein the unselected first DSG line is coupled to a first DSG transistor in an unselected set of the two adjacent sets of the memory strings. Attached Figure Description

[0023] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate various aspects of this disclosure and, together with the specification, further serve to explain the principles of this disclosure and enable those skilled in the art to make and use this disclosure.

[0024] Figure 1 A schematic diagram of a memory device including peripheral circuitry is shown, according to some aspects of this disclosure.

[0025] Figure 2 A side view of a cross-section of a memory cell array including NAND memory strings is shown, according to some aspects of this disclosure.

[0026] Figure 3 A block diagram of a memory device including a memory cell array and peripheral circuitry, according to some aspects of this disclosure, is shown.

[0027] Figure 4 A schematic diagram of a NAND memory string is shown, representing some aspects of this disclosure.

[0028] Figure 5A A plan view of a memory string array is shown, according to some aspects of this disclosure.

[0029] Figure 5B A plan view of another memory string array is shown, according to some aspects of this disclosure.

[0030] Figure 6 A plan view of the NAND memory string and DSG cutout is shown according to some aspects of this disclosure.

[0031] Figure 7A A side view of a memory cell array according to some aspects of this disclosure and the channel potential of a NAND memory string are shown, the memory cell array including NAND memory strings, DSG cutouts and various types of DSG transistors.

[0032] Figure 7B A perspective view of a memory cell array including NAND memory strings and various types of DSG transistors is shown, according to some aspects of this disclosure.

[0033] Figure 8A and Figure 8B The waveform of the word line voltage applied to the select word line during programming operations is shown according to some aspects of this disclosure.

[0034] Figure 9 The timing diagram of the programming operation is shown.

[0035] Figure 10A timing diagram of programming operations according to some aspects of this disclosure is shown.

[0036] Figure 11 The timing diagram for the read / verify operation is shown.

[0037] Figure 12 A timing diagram of read / verification operations according to some aspects of this disclosure is shown.

[0038] Figure 13 The voltage applied to the DSG line during operation is shown according to some aspects of this disclosure.

[0039] Figure 14 A flowchart of a method for operating a memory device according to some aspects of this disclosure is shown.

[0040] Figure 15 A block diagram of a system having a memory device according to some aspects of this disclosure is shown.

[0041] Figure 16A A diagram of a memory card having a memory device is shown, according to some aspects of this disclosure.

[0042] Figure 16B A diagram of a solid-state drive (SSD) with a memory device is shown, according to some aspects of this disclosure.

[0043] This disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0044] Generally, terms can be understood at least partly from their use in context. For example, the term "one or more," as used herein, can be used, at least partly depending on the context, to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a," "an," or "described" can be understood to convey either a singular or a plural usage, at least partly depending on the context. Furthermore, the term "based on" can be understood not necessarily to convey an exclusive set of factors, but can also, at least partly depending on the context, allow for the presence of other factors that are not necessarily explicitly described.

[0045] A structure known as a "DSG notch" can be used to divide memory strings in a NAND flash memory device (e.g., a three-dimensional (3D) NAND memory string) into different sets along the bit line direction (also called the y-direction), allowing these sets to be controlled individually during operations (e.g., programming or read / verify operations). To increase storage density, DSG notches can be placed between two rows of memory strings. However, due to process variations in forming DSG notches, in some memory strings, the gate structure corresponding to a portion of the semiconductor channel can be removed through the DSG notch, resulting in current leakage between the corresponding DSG transistor and the bit line for the unselected set of the memory string during operations (e.g., programming or read / verify operations). Potential coupling from adjacent selected sets of the memory string during operations (e.g., programming operations) can exacerbate the current leakage problem of the unselected set of the memory string. Current leakage between the DSG transistor and the bit line can affect the performance of the memory device by introducing programming interference, for example, during programming operations, and noise, during read / verify operations.

[0046] To address one or more of the aforementioned problems, this disclosure improves various operations (e.g., programming and read / verify operations) by applying a negative voltage instead of ground to the DSG transistors of the memory string in the unselected set of the memory string, ensuring that the DSG transistors and semiconductor channels of the corresponding memory string are completely shut off to avoid current leakage. Furthermore, to suppress hot carrier injection (HCI) and gate-induced drain leakage (GIDL) effects caused by the negative voltage applied to the DSG transistors in the unselected set of the memory string (which can cause threshold voltage drift in the DSG transistors), this disclosure also provides various methods to further improve the operation of the memory device. In some embodiments, the memory string includes additional DSG transistors unaffected by the DSG cutout, and a positive voltage is applied to these additional DSG transistors to smooth potential changes in the semiconductor channel, thereby suppressing HCI and GIDL effects. In some embodiments, a negative voltage is applied only to the DSG transistors in the unselected set of the memory string adjacent to the selected set, but not to other DSG transistors in other non-adjacent unselected sets of the memory string, thereby suppressing HCI and GIDL effects in non-adjacent sets.

[0047] Figure 1A schematic circuit diagram of a memory device 100 including peripheral circuitry according to some aspects of this disclosure is shown. The memory device 100 may include a memory cell array 101 and peripheral circuitry 102 coupled to the memory cell array 101. The memory cell array 101 may be a NAND flash memory cell array, wherein memory cells 106 are provided in the form of an array of NAND memory strings 108 all extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 108 includes a plurality of memory cells 106 connected in series and stacked vertically. Each memory cell 106 may hold a continuous analog value (e.g., voltage or charge) depending on the number of electrons trapped in the region of the memory cell 106. Each memory cell 106 may be a floating-gate type memory cell including a floating-gate transistor or a charge-trapping type memory cell including a charge-trapping transistor.

[0048] In some implementations, each memory cell 106 is an SLC having two possible levels (memory states) and thus capable of storing one bit of data. For example, a first level "0" may correspond to a first threshold voltage range, and a second level "1" may correspond to a second threshold voltage range. In some implementations, each memory cell 106 is an xLC capable of storing more than a single bit of data in more than four levels. For example, an xLC may store two bits per cell (MLC), three bits per cell (TLC), or four bits per cell (QLC). Each xLC can be programmed to assume a series of possible nominal stored values ​​(i.e., 2^N corresponding to N bits of data). N (pieces). In some embodiments, at least one of the memory cells 106 is set to 2. N One of the levels corresponds to an N-bit data segment, where N is an integer greater than 1.

[0049] like Figure 1As shown, each NAND memory string 108 may further include a source select gate (SSG) transistor 110 (also referred to as a bottom select gate (BSG) transistor) at its source end and a drain select gate (DSG) transistor 112 (also referred to as a top select gate (TSG) transistor) at its drain end. The SSG transistor 110 and DSG transistor 112 may be configured to activate and select the NAND memory string 108 (column of the array) during read and program operations. In some embodiments, the sources of the NAND memory strings 108 in the same block 104 are coupled via the same source line (SL) 114 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 108 in the same block 104 have an array common source (ACS). According to some embodiments, the drain of each NAND memory string 108 is coupled to a corresponding bit line 116, from which data can be read or written via an output bus (not shown). In some implementations, each NAND memory string 108 is configured to be selected or deselected by applying a selection voltage (e.g., a positive voltage greater than the threshold voltage of the DSG transistor 112) or a deselection voltage (e.g., a ground voltage) to the gate of the corresponding DSG transistor 112 via one or more DSG lines 113 and / or by applying a selection voltage (e.g., a positive voltage greater than the threshold voltage of the SSG transistor 110) or a deselection voltage (e.g., a ground voltage) to the gate of the corresponding SSG transistor 110 via one or more SSG lines 115.

[0050] like Figure 1 As shown, NAND memory strings 108 can be organized into multiple blocks 104, each block 104 may have a common source line 114, for example, coupled to an ACS. In some embodiments, each block 104 is a basic data unit for erase operations, i.e., all memory cells 106 on the same block 104 are erased simultaneously. To erase memory cells 106 in a selected block 104, an erase voltage (Vers), such as a high positive bias voltage (e.g., 20V or greater), can be used to bias the source line 114 coupled to the selected block 104 and the unselected block 104 in the same plane as the selected block 104. Memory cells 106 of adjacent NAND memory strings 108 can be coupled via word lines 118, which select which row of memory cells 106 is affected by read and program operations. In some embodiments, each word line 118 is coupled to multiple memory cells 106. Each word line 118 may include multiple control gates (gate electrodes) and gate lines coupled to the control gates at each memory cell 106.

[0051] like Figure 1As shown, the memory cell array 101 may include an array of memory cells 106 arranged in multiple rows and columns in each block 104. According to some embodiments, one column of memory cells corresponds to a NAND memory string 108. Multiple rows of memory cells 106 may be coupled to word lines 118, and multiple columns of memory cells 106 may be coupled to bit lines 116. Peripheral circuitry 102 may be coupled to the memory cell array 101 via bit lines 116 and word lines 118.

[0052] Figure 2 A side view of a cross-section of a memory cell array 101 including NAND memory strings 108, according to some aspects of this disclosure, is shown. Figure 2 As shown, the NAND memory string 108 may extend vertically through the memory stack 204 above the substrate 202. The substrate 202 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any suitable material thereof.

[0053] The memory stack 204 may include staggered gate conductive layers 206 and gate-to-gate dielectric layers 208. The number of logarithms of the gate conductive layers 206 and gate-to-gate dielectric layers 208 in the memory stack 204 determines the number of memory cells 106 in the memory cell array 101. The gate conductive layers 206 may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicides, or any combination thereof. In some embodiments, each gate conductive layer 206 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 206 includes a doped polysilicon layer. Each gate conductive layer 206 may include a control gate surrounding the gate of the memory cell 106, the gate of the DSG transistor 112, or the gate of the SSG transistor 110, and may extend laterally as a DSG line 113 at the top of the memory stack 204, an SSG line 115 at the bottom of the memory stack 204, or a word line 118 between DSG lines 113 and SSG lines 115.

[0054] Consistent with the scope of this disclosure, a DSG cutout 210 (also referred to as a TSG cutout) is formed through the DSG line 113. The DSG cutout 210 "cuts" and thus electrically isolates the DSG line 113 between adjacent regions (e.g., referred to herein as "sets"), allowing individual control of the DSG line 113 and DSG transistor 112 in different sets during read / verify operations and / or programming operations. Although the DSG cutout 210 extends vertically through... Figure 2The two DSG lines 113 are shown, but it should be understood that the number of DSG lines through which the DSG cut 210 extends can vary in different examples, as detailed below.

[0055] like Figure 2 As shown, the NAND memory string 108 includes a channel structure extending vertically through the memory stack 204. In some embodiments, the channel structure includes channel holes filled with one or more semiconductor materials (e.g., as semiconductor channels) and one or more dielectric materials (e.g., as memory films). It should be understood that, although Figure 2 Additional components, not shown, that can form the memory cell array 101, include, but are not limited to, gate line gaps / source contacts, local contacts, interconnect layers, etc.

[0056] Return to reference Figure 1 The peripheral circuitry 102 can be coupled to the memory cell array 101 via bit line 116, word line 118, source line 114, SSG line 115, and DSG line 113. The peripheral circuitry 102 may include any suitable analog, digital, and mixed-signal circuitry for facilitating the operation of the memory cell array 101 by applying voltage and / or current signals to each selected memory cell 106 via bit line 116, word line 118, source line 114, SSG line 115, and DSG line 113, and sensing voltage and / or current signals from each selected memory cell 106. The peripheral circuitry 102 may include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 3 Some exemplary peripheral circuitry is shown, including a page buffer / sensor amplifier 304, a column decoder / bit line driver 306, a row decoder / word line driver 308, a voltage generator 310, control logic 312, a register 314, an interface (I / F) 316, and a data bus 318. It should be understood that in some examples, additional peripheral circuitry may also be included. Figure 3 Additional peripheral circuitry not shown.

[0057] Page buffer / sensor amplifier 304 can be configured to sense (read) data from memory cell array 101 and program (write) data to memory cell array 101 according to control signals from control logic 312. In one example, page buffer / sensor amplifier 304 can store one or more pages of programming data (write data, referred to herein as "data pages") to be programmed. In another example, page buffer / sensor amplifier 304 can verify the programmed select memory cell 106 in each programming / verification cycle of a programming operation to ensure that data has been correctly programmed into the memory cell 106 coupled to select word line 118. In yet another example, page buffer / sensor amplifier 304 can also sense a low-power signal from bit line 116 representing data bits stored in memory cell 106 and amplify small voltage swings to a recognizable logic level during read operations.

[0058] The column decoder / bit line driver 306 can be configured, controlled by control logic 312, to select one or more NAND memory strings 108 by applying bit line voltages generated by voltage generator 310. The row decoder / word line driver 308 can be configured, controlled by control logic 312, to select / deselect block 104 of memory cell array 101 and to select / deselect word lines of block 104. The row decoder / word line driver 308 can also be configured to drive word lines 118 using word line voltages generated by voltage generator 310. In some embodiments, the row decoder / word line driver 118 can also select / deselect and also drive SSG lines 115 and DSG lines 113. The voltage generator 310 can be configured, controlled by control logic 122, to generate word line voltages (e.g., read voltage, programming voltage, channel pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to memory cell array 101.

[0059] Control logic 312 can be coupled to each of the aforementioned peripheral circuits and configured to control the operation of each peripheral circuit. Register 314 can be coupled to control logic 312 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses used to control the operation of each peripheral circuit. Interface 316 can be coupled to control logic 312 and acts as a control buffer to buffer and relay control commands received from the memory controller (not shown) and / or the host (not shown) to control logic 312, and to buffer and relay status information received from control logic 312 to the memory controller and / or the host. Interface 316 can also be coupled to column decoder / bitline driver 306 via data bus 318 and acts as a data input / output (I / O) interface and data buffer to buffer and relay data to and from memory cell array 101.

[0060] Figure 4 A schematic diagram of a NAND memory string is shown, representing some aspects of this disclosure. Figure 4 Blocks are shown (e.g., Figure 1 NAND memory strings in 104 (e.g., Figure 1 An example of a 108) array. Figure 4 As shown, in the vertical direction (z-direction) from top to bottom, each NAND memory string can be coupled to multiple lines in different rows, such as bit lines (BLs, e.g., ... Figure 1 116), DSG line (DSGL, for example, Figure 1 113), word line (WL, for example, Figure 1 118), SSG line (SSGL, for example, Figure 1 115 in the middle) and common source line (CSL, for example, Figure 1 (114 in the middle). For example Figure 4 As shown, word lines can extend laterally in both the word line direction (x direction) and the bit line direction (y direction) to connect memory cells of a NAND memory string, and word line voltages can be applied during operations (e.g., programming operations or read / verify operations).

[0061] like Figure 4 As shown, in some operations, the bit line can be a select bit line (Sel BL) with a selected voltage (e.g., ground voltage GND) applied or an inhibit bit line (Inhibit BL) with an inhibit voltage (e.g., positive power supply voltage Vdd) applied. As for the DSG lines, the DSG lines can be continuous in the word line direction (x-direction) to connect the DSG transistors of the NAND memory string located at the same position in the y-direction, but can be slit by DSG lines in the bit line direction (y-direction). Figure 4 Not shown in the image, for example Figure 2 The DSG lines in the selected and unselected sets (210) are separated to form electrically isolated sets that can be controlled individually during programming operations. During those operations, different voltages may also be applied to the DSG lines in the selected and unselected sets. In some embodiments, the DSG lines in the selected set are selected DSG lines (Sel DSGL) with a selected voltage (e.g., a positive supply voltage Vcc > Vdd), and the DSG lines in the unselected set are unselected DSG lines (Unsel DSGL) with an unselected (deselected) voltage applied. Consistent with the scope of this disclosure, to suppress current leakage between the bit lines and the DSG transistor 402 in the unselected set, a negative voltage (Vnxd) instead of ground can be used as the unselected voltage applied to the unselected DSG lines to ensure that the DSG transistor 402 in the unselected set is completely turned off during operation, as described in detail below.

[0062] Figure 5A A plan view of an array of NAND memory strings 108 is shown, according to some aspects of this disclosure. Figure 5B A plan view of another array of NAND memory strings 108 is shown, according to some aspects of this disclosure. (See diagram below.) Figure 5A and 5B As shown, the NAND memory strings 108 can be divided into different blocks in a planar view using an insulating structure of one type (e.g., gate line gaps (GLS) 502). Each GLS 502 can extend laterally through the memory array region in the word line direction (x-direction) and also vertically through all gate conductive layers 206 to electrically isolate the NAND memory strings 108 in different blocks. The GLS 502 may include a dielectric material, such as silicon oxide. Within each block, the NAND memory strings 108 can be further divided into different sets in a planar view using another type of insulating structure (e.g., DSG notch 210). The DSG notch 210 may include a dielectric material, such as silicon oxide. The sets of NAND memory strings 108 can be "selected sets" or "unselected sets" in operations (e.g., programming operations or read / verify operations), depending on whether the voltage applied to the DSG lines 113 in that set is a selection voltage that turns on the corresponding DSG transistor 112 or an unselected voltage that turns off the corresponding DSG transistor 112. In some implementations, one of the sets in a block is the selected set, while the rest of the sets in the block are the unselected sets.

[0063] Each DSG notch 210 can extend vertically through some of the gate conductive layers 206, such as one or more DSG lines 113, to "cut" those DSG lines 113, thereby electrically isolating the corresponding DSG transistors 112 in different sets. In a plan view, the DSG notch 210 can also extend laterally within the block in different ways, for example as... Figure 5A The straight line shown or as Figure 5B The serpentine line shown. Figure 5A and 5B As shown, the array of NAND memory strings 108 can be arranged in different sets in the bit line direction (y direction), and each DSG cutout 210 can be disposed between two adjacent sets of NAND memory strings 108. In some embodiments, each DSG cutout 210 electrically isolates the DSG transistors 112 of two adjacent sets of NAND memory strings 108.

[0064] Figure 6 A plan view of the NAND memory string 108 and DSG cutout 210 according to some aspects of this disclosure is shown. (See above regarding...) Figure 2 As described, the NAND memory string 108 may include a channel structure having channel holes filled with one or more semiconductor materials (e.g., as semiconductor channel 602) and one or more dielectric materials (e.g., as memory film 604). In some embodiments, the semiconductor channel 602 includes silicon, such as polysilicon. In some embodiments, the memory film 604 is a composite dielectric layer including a tunneling layer 606, a storage layer 608 (also referred to as a "charge trap / storage layer"), and a barrier layer 610. The channel structure may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel 602, tunneling layer 606, storage layer 608, and barrier layer 610 are arranged radially from the center toward the outer surface of the pillar in this order. The tunneling layer 606 may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer 608 may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The barrier layer 610 may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film 604 may comprise a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO). The memory film 604 and the surrounding gate electrode 612 (e.g., Figure 2 A portion of the gate conductive layer 206 surrounding the NAND memory string 108 can form a gate structure surrounding the semiconductor channel 602 to control the current in the semiconductor channel 602.

[0065] When a DSG notch 210 is formed between adjacent rows of a NAND memory string 108, due to process limitations, the size of the DSG notch 210 in the bit line direction (y-direction) may exceed the spacing between adjacent rows of the NAND memory string 108, allowing a portion of the channel structure in the NAND memory string 108 to be replaced by the DSG notch 210. However, due to process variations in forming the DSG notch 210, the semiconductor channel 602 and the corresponding gate structure (memory film 604 and gate electrode 612) may be affected by the DSG notch 210 to the same extent (e.g., Figure 6 (as shown in the example on the left) or different degrees of influence (such as) Figure 6 (As shown in the example on the right). Figure 6 As shown in the example on the right, for the NAND memory string 108 in the lower row, the semiconductor channel 602 can remain intact, while a portion of the gate structure (memory film 604 and gate electrode 612) surrounding the semiconductor channel 602 can be replaced by the DSG cutout 210 (in the dashed box). As a result, the current in the portion of the semiconductor channel 602 within the dashed box cannot be controlled by the surrounding gate structure. Therefore, when the lower row of the NAND memory string 108 is in an unselected set during operation, the DSG transistor 112 in the lower row may not be fully turned off when a normal unselected voltage (e.g., ground voltage) is applied to its gate, thus creating a current leakage path between the DSG transistor 112 and the bit line 116. Furthermore, when the NAND memory string 108 in the upper row is in the select set during operation, a positive select voltage is applied to the gate of the DSG transistor in the select set, such that the potential coupling from the selected NAND memory string 108 may further increase the leakage current in a portion (in the dashed box) of the semiconductor channel 602 in the unselected NAND memory string 108.

[0066] In order to suppress or even avoid the above-mentioned... Figure 6 The current leakage caused by the described DSG cutout 210, consistent with the scope of this disclosure, allows the normal deselection voltage (e.g., ground voltage) to be replaced by an enhanced deselection voltage (e.g., a negative voltage) applied to the gate of the DSG transistor 112, thereby ensuring that the DSG transistors 112 in the unselected set can be completely turned off during operation (e.g., programming or read / verify operations), even if due to... Figure 6 The DSG cut 210 shown on the right forms a leakage path. For example, as... Figure 4 As shown, a negative voltage (Vnxd) (instead of ground voltage) can be used as an unselected voltage applied to the unselected DSG line to ensure that the DSG transistors 402 in the unselected set are completely turned off during operation.

[0067] Replacing the unselected voltage applied to the unselected DSG line from ground to a negative voltage can result in a large potential gap between the DSG transistor and the memory cell in the semiconductor channel of the unselected NAND memory string (unselected NAND memory string), which may in turn introduce HCI and GILD effects into the semiconductor channel. However, HCI and GILD effects can shift the threshold voltage of the DSG transistor downwards and the threshold voltage of the memory cell closer to the DSG transistor upwards, thus affecting device performance. According to some aspects of this disclosure, additional DSG transistors can be included in the NAND memory string, and a positive voltage can be applied to the additional DSG transistors to generate a smoother potential gradient in the semiconductor channel of the unselected NAND memory string, thereby suppressing the threshold voltage shift caused by HCI / GILD.

[0068] Figure 7A A side view of a memory cell array according to some aspects of this disclosure is shown, along with the channel potential of a NAND memory string 108, which includes a NAND memory string 108, a DSG notch 210, and various types of DSG transistors. Figure 7B A perspective view of a memory cell array including NAND memory strings 108 and various types of DSG transistors, according to some aspects of this disclosure, is shown. Figure 7A and 7B As shown, the NAND memory string 108 may include, from top to bottom (in the z-direction), one or more coarse DSG transistors (CDSG) coupled to one or more coarse DSG lines 702 (coarse DSGL), one or more buffer DSG transistors (BDSG) coupled to one or more buffer DSG lines 704 (buffer DSGL), and one or more fine DSG transistors (FDSG) coupled to one or more fine DSG lines 706 (fine DSGL). Figure 7AAs shown, according to some embodiments, the DSG notch 210 extends vertically (in the z-direction) through the coarse DSG line 702 and stops before reaching the fine DSG line 706. In some embodiments, the buffer DSG line 704 (and the buffer DSG transistor) is closer to the DSG notch 210 (in the z-direction) vertically than the fine DSG line 706 (and the fine DSG transistor). It should be understood that due to process variations, the DSG notch 210 may stop before reaching the buffer DSG line 704, or it may extend through some of the buffer DSG lines 704. That is, according to some embodiments, the DSG notch 210 cuts each coarse DSG line 702 to electrically isolate the coarse DSG transistors in two adjacent sets, but does not cut any of the fine DSG lines 706, such that the fine DSG transistors in adjacent sets are still electrically connected through the fine DSG lines 706. The buffer DSG line 704 can be used as a "buffer" to ensure that the DSG notch 210 does not extend to the fine DSG line 706. In some implementations, coarse DSG transistors are controlled at the set level (per set control) because coarse DSG lines 702 in a block are cut by DSG cutouts 210 between different sets, while fine DSG transistors and buffered DSG transistors are controlled at the block level (per block control) because fine DSG lines 706 and buffered DSG lines 704 in the same block are not cut by DSG cutouts 210.

[0069] In some implementations, a negative voltage (Vnxd) is applied to the coarse DSG line 702, a first positive voltage (Vdd) is applied to the buffered DSG line 704, and a second positive voltage (Vcc or Vpass) greater than the first positive voltage is applied to the fine DSG line 706. As a result, potential changes in the semiconductor channel 602 of the NAND memory string 108 in the unselected set during operations (e.g., programming operations or read / verify operations) may... Figure 7AThe right side is smoothed. In one example, when a positive pass voltage Vpass (greater than the positive supply voltage Vcc) is applied to word line 118 and fine DSG line 706, the potential in semiconductor channel 602 gradually increases from Vnxd (in the region corresponding to the coarse DSG transistor) to Vdd (in the region corresponding to the buffer DSG transistor), and then to Vpass (in the region corresponding to the fine DSG transistor and memory cell). In another example, when a positive supply voltage Vcc is applied to fine DSG line 706, the potential in semiconductor channel 602 gradually increases from Vnxd (in the region corresponding to the coarse DSG transistor) to Vdd (in the region corresponding to the buffer DSG transistor), then to Vcc (in the region corresponding to the fine DSG transistor), and then to Vpass (in the region corresponding to the memory cell). As a result, threshold voltage shift caused by HCI / GIDL can be suppressed by introducing fine and buffer DSG transistors that are positively biased during operation.

[0070] The operation of the schemes disclosed herein may include any appropriate operation of a memory device (e.g., a NAND flash memory device) that controls a separate set of memory strings (each set controlled), including but not limited to programming and reading operations.

[0071] To perform programming operations, in addition to the page buffer / sensor amplifier 304 providing a corresponding data segment to each selected memory cell 106, the row decoder / word line driver 308 can be configured to apply programming and verification voltages to the select word line 118 coupled to the selected row of memory cell 106 in one or more programming / verification cycles, so as to raise the threshold voltage of each selected memory cell 106 to a desired level (to within a desired threshold voltage range) based on the corresponding data segment. For example, Figure 8A and Figure 8B The waveform of the word line voltage applied to the select word line during programming operations is shown according to some aspects of this disclosure.

[0072] like Figure 8A and 8B As shown, according to some embodiments, the programming operation includes one or more loops 802, each loop including a programming cycle 804 and a verification cycle 806. Figure 8BAs shown, in each cycle 802, the row decoder / word line driver 308 can be configured to apply a programming voltage (Vpgm) on the select word line 118 in programming cycle 804 to select a row of memory cell 106, and sequentially apply one or more verification voltages (Vvfy) in verification cycle 806 to verify the selected row of memory cell 106. That is, in each cycle 802, the peripheral circuitry 102 can perform verification of the selected row of memory cell 106 at one or more levels in verification cycle 806 after applying the programming voltage in programming cycle 804. According to some embodiments, the number of verification voltages applied in verification cycle 806 depends on the level programmed by a particular cycle 802. As a result, at the end of the programming operation, for example, the selected memory cell 106 can be programmed to 2... N In one of the voltage levels, N is a positive integer.

[0073] As mentioned above Figure 8B As described, a programming operation may include a programming process executed in programming cycle 804 and a verification process executed in verification cycle 806. For ease of description, the term "programming operation" as used herein may refer to the programming process within a programming operation, and the term "verification operation" as used herein may refer to the verification process within a programming operation. Since the verification process within a programming operation is similar to a read operation, the term "read / verify operation" as used herein may refer to the read operation and / or the verification process within a programming operation.

[0074] Figure 9 A timing diagram of the programming operations is shown. Specifically, Figure 9A programming cycle 804 corresponding to a programming operation includes a pre-pulse period 902 and a programming period 904. In the pre-pulse period 902, a positive select voltage (e.g., Vcc) is applied to each select and unselected DSG line (DSGL) to turn on the select and unselected DSG transistors, and a positive bias voltage is applied to each select bit line (BL) to remove residual electrons from the semiconductor channels of the NAND memory string. The channel potential is set to the desired level before programming period 904, also known as "pre-pulse channel cleaning." In programming period 904, a programming voltage (Vpgm) is applied to the select word line (WL) to program the selected memory cells coupled to the select word line, and various positive voltages at different levels (e.g., Vcc and Vpass) are applied to each select DSG line and unselected word line to turn on the semiconductor channels of the selected NAND memory string (the NAND memory string in the select set) for programming. For example, a positive supply voltage (Vcc) can be applied to the select DSG line to turn on the select DSG transistor, and a positive pass voltage (Vpass) greater than the positive supply voltage (Vcc) can be applied to each unselected word line to turn on each unselected memory cell. Furthermore, a three-bit line bias voltage (V3bl) can be applied to the select bit line in conjunction with the positive supply voltage (Vcc) applied to each select DSG line to achieve fine-tuning of the threshold voltage for the programmable memory cell.

[0075] like Figure 9 As shown, for unselected NAND memory strings (NAND memory strings in the unselected set), a ground voltage (GND) is applied to the unselected DSG line to turn off the unselected DSG transistor, thereby cutting off the semiconductor channel and current within it. As mentioned above, due to process limitations and variations, the semiconductor channel of some unselected NAND memory strings may not be completely cut off by applying a ground voltage to the unselected DSG line, resulting in current leakage.

[0076] Figure 10 A timing diagram of programming operations according to some aspects of this disclosure is shown. Specifically, Figure 10 This corresponds to a programming cycle 804 in the programming operation, which includes a pre-pulse period 1002 and a programming period 1004. (As mentioned above...) Figure 7A and 7BAs described, in a programming operation, selecting a NAND memory string may include a select coarse DSG transistor coupled to one or more select coarse DSG lines (DSGL), and not selecting a NAND memory string may include an unselect coarse DSG transistor coupled to one or more unselect coarse DSG lines (DSGL); the selected and unselected NAND memory strings may also include buffer DSG transistors coupled to one or more buffer DSG lines (DSGL) and fine DSG transistors coupled to one or more fine DSG lines (DSGL). In some embodiments, select coarse DSG lines and unselect coarse DSG lines are isolated by DSG cutouts between different sets, fine DSG lines within the same block are not isolated by DSG cutouts, and buffer DSG lines within the same block may or may not be isolated by DSG cutouts.

[0077] like Figure 10 As shown, during the pre-pulse period 1002, the word line driver 308 of the peripheral circuit 102 can be configured to apply a positive selection voltage to each select coarse DSG line and unselect coarse DSG line, buffer DSG line, and fine DSG line to turn on the select coarse DSG transistor and unselect coarse DSG transistor, buffer DSG transistor, and fine DSG transistor, and apply a positive bias voltage to each select bit line (BL) to remove residual electrons from the semiconductor channel of the NAND memory string and set the channel potential to the desired level before the programming period 1004 (also referred to as "pre-pulse channel cleaning"). In some embodiments, the positive selection voltage applied to each select coarse DSG line and unselect coarse DSG line is greater than... Figure 9 The positive pass voltage (Vpass) of the positive supply voltage (Vcc) in the example shown allows for the compensation of threshold voltage variations in the coarse DSG transistors caused by process limitations and variations in the DSG notch, with the increased select voltage Vpass ensuring that all coarse DSG transistors are turned on during the pre-pulse period 1002. In some implementations, the positive select voltage applied to each buffer DSG line and fine DSG line is the positive supply voltage (e.g., Vcc), which is less than the positive pass voltage (Vpass) applied to the coarse DSG line because the threshold voltages of the buffer DSG transistors and fine DSG transistors are not affected by the DSG notch.

[0078] like Figure 10As shown, during programming phase 1004, the word line driver 308 of the peripheral circuitry 102 can be configured to apply a programming voltage (Vpgm) to the select word line to program the selected memory cell coupled to the select word line. The word line driver 308 can also be configured to apply various positive voltages of different levels (e.g., Vcc, Vdd, and Vpass) to select coarse DSG lines, buffered DSG lines, fine DSG lines, and unselected word lines, thereby turning on the semiconductor channels of the selected NAND memory string for programming. In some embodiments, the positive select voltage applied to each select coarse DSG line is greater than... Figure 9 The positive pass voltage (Vpass) of the positive supply voltage (Vcc) in the example shown allows for the compensation of threshold voltage variations in the select coarse DSG transistors caused by process limitations and variations in the DSG notch, ensuring that all select coarse DSG transistors are turned on during programming phase 1004. In one example, the same positive pass voltage (Vpass) may also be applied to the unselected word line during programming phase 1004. In some implementations, the positive select voltage applied to each fine DSG line is a first positive supply voltage (Vcc) that is greater than the second positive supply voltage (Vdd) applied to each buffered fine DSG line. For example, Vpass > Vcc > Vdd. In some implementations, a three-bit line bias voltage (V3bl) is applied to the select bit line in conjunction with the positive supply voltage (Vcc) applied to each fine DSG line to achieve fine-tuning of the threshold voltage of the programmable memory cell.

[0079] Figure 9 In the example, the two functions of the selected DSG transistor, namely (1) turning on the semiconductor channel and (2) fine-tuning the threshold voltage of the programmed memory cell, can be respectively determined by... Figure 10 The selection of the NAND memory string is performed using coarse and fine DSG transistors, as described above. Instead of using the same positive selection voltage Vcc for both functions, a higher positive selection voltage Vpass (instead of Vcc) can be used to ensure that each semiconductor channel of each NAND memory string is open even under the influence of the DSG cut, while the lower positive selection voltage Vcc can still be used to fine-tune the threshold voltage of the programmable memory cell using the three-bit line bias voltage applied to the select bit line.

[0080] Regarding the unselected NAND memory strings in the unselected set, such as Figure 10 As shown, during programming phase 1004, the word line driver 308 of the peripheral circuit 102 can be configured to apply a negative voltage (Vnxd) to each unselected coarse DSG line during the application of a programming voltage to the selected word line. This is in contrast to the application of a ground voltage to each unselected DSG line. Figure 9 Compared to the example, a negative voltage applied to the gate of an unselected coarse DSG transistor may suppress current leakage even under the influence of the DSG cut and help ensure that the semiconductor channel of the unselected NAND memory string is closed. In some implementations, the negative voltage is between about -5V and about 0V, for example, between -5V and 0V (e.g., -5V, -4.5V, -4V, -3.5V, -3V, -2.5V, -2V, -1.5V, -1V, -0.5V, -0.4V, -0.3V, -0.2V, -0.1V, any range defined by any one of these values ​​as the lower end, or any range defined by any two of these values).

[0081] On the other hand, according to some embodiments, during the application of a negative voltage to the unselected coarse DSG line, positive voltages (Vcc and Vdd) of different levels are applied to the fine DSG line and the buffered DSG line, respectively, as described above. As a result, even when a negative voltage is applied to the unselected coarse DSG line, a smooth potential gradient can be formed in the semiconductor channel of the unselected NAND memory string (e.g., as shown in the image). Figure 7A (as shown in the figure), thereby suppressing the HCI effect that may be caused by negative voltage.

[0082] Figure 11 A timing diagram of the read / verify operation is shown. Specifically, Figure 11 A verification cycle 804 corresponding to a programming or reading operation includes a pre-pulse period 1102 and a read / verify period 1104. In the pre-pulse period 1102, positive selection voltages (e.g., Vcc and Vpass) are applied to each selected DSG line (DSGL) and unselected DSG line, as well as each selected word line (WL) and unselected word line, to turn on the selected DSG transistors and unselected DSG transistors, and to select and unselect memory cells. A ground voltage is applied to each selected bit line (BL) to remove residual electrons from the semiconductor channels of the NAND memory string. The channel potential is set to the desired level before the read / verify period 1104, a process also known as "pre-pulse channel cleaning." During the read / verify phase 1104, a read / verify voltage (Vrd / Vvfy) is applied to the select word line to read / verify the selected memory cell coupled to the select word line, and a positive voltage (e.g., Vpass) is applied to each select DSG line and unselected word line to turn on the semiconductor channel of the selected NAND memory string for read / verify. Furthermore, during the application of the read / verify voltage to the select word line, a bias voltage (Vbl) is applied to the select bit line.

[0083] like Figure 11As shown, for an unselected NAND memory string, a ground voltage (GND) is applied to the unselected DSG line to turn off the unselected DSG transistor, thereby cutting off the semiconductor channel and current within it. As mentioned above, due to process limitations and variations, the semiconductor channel of some unselected NAND memory strings may not be completely cut off by applying a ground voltage to the unselected DSG line, resulting in current leakage.

[0084] Figure 12 A timing diagram of read / verification operations according to some aspects of this disclosure is shown. Specifically, Figure 12 A verification cycle 804 corresponds to a programming or reading operation, which includes a pre-pulse period 1202 and a read / verify period 1204. (As mentioned above...) Figure 7A and 7B As described, in a read / verify operation, selecting a NAND memory string may include a select coarse DSG transistor coupled to one or more select coarse DSG lines (DSGL), and not selecting a NAND memory string may include an unselect coarse DSG transistor coupled to one or more unselect coarse DSG lines (DSGL); the selected and unselected NAND memory strings may also include buffer DSG transistors coupled to one or more buffer DSG lines (DSGL) and fine DSG transistors coupled to one or more fine DSG lines (DSGL). In some embodiments, select coarse DSG lines and unselect coarse DSG lines are isolated by DSG cuts between different sets, fine DSG lines within the same block are not isolated by DSG cuts, and buffer DSG lines within the same block may or may not be isolated by DSG cuts.

[0085] like Figure 12 As shown, during the pre-pulse period 1202, the word line driver 308 of the peripheral circuit 102 can be configured to apply various positive selection voltages (e.g., Vdd, Vcc, and Vpass) of different levels to each selected coarse DSG line and unselected coarse DSG line, buffered DSG line, and fine DSG line to turn on the selected coarse DSG transistor and unselected coarse DSG transistor, buffered DSG transistor, and fine DSG transistor, and apply a ground voltage to each selected bit line (BL) to remove residual electrons in the semiconductor channel of the NAND memory string, and set the channel potential to the desired level before the read / verify period 1204, also known as "pre-pulse channel cleaning".

[0086] like Figure 12As shown, during the read / verify phase 1204, the word line driver 308 of the peripheral circuitry 102 can be configured to apply a read / verify voltage (Vrd / Vvfy) to the select word line to read or verify the selected memory cell coupled to the select word line. The word line driver 308 can also be configured to apply various positive voltages of different levels (e.g., Vcc, Vdd, and Vpass) to select the coarse DSG line, buffered DSG line, fine DSG line, and unselected word line to turn on the semiconductor channel of the selected NAND memory string for read / verify. In some embodiments, the same positive voltage is maintained on the coarse DSG line, buffered DSG line, fine DSG line, or unselected word line from the pre-pulse phase 1202 to the read / verify phase 1204. In some implementations, the positive select voltage applied to each select coarse DSG line is a positive pass voltage (Vpass) greater than the positive supply voltage (Vcc), such that threshold voltage variations in the select coarse DSG transistors caused by process limitations and variations in the DSG notch can be compensated for by the increased select voltage Vpass. This ensures that all select coarse DSG transistors are turned on during read / verify phase 1204. In one example, the same positive pass voltage (Vpass) may also be applied to the unselected word line during read / verify phase 1204. In some implementations, the positive select voltage applied to each fine DSG line is a positive pass voltage (Vpass) or a first positive supply voltage (Vcc) greater than the second positive supply voltage (Vdd) applied to each buffered fine DSG line. For example, Vpass > Vcc > Vdd. In some implementations, a bias voltage (Vbl) is applied to the select bit line during the application of the read / verify voltage to the select word line.

[0087] Regarding the unselected NAND memory strings in the unselected set, such as Figure 12 As shown, during the read / verify phase 1204, the word line driver 308 of the peripheral circuitry 102 can be configured to apply a negative voltage (Vnxd) to each unselected coarse DSG line during the period when a read / verify voltage is applied to the selected word line. This is in contrast to the application of a ground voltage to each unselected DSG line. Figure 11Compared to the example, a negative voltage applied to the gate of an unselected coarse DSG transistor may suppress current leakage even under the influence of the DSG cut and help ensure that the semiconductor channel of the unselected NAND memory string is closed. In some implementations, the negative voltage is between about -5V and about 0V, for example, between -5V and 0V (e.g., -5V, -4.5V, -4V, -3.5V, -3V, -2.5V, -2V, -1.5V, -1V, -0.5V, -0.4V, -0.3V, -0.2V, -0.1V, any range defined by any one of these values ​​as the lower end, or any range defined by any two of these values).

[0088] On the other hand, according to some embodiments, during the application of a negative voltage to the unselected coarse DSG line, positive voltages of different levels (Vpass / Vcc and Vdd) are applied to the fine DSG line and the buffered DSG line, respectively, as described above. As a result, even when a negative voltage is applied to the unselected coarse DSG line, a smooth potential gradient can be formed in the semiconductor channel of the unselected NAND memory string (e.g., as shown in the image). Figure 7A (as shown in the figure), thereby suppressing the HCI effect that may be caused by negative voltage.

[0089] As described above, replacing the unselected voltage applied to unselected DSG lines from ground to a negative voltage may introduce HCI and GILD effects into the semiconductor channel. This could lower the threshold voltage of the DSG transistor and raise the threshold voltage of memory cells near the DSG transistor, thereby affecting device performance. According to some aspects of this disclosure, a negative voltage is applied only to unselected DSG lines in the unselected set of a memory string that are adjacent to the selected set of the memory string, but not to unselected DSG lines in the unselected sets of other non-adjacent memory strings, thereby avoiding HCI and GILD effects in non-adjacent memory string sets.

[0090] For example, Figure 13 The voltage applied to the DSG line during operation is shown according to some aspects of this disclosure. For example... Figure 13 As shown, the memory device may include a DSG cutout in the block (e.g., in...). Figure 5A and Figure 5BMultiple sets of NAND flash memory strings are isolated. During operation (e.g., programming or read / verify operations), one of these sets can be selected as the selected set, while the remaining sets can be left unselected as unselected sets. For the selected set, a positive pass voltage (Vpass) can be applied to the DSG line (selected DSG line) during operation, as described in detail above. Regarding the unselected set, various unselected voltages (Vnxd and GND) of different levels can be applied to the DSG line (unselected DSG line) depending on whether the unselected set is adjacent to the selected set (and therefore affected by Vpass) or not adjacent to the selected set (and therefore not affected by Vpass). In some embodiments, as described in detail above, a negative voltage (Vnxd) is applied to the unselected DSG line in the unselected set adjacent to the selected set to suppress current leakage in the adjacent set. Conversely, according to some embodiments, a ground voltage (GND) is applied to the unselected DSG line in the unselected set not adjacent to the selected set to avoid HCI and GIDL effects in the non-adjacent set.

[0091] Figure 14 A flowchart of a method 1400 for operating a memory device according to some aspects of this disclosure is shown. The memory device can be any suitable memory device disclosed herein, such as memory device 100. Method 1400 can be implemented by peripheral circuitry 102 (e.g., line decoder / word line driver 308, page buffer / sensor amplifier 304, and control logic 312). It should be understood that the operations shown in method 1400 are not exhaustive, and other operations may be performed before, after, or between any of the shown operations. Furthermore, some operations may be performed simultaneously or in conjunction with... Figure 14 The different execution orders shown.

[0092] Method 1400 can be applied to a memory device comprising: a memory string, each memory string including a first DSG transistor; an insulating structure disposed between two adjacent sets of the memory strings and electrically isolating the first DSG transistors in the two adjacent sets of the memory strings; and first DSG lines, each first DSG line coupled to a first DSG transistor in a corresponding set of the two adjacent sets of the memory strings. In some embodiments, unselected first DSG lines are coupled to first DSG transistors in unselected sets of the two adjacent sets of the memory strings. In some embodiments, the insulating structure extends laterally in a straight or serpentine manner and extends vertically through the first DSG lines. In some embodiments, each memory string further includes a second DSG transistor, and the memory device further includes a second DSG line coupled to the second DSG transistor of the memory string. In some embodiments, each memory string further includes a third DSG transistor, and the memory device further includes a third DSG line coupled to the second DSG transistor of the memory string. In some embodiments, the third DSG line is closer to the insulating structure in the vertical direction than the second DSG line.

[0093] For example, such as Figure 5A , 5B As shown in 7A and 7B, the NAND memory string 108 may include, from top to bottom in the vertical direction (z-direction), a coarse DSG transistor (first DSG transistor) coupled to a coarse DSG line 702 (first DSG line), a buffer DSG transistor (third DSG transistor) coupled to a buffer DSG line 704 (third DSG line), and a fine DSG transistor (second DSG transistor) coupled to a fine DSG line 706 (second DSG line). The memory device may also include a DSG notch 210 disposed between two adjacent sets of the NAND memory string 108 in the bit line direction (y-direction) of the plan view and electrically isolating the coarse DSG transistors in the two adjacent sets. The DSG notch 210 may extend laterally in the word line direction (x-direction) of the plan view in a straight line or a serpentine line, and extend vertically through the coarse DSG line 702 and stop before reaching the fine DSG line 706.

[0094] refer to Figure 14Method 1400 begins at operation 1402, wherein a negative voltage is applied to an unselected first DSG line during operation of the memory device. At operation 1404, while the negative voltage is applied to the unselected first DSG line, a programming voltage or read / verify voltage is applied to a select word line in the word lines to program, read, or verify a selected memory cell coupled to the select word line. At operation 1406, while the negative voltage is applied to the unselected first DSG line, a first positive voltage is applied to a second DSG line to turn on a second DSG transistor. At operation 1408, while the negative voltage is applied to the unselected first DSG line, a second positive voltage less than the first positive voltage is applied to a third DSG line to turn on a third DSG transistor. At operation 1410, while the negative voltage is applied to the unselected first DSG line, a third positive voltage is applied to a selected first DSG line in the first DSG lines, the selected first DSG line being coupled to a first DSG transistor in a selected set of two adjacent sets in the memory string. In some implementations, the third positive voltage is greater than the first positive voltage.

[0095] For example, such as Figure 1-3 and Figure 10 As shown, during the programming phase 1004 of the programming operation, a negative voltage (Vnxd) can be applied by the word line driver 308 of the peripheral circuit 102 to the unselected coarse DSG line (unselected first DSG line) to turn off the unselected coarse DSG transistor (unselected first DSG transistor) coupled in the unselected set. While the negative voltage is applied to the unselected coarse DSG line, the word line driver 308 of the peripheral circuit 102 can apply a programming voltage (Vprm) to the select word line to program the coupled select memory cell. During the application of a negative voltage to the unselected coarse DSG line, the word line driver 308 of the peripheral circuit 102 can apply a first positive power supply voltage (Vcc) to the fine DSG line (second DSG line) to turn on the fine DSG transistors (second DSG transistors) coupled in the selected set and the unselected set, and apply a second positive power supply voltage (Vdd) less than the first positive power supply voltage (Vdd) to the buffered DSG line (third DSG line) to turn on the buffered DSG transistors (third DSG transistors) coupled in the selected set and the unselected set. During the application of a negative voltage to the unselected coarse DSG line, the word line driver 308 of the peripheral circuit 102 can apply a positive pass voltage (Vpass) greater than the first positive power supply voltage (Vcc) to the selected coarse DSG line (selected first DSG line) to turn on the selected coarse DSG transistors (selected first DSG transistors) coupled in the selected set.

[0096] For example, such as Figure 1-3 and Figure 12As shown, during the read / verify phase 1204 of the read / verify operation, a negative voltage (Vnxd) can be applied by the word line driver 308 of the peripheral circuit 102 to the unselected coarse DSG line (unselected first DSG line) to turn off the unselected coarse DSG transistor (unselected first DSG transistor) coupled in the unselected set. During the application of the negative voltage to the unselected coarse DSG line, the word line driver 308 of the peripheral circuit 102 can apply a read voltage (Vrd) or a verification voltage (Vvfy) to the select word line to read or verify the coupled selected memory cell. During the application of a negative voltage to the unselected coarse DSG line, the word line driver 308 of the peripheral circuit 102 can apply a first positive power supply voltage (Vcc or Vpass) to the fine DSG line (second DSG line) to turn on the fine DSG transistors (second DSG transistors) coupled in the selected set and the unselected set, and apply a second positive power supply voltage (Vdd) less than the first positive power supply voltage (Vdd or Vpass) to the buffered DSG line (third DSG line) to turn on the buffered DSG transistors (third DSG transistors) coupled in the selected set and the unselected set. During the application of a negative voltage to the unselected coarse DSG line, the word line driver 308 of the peripheral circuit 102 can apply a positive pass voltage (Vpass) to the selected coarse DSG line (selected first DSG line) to turn on the selected coarse DSG transistors (selected first DSG transistors) coupled in the selected set.

[0097] At operation 1412, a ground voltage is applied to an additional first DSG line, which is coupled to a first DSG transistor in an additional unselected set of the memory string. This additional unselected set is not adjacent to the selected sets in two adjacent sets of the memory string. For example, as... Figure 1-3 and Figure 13 As shown, a negative voltage (Vndx) can be applied by the word line driver 308 of the peripheral circuit 102 to the unselected DSG lines in the unselected set adjacent to the selected set of the memory string, so that the unselected DSG transistors coupled in the adjacent unselected set are turned off. Conversely, a ground voltage (GND) can be applied by the word line driver 308 of the peripheral circuit 102 to the unselected DSG lines in the unselected set not adjacent to the selected set of the memory string, so that the unselected DSG transistors coupled in the non-adjacent unselected set are turned off.

[0098] Figure 15A block diagram of a system 1500 having a memory device according to some aspects of this disclosure is shown. System 1500 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 15 As shown, system 1500 may include host 1508 and having one or more memory devices 100 (in Figure 1 The memory system 1502 includes a memory controller 1506 and a memory device 1508. The host 1508 may be a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 1508 may be configured to send data to or receive data from the memory device 100.

[0099] Memory device 100 can be any memory device disclosed herein. According to some embodiments, memory controller 1506 is coupled to memory device 100 and host 1508 and configured to control memory device 100. Memory controller 1506 can manage data stored in memory device 100 and communicate with host 1508. In some embodiments, memory controller 1506 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, Compact Flash (CF) card, Universal Serial Bus (USB) flash drive, or other media for electronic devices (e.g., personal computers, digital cameras, mobile phones, etc.). In some embodiments, memory controller 1506 is designed to operate in a high duty cycle environment SSD or embedded multimedia card (eMMC) used for data storage in mobile devices (e.g., smartphones, tablets, laptops, etc.) and enterprise storage arrays. Memory controller 1506 can be configured to control the operation of memory device 100, such as read, erase, and program operations. The memory controller 1506 can also be configured to manage various functions relating to data stored or to be stored in the memory device 100, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 1506 is also configured to process error correction codes (ECC) relating to data read from or written to the memory device 100. Any other suitable functions may also be performed by the memory controller 1506, such as formatting the memory device 100. The memory controller 1506 may communicate with an external device (e.g., a host 1508) according to a specific communication protocol. For example, the memory controller 1506 may communicate with an external device via at least one of a variety of interface protocols, such as USB, Multimedia Card (MMC), Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.

[0100] The memory controller 1506 and one or more memory devices 100 can be integrated into various types of storage devices, for example, included in the same package, such as a Universal Flash Storage (UFS) package or an eMMC package. That is, the memory system 1502 can be implemented and packaged into different types of end electronic products. Figure 16AIn one example shown, the memory controller 1506 and a single memory device 100 can be integrated into a memory card 1602. The memory card 1602 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 1602 may further include a connection between the memory card 1601 and a host computer (e.g., Figure 15 The host 1508 is coupled to the memory card connector 1604. In such a... Figure 16B In another example shown, the memory controller 1506 and multiple memory devices 100 can be integrated into the SSD 1606. The SSD 1606 may also include an SSD connector 1608 that connects the SSD 1606 to a host computer (e.g., Figure 15 The host 1508 is coupled to the SSD 1606. In some embodiments, the storage capacity and / or operating speed of the SSD 1606 is greater than that of the memory card 1602.

[0101] The foregoing description of a particular implementation can be easily modified and / or adjusted for various applications. Therefore, based on the teachings and guidance given herein, these adjustments and modifications are intended to fall within the meaning and scope of equivalents of the disclosed implementations.

[0102] The scope and extent of this disclosure should not be limited to any of the embodiments described in the foregoing exemplary embodiments, but should be defined solely by the appended claims and their equivalents.

[0103] Although specific configurations and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Therefore, other configurations and arrangements may be used without departing from the scope of this disclosure. Furthermore, the subject matter described in this disclosure can be used in a variety of other applications. The functional and structural features described in this disclosure can be combined, adjusted, modified, and rearranged with each other in a manner consistent with the scope of this disclosure.

Claims

1. A memory device, comprising: Memory strings, each memory string including a first drain-select gate (DSG) transistor; An insulating structure is disposed between two adjacent sets of the memory string and electrically isolates the first DSG transistors of the two adjacent sets of the memory string. First DSG line, each of the first DSG lines being coupled to the first DSG transistor in a corresponding set of two adjacent sets of the memory string; as well as The peripheral circuitry is coupled to the memory string via the first DSG line and is configured to, in operation, apply a negative voltage to an unselected first DSG line in the first DSG line, wherein the unselected first DSG line is coupled to the first DSG transistor in the unselected set of two adjacent sets of the memory string.

2. The memory device according to claim 1, wherein, The insulation structure extends laterally in a straight or serpentine pattern and extends vertically through the first DSG line.

3. The memory device according to claim 1 or 2, wherein, Each of the memory strings further includes a memory cell, and the memory device further includes word lines coupled to the memory cells of the memory strings; and The operation includes a programming operation, and the peripheral circuitry is further configured to: during the programming operation, while the negative voltage is applied to the unselected first DSG line, apply a programming voltage to the select word line among the word lines to program the select memory cell coupled to the select word line in the memory cell.

4. The memory device according to claim 2, wherein, Each of the memory strings further includes a memory cell, and the memory device further includes word lines coupled to the memory cells of the memory strings; and The operation includes a read operation or a verification operation, and the peripheral circuitry is further configured to: during the read operation or the verification operation, while the negative voltage is applied to the unselected first DSG line, apply a read / verify voltage to the select word line in the word line to read or verify the selected memory cell coupled to the select word line in the memory cell.

5. The memory device according to claim 3 or 4, wherein, Each of the memory strings further includes a second DSG transistor, and the memory device further includes a second DSG line coupled to the second DSG transistor of the memory string; and The peripheral circuit is also configured to apply a first positive voltage to the second DSG line while the negative voltage is applied to the unselected first DSG line, so as to turn on the second DSG transistor.

6. The memory device according to claim 5, wherein, Each of the memory strings also includes a third DSG transistor, and the memory device further includes a third DSG line coupled to the third DSG transistor of the memory string, the third DSG line being closer to the insulating structure in the vertical direction than the second DSG line; and The peripheral circuit is further configured to apply a second positive voltage, less than the first positive voltage, to the third DSG line while the negative voltage is applied to the unselected first DSG line, so as to turn on the third DSG transistor.

7. The memory device according to claim 6, wherein, The insulation structure extends vertically through the first DSG line and stops before reaching the second DSG line.

8. The memory device according to any one of claims 1-7, wherein, The peripheral circuitry is further configured to, during the operation, apply a third positive voltage to select the first DSG line in the first DSG line, the select first DSG line being coupled to the first DSG transistor in the select set of the two adjacent sets of the memory string.

9. The memory device of claim 8, further comprising an additional first DSG line coupled to a first DSG transistor in an additional unselected set of the memory string, the additional unselected set being non-adjacent to the selected set in one of the two adjacent sets of the memory string. in, The peripheral circuitry is also configured to apply a ground voltage to the additional first DSG line during the operation.

10. The memory device according to any one of claims 1-9, wherein, The memory device is a NAND flash memory device.

11. A method for operating a memory device, the memory device comprising: Memory strings, each memory string including a first drain-select gate (DSG) transistor; An insulating structure is disposed between two adjacent sets of the memory string and electrically isolates the first DSG transistors of the two adjacent sets of the memory string. And a first DSG line, each first DSG line being coupled to a first DSG transistor in a corresponding set of two adjacent sets of the memory string, the method comprising: In operation, a negative voltage is applied to an unselected first DSG line in the first DSG line, wherein the unselected first DSG line is coupled to the first DSG transistor in the unselected set of the two adjacent sets of the memory string.

12. The method according to claim 11, wherein, The insulation structure extends laterally in a straight or serpentine pattern and extends vertically through the first DSG line.

13. The method according to claim 11 or 12, wherein, Each of the memory strings also includes a memory cell, and the memory device further includes a word line coupled to the memory cell of the memory string; and The operation includes a programming operation, and the method includes: during the programming operation, while the negative voltage is applied to the unselected first DSG line, applying a programming voltage to a select word line among the word lines to program a select memory cell in the memory cell coupled to the select word line.

14. The method according to claim 12, wherein, Each of the memory strings also includes a memory cell, and the memory device further includes a word line coupled to the memory cell of the memory string; and The operation includes a read operation or a verification operation, and the method includes: during the read operation or the verification operation, while the negative voltage is applied to the unselected first DSG line, applying a read / verify voltage to a select word line in the word line to read or verify a selected memory cell in the memory cell coupled to the select word line.

15. The method according to claim 13 or 14, wherein, Each of the memory strings also includes a second DSG transistor, and the memory device further includes a second DSG line coupled to the second DSG transistor of the memory string; and The method further includes: applying a first positive voltage to the second DSG line while the negative voltage is applied to the unselected first DSG line, so as to turn on the second DSG transistor.

16. The method according to claim 15, wherein, Each of the memory strings also includes a third DSG transistor, and the memory device further includes a third DSG line coupled to the third DSG transistor of the memory string, the third DSG line being closer to the insulating structure in the vertical direction than the second DSG line; and The method further includes: while applying the negative voltage to the unselected first DSG line, applying a second positive voltage, less than the first positive voltage, to the third DSG line to turn on the third DSG transistor.

17. The method according to claim 16, wherein, The insulation structure extends vertically through the first DSG line and stops before reaching the second DSG line.

18. The method according to any one of claims 11-17, further comprising: In the operation, a third positive voltage is applied to the first DSG line to select the first DSG line, which is coupled to the first DSG transistor in the selection set of the two adjacent sets of the memory string.

19. The method according to claim 18, wherein, The memory device further includes an additional first DSG line coupled to a first DSG transistor in an additional unselected set of the memory string, the additional unselected set being non-adjacent to the selected set in one of the two adjacent sets of the memory string; and The method further includes applying a ground voltage to the additional first DSG line during the operation.

20. A system comprising: A memory device, the memory device comprising: Memory strings, each memory string including a first drain-select gate (DSG) transistor; An insulating structure is disposed between two adjacent sets of the memory string and electrically isolates the first DSG transistors of the two adjacent sets of the memory string. First DSG lines, each of the first DSG lines being coupled to a first DSG transistor in a corresponding set of two adjacent sets of the memory string; and Peripheral circuitry, coupled to the memory string via the first DSG line, and configured to: in operation, apply a negative voltage to an unselected first DSG line within the first DSG line, wherein the unselected first DSG line is coupled to a first DSG transistor in an unselected set of two adjacent sets of the memory string; and A memory controller, which is coupled to the memory device and configured to control the memory device.

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